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# TCL File Generated by Component Editor 12.0
# Thu Sep 12 21:20:16 CST 2013
# DO NOT MODIFY
#
# dm9000a "dm9000a" v1.0
# null 2013.09.12.21:20:16
#
#
#
# request TCL package from ACDS 12.0
#
package require -exact qsys 12.0
#
# module dm9000a
#
set_module_property NAME dm9000a
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP my_lib
set_module_property DISPLAY_NAME dm9000a
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL DM9000A_IF
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file DM9000A_IF.v VERILOG PATH hdl/DM9000A_IF.v
add_fileset SIM_VHDL SIM_VHDL "" ""
set_fileset_property SIM_VHDL TOP_LEVEL DM9000A_IF
set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file dm9000a_hw.tcl OTHER PATH dm9000a_hw.tcl
#
# parameters
#
#
# display items
#
#
# connection point avalon_slave_0
#
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressAlignment DYNAMIC
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock_sink
set_interface_property avalon_slave_0 associatedReset clock_sink_reset
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 1
set_interface_property avalon_slave_0 isMemoryDevice false
set_interface_property avalon_slave_0 isNonVolatileStorage false
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 printableDevice false
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitStates 4
set_interface_property avalon_slave_0 readWaitTime 4
set_interface_property avalon_slave_0 setupTime 1
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitStates 4
set_interface_property avalon_slave_0 writeWaitTime 4
set_interface_property avalon_slave_0 ENABLED true
add_interface_port avalon_slave_0 iDATA writedata Input 32
add_interface_port avalon_slave_0 iCMD address Input 1
add_interface_port avalon_slave_0 iRD_N read_n Input 1
add_interface_port avalon_slave_0 iWR_N write_n Input 1
add_interface_port avalon_slave_0 iCS_N chipselect_n Input 1
add_interface_port avalon_slave_0 oDATA readdata Output 32
#
# connection point clock_sink
#
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
add_interface_port clock_sink iCLK clk Input 1
#
# connection point clock_sink_reset
#
add_interface clock_sink_reset reset end
set_interface_property clock_sink_reset associatedClock clock_sink
set_interface_property clock_sink_reset synchronousEdges DEASSERT
set_interface_property clock_sink_reset ENABLED true
add_interface_port clock_sink_reset iRST_N reset_n Input 1
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock ""
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
add_interface_port conduit_end iOSC_50 export Input 1
add_interface_port conduit_end ENET_DATA export Bidir 16
add_interface_port conduit_end ENET_CMD export Output 1
add_interface_port conduit_end ENET_RD_N export Output 1
add_interface_port conduit_end ENET_WR_N export Output 1
add_interface_port conduit_end ENET_CS_N export Output 1
add_interface_port conduit_end ENET_RST_N export Output 1
add_interface_port conduit_end ENET_INT export Input 1
add_interface_port conduit_end ENET_CLK export Output 1
#
# connection point interrupt_sender
#
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint avalon_slave_0
set_interface_property interrupt_sender associatedClock clock_sink
set_interface_property interrupt_sender associatedReset clock_sink_reset
set_interface_property interrupt_sender ENABLED true
add_interface_port interrupt_sender oINT irq Output 1
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