800x600

8 files changed, 443 insertions, 372 deletions

diff --git a/.gitignore b/.gitignore
index fad1fd2..baecc1f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -30,3 +30,7 @@ obj/
 public.mk
 summary.html
 system.h
+*.swp
+software/elf.flash
+software/sof.flash
+
diff --git a/GPU/hdl/GPU_IF.v b/GPU/hdl/GPU_IF.v
index 16c234d..94bc137 100644
--- a/GPU/hdl/GPU_IF.v
+++ b/GPU/hdl/GPU_IF.v
@@ -4,239 +4,283 @@
 // created in component editor.  It ties off all outputs to ground and
 // ignores all inputs.  It needs to be edited to make it do something
 // useful.
-// 
+//
 // This file will not be automatically regenerated.  You should check it in
 // to your version control system if you want to keep it.
 
 `timescale 1 ps / 1 ps
 module gpuv2 #(
-		parameter AUTO_CLOCK_CLOCK_RATE = "-1"
-	) (
-		input  wire       clk,       //        clock.clk
-		input  wire       rst_n,     //        reset.reset_n
-		input  wire       vga_clk,   //      vga_out.export
-		output reg [2:0] vga_red,    //             .export
-		output reg [2:0] vga_green,  //             .export
-		output reg [2:0] vga_blue,   //             .export
-		output reg        vga_hs,    //             .export
-		output reg        vga_vs,    //             .export
-		input  wire [31:0] data,     // avalon_slave.writedata
-		input  wire       wr_n,      //             .write_n
-		input  wire       cs_n,      //             .chipselect_n
-		input  wire [6:0] address    //             .address
-	);
-
-
-  reg [9:0] sprite_x;
-  reg [9:0] sprite_y;
-  reg [9:0] bat0_y;
-  reg [9:0] bat1_y;
-
-  reg [15:0] sprite[0:15];
-  
-  wire [4:0] reg_addr;
- 
-  assign reg_addr = address[6:2];
-  
-  wire [9:0] offset;
-  
-  assign offset = 10'h80;
-  
-  reg [2:0] sprite_red;
-  reg [2:0] sprite_green;
-  reg [2:0] sprite_blue;
-  
-  reg blanking;
-  
-  always @(posedge clk or negedge rst_n)
-  begin
-	if (rst_n == 0) begin
-		   blanking <= 0;
-			sprite_x <= 10'd127+offset;
-			sprite_y <= 10'd127+offset;
-			bat0_y <= 10'd100+offset;
-			bat1_y <= 10'd200+offset;
-			
-			sprite[0]=16'b1111111111111111;
-			sprite[1]=16'b1000000000000001;
-			sprite[2]=16'b1000000000000001;
-			sprite[3]=16'b1000000000000001;
-			sprite[4]=16'b1000000000000001;
-			sprite[5]=16'b1000000000000001;
-			sprite[6]=16'b1000000000000001;
-			sprite[7]=16'b1000000000000001;
-			sprite[8]=16'b1000000000000001;
-			sprite[9]=16'b1000000000000001;
-			sprite[10]=16'b1000000000000001;
-			sprite[11]=16'b1000000000000001;
-			sprite[12]=16'b1000000000000001;
-			sprite[13]=16'b1000000000000001;
-			sprite[14]=16'b1000000000000001;
-			sprite[15]=16'b1111111111111111;
-			
-			sprite_red[2:0]=3'b111;
-			sprite_green[2:0]=3'b000;
-			sprite_blue[2:0]=3'b111;
-			
-	end else if (~cs_n && ~wr_n) begin
-		if (reg_addr[4]) begin
-			sprite[reg_addr[3:0]]<=data[15:0];
-		end else begin
-			case (reg_addr[2:0]) 
-				3'd0:
-					blanking <= data[0];
-				3'd1:
-					sprite_x <= data[9:0];
-				3'd2:
-					sprite_y <= data[9:0];
-				3'd3:
-					bat0_y <= data[9:0];
-				3'd4:
-					bat1_y <= data[9:0];
-				3'd5:
-					begin
-						sprite_red <= data[8:6];
-						sprite_green <= data[5:3];
-						sprite_blue <= data[2:0];
-					end
-			endcase
-		end
-	end
-  end
-
-
-  reg trig_25M;
-  always @ (posedge vga_clk)
-  begin
-    if(!rst_n)
-      trig_25M <= 1'b0;
+           parameter AUTO_CLOCK_CLOCK_RATE = "-1"
+       ) (
+           input wire clk,         //        clock.clk
+           input wire rst_n,       //        reset.reset_n
+           input wire vga_clk,     //      vga_out.export
+           output reg [2: 0] vga_red,      //             .export
+           output reg [2: 0] vga_green,    //             .export
+           output reg [2: 0] vga_blue,     //             .export
+           output reg vga_hs,      //             .export
+           output reg vga_vs,      //             .export
+           input wire [31: 0] data,       // avalon_slave.writedata
+           input wire wr_n,        //             .write_n
+           input wire cs_n,        //             .chipselect_n
+           input wire [6: 0] address    //             .address
+       );
+
+
+
+
+localparam [4: 0]
+           GPU_REG_BLANK = 4'h0,
+           GPU_REG_SPRITE_X = 4'h1,
+           GPU_REG_SPRITE_Y = 4'h2,
+           GPU_REG_BAT0_Y = 4'h3,
+           GPU_REG_BAT1_Y = 4'h4,
+           GPU_REG_SPRITE_COLOUR = 4'h5,
+           GPU_REG_SPRITE_BASE = 4'h10;
+
+
+/* 
+// 640x480 60Hz 25MHz
+localparam [13: 0] GPU_ZERO = 14'd0,
+           GPU_H_ACTIVE = 14'd640,
+           GPU_H_SYNC_START = 14'd656,
+           GPU_H_SYNC_END = 14'd752,
+           GPU_H_TOTAL = 14'd799,
+           GPU_V_ACTIVE = 14'd480,
+           GPU_V_SYNC_START = 14'd490,
+           GPU_V_SYNC_END = 14'd492,
+           GPU_V_TOTAL = 14'd524;
+
+
+reg pixel_clk;
+always @ (posedge vga_clk) begin
+    if (!rst_n)
+        pixel_clk <= 1'b0;
     else
-      trig_25M <= ~trig_25M;
-  end 
-  
-  reg [9:0] vector_x;
-  always @ (posedge vga_clk or negedge rst_n)
-  begin
-    if(!rst_n)
-      vector_x <= offset;
-    else if(trig_25M)
-      begin
-        if(vector_x != (10'd799 + offset))
-			vector_x <= vector_x + 1'b1;
+        pixel_clk <= ~pixel_clk;
+end
+
+*/
+
+// 800x600 75Hz 49.5MHz
+localparam [13: 0] GPU_ZERO = 14'd0,
+           GPU_H_ACTIVE = 14'd800,
+           GPU_H_SYNC_START = 14'd816,
+           GPU_H_SYNC_END = 14'd896,
+           GPU_H_TOTAL = 14'd1055,
+           GPU_V_ACTIVE = 14'd600,
+           GPU_V_SYNC_START = 14'd601,
+           GPU_V_SYNC_END = 14'd604,
+           GPU_V_TOTAL = 14'd625;
+
+wire pixel_clk=vga_clk;
+
+localparam [13: 0] GPU_OFFSET=14'h80,
+                   BAT_WIDTH=14'd4,
+		   NET_WIDTH=14'd4;
+
+reg blanking;
+reg [13: 0] sprite_x, sprite_y, bat0_y, bat1_y;
+reg [2: 0] sprite_red, sprite_green, sprite_blue;
+reg [15: 0] sprite[0: 15];
+
+assign reg_addr = address[6: 2];
+wire [4: 0] reg_addr;
+
+always @(posedge clk or negedge rst_n) begin
+    if (rst_n == 0) begin
+        blanking <= 1;
+        sprite_x <= GPU_ZERO;
+        sprite_y <= GPU_ZERO;
+        bat0_y <= GPU_ZERO;
+        bat1_y <= GPU_ZERO;
+
+        sprite[0] = 16'b1111111111111111;
+        sprite[1] = 16'b1000000000000001;
+        sprite[2] = 16'b1000000000000001;
+        sprite[3] = 16'b1000000000000001;
+        sprite[4] = 16'b1000000000000001;
+        sprite[5] = 16'b1000000000000001;
+        sprite[6] = 16'b1000000000000001;
+        sprite[7] = 16'b1000000000000001;
+        sprite[8] = 16'b1000000000000001;
+        sprite[9] = 16'b1000000000000001;
+        sprite[10] = 16'b1000000000000001;
+        sprite[11] = 16'b1000000000000001;
+        sprite[12] = 16'b1000000000000001;
+        sprite[13] = 16'b1000000000000001;
+        sprite[14] = 16'b1000000000000001;
+        sprite[15] = 16'b1111111111111111;
+
+        sprite_red[2: 0] = 3'b111;
+        sprite_green[2: 0] = 3'b000;
+        sprite_blue[2: 0] = 3'b111;
+
+    end
+    else if (~cs_n && ~wr_n) begin
+        if (reg_addr[4]) begin
+            sprite[reg_addr[3: 0]] <= data[15: 0];
+        end
+        else begin
+            case (reg_addr[4: 0])
+                GPU_REG_BLANK:
+                    blanking <= data[0];
+                GPU_REG_SPRITE_X:
+                    sprite_x <= data[13: 0];
+                GPU_REG_SPRITE_Y:
+                    sprite_y <= data[13: 0];
+                GPU_REG_BAT0_Y:
+                    bat0_y <= data[13: 0];
+                GPU_REG_BAT1_Y:
+                    bat1_y <= data[13: 0];
+                GPU_REG_SPRITE_COLOUR: begin
+                    sprite_red <= data[8: 6];
+                    sprite_green <= data[5: 3];
+                    sprite_blue <= data[2: 0];
+                end
+            endcase
+        end
+    end
+end
+
+
+reg [13: 0] vector_x;
+always @ (posedge pixel_clk or negedge rst_n) begin
+    if (!rst_n)
+        vector_x <= GPU_OFFSET;
+    else begin
+        if (vector_x != (GPU_H_TOTAL + GPU_OFFSET))
+            vector_x <= vector_x + 1'b1;
         else
-          vector_x <= offset;
-      end
-  end 
-  
-  reg [9:0] vector_y;
-  always @ (posedge vga_clk or negedge rst_n)
-  begin
-    if(!rst_n)
-      vector_y <= offset;
-    else if(trig_25M)
-      begin
-        if(vector_x == (10'd799 + offset))
-          begin
-            if(vector_y != (10'd524 + offset))
-              vector_y <= vector_y + 1'b1;
+            vector_x <= GPU_OFFSET;
+    end
+end
+
+
+reg [13: 0] vector_y;
+always @ (posedge pixel_clk or negedge rst_n) begin
+    if (!rst_n)
+        vector_y <= GPU_OFFSET;
+    else begin
+        if (vector_x == (GPU_H_TOTAL + GPU_OFFSET )) begin
+            if (vector_y != (GPU_V_TOTAL + GPU_OFFSET))
+                vector_y <= vector_y + 1'b1;
             else
-              vector_y <= offset;
-          end
-      end
-  end
-  
-  always @ (posedge vga_clk or negedge rst_n)
-  begin
-    if(!rst_n)
-      vga_hs <= 1'b0;
-    else if(trig_25M)
-      begin
-        if(vector_x >= (10'd656 + offset) && vector_x < (10'd752+offset))
-          vga_hs <= 1'b0;
+                vector_y <= GPU_OFFSET;
+        end
+    end
+end
+
+
+always @ (posedge pixel_clk or negedge rst_n) begin
+    if (!rst_n)
+        vga_hs <= 1'b0;
+    else begin
+        if (vector_x >= (GPU_H_SYNC_START + GPU_OFFSET) && vector_x < (GPU_H_SYNC_END + GPU_OFFSET))
+            vga_hs <= 1'b0;
         else
-          vga_hs <= 1'b1;
-      end
-  end
-  
-  always @ (posedge vga_clk or negedge rst_n)
-  begin
-    if(!rst_n)
-      vga_vs <= 1'b0;
-    else if(trig_25M)
-      begin
-        if(vector_y >= (10'd490+offset) && vector_y < (10'd492+offset))
-          vga_vs <= 1'b0;
+            vga_hs <= 1'b1;
+    end
+end
+
+always @ (posedge  pixel_clk or negedge rst_n) begin
+    if (!rst_n)
+        vga_vs <= 1'b0;
+    else begin
+        if (vector_y >= (GPU_V_SYNC_START + GPU_OFFSET) && vector_y < (GPU_V_SYNC_END + GPU_OFFSET))
+            vga_vs <= 1'b0;
+        else
+            vga_vs <= 1'b1;
+    end
+end
+
+
+
+
+reg px_blank;
+
+always @ (posedge pixel_clk or negedge rst_n) begin
+    if (!rst_n)
+        px_blank <= 1;
+    else begin
+        if (vector_x >= GPU_OFFSET && vector_x < (GPU_H_ACTIVE + GPU_OFFSET) && vector_y >= GPU_OFFSET && vector_y < (GPU_V_ACTIVE + GPU_OFFSET))
+            px_blank <= blanking;
+        else
+            px_blank <= 1;
+    end
+end
+
+
+
+reg px_bat;
+
+always @ (posedge pixel_clk or negedge rst_n) begin
+    if (!rst_n) begin
+        px_bat <= 0;
+    end
+    else begin
+        if (vector_x < (BAT_WIDTH + GPU_OFFSET) && vector_y >= ( bat0_y - 20 ) && vector_y <= (bat0_y + 20) )
+            px_bat <= 1;
+        else if (vector_x >= (GPU_OFFSET + GPU_H_ACTIVE - BAT_WIDTH) && vector_y >= ( bat1_y - 20 ) && vector_y <= (bat1_y + 20) )
+            px_bat <= 1 ;
         else
-          vga_vs <= 1'b1;
-      end
-  end
-  
-  
-  
-  reg px_bat;
-  reg px_net;
-  reg px_sprite;
-  reg px_blank;
-  
-  always @ (posedge vga_clk or negedge rst_n)
-  begin
-    if(!rst_n) begin
-		px_bat <= 0;
-		px_net <= 0;
-		px_sprite <= 0;
-		px_blank <= 1;
-    end else if(trig_25M) begin
-        if(vector_x>= offset && vector_x < (10'd640+offset) && vector_y >= offset && vector_y < (10'd480+offset)) 
-				px_blank<= blanking;
-			else
-				px_blank<=1;
-				
-			if(vector_x >= (sprite_x - 8 )&& vector_x <=( sprite_x + 7 )
-				&& vector_y >= (sprite_y - 8) && vector_y <= (sprite_y + 7))
-				px_sprite <= sprite[(vector_y - (sprite_y - 8)) & 15 ][(vector_x - (sprite_x -8))& 15 ];
-			else
-				px_sprite <= 0;
-				
-		  if (vector_x  < (10'd4+offset)  && vector_y >=( bat0_y - 20 ) && vector_y <= (bat0_y + 20) )
-					px_bat <= 1;
-		   else if (vector_x >= (10'd636 + offset) && vector_y >=( bat1_y - 20 ) && vector_y <= (bat1_y + 20) )
-				px_bat <=1 ;
-			else	
-				px_bat <=0;
-			
-					
-			if (vector_x >= (10'd318 +offset) && vector_x < (10'd322+offset))
-			  px_net <= {3{vector_y[3]}};
-			else 
-				px_net <= 0;
-				
-     end
-  end
-  
-  always begin
-	if (px_blank) begin
-		vga_red = 3'b000;
-		vga_green = 3'b000;
-		vga_blue = 3'b000;
-	end else if (px_bat) begin
-   	vga_red= 3'b111;
-		vga_green=3'b111;
-		vga_blue=3'b111;
-   end else if (px_sprite) begin
-		vga_red = sprite_red;
-		vga_green= sprite_green;
-		vga_blue = sprite_blue;
-	end else if (px_net) begin
-		vga_red= 3'b111;
-		vga_green=3'b111;
-		vga_blue=3'b111;
-	end else begin
-		vga_red = 3'b000;
-		vga_green = 3'b000;
-		vga_blue = 3'b000;
-	end
-		
-  
-  end
-  
+            px_bat <= 0;
+    end
+end
+
+
+
+reg px_net;
+
+always @ (posedge pixel_clk or negedge rst_n) begin
+    if (!rst_n)
+        px_net <= 0;
+    else begin
+        if (vector_x >= (GPU_OFFSET + ( (GPU_H_ACTIVE - NET_WIDTH) / 2) ) && vector_x < ( GPU_OFFSET + ((GPU_H_ACTIVE + NET_WIDTH) / 2)))
+            px_net <= {3{vector_y[3]}};
+        else
+            px_net <= 0;
+    end
+end
+
+
+
+reg px_sprite;
+
+always @ (posedge pixel_clk or negedge rst_n) begin
+    if (!rst_n)
+        px_sprite <= 0;
+    else begin
+        if (vector_x >= (sprite_x - 8 ) && vector_x <= ( sprite_x + 7 )
+                && vector_y >= (sprite_y - 8) && vector_y <= (sprite_y + 7))
+            px_sprite <= sprite[(vector_y - (sprite_y - 8)) & 15 ][(vector_x - (sprite_x - 8)) & 15 ];
+        else
+            px_sprite <= 0;
+    end
+end
+
+always begin
+    if (px_blank) begin
+        vga_red = 3'b000;
+        vga_green = 3'b000;
+        vga_blue = 3'b000;
+    end else if (px_bat) begin
+        vga_red = 3'b111;
+        vga_green = 3'b111;
+        vga_blue = 3'b111;
+    end else if (px_sprite) begin
+        vga_red = sprite_red;
+        vga_green = sprite_green;
+        vga_blue = sprite_blue;
+    end else if (px_net) begin
+        vga_red = 3'b111;
+        vga_green = 3'b111;
+        vga_blue = 3'b111;
+    end else begin
+        vga_red = 3'b000;
+        vga_green = 3'b000;
+        vga_blue = 3'b000;
+    end
+end
+
 endmodule
diff --git a/pong3.pin b/pong3.pin
index d658730..85a0886 100644
--- a/pong3.pin
+++ b/pong3.pin
@@ -236,14 +236,14 @@ GND*                         : 169       :        :                   :
 GND*                         : 170       :        :                   :         : 2         :                
 GND*                         : 171       :        :                   :         : 2         :                
 VCCIO2                       : 172       : power  :                   : 3.3V    : 2         :                
-seven_seg[7]                 : 173       : output : 3.3-V LVTTL       :         : 2         : N              
+GND*                         : 173       :        :                   :         : 2         :                
 GND                          : 174       : gnd    :                   :         :           :                
 GND*                         : 175       :        :                   :         : 2         :                
 GND*                         : 176       :        :                   :         : 2         :                
 GND                          : 177       : gnd    :                   :         :           :                
 VCCINT                       : 178       : power  :                   : 1.2V    :           :                
 GND*                         : 179       :        :                   :         : 2         :                
-GND*                         : 180       :        :                   :         : 2         :                
+seven_seg[7]                 : 180       : output : 3.3-V LVTTL       :         : 2         : N              
 GND*                         : 181       :        :                   :         : 2         :                
 GND*                         : 182       :        :                   :         : 2         :                
 VCCIO2                       : 183       : power  :                   : 3.3V    : 2         :                
diff --git a/pong3.v b/pong3.v
index 0ad6803..1f5f68e 100644
--- a/pong3.v
+++ b/pong3.v
@@ -1,112 +1,112 @@
-module pong3(

-		clk,

-		rst_n,

-		

-		sdram_clk      ,//connected to the CLK port of SDRAM  

-		sdram_cke      ,//connected to the CKE port of SDRAM  

-		sdram_cs_n     ,//connected to the CS_n port of SDRAM 

-		sdram_ras_n    ,//connected to the RAS_n port of SDRAM

-		sdram_cas_n    ,//connected to the CAS_n port of SDRAM

-		sdram_we_n     ,//connected to the WE_n port of SDRAM 

-		sdram_ba       ,//connected to the BA port of SDRAM 

-		sdram_addr     ,//connected to the ADDR port of SDRAM   

-		sdram_dqm      ,//connected to the DQM port of SDRAM 

-		sdram_dq       ,//connected to the DQ port of SDRAM

-		

-		dm9000_int  ,

-		dm9000_rst_n,

-		dm9000_cs_n ,

-    	dm9000_cmd  ,

-    	dm9000_rd_n ,

-    	dm9000_wr_n ,

-    	dm9000_data ,

-		

-      vga_hs,

-      vga_vs,

-      vga_red,

-      vga_green,

-      vga_blue,

-    	

-		seven_seg

-	);

-	

-	input clk;

-	input rst_n;

-	

-	output			sdram_clk  ;

-	output			sdram_cke  ;

-	output			sdram_cs_n ;

-	output			sdram_ras_n;

-	output			sdram_cas_n;

-	output			sdram_we_n ;

-	output [ 1 : 0]	sdram_ba   ;

-	output [12 : 0]	sdram_addr ;

-	output [ 1 : 0]	sdram_dqm  ;

-	inout  [15 : 0]	sdram_dq   ;

-	

-	input           dm9000_int  ;

-	output			dm9000_rst_n;

-   output 			dm9000_cs_n ;

-   output 			dm9000_cmd  ;

-   output 			dm9000_rd_n ;

-   output 			dm9000_wr_n ;

-   inout  [15:0]	dm9000_data ;

-	

-	output [ 7:0] seven_seg;

-

-

-   output vga_hs;

-   output vga_vs;

-   output [2:0] vga_red;

-   output [2:0] vga_green;

-   output [2:0] vga_blue;		

-

-	

-	wire sclk;

-	

-	

-	pll u_pll(

-		.inclk0(clk      ),

-		.c0    (sclk     ),

-		.c1    (sdram_clk)

-	);

-	

-	

-	

-	my_sys u_my_sys(

-		.reset_reset_n     (rst_n      ),
-		.clk_clk           (sclk       ),
-		.sdram_0_wire_addr (sdram_addr ),
-		.sdram_0_wire_ba   (sdram_ba   ),
-		.sdram_0_wire_cas_n(sdram_cas_n),
-		.sdram_0_wire_cke  (sdram_cke  ),
-		.sdram_0_wire_cs_n (sdram_cs_n ),
-		.sdram_0_wire_dq   (sdram_dq   ),
-		.sdram_0_wire_dqm  (sdram_dqm  ),
-		.sdram_0_wire_ras_n(sdram_ras_n),
-		.sdram_0_wire_we_n (sdram_we_n ),
-		.pio_0_d_export    (seven_seg  ),

-		

-		

-		.gpu_0_vga_red(vga_red),

-		.gpu_0_vga_green(vga_green),

-		.gpu_0_vga_blue(vga_blue),

-		.gpu_0_vga_hs(vga_hs),

-		.gpu_0_vga_vs(vga_vs),

-		.gpu_0_vga_clk(clk),

-		

-    	.dm9000a_0_conduit_end_iOSC_50   (            ),
-		.dm9000a_0_conduit_end_ENET_DATA (dm9000_data ),
-		.dm9000a_0_conduit_end_ENET_CMD  (dm9000_cmd  ),
-		.dm9000a_0_conduit_end_ENET_RD_N (dm9000_rd_n ),
-		.dm9000a_0_conduit_end_ENET_WR_N (dm9000_wr_n ),
-		.dm9000a_0_conduit_end_ENET_CS_N (dm9000_cs_n ),
-		.dm9000a_0_conduit_end_ENET_RST_N(dm9000_rst_n),
-		.dm9000a_0_conduit_end_ENET_INT  (dm9000_int  ),
-		.dm9000a_0_conduit_end_ENET_CLK  (            ) 

-	);

-

-	

-	

-	

-endmodule 
+module pong3(
+    clk,
+    rst_n,
+
+    sdram_clk,		//connected to the CLK port of SDRAM
+    sdram_cke,		//connected to the CKE port of SDRAM
+    sdram_cs_n,		//connected to the CS_n port of SDRAM
+    sdram_ras_n,	//connected to the RAS_n port of SDRAM
+    sdram_cas_n,	//connected to the CAS_n port of SDRAM
+    sdram_we_n,		//connected to the WE_n port of SDRAM
+    sdram_ba,		//connected to the BA port of SDRAM
+    sdram_addr,		//connected to the ADDR port of SDRAM
+    sdram_dqm,		//connected to the DQM port of SDRAM
+    sdram_dq,		//connected to the DQ port of SDRAM
+
+    dm9000_int  ,
+    dm9000_rst_n,
+    dm9000_cs_n ,
+    dm9000_cmd  ,
+    dm9000_rd_n ,
+    dm9000_wr_n ,
+    dm9000_data ,
+
+    vga_hs,
+    vga_vs,
+    vga_red,
+    vga_green,
+    vga_blue,
+
+    seven_seg
+);
+
+input clk;
+input rst_n;
+
+output sdram_clk  ;
+output sdram_cke  ;
+output sdram_cs_n ;
+output sdram_ras_n;
+output sdram_cas_n;
+output sdram_we_n ;
+output [ 1 : 0]	sdram_ba   ;
+output [12 : 0]	sdram_addr ;
+output [ 1 : 0]	sdram_dqm  ;
+inout  [15 : 0]	sdram_dq   ;
+
+input  dm9000_int  ;
+output dm9000_rst_n;
+output dm9000_cs_n ;
+output dm9000_cmd  ;
+output dm9000_rd_n ;
+output dm9000_wr_n ;
+inout  [15:0] dm9000_data ;
+
+output [ 7:0] seven_seg;
+
+
+output vga_hs;
+output vga_vs;
+output [2:0] vga_red;
+output [2:0] vga_green;
+output [2:0] vga_blue;
+
+
+wire sclk;
+
+
+pll u_pll(
+    .inclk0(clk      ),
+    .c0    (sclk     ),
+    .c1    (sdram_clk)
+);
+
+
+
+my_sys u_my_sys(
+    .reset_reset_n     (rst_n      ),
+    .clk_clk           (sclk       ),
+    .sdram_0_wire_addr (sdram_addr ),
+    .sdram_0_wire_ba   (sdram_ba   ),
+    .sdram_0_wire_cas_n(sdram_cas_n),
+    .sdram_0_wire_cke  (sdram_cke  ),
+    .sdram_0_wire_cs_n (sdram_cs_n ),
+    .sdram_0_wire_dq   (sdram_dq   ),
+    .sdram_0_wire_dqm  (sdram_dqm  ),
+    .sdram_0_wire_ras_n(sdram_ras_n),
+    .sdram_0_wire_we_n (sdram_we_n ),
+    .pio_0_d_export    (seven_seg  ),
+
+
+    .gpu_0_vga_red(vga_red),
+    .gpu_0_vga_green(vga_green),
+    .gpu_0_vga_blue(vga_blue),
+    .gpu_0_vga_hs(vga_hs),
+    .gpu_0_vga_vs(vga_vs),
+    .gpu_0_vga_clk(clk),
+
+    .dm9000a_0_conduit_end_iOSC_50   (            ),
+    .dm9000a_0_conduit_end_ENET_DATA (dm9000_data ),
+    .dm9000a_0_conduit_end_ENET_CMD  (dm9000_cmd  ),
+    .dm9000a_0_conduit_end_ENET_RD_N (dm9000_rd_n ),
+    .dm9000a_0_conduit_end_ENET_WR_N (dm9000_wr_n ),
+    .dm9000a_0_conduit_end_ENET_CS_N (dm9000_cs_n ),
+    .dm9000a_0_conduit_end_ENET_RST_N(dm9000_rst_n),
+    .dm9000a_0_conduit_end_ENET_INT  (dm9000_int  ),
+    .dm9000a_0_conduit_end_ENET_CLK  (            )
+);
+
+
+
+
+endmodule
diff --git a/software/Makefile b/software/Makefile
index 13116c7..ffbafea 100644
--- a/software/Makefile
+++ b/software/Makefile
@@ -28,13 +28,13 @@ elf.flash: ${ELFDIR}/${ELF} sof.flash
 	
 
 
-load_elf.stamp:load_sof.stamp ${ELFDIR}/${ELF}
+load_elf.stamp:${ELFDIR}/${ELF} load_sof.stamp
 	./wrap.sh nios2-download  ${ELFDIR}/${ELF} -g
 
 load_sof.stamp: ${SOF}
 	./wrap.sh quartus_pgm -m JTAG -o 'p;../pong3.sof'
 
-${ELFDIR}/${ELF}: ${BSPDIR}/libhal_bsp.a
+${ELFDIR}/${ELF}: ${BSPDIR}/libhal_bsp.a $(wildcard ${ELFDIR}/*.[chHC])
 	./wrap.sh ${MAKE} -C ${ELFDIR}
 
 
diff --git a/software/pong3/GPU.h b/software/pong3/GPU.h
new file mode 100644
index 0000000..3883381
--- /dev/null
+++ b/software/pong3/GPU.h
@@ -0,0 +1,29 @@
+/*
+ * GPU.h
+ *
+ *  Created on: Oct 11, 2013
+ *      Author: root
+ */
+
+#ifndef GPU_H_
+#define GPU_H_
+
+#define GPU_OFFSET		0x80
+#if 0
+#define GPU_WIDTH 		640
+#define GPU_HEIGHT		480
+#else
+#define GPU_WIDTH 		800
+#define GPU_HEIGHT		600
+#endif
+
+#define GPU_REG_BLANK		0x0
+#define GPU_REG_SPRITE_X	0x1
+#define GPU_REG_SPRITE_Y	0x2
+#define GPU_REG_BAT0_Y		0x3
+#define GPU_REG_BAT1_Y		0x4
+#define GPU_REG_SPRITE_COLOUR	0x5
+#define GPU_REG_SPRITE_BASE	0x10
+ 
+
+#endif /* GPU_H_ */
diff --git a/software/pong3/pong3.c b/software/pong3/pong3.c
index 0e88ac8..39ee99c 100644
--- a/software/pong3/pong3.c
+++ b/software/pong3/pong3.c
@@ -3,10 +3,14 @@
 #include <unistd.h>
 #include <stdlib.h>
 #include <string.h>
+#include <stdint.h>
 #include "system.h"
 
+#include "GPU.h"
+
 #define msleep(msec) usleep(1000*msec);
 
+ 
 static void
 gpu_write (unsigned int reg, unsigned int data)
 {
@@ -16,27 +20,17 @@ gpu_write (unsigned int reg, unsigned int data)
 static void
 load_sprite (void)
 {
+  const uint16_t sprite[16]={ 0x00C0, 0x03E0, 0x0FF8, 0x1FFE, 0x3FC7, 0x3F83, 0x3933, 0x3987, 0x3D37, 0x3D37, 0x3D87, 0x3FFF, 0x1FFE, 0x07F8, 0x01E0, 0x00C0 };
+  const unsigned int n=sizeof(sprite)/sizeof(uint16_t);
+  unsigned int i;
+
   //                      RRR GGG BBB
   // set the sprite color 111 010 000 - orange
-  gpu_write (5, 0x01D0);
+  gpu_write (GPU_REG_SPRITE_COLOUR, 0x01D0);
 
   // squirt the bromium logo into the sprite
-  gpu_write (0x10, 0x00C0);
-  gpu_write (0x11, 0x03E0);
-  gpu_write (0x12, 0x0FF8);
-  gpu_write (0x13, 0x1FFE);
-  gpu_write (0x14, 0x3FC7);
-  gpu_write (0x15, 0x3F83);
-  gpu_write (0x16, 0x3933);
-  gpu_write (0x17, 0x3987);
-  gpu_write (0x18, 0x3D37);
-  gpu_write (0x19, 0x3D37);
-  gpu_write (0x1a, 0x3D87);
-  gpu_write (0x1b, 0x3FFF);
-  gpu_write (0x1c, 0x1FFE);
-  gpu_write (0x1d, 0x07F8);
-  gpu_write (0x1e, 0x01E0);
-  gpu_write (0x1f, 0x00C0);
+  for (i=0;i<n;++i) 
+	  gpu_write (GPU_REG_SPRITE_BASE+i,sprite[i]);
 }
 
 
@@ -83,10 +77,10 @@ find_intersection (int x, int y, int xd, int yd, int t)
       x += xd;
       y += yd;
 
-      if (squish (&y, 0, 480))
+      if (squish (&y, 0, GPU_HEIGHT))
         yd = -yd;
 
-      if (squish (&x, 0, 640))
+      if (squish (&x, 0, GPU_WIDTH))
         xd = -xd;
     }
 
@@ -118,7 +112,7 @@ main (void)
       yd = 1;
 
       dbat0 = find_intersection (x + xd, y + yd, xd, yd, 0);
-      dbat1 = find_intersection (x + xd, y + yd, xd, yd, 639);
+      dbat1 = find_intersection (x + xd, y + yd, xd, yd, GPU_WIDTH-1);
 
       while (!missed)
         {
@@ -126,10 +120,10 @@ main (void)
           y += yd;
 
 
-          if (squish (&y, 0, 480))
+          if (squish (&y, 0, GPU_HEIGHT))
             yd = -yd;
 
-          if (squish (&x, 0, 640))
+          if (squish (&x, 0, GPU_WIDTH))
             {
               xd = (rand () % 3) + 1;
               if (x)
@@ -140,13 +134,13 @@ main (void)
               if (x)
                 {
                   dbat0 = find_intersection (x + xd, y + yd, xd, yd, 0);
-                  dbat1 = 480 / 2;
+                  dbat1 = GPU_HEIGHT / 2;
                 }
               else
                 {
-                  dbat0 = 480 / 2;
+                  dbat0 = GPU_HEIGHT / 2;
 
-                  dbat1 = find_intersection (x + xd, y + yd, xd, yd, 639);
+                  dbat1 = find_intersection (x + xd, y + yd, xd, yd, GPU_WIDTH-1);
                 }
             }
 
@@ -154,10 +148,10 @@ main (void)
           move_bat (&bat1, dbat1);
 
 
-          gpu_write (1, x + 0x80);
-          gpu_write (2, y + 0x80);
-          gpu_write (3, bat0 + 0x80);
-          gpu_write (4, bat1 + 0x80);
+          gpu_write (1, x + GPU_OFFSET);
+          gpu_write (2, y + GPU_OFFSET);
+          gpu_write (3, bat0 + GPU_OFFSET);
+          gpu_write (4, bat1 + GPU_OFFSET);
 
           gpu_write (0, 0);
 
diff --git a/software/pong3_bsp/settings.bsp b/software/pong3_bsp/settings.bsp
index 6bafac0..acec6f1 100644
--- a/software/pong3_bsp/settings.bsp
+++ b/software/pong3_bsp/settings.bsp
@@ -2,8 +2,8 @@
 <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
         <BspType>hal</BspType>
         <BspVersion>default</BspVersion>
-        <BspGeneratedTimeStamp>Oct 10, 2013 11:06:28 PM</BspGeneratedTimeStamp>
-        <BspGeneratedUnixTimeStamp>1381442788161</BspGeneratedUnixTimeStamp>
+        <BspGeneratedTimeStamp>Oct 11, 2013 9:35:07 AM</BspGeneratedTimeStamp>
+        <BspGeneratedUnixTimeStamp>1381480507860</BspGeneratedUnixTimeStamp>
         <BspGeneratedLocation>/home/root/projects/altera/pong3/software/pong3_bsp</BspGeneratedLocation>
         <BspSettingsFile>./settings.bsp</BspSettingsFile>
         <SopcDesignFile>../../my_sys.sopcinfo</SopcDesignFile>