1 files changed, 6 insertions, 7 deletions
diff --git a/quartus/mc6845.vhd b/quartus/mc6845.vhd
index 5abbbd2..31208ea 100644
--- a/quartus/mc6845.vhd
+++ b/quartus/mc6845.vhd
@@ -70,7 +70,6 @@ port (
 	);
 end entity;
 
--- altera message_off 10036
 architecture rtl of mc6845 is
 
 -- Host-accessible registers
@@ -232,7 +231,7 @@ begin
 	end process; -- registers
 	
 	-- Horizontal, vertical and address counters
-	process(CLOCK,nRESET,CLKEN)
+	process(CLOCK,nRESET)
 	variable ma_row_start : unsigned(13 downto 0);
 	variable max_scan_line : unsigned(4 downto 0);
 	begin
@@ -319,7 +318,7 @@ begin
 	
 	-- Signals to mark hsync and half way points for generating
 	-- vsync in even and odd fields
-	process(h_counter,r02_h_sync_pos)
+	process(h_counter)
 	begin
 		h_sync_start <= '0';
 		h_half_way <= '0';
@@ -333,7 +332,7 @@ begin
 	end process;
 	
 	-- Video timing and sync counters
-	process(CLOCK,nRESET,CLKEN)
+	process(CLOCK,nRESET)
 	begin
 		if nRESET = '0' then
 			-- H
@@ -400,7 +399,7 @@ begin
 	end process;
 	
 	-- Address generation
-	process(CLOCK,nRESET,CLKEN)
+	process(CLOCK,nRESET)
 	variable slv_line : std_logic_vector(4 downto 0);
 	begin
 		if nRESET = '0' then
@@ -424,7 +423,7 @@ begin
 	end process;
 	
 	-- Cursor control
-	process(CLOCK,nRESET,CLKEN)
+	process(CLOCK,nRESET)
 	variable cursor_line : std_logic;
 	begin	
 		-- Internal cursor enable signal delayed by 1 clock to line up
@@ -460,7 +459,7 @@ begin
 	end process;
 	
 	-- Light pen capture
-	process(CLOCK,nRESET,CLKEN)
+	process(CLOCK,nRESET)
 	begin
 		if nRESET = '0' then
 			lpstb_i <= '0';