with_line_doubler

1 files changed, 50 insertions, 5 deletions

diff --git a/quartus/bbc_micro_de1.vhd b/quartus/bbc_micro_de1.vhd
index e109c36..d78fe69 100644
--- a/quartus/bbc_micro_de1.vhd
+++ b/quartus/bbc_micro_de1.vhd
@@ -279,6 +279,30 @@ port (
 	);

 end component;

 

+

+component line_doubler is

+port (

+	CLOCK		:	in	std_logic;

+	-- Clock enable qualifies display cycles (interleaved with CPU cycles)

+	CLKEN		:	in	std_logic;

+	nRESET		:	in	std_logic;

+	

+	-- Video in (teletext mode)

+	R_IN		:	in	std_logic;

+	G_IN		:	in	std_logic;

+	B_IN		:	in	std_logic;

+	HS_IN		:	in	std_logic;

+	VS_IN		:	in	std_logic;

+	

+	-- Video out

+	R_OUT			:	out	std_logic;

+	G_OUT			:	out	std_logic;

+	B_OUT			:	out	std_logic;

+	HS_OUT			:	out	std_logic;

+	VS_OUT			:	out	std_logic

+	);

+end component;

+

 --------------------------------

 -- SAA5050 Teletext Generator

 --------------------------------

@@ -610,6 +634,13 @@ signal r_out			:	std_logic;
 signal g_out			:	std_logic;

 signal b_out			:	std_logic;

 

+-- line doubler signals

+signal ld_r_out		:	std_logic;

+signal ld_g_out		:	std_logic;

+signal ld_b_out		:	std_logic;

+signal ld_hsync		:	std_logic;

+signal ld_vsync		:	std_logic;

+

 -- SAA5050 signals

 signal ttxt_glr			:	std_logic;

 signal ttxt_dew			:	std_logic;

@@ -801,6 +832,16 @@ begin
 		r_out, g_out, b_out

 		);

 		

+   ld : line_doubler port map (

+		clock,

+		vid_clken,

+		reset_n,

+		r_out, g_out, b_out,

+		crtc_hsync,crtc_vsync,

+		ld_r_out,ld_g_out,ld_b_out,

+		ld_hsync, ld_vsync

+		);

+			

 	teletext : saa5050 port map (

 		CLOCK_24(0), -- This runs at 6 MHz, which we can't derive from the 32 MHz clock

 		ttxt_clken,

@@ -1182,12 +1223,16 @@ begin
 	ttxt_crs <= not crtc_ra(0);

 	ttxt_lose <= crtc_de;

 	

+	

+	-- line doubler

+	

+	

 	-- CRTC drives video out (CSYNC on HSYNC output, VSYNC high)

-	VGA_HS <= not (crtc_hsync xor crtc_vsync);

-	VGA_VS <= '1';

-	VGA_R <= r_out & r_out & r_out & r_out;

-	VGA_G <= g_out & g_out & g_out & g_out;

-	VGA_B <= b_out & b_out & b_out & b_out;

+	VGA_HS <= ld_hsync;

+	VGA_VS <= ld_vsync;

+	VGA_R <= (others => ld_r_out);

+	VGA_G <= (others => ld_g_out);

+	VGA_B <= (others => ld_b_out);

 	

 	-- Connections to System VIA

 	-- ADC