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+-- BBC Micro for Altera DE1
+--
+-- Copyright (c) 2009-2011 Mike Stirling
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- * Redistributions of source code must retain the above copyright notice,
+--   this list of conditions and the following disclaimer.
+--
+-- * Redistributions in synthesized form must reproduce the above copyright
+--   notice, this list of conditions and the following disclaimer in the
+--   documentation and/or other materials provided with the distribution.
+--
+-- * Neither the name of the author nor the names of other contributors may
+--   be used to endorse or promote products derived from this software without
+--   specific prior written agreement from the author.
+--
+-- * License is granted for non-commercial use only.  A fee may not be charged
+--   for redistributions as source code or in synthesized/hardware form without 
+--   specific prior written agreement from the author.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+-- Convert BCD to 7-segment display characters
+entity seg7 is
+port (
+	D			: in std_logic_vector(3 downto 0);
+	Q			: out std_logic_vector(6 downto 0)
+);
+end seg7;
+
+architecture seg7_arch of seg7 is
+begin
+	Q <=	"1000000" when D = "0000" else
+			"1111001" when D = "0001" else
+			"0100100" when D = "0010" else
+			"0110000" when D = "0011" else
+			"0011001" when D = "0100" else
+			"0010010" when D = "0101" else
+			"0000010" when D = "0110" else
+			"1111000" when D = "0111" else
+			"0000000" when D = "1000" else
+			"0010000" when D = "1001" else
+			"0001000" when D = "1010" else
+			"0000011" when D = "1011" else
+			"1000110" when D = "1100" else
+			"0100001" when D = "1101" else
+			"0000110" when D = "1110" else
+			"0001110";
+end seg7_arch;
+