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-rw-r--r--bbc_micro_de1.vhd179
1 files changed, 96 insertions, 83 deletions
diff --git a/bbc_micro_de1.vhd b/bbc_micro_de1.vhd
index e109c36..96ee44b 100644
--- a/bbc_micro_de1.vhd
+++ b/bbc_micro_de1.vhd
@@ -74,44 +74,44 @@ generic (
);
port (
-- Clocks
- CLOCK_24 : in std_logic_vector(1 downto 0);
- CLOCK_27 : in std_logic_vector(1 downto 0);
+-- CLOCK_24 : in std_logic_vector(1 downto 0);
+-- CLOCK_27 : in std_logic_vector(1 downto 0);
CLOCK_50 : in std_logic;
- EXT_CLOCK : in std_logic;
+-- EXT_CLOCK : in std_logic;
-- Switches
- SW : in std_logic_vector(9 downto 0);
+-- SW : in std_logic_vector(9 downto 0);
-- Buttons
- KEY : in std_logic_vector(3 downto 0);
+-- KEY : in std_logic_vector(3 downto 0);
-- 7 segment displays
HEX0 : out std_logic_vector(6 downto 0);
- HEX1 : out std_logic_vector(6 downto 0);
- HEX2 : out std_logic_vector(6 downto 0);
- HEX3 : out std_logic_vector(6 downto 0);
+-- HEX1 : out std_logic_vector(6 downto 0);
+-- HEX2 : out std_logic_vector(6 downto 0);
+-- HEX3 : out std_logic_vector(6 downto 0);
-- Red LEDs
- LEDR : out std_logic_vector(9 downto 0);
+-- LEDR : out std_logic_vector(9 downto 0);
-- Green LEDs
- LEDG : out std_logic_vector(7 downto 0);
+-- LEDG : out std_logic_vector(7 downto 0);
-- VGA
- VGA_R : out std_logic_vector(3 downto 0);
- VGA_G : out std_logic_vector(3 downto 0);
- VGA_B : out std_logic_vector(3 downto 0);
+ VGA_R : out std_logic_vector(2 downto 0);
+ VGA_G : out std_logic_vector(2 downto 0);
+ VGA_B : out std_logic_vector(2 downto 0);
VGA_HS : out std_logic;
VGA_VS : out std_logic;
-- Serial
- UART_RXD : in std_logic;
- UART_TXD : out std_logic;
+-- UART_RXD : in std_logic;
+-- UART_TXD : out std_logic;
-- PS/2 Keyboard
PS2_CLK : inout std_logic;
PS2_DAT : inout std_logic;
-- I2C
- I2C_SCLK : inout std_logic;
- I2C_SDAT : inout std_logic;
+-- I2C_SCLK : inout std_logic;
+-- I2C_SDAT : inout std_logic;
-- Audio
AUD_XCK : out std_logic;
@@ -129,23 +129,23 @@ port (
SRAM_WE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
-
- -- SDRAM
- DRAM_ADDR : out std_logic_vector(11 downto 0);
- DRAM_DQ : inout std_logic_vector(15 downto 0);
- DRAM_BA_0 : in std_logic;
- DRAM_BA_1 : in std_logic;
- DRAM_CAS_N : in std_logic;
- DRAM_CKE : in std_logic;
- DRAM_CLK : in std_logic;
- DRAM_CS_N : in std_logic;
- DRAM_LDQM : in std_logic;
- DRAM_RAS_N : in std_logic;
- DRAM_UDQM : in std_logic;
- DRAM_WE_N : in std_logic;
-
+--
+-- -- SDRAM
+-- DRAM_ADDR : out std_logic_vector(11 downto 0);
+-- DRAM_DQ : inout std_logic_vector(15 downto 0);
+-- DRAM_BA_0 : in std_logic;
+-- DRAM_BA_1 : in std_logic;
+-- DRAM_CAS_N : in std_logic;
+-- DRAM_CKE : in std_logic;
+-- DRAM_CLK : in std_logic;
+-- DRAM_CS_N : in std_logic;
+-- DRAM_LDQM : in std_logic;
+-- DRAM_RAS_N : in std_logic;
+-- DRAM_UDQM : in std_logic;
+-- DRAM_WE_N : in std_logic;
+--
-- Flash
- FL_ADDR : out std_logic_vector(21 downto 0);
+ FL_ADDR : out std_logic_vector(16 downto 0);
FL_DQ : inout std_logic_vector(7 downto 0);
FL_RST_N : out std_logic;
FL_OE_N : out std_logic;
@@ -156,11 +156,11 @@ port (
SD_nCS : out std_logic;
SD_MOSI : out std_logic;
SD_SCLK : out std_logic;
- SD_MISO : in std_logic;
+ SD_MISO : in std_logic
-- GPIO
- GPIO_0 : inout std_logic_vector(35 downto 0);
- GPIO_1 : inout std_logic_vector(35 downto 0)
+-- GPIO_0 : inout std_logic_vector(35 downto 0);
+-- GPIO_1 : inout std_logic_vector(35 downto 0)
);
end entity;
@@ -560,6 +560,7 @@ signal mhz1_clken : std_logic; -- 1 MHz bus and associated peripherals, 6522 ph
-- SAA5050 needs a 6 MHz clock enable relative to a 24 MHz clock
signal ttxt_clken_counter : unsigned(1 downto 0);
signal ttxt_clken : std_logic;
+signal CLOCK_24 : std_logic;
-- Debugger connections
signal debug_irq_in_n : std_logic;
@@ -720,35 +721,35 @@ begin
-- 32 MHz master clock
pll: pll32 port map (
pll_reset,
- CLOCK_24(0),
+ CLOCK_24,
clock,
pll_locked );
-
- -- Hardware debugger block (single-step, breakpoints)
- debug: debugger port map (
- clock,
- hard_reset_n,
- cpu_clken,
- cpu_debug_clken,
- debug_irq_in_n,
- cpu_irq_n,
- cpu_a(15 downto 0), cpu_r_nw, cpu_sync,
- debug_aux,
- SW(8), -- RUN
- KEY(3), -- STEP
- KEY(2), -- MODE
- KEY(1), -- DIGIT
- KEY(0), -- SET
- HEX3, HEX2, HEX1, HEX0,
- LEDR(3), -- BREAKPOINT
- LEDR(2) -- WATCHPOINT
- );
-
+--
+-- -- Hardware debugger block (single-step, breakpoints)
+-- debug: debugger port map (
+-- clock,
+-- hard_reset_n,
+-- cpu_clken,
+-- cpu_debug_clken,
+-- debug_irq_in_n,
+-- cpu_irq_n,
+-- cpu_a(15 downto 0), cpu_r_nw, cpu_sync,
+-- debug_aux,
+-- SW(8), -- RUN
+-- KEY(3), -- STEP
+-- KEY(2), -- MODE
+-- KEY(1), -- DIGIT
+-- KEY(0), -- SET
+-- HEX3, HEX2, HEX1, HEX0,
+-- LEDR(3), -- BREAKPOINT
+-- LEDR(2) -- WATCHPOINT
+-- );
+--
-- 6502 CPU
cpu : T65 port map (
cpu_mode,
reset_n,
- cpu_debug_clken,
+ cpu_clken,
clock,
cpu_ready,
cpu_abort_n,
@@ -802,7 +803,7 @@ begin
);
teletext : saa5050 port map (
- CLOCK_24(0), -- This runs at 6 MHz, which we can't derive from the 32 MHz clock
+ CLOCK_50, -- This runs at 6 MHz, which we can't derive from the 32 MHz clock
ttxt_clken,
reset_n,
clock, -- Data input is synchronised from the bus clock domain
@@ -889,7 +890,8 @@ begin
keyb_out,
keyb_int,
keyb_break,
- SW(7 downto 0)
+ "00000000"
+-- SW(7 downto 0)
);
-- Sound generator (and drive logic for I2S codec)
@@ -900,27 +902,28 @@ begin
sound_ao
);
i2s : i2s_intf port map (
- CLOCK_24(0), reset_n,
+ CLOCK_24, reset_n,
pcm_inl, pcm_inr,
std_logic_vector(sound_ao) & "00000000",
std_logic_vector(sound_ao) & "00000000",
AUD_XCK, AUD_DACLRCK,
AUD_BCLK, AUD_DACDAT, AUD_ADCDAT
);
- i2c : i2c_loader
- generic map (
- log2_divider => 7
- )
- port map (
- clock, reset_n,
- I2C_SCLK, I2C_SDAT,
- LEDR(5), -- IS_DONE
- LEDR(4) -- IS_ERROR
- );
+-- i2c : i2c_loader
+-- generic map (
+-- log2_divider => 7
+-- )
+-- port map (
+-- clock, reset_n,
+-- I2C_SCLK, I2C_SDAT,
+-- LEDR(5), -- IS_DONE
+-- LEDR(4) -- IS_ERROR
+-- );
-- Asynchronous reset
-- PLL is reset by external reset switch
- pll_reset <= not SW(9);
+-- pll_reset <= not SW(9);
+ pll_reset <= '1';
-- Keyboard and System VIA are reset by external reset switch or PLL being out of lock
hard_reset_n <= not (pll_reset or not pll_locked);
-- Rest of system is reset by all of the above plus the keyboard BREAK key
@@ -937,6 +940,16 @@ begin
cpu_cycle <= not (clken_counter(0) or clken_counter(1) or clken_counter(2) or clken_counter(3)); -- 0/16
cpu_clken <= cpu_cycle and not cpu_cycle_mask;
+ clock_gen_24: process(CLOCK_50,reset_n)
+ begin
+ if reset_n = '0' then
+ CLOCK_24 <= '0';
+ elsif rising_edge(CLOCK_50) then
+ CLOCK_24 <= not CLOCK_24;
+ end if;
+ end process;
+
+
clk_gen: process(clock,reset_n)
begin
if reset_n = '0' then
@@ -964,11 +977,11 @@ begin
end if;
end process;
- ttxt_clk_gen: process(CLOCK_24(0),reset_n)
+ ttxt_clk_gen: process(CLOCK_50,reset_n)
begin
if reset_n = '0' then
ttxt_clken_counter <= (others => '0');
- elsif rising_edge(CLOCK_24(0)) then
+ elsif rising_edge(CLOCK_24) then
ttxt_clken_counter <= ttxt_clken_counter + 1;
end if;
end process;
@@ -1090,7 +1103,7 @@ begin
FL_CE_N <= '0';
FL_OE_N <= '0';
FL_WE_N <= '1';
- FL_ADDR(21 downto 17) <= ROM_OFFSET(7 downto 3);
+-- FL_ADDR(21 downto 17) <= ROM_OFFSET(7 downto 3);
FL_ADDR(16 downto 14) <=
"111" when mos_enable = '1' else
"0" & romsel(1 downto 0);
@@ -1185,9 +1198,9 @@ begin
-- CRTC drives video out (CSYNC on HSYNC output, VSYNC high)
VGA_HS <= not (crtc_hsync xor crtc_vsync);
VGA_VS <= '1';
- VGA_R <= r_out & r_out & r_out & r_out;
- VGA_G <= g_out & g_out & g_out & g_out;
- VGA_B <= b_out & b_out & b_out & b_out;
+ VGA_R <= r_out & r_out & r_out;
+ VGA_G <= g_out & g_out & g_out;
+ VGA_B <= b_out & b_out & b_out;
-- Connections to System VIA
-- ADC
@@ -1252,14 +1265,14 @@ begin
end process;
-- Keyboard LEDs
- LEDR(0) <= not caps_lock_led_n;
- LEDR(1) <= not shift_lock_led_n;
+-- LEDR(0) <= not caps_lock_led_n;
+-- LEDR(1) <= not shift_lock_led_n;
-----------------
-- DEBUG STUFF
-----------------
- GPIO_0(0) <= not (crtc_hsync xor crtc_vsync);
- GPIO_0(1) <= crtc_de;
+-- GPIO_0(0) <= not (crtc_hsync xor crtc_vsync);
+-- GPIO_0(1) <= crtc_de;
end architecture;