From 3f2546b2ef55b661fd8dd69682b38992225e86f6 Mon Sep 17 00:00:00 2001 From: fishsoupisgood Date: Mon, 29 Apr 2019 01:17:54 +0100 Subject: Initial import of qemu-2.4.1 --- roms/u-boot/doc/README.bus_vcxk | 68 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 roms/u-boot/doc/README.bus_vcxk (limited to 'roms/u-boot/doc/README.bus_vcxk') diff --git a/roms/u-boot/doc/README.bus_vcxk b/roms/u-boot/doc/README.bus_vcxk new file mode 100644 index 00000000..5bd3c652 --- /dev/null +++ b/roms/u-boot/doc/README.bus_vcxk @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2008-2009 + * BuS Elektronik GmbH & Co. KG + * Jens Scharsig + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +U-Boot vcxk video controller driver +====================================== + +By defining CONFIG_VIDEO_VCXK this driver can be used with VC2K, VC4K and +VC8K devices on following boards: + +board | ARCH | Vendor +----------------------------------------------------------------------- +EB+CPU5282-T1 | MCF5282 | BuS Elektronik GmbH & Co. KG +EB+MCF-EVB123 | MCF5282 | BuS Elektronik GmbH & Co. KG +EB+CPUx9K2 | AT91RM9200 | BuS Elektronik GmbH & Co. KG +ZLSA | AT91RM9200 | Ruf Telematik AG + +Driver configuration +-------------------- + +The driver needs some defines to describe the target hardware: + +CONFIG_SYS_VCXK_BASE + + base address of VCxK hardware memory + +CONFIG_SYS_VCXK_DEFAULT_LINEALIGN + + defines the physical alignment of a pixel row + +CONFIG_SYS_VCXK_DOUBLEBUFFERED + + some boards that use vcxk prevent read from framebuffer memory. + define this option to enable double buffering (needs 16KiB RAM) + +CONFIG_SYS_VCXK__PIN + + defines the number of the I/O line PIN in the port + valid values for are: + + ACKNOWLEDGE + describes the acknowledge line from vcxk hardware + + ENABLE + describes the enable line to vcxk hardware + + INVERT + describes the invert line to vcxk hardware + + RESET + describes the reset line to vcxk hardware + + REQUEST + describes the request line to vcxk hardware + +CONFIG_SYS_VCXK__PORT + + defines the I/O port which is connected with the line + for valid values for see CONFIG_SYS_VCXK__PIN + +CONFIG_SYS_VCXK__DDR + + defines the register which configures the direction + for valid values for see CONFIG_SYS_VCXK__PIN -- cgit v1.2.3