From 3f2546b2ef55b661fd8dd69682b38992225e86f6 Mon Sep 17 00:00:00 2001 From: fishsoupisgood Date: Mon, 29 Apr 2019 01:17:54 +0100 Subject: Initial import of qemu-2.4.1 --- roms/u-boot/board/esd/cpciiser4/Makefile | 8 + roms/u-boot/board/esd/cpciiser4/cpciiser4.c | 165 ++ roms/u-boot/board/esd/cpciiser4/cpciiser4.h | 28 + roms/u-boot/board/esd/cpciiser4/flash.c | 68 + roms/u-boot/board/esd/cpciiser4/fpgadata.c | 4136 +++++++++++++++++++++++++++ 5 files changed, 4405 insertions(+) create mode 100644 roms/u-boot/board/esd/cpciiser4/Makefile create mode 100644 roms/u-boot/board/esd/cpciiser4/cpciiser4.c create mode 100644 roms/u-boot/board/esd/cpciiser4/cpciiser4.h create mode 100644 roms/u-boot/board/esd/cpciiser4/flash.c create mode 100644 roms/u-boot/board/esd/cpciiser4/fpgadata.c (limited to 'roms/u-boot/board/esd/cpciiser4') diff --git a/roms/u-boot/board/esd/cpciiser4/Makefile b/roms/u-boot/board/esd/cpciiser4/Makefile new file mode 100644 index 00000000..b8d6bea6 --- /dev/null +++ b/roms/u-boot/board/esd/cpciiser4/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = cpciiser4.o flash.o ../common/misc.o diff --git a/roms/u-boot/board/esd/cpciiser4/cpciiser4.c b/roms/u-boot/board/esd/cpciiser4/cpciiser4.c new file mode 100644 index 00000000..e61cd5b1 --- /dev/null +++ b/roms/u-boot/board/esd/cpciiser4/cpciiser4.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2000 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "cpciiser4.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern void lxt971_no_sleep(void); + + +/* ------------------------------------------------------------------------- */ + +#if 0 +#define FPGA_DEBUG +#endif + +#if 0 +#define FPGA_DEBUG2 +#endif + +/* fpga configuration data - generated by bin2cc */ +const unsigned char fpgadata[] = { +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +int board_early_init_f (void) +{ + int index, len, i; + int status; + +#ifdef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + + /* + * Boot onboard FPGA + */ + status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); + if (status != 0) { + /* booting FPGA failed */ +#ifndef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + printf ("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf ("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("FPGA: %s\n", &(fpgadata[index + 1])); + index += len + 3; + } + putc ('\n'); + /* delayed reboot */ + for (i = 20; i > 0; i--) { + printf ("Rebooting in %2d seconds \r", i); + for (index = 0; index < 1000; index++) + udelay (1000); + } + putc ('\n'); + do_reset (NULL, 0, 0, NULL); + } + + /* + * Init FPGA via RESET (read access on CS3) + */ + in_8((void *)0xf0200000); + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive + * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + /* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + int index; + int len; + char str[64]; + int i = getenv_f("serial#", str, sizeof (str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming AR405"); + } else { + puts(str); + } + + puts ("\nFPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("%s ", &(fpgadata[index + 1])); + index += len + 3; + } + + putc ('\n'); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return 0; +} diff --git a/roms/u-boot/board/esd/cpciiser4/cpciiser4.h b/roms/u-boot/board/esd/cpciiser4/cpciiser4.h new file mode 100644 index 00000000..75e7950b --- /dev/null +++ b/roms/u-boot/board/esd/cpciiser4/cpciiser4.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/**************************************************************************** + * FLASH Memory Map as used by TQ Monitor: + * + * Start Address Length + * +-----------------------+ 0x4000_0000 Start of Flash ----------------- + * | MON8xx code | 0x4000_0100 Reset Vector + * +-----------------------+ 0x400?_???? + * | (unused) | + * +-----------------------+ 0x4001_FF00 + * | Ethernet Addresses | 0x78 + * +-----------------------+ 0x4001_FF78 + * | (Reserved for MON8xx) | 0x44 + * +-----------------------+ 0x4001_FFBC + * | Lock Address | 0x04 + * +-----------------------+ 0x4001_FFC0 ^ + * | Hardware Information | 0x40 | MON8xx + * +=======================+ 0x4002_0000 (sector border) ----------------- + * | Autostart Header | | Applications + * | ... | v + * + *****************************************************************************/ diff --git a/roms/u-boot/board/esd/cpciiser4/flash.c b/roms/u-boot/board/esd/cpciiser4/flash.c new file mode 100644 index 00000000..34bdc053 --- /dev/null +++ b/roms/u-boot/board/esd/cpciiser4/flash.c @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + + /* Init: no FLASHes known */ + for (i=0; i