From b8de35658ffd78ad8b22f91ccbbd3d63663afda9 Mon Sep 17 00:00:00 2001 From: Alexsander Akers Date: Tue, 25 Jan 2022 15:03:22 -0500 Subject: Sensor Watch Simulator (#35) * Put something on screen * Use the 32bit watch_date_time repr to pass from JS * Implement periodic callbacks * Clear display on enabling * Hook up watch_set_led_color() to SVG (green-only) * Make debug output full-width * Remove default Emscripten canvas * Implement sleep and button clicks * Fix time zone conversion bug in beats-time app * Clean up warnings * Fix pin levels * Set time zone to browser value (if available) * Add basic backup data saving * Silence format specifier warnings in both targets * Remove unnecessary, copied files * Use RTC pointer to clear callbacks (if available) * Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES * Change each face to const preprocessor definition * Remove Intl.DateTimeFormat usage * Update shell.html title, header * Add touch start/end event handlers on SVG buttons * Update shell.html * Update folder structure (shared, simulator, hardware under watch-library) * Tease out shared components from watch_slcd * Clean up simulator watch_slcd.c inline JS calls * Fix missing newlines at end of file * Add simulator warnings (except format, unused-paremter) * Implement remaining watch_rtc functions * Fix button bug on mouse down then drag out * Implement remaining watch_slcd functions * Link keyboard events to buttons (for keys A, L, M) * Rewrite event handling (mouse, touch, keyboard) in C * Set explicit text UTF-8 charset in shell.html * Address PR comments * Remove unused directories from include paths --- apps/beats-time/app.c | 4 +- make.mk | 193 +- movement/README.md | 28 +- movement/lib/TOTP-MCU/TOTP.c | 2 +- movement/lib/TOTP-MCU/sha1.c | 8 +- movement/movement.c | 27 +- movement/watch_faces/clock/simple_clock_face.h | 14 +- movement/watch_faces/clock/world_clock_face.h | 14 +- movement/watch_faces/complications/beats_face.c | 4 +- movement/watch_faces/complications/beats_face.h | 14 +- movement/watch_faces/complications/blinky_face.h | 16 +- .../watch_faces/complications/countdown_face.h | 14 +- movement/watch_faces/complications/day_one_face.c | 2 +- movement/watch_faces/complications/day_one_face.h | 14 +- .../watch_faces/complications/pulsometer_face.h | 16 +- .../watch_faces/complications/stopwatch_face.h | 16 +- .../complications/sunrise_sunset_face.h | 14 +- movement/watch_faces/complications/totp_face.h | 14 +- movement/watch_faces/demos/character_set_face.h | 16 +- movement/watch_faces/demos/demo_face.h | 16 +- movement/watch_faces/demos/hello_there_face.h | 14 +- movement/watch_faces/demos/lis2dh_logging_face.c | 18 +- movement/watch_faces/demos/lis2dh_logging_face.h | 14 +- movement/watch_faces/demos/voltage_face.c | 2 +- movement/watch_faces/demos/voltage_face.h | 16 +- movement/watch_faces/settings/preferences_face.h | 16 +- movement/watch_faces/settings/set_time_face.h | 14 +- .../thermistor/thermistor_logging_face.h | 14 +- .../thermistor/thermistor_readout_face.h | 14 +- rules.mk | 10 + watch-library/config/RTE_Components.h | 54 - watch-library/config/hpl_dmac_config.h | 3122 ------- watch-library/config/hpl_eic_config.h | 736 -- watch-library/config/hpl_gclk_config.h | 388 - watch-library/config/hpl_mclk_config.h | 85 - watch-library/config/hpl_nvmctrl_config.h | 38 - watch-library/config/hpl_osc32kctrl_config.h | 177 - watch-library/config/hpl_oscctrl_config.h | 483 - watch-library/config/hpl_port_config.h | 284 - watch-library/config/hpl_rtc_config.h | 318 - watch-library/config/hpl_sercom_config.h | 303 - watch-library/config/hpl_slcd_config.h | 239 - watch-library/config/hpl_systick_config.h | 18 - watch-library/config/hpl_trng_config.h | 27 - watch-library/config/nv_storage_config.h | 51 - watch-library/config/peripheral_clk_config.h | 266 - watch-library/driver/lis2dh.c | 143 - watch-library/driver/lis2dh.h | 222 - watch-library/driver/lis2dw.c | 139 - watch-library/driver/lis2dw.h | 265 - watch-library/hal/documentation/ext_irq.rst | 39 - watch-library/hal/documentation/flash.rst | 52 - .../hal/documentation/i2c_master_sync.rst | 87 - watch-library/hal/documentation/rand_sync.rst | 43 - watch-library/hal/documentation/slcd_sync.rst | 82 - .../hal/documentation/spi_master_sync.rst | 51 - watch-library/hal/documentation/usart_sync.rst | 58 - watch-library/hal/include/hal_atomic.h | 120 - watch-library/hal/include/hal_calendar.h | 0 watch-library/hal/include/hal_delay.h | 89 - watch-library/hal/include/hal_ext_irq.h | 118 - watch-library/hal/include/hal_flash.h | 209 - watch-library/hal/include/hal_gpio.h | 201 - watch-library/hal/include/hal_i2c_m_sync.h | 244 - watch-library/hal/include/hal_init.h | 72 - watch-library/hal/include/hal_io.h | 110 - watch-library/hal/include/hal_rand_sync.h | 134 - watch-library/hal/include/hal_slcd_sync.h | 168 - watch-library/hal/include/hal_sleep.h | 74 - watch-library/hal/include/hal_spi_m_sync.h | 221 - watch-library/hal/include/hal_usart_sync.h | 247 - watch-library/hal/include/hpl_calendar.h | 75 - watch-library/hal/include/hpl_core.h | 56 - watch-library/hal/include/hpl_delay.h | 97 - watch-library/hal/include/hpl_dma.h | 176 - watch-library/hal/include/hpl_ext_irq.h | 95 - watch-library/hal/include/hpl_flash.h | 265 - watch-library/hal/include/hpl_gpio.h | 185 - watch-library/hal/include/hpl_i2c_m_async.h | 205 - watch-library/hal/include/hpl_i2c_m_sync.h | 185 - watch-library/hal/include/hpl_i2c_s_async.h | 184 - watch-library/hal/include/hpl_i2c_s_sync.h | 184 - watch-library/hal/include/hpl_init.h | 124 - watch-library/hal/include/hpl_irq.h | 116 - watch-library/hal/include/hpl_missing_features.h | 37 - watch-library/hal/include/hpl_rand_sync.h | 99 - watch-library/hal/include/hpl_reset.h | 92 - watch-library/hal/include/hpl_slcd.h | 49 - watch-library/hal/include/hpl_slcd_sync.h | 154 - watch-library/hal/include/hpl_sleep.h | 88 - watch-library/hal/include/hpl_spi.h | 163 - watch-library/hal/include/hpl_spi_async.h | 131 - watch-library/hal/include/hpl_spi_dma.h | 88 - watch-library/hal/include/hpl_spi_m_async.h | 243 - watch-library/hal/include/hpl_spi_m_dma.h | 182 - watch-library/hal/include/hpl_spi_m_sync.h | 166 - watch-library/hal/include/hpl_spi_s_async.h | 232 - watch-library/hal/include/hpl_spi_s_sync.h | 232 - watch-library/hal/include/hpl_spi_sync.h | 70 - watch-library/hal/include/hpl_time_measure.h | 94 - watch-library/hal/include/hpl_timer.h | 160 - watch-library/hal/include/hpl_usart.h | 113 - watch-library/hal/include/hpl_usart_async.h | 270 - watch-library/hal/include/hpl_usart_sync.h | 254 - watch-library/hal/include/hpl_user_area.h | 123 - watch-library/hal/src/hal_atomic.c | 66 - watch-library/hal/src/hal_calendar.c | 0 watch-library/hal/src/hal_delay.c | 80 - watch-library/hal/src/hal_ext_irq.c | 188 - watch-library/hal/src/hal_flash.c | 314 - watch-library/hal/src/hal_gpio.c | 44 - watch-library/hal/src/hal_i2c_m_sync.c | 258 - watch-library/hal/src/hal_init.c | 47 - watch-library/hal/src/hal_io.c | 58 - watch-library/hal/src/hal_rand_sync.c | 122 - watch-library/hal/src/hal_slcd_sync.c | 150 - watch-library/hal/src/hal_sleep.c | 73 - watch-library/hal/src/hal_spi_m_sync.c | 201 - watch-library/hal/src/hal_usart_sync.c | 276 - watch-library/hal/utils/include/compiler.h | 64 - watch-library/hal/utils/include/err_codes.h | 73 - watch-library/hal/utils/include/events.h | 54 - watch-library/hal/utils/include/parts.h | 41 - watch-library/hal/utils/include/utils.h | 368 - watch-library/hal/utils/include/utils_assert.h | 93 - .../hal/utils/include/utils_decrement_macro.h | 309 - watch-library/hal/utils/include/utils_event.h | 115 - .../hal/utils/include/utils_increment_macro.h | 308 - watch-library/hal/utils/include/utils_list.h | 164 - .../hal/utils/include/utils_recursion_macro.h | 69 - .../hal/utils/include/utils_repeat_macro.h | 322 - watch-library/hal/utils/src/utils_assert.c | 46 - watch-library/hal/utils/src/utils_event.c | 125 - watch-library/hal/utils/src/utils_list.c | 136 - watch-library/hal/utils/src/utils_syscalls.c | 152 - .../hardware/hal/documentation/ext_irq.rst | 39 + watch-library/hardware/hal/documentation/flash.rst | 52 + .../hardware/hal/documentation/i2c_master_sync.rst | 87 + .../hardware/hal/documentation/rand_sync.rst | 43 + .../hardware/hal/documentation/slcd_sync.rst | 82 + .../hardware/hal/documentation/spi_master_sync.rst | 51 + .../hardware/hal/documentation/usart_sync.rst | 58 + watch-library/hardware/hal/include/hal_atomic.h | 120 + watch-library/hardware/hal/include/hal_calendar.h | 0 watch-library/hardware/hal/include/hal_delay.h | 89 + watch-library/hardware/hal/include/hal_ext_irq.h | 118 + watch-library/hardware/hal/include/hal_flash.h | 209 + watch-library/hardware/hal/include/hal_gpio.h | 201 + .../hardware/hal/include/hal_i2c_m_sync.h | 244 + watch-library/hardware/hal/include/hal_init.h | 72 + watch-library/hardware/hal/include/hal_io.h | 110 + watch-library/hardware/hal/include/hal_rand_sync.h | 134 + watch-library/hardware/hal/include/hal_slcd_sync.h | 168 + watch-library/hardware/hal/include/hal_sleep.h | 74 + .../hardware/hal/include/hal_spi_m_sync.h | 221 + .../hardware/hal/include/hal_usart_sync.h | 247 + watch-library/hardware/hal/include/hpl_calendar.h | 75 + watch-library/hardware/hal/include/hpl_core.h | 56 + watch-library/hardware/hal/include/hpl_delay.h | 97 + watch-library/hardware/hal/include/hpl_dma.h | 176 + watch-library/hardware/hal/include/hpl_ext_irq.h | 95 + watch-library/hardware/hal/include/hpl_flash.h | 265 + watch-library/hardware/hal/include/hpl_gpio.h | 185 + .../hardware/hal/include/hpl_i2c_m_async.h | 205 + .../hardware/hal/include/hpl_i2c_m_sync.h | 185 + .../hardware/hal/include/hpl_i2c_s_async.h | 184 + .../hardware/hal/include/hpl_i2c_s_sync.h | 184 + watch-library/hardware/hal/include/hpl_init.h | 124 + watch-library/hardware/hal/include/hpl_irq.h | 116 + .../hardware/hal/include/hpl_missing_features.h | 37 + watch-library/hardware/hal/include/hpl_rand_sync.h | 99 + watch-library/hardware/hal/include/hpl_reset.h | 92 + watch-library/hardware/hal/include/hpl_slcd.h | 49 + watch-library/hardware/hal/include/hpl_slcd_sync.h | 154 + watch-library/hardware/hal/include/hpl_sleep.h | 88 + watch-library/hardware/hal/include/hpl_spi.h | 163 + watch-library/hardware/hal/include/hpl_spi_async.h | 131 + watch-library/hardware/hal/include/hpl_spi_dma.h | 88 + .../hardware/hal/include/hpl_spi_m_async.h | 243 + watch-library/hardware/hal/include/hpl_spi_m_dma.h | 182 + .../hardware/hal/include/hpl_spi_m_sync.h | 166 + .../hardware/hal/include/hpl_spi_s_async.h | 232 + .../hardware/hal/include/hpl_spi_s_sync.h | 232 + watch-library/hardware/hal/include/hpl_spi_sync.h | 70 + .../hardware/hal/include/hpl_time_measure.h | 94 + watch-library/hardware/hal/include/hpl_timer.h | 160 + watch-library/hardware/hal/include/hpl_usart.h | 113 + .../hardware/hal/include/hpl_usart_async.h | 270 + .../hardware/hal/include/hpl_usart_sync.h | 254 + watch-library/hardware/hal/include/hpl_user_area.h | 123 + watch-library/hardware/hal/src/hal_atomic.c | 66 + watch-library/hardware/hal/src/hal_calendar.c | 0 watch-library/hardware/hal/src/hal_delay.c | 80 + watch-library/hardware/hal/src/hal_ext_irq.c | 188 + watch-library/hardware/hal/src/hal_flash.c | 314 + watch-library/hardware/hal/src/hal_gpio.c | 44 + watch-library/hardware/hal/src/hal_i2c_m_sync.c | 258 + watch-library/hardware/hal/src/hal_init.c | 47 + watch-library/hardware/hal/src/hal_io.c | 58 + watch-library/hardware/hal/src/hal_rand_sync.c | 122 + watch-library/hardware/hal/src/hal_slcd_sync.c | 150 + watch-library/hardware/hal/src/hal_sleep.c | 73 + watch-library/hardware/hal/src/hal_spi_m_sync.c | 201 + watch-library/hardware/hal/src/hal_usart_sync.c | 276 + .../hardware/hal/utils/include/compiler.h | 66 + .../hardware/hal/utils/include/err_codes.h | 73 + watch-library/hardware/hal/utils/include/events.h | 54 + watch-library/hardware/hal/utils/include/parts.h | 41 + watch-library/hardware/hal/utils/include/utils.h | 368 + .../hardware/hal/utils/include/utils_assert.h | 93 + .../hal/utils/include/utils_decrement_macro.h | 309 + .../hardware/hal/utils/include/utils_event.h | 115 + .../hal/utils/include/utils_increment_macro.h | 308 + .../hardware/hal/utils/include/utils_list.h | 164 + .../hal/utils/include/utils_recursion_macro.h | 69 + .../hal/utils/include/utils_repeat_macro.h | 322 + .../hardware/hal/utils/src/utils_assert.c | 46 + watch-library/hardware/hal/utils/src/utils_event.c | 125 + watch-library/hardware/hal/utils/src/utils_list.c | 136 + .../hardware/hal/utils/src/utils_syscalls.c | 152 + .../hardware/hpl/core/hpl_core_m0plus_base.c | 202 + watch-library/hardware/hpl/core/hpl_core_port.h | 63 + watch-library/hardware/hpl/core/hpl_init.c | 74 + watch-library/hardware/hpl/dmac/hpl_dmac.c | 244 + watch-library/hardware/hpl/eic/hpl_eic.c | 255 + watch-library/hardware/hpl/gclk/hpl_gclk.c | 164 + watch-library/hardware/hpl/gclk/hpl_gclk_base.h | 87 + watch-library/hardware/hpl/mclk/hpl_mclk.c | 46 + watch-library/hardware/hpl/nvmctrl/hpl_nvmctrl.c | 782 ++ .../hardware/hpl/osc32kctrl/hpl_osc32kctrl.c | 86 + watch-library/hardware/hpl/oscctrl/hpl_oscctrl.c | 179 + watch-library/hardware/hpl/pm/hpl_pm.c | 77 + watch-library/hardware/hpl/pm/hpl_pm_base.h | 45 + watch-library/hardware/hpl/port/hpl_gpio_base.h | 170 + watch-library/hardware/hpl/sercom/hpl_sercom.c | 2932 ++++++ watch-library/hardware/hpl/slcd/hpl_slcd.c | 289 + watch-library/hardware/hpl/slcd/hpl_slcd_cm.h | 59 + watch-library/hardware/hpl/systick/hpl_systick.c | 104 + watch-library/hardware/hpl/trng/hpl_trng.c | 110 + watch-library/hardware/hri/hri_ac_l22.h | 1746 ++++ watch-library/hardware/hri/hri_adc_l22.h | 2803 ++++++ watch-library/hardware/hri/hri_aes_l22.h | 1213 +++ watch-library/hardware/hri/hri_ccl_l22.h | 776 ++ watch-library/hardware/hri/hri_dmac_l22.h | 4559 ++++++++++ watch-library/hardware/hri/hri_dsu_l22.h | 1163 +++ watch-library/hardware/hri/hri_eic_l22.h | 1463 +++ watch-library/hardware/hri/hri_evsys_l22.h | 1333 +++ watch-library/hardware/hri/hri_freqm_l22.h | 464 + watch-library/hardware/hri/hri_gclk_l22.h | 770 ++ watch-library/hardware/hri/hri_l22.h | 70 + watch-library/hardware/hri/hri_mclk_l22.h | 2300 +++++ watch-library/hardware/hri/hri_mtb_l22.h | 551 ++ watch-library/hardware/hri/hri_nvic_l22.h | 269 + watch-library/hardware/hri/hri_nvmctrl_l22.h | 1104 +++ watch-library/hardware/hri/hri_osc32kctrl_l22.h | 1233 +++ watch-library/hardware/hri/hri_oscctrl_l22.h | 3451 +++++++ watch-library/hardware/hri/hri_pac_l22.h | 1076 +++ watch-library/hardware/hri/hri_pm_l22.h | 592 ++ watch-library/hardware/hri/hri_port_l22.h | 2357 +++++ watch-library/hardware/hri/hri_rstc_l22.h | 132 + watch-library/hardware/hri/hri_rtc_l22.h | 9084 +++++++++++++++++++ watch-library/hardware/hri/hri_sercom_l22.h | 7827 ++++++++++++++++ watch-library/hardware/hri/hri_slcd_l22.h | 5440 +++++++++++ watch-library/hardware/hri/hri_supc_l22.h | 2532 ++++++ watch-library/hardware/hri/hri_systemcontrol_l22.h | 498 ++ watch-library/hardware/hri/hri_systick_l22.h | 219 + watch-library/hardware/hri/hri_tc_l22.h | 2899 ++++++ watch-library/hardware/hri/hri_tcc_l22.h | 9462 ++++++++++++++++++++ watch-library/hardware/hri/hri_trng_l22.h | 380 + watch-library/hardware/hri/hri_usb_l22.h | 4713 ++++++++++ watch-library/hardware/hri/hri_wdt_l22.h | 617 ++ watch-library/hardware/hw/driver_init.c | 96 + watch-library/hardware/hw/driver_init.h | 59 + watch-library/hardware/include/component-version.h | 64 + watch-library/hardware/include/component/ac.h | 586 ++ watch-library/hardware/include/component/adc.h | 748 ++ watch-library/hardware/include/component/aes.h | 325 + watch-library/hardware/include/component/ccl.h | 188 + watch-library/hardware/include/component/dmac.h | 1117 +++ watch-library/hardware/include/component/dsu.h | 629 ++ watch-library/hardware/include/component/eic.h | 422 + watch-library/hardware/include/component/evsys.h | 496 + watch-library/hardware/include/component/freqm.h | 233 + watch-library/hardware/include/component/gclk.h | 221 + watch-library/hardware/include/component/mclk.h | 380 + watch-library/hardware/include/component/mtb.h | 382 + watch-library/hardware/include/component/nvmctrl.h | 528 ++ .../hardware/include/component/osc32kctrl.h | 313 + watch-library/hardware/include/component/oscctrl.h | 694 ++ watch-library/hardware/include/component/pac.h | 497 + watch-library/hardware/include/component/pm.h | 222 + watch-library/hardware/include/component/port.h | 343 + watch-library/hardware/include/component/rstc.h | 112 + watch-library/hardware/include/component/rtc.h | 2008 +++++ watch-library/hardware/include/component/sercom.h | 1501 ++++ watch-library/hardware/include/component/slcd.h | 1173 +++ watch-library/hardware/include/component/supc.h | 603 ++ watch-library/hardware/include/component/tc.h | 829 ++ watch-library/hardware/include/component/tcc.h | 1702 ++++ watch-library/hardware/include/component/trng.h | 172 + watch-library/hardware/include/component/usb.h | 1001 +++ watch-library/hardware/include/component/wdt.h | 300 + watch-library/hardware/include/core_cm0plus.h | 822 ++ watch-library/hardware/include/core_cmFunc.h | 637 ++ watch-library/hardware/include/core_cmInstr.h | 880 ++ watch-library/hardware/include/instance/ac.h | 74 + watch-library/hardware/include/instance/adc.h | 89 + watch-library/hardware/include/instance/aes.h | 102 + watch-library/hardware/include/instance/ccl.h | 58 + watch-library/hardware/include/instance/dmac.h | 98 + watch-library/hardware/include/instance/dsu.h | 95 + watch-library/hardware/include/instance/eic.h | 66 + watch-library/hardware/include/instance/evsys.h | 250 + watch-library/hardware/include/instance/freqm.h | 60 + watch-library/hardware/include/instance/gclk.h | 130 + watch-library/hardware/include/instance/mclk.h | 63 + watch-library/hardware/include/instance/mtb.h | 89 + watch-library/hardware/include/instance/nvmctrl.h | 80 + .../hardware/include/instance/osc32kctrl.h | 61 + watch-library/hardware/include/instance/oscctrl.h | 86 + watch-library/hardware/include/instance/pac.h | 66 + watch-library/hardware/include/instance/pm.h | 56 + watch-library/hardware/include/instance/port.h | 155 + watch-library/hardware/include/instance/ptc.h | 43 + watch-library/hardware/include/instance/rstc.h | 46 + watch-library/hardware/include/instance/rtc.h | 142 + watch-library/hardware/include/instance/sercom0.h | 142 + watch-library/hardware/include/instance/sercom1.h | 142 + watch-library/hardware/include/instance/sercom2.h | 142 + watch-library/hardware/include/instance/sercom3.h | 142 + watch-library/hardware/include/instance/sercom4.h | 142 + watch-library/hardware/include/instance/sercom5.h | 142 + watch-library/hardware/include/instance/slcd.h | 126 + watch-library/hardware/include/instance/supc.h | 65 + watch-library/hardware/include/instance/tc0.h | 109 + watch-library/hardware/include/instance/tc1.h | 109 + watch-library/hardware/include/instance/tc2.h | 109 + watch-library/hardware/include/instance/tc3.h | 109 + watch-library/hardware/include/instance/tcc0.h | 115 + watch-library/hardware/include/instance/trng.h | 51 + watch-library/hardware/include/instance/usb.h | 184 + watch-library/hardware/include/instance/wdt.h | 55 + watch-library/hardware/include/pio/saml22g16a.h | 947 ++ watch-library/hardware/include/pio/saml22g17a.h | 947 ++ watch-library/hardware/include/pio/saml22g18a.h | 947 ++ watch-library/hardware/include/pio/saml22j16a.h | 1265 +++ watch-library/hardware/include/pio/saml22j17a.h | 1265 +++ watch-library/hardware/include/pio/saml22j18a.h | 1265 +++ watch-library/hardware/include/pio/saml22n16a.h | 1851 ++++ watch-library/hardware/include/pio/saml22n17a.h | 1851 ++++ watch-library/hardware/include/pio/saml22n18a.h | 1851 ++++ watch-library/hardware/include/sam.h | 55 + watch-library/hardware/include/saml22.h | 60 + watch-library/hardware/include/saml22g16a.h | 596 ++ watch-library/hardware/include/saml22g17a.h | 596 ++ watch-library/hardware/include/saml22g18a.h | 596 ++ watch-library/hardware/include/saml22j16a.h | 596 ++ watch-library/hardware/include/saml22j17a.h | 596 ++ watch-library/hardware/include/saml22j18a.h | 596 ++ watch-library/hardware/include/saml22n16a.h | 608 ++ watch-library/hardware/include/saml22n17a.h | 608 ++ watch-library/hardware/include/saml22n18a.h | 608 ++ watch-library/hardware/include/system_saml22.h | 48 + watch-library/hardware/linker/saml22j18.ld | 145 + watch-library/hardware/main.c | 85 + watch-library/hardware/startup_saml22.c | 225 + watch-library/hardware/watch/tusb_config.h | 91 + watch-library/hardware/watch/watch.c | 44 + watch-library/hardware/watch/watch_adc.c | 179 + watch-library/hardware/watch/watch_buzzer.c | 64 + watch-library/hardware/watch/watch_deepsleep.c | 209 + watch-library/hardware/watch/watch_extint.c | 111 + watch-library/hardware/watch/watch_gpio.c | 61 + watch-library/hardware/watch/watch_i2c.c | 93 + watch-library/hardware/watch/watch_led.c | 69 + watch-library/hardware/watch/watch_private.c | 423 + watch-library/hardware/watch/watch_rtc.c | 195 + watch-library/hardware/watch/watch_slcd.c | 101 + watch-library/hardware/watch/watch_uart.c | 89 + watch-library/hpl/core/hpl_core_m0plus_base.c | 202 - watch-library/hpl/core/hpl_core_port.h | 63 - watch-library/hpl/core/hpl_init.c | 74 - watch-library/hpl/dmac/hpl_dmac.c | 244 - watch-library/hpl/eic/hpl_eic.c | 255 - watch-library/hpl/gclk/hpl_gclk.c | 164 - watch-library/hpl/gclk/hpl_gclk_base.h | 87 - watch-library/hpl/mclk/hpl_mclk.c | 46 - watch-library/hpl/nvmctrl/hpl_nvmctrl.c | 782 -- watch-library/hpl/osc32kctrl/hpl_osc32kctrl.c | 86 - watch-library/hpl/oscctrl/hpl_oscctrl.c | 179 - watch-library/hpl/pm/hpl_pm.c | 77 - watch-library/hpl/pm/hpl_pm_base.h | 45 - watch-library/hpl/port/hpl_gpio_base.h | 170 - watch-library/hpl/sercom/hpl_sercom.c | 2932 ------ watch-library/hpl/slcd/hpl_slcd.c | 289 - watch-library/hpl/slcd/hpl_slcd_cm.h | 59 - watch-library/hpl/systick/hpl_systick.c | 104 - watch-library/hpl/trng/hpl_trng.c | 110 - watch-library/hri/hri_ac_l22.h | 1746 ---- watch-library/hri/hri_adc_l22.h | 2803 ------ watch-library/hri/hri_aes_l22.h | 1213 --- watch-library/hri/hri_ccl_l22.h | 776 -- watch-library/hri/hri_dmac_l22.h | 4559 ---------- watch-library/hri/hri_dsu_l22.h | 1163 --- watch-library/hri/hri_eic_l22.h | 1463 --- watch-library/hri/hri_evsys_l22.h | 1333 --- watch-library/hri/hri_freqm_l22.h | 464 - watch-library/hri/hri_gclk_l22.h | 770 -- watch-library/hri/hri_l22.h | 70 - watch-library/hri/hri_mclk_l22.h | 2300 ----- watch-library/hri/hri_mtb_l22.h | 551 -- watch-library/hri/hri_nvic_l22.h | 269 - watch-library/hri/hri_nvmctrl_l22.h | 1104 --- watch-library/hri/hri_osc32kctrl_l22.h | 1233 --- watch-library/hri/hri_oscctrl_l22.h | 3451 ------- watch-library/hri/hri_pac_l22.h | 1076 --- watch-library/hri/hri_pm_l22.h | 592 -- watch-library/hri/hri_port_l22.h | 2357 ----- watch-library/hri/hri_rstc_l22.h | 132 - watch-library/hri/hri_rtc_l22.h | 9084 ------------------- watch-library/hri/hri_sercom_l22.h | 7827 ---------------- watch-library/hri/hri_slcd_l22.h | 5440 ----------- watch-library/hri/hri_supc_l22.h | 2532 ------ watch-library/hri/hri_systemcontrol_l22.h | 498 -- watch-library/hri/hri_systick_l22.h | 219 - watch-library/hri/hri_tc_l22.h | 2899 ------ watch-library/hri/hri_tcc_l22.h | 9462 -------------------- watch-library/hri/hri_trng_l22.h | 380 - watch-library/hri/hri_usb_l22.h | 4713 ---------- watch-library/hri/hri_wdt_l22.h | 617 -- watch-library/hw/driver_init.c | 96 - watch-library/hw/driver_init.h | 59 - watch-library/include/component-version.h | 64 - watch-library/include/component/ac.h | 586 -- watch-library/include/component/adc.h | 748 -- watch-library/include/component/aes.h | 325 - watch-library/include/component/ccl.h | 188 - watch-library/include/component/dmac.h | 1117 --- watch-library/include/component/dsu.h | 629 -- watch-library/include/component/eic.h | 422 - watch-library/include/component/evsys.h | 496 - watch-library/include/component/freqm.h | 233 - watch-library/include/component/gclk.h | 221 - watch-library/include/component/mclk.h | 380 - watch-library/include/component/mtb.h | 382 - watch-library/include/component/nvmctrl.h | 528 -- watch-library/include/component/osc32kctrl.h | 313 - watch-library/include/component/oscctrl.h | 694 -- watch-library/include/component/pac.h | 497 - watch-library/include/component/pm.h | 222 - watch-library/include/component/port.h | 343 - watch-library/include/component/rstc.h | 112 - watch-library/include/component/rtc.h | 2008 ----- watch-library/include/component/sercom.h | 1501 ---- watch-library/include/component/slcd.h | 1173 --- watch-library/include/component/supc.h | 603 -- watch-library/include/component/tc.h | 829 -- watch-library/include/component/tcc.h | 1702 ---- watch-library/include/component/trng.h | 172 - watch-library/include/component/usb.h | 1001 --- watch-library/include/component/wdt.h | 300 - watch-library/include/core_cm0plus.h | 822 -- watch-library/include/core_cmFunc.h | 637 -- watch-library/include/core_cmInstr.h | 880 -- watch-library/include/instance/ac.h | 74 - watch-library/include/instance/adc.h | 89 - watch-library/include/instance/aes.h | 102 - watch-library/include/instance/ccl.h | 58 - watch-library/include/instance/dmac.h | 98 - watch-library/include/instance/dsu.h | 95 - watch-library/include/instance/eic.h | 66 - watch-library/include/instance/evsys.h | 250 - watch-library/include/instance/freqm.h | 60 - watch-library/include/instance/gclk.h | 130 - watch-library/include/instance/mclk.h | 63 - watch-library/include/instance/mtb.h | 89 - watch-library/include/instance/nvmctrl.h | 80 - watch-library/include/instance/osc32kctrl.h | 61 - watch-library/include/instance/oscctrl.h | 86 - watch-library/include/instance/pac.h | 66 - watch-library/include/instance/pm.h | 56 - watch-library/include/instance/port.h | 155 - watch-library/include/instance/ptc.h | 43 - watch-library/include/instance/rstc.h | 46 - watch-library/include/instance/rtc.h | 142 - watch-library/include/instance/sercom0.h | 142 - watch-library/include/instance/sercom1.h | 142 - watch-library/include/instance/sercom2.h | 142 - watch-library/include/instance/sercom3.h | 142 - watch-library/include/instance/sercom4.h | 142 - watch-library/include/instance/sercom5.h | 142 - watch-library/include/instance/slcd.h | 126 - watch-library/include/instance/supc.h | 65 - watch-library/include/instance/tc0.h | 109 - watch-library/include/instance/tc1.h | 109 - watch-library/include/instance/tc2.h | 109 - watch-library/include/instance/tc3.h | 109 - watch-library/include/instance/tcc0.h | 115 - watch-library/include/instance/trng.h | 51 - watch-library/include/instance/usb.h | 184 - watch-library/include/instance/wdt.h | 55 - watch-library/include/pio/saml22g16a.h | 947 -- watch-library/include/pio/saml22g17a.h | 947 -- watch-library/include/pio/saml22g18a.h | 947 -- watch-library/include/pio/saml22j16a.h | 1265 --- watch-library/include/pio/saml22j17a.h | 1265 --- watch-library/include/pio/saml22j18a.h | 1265 --- watch-library/include/pio/saml22n16a.h | 1851 ---- watch-library/include/pio/saml22n17a.h | 1851 ---- watch-library/include/pio/saml22n18a.h | 1851 ---- watch-library/include/sam.h | 55 - watch-library/include/saml22.h | 60 - watch-library/include/saml22g16a.h | 596 -- watch-library/include/saml22g17a.h | 596 -- watch-library/include/saml22g18a.h | 596 -- watch-library/include/saml22j16a.h | 596 -- watch-library/include/saml22j17a.h | 596 -- watch-library/include/saml22j18a.h | 596 -- watch-library/include/saml22n16a.h | 608 -- watch-library/include/saml22n17a.h | 608 -- watch-library/include/saml22n18a.h | 608 -- watch-library/include/system_saml22.h | 48 - watch-library/linker/saml22j18.ld | 145 - watch-library/main.c | 85 - watch-library/shared/config/RTE_Components.h | 54 + watch-library/shared/config/hpl_dmac_config.h | 3122 +++++++ watch-library/shared/config/hpl_eic_config.h | 736 ++ watch-library/shared/config/hpl_gclk_config.h | 388 + watch-library/shared/config/hpl_mclk_config.h | 85 + watch-library/shared/config/hpl_nvmctrl_config.h | 38 + .../shared/config/hpl_osc32kctrl_config.h | 177 + watch-library/shared/config/hpl_oscctrl_config.h | 483 + watch-library/shared/config/hpl_port_config.h | 284 + watch-library/shared/config/hpl_rtc_config.h | 318 + watch-library/shared/config/hpl_sercom_config.h | 303 + watch-library/shared/config/hpl_slcd_config.h | 239 + watch-library/shared/config/hpl_systick_config.h | 18 + watch-library/shared/config/hpl_trng_config.h | 27 + watch-library/shared/config/nv_storage_config.h | 51 + .../shared/config/peripheral_clk_config.h | 266 + watch-library/shared/driver/lis2dh.c | 143 + watch-library/shared/driver/lis2dh.h | 222 + watch-library/shared/driver/lis2dw.c | 139 + watch-library/shared/driver/lis2dw.h | 265 + watch-library/shared/watch/watch.h | 83 + watch-library/shared/watch/watch_adc.h | 174 + watch-library/shared/watch/watch_app.h | 108 + watch-library/shared/watch/watch_buzzer.h | 164 + watch-library/shared/watch/watch_deepsleep.h | 159 + watch-library/shared/watch/watch_extint.h | 85 + watch-library/shared/watch/watch_gpio.h | 76 + watch-library/shared/watch/watch_i2c.h | 106 + watch-library/shared/watch/watch_led.h | 93 + watch-library/shared/watch/watch_private.h | 50 + watch-library/shared/watch/watch_private_display.c | 137 + watch-library/shared/watch/watch_private_display.h | 146 + watch-library/shared/watch/watch_rtc.h | 164 + watch-library/shared/watch/watch_slcd.h | 151 + watch-library/shared/watch/watch_uart.h | 58 + watch-library/shared/watch/watch_utility.c | 172 + watch-library/shared/watch/watch_utility.h | 100 + watch-library/simulator/hpl/port/hpl_gpio_base.h | 87 + watch-library/simulator/main.c | 70 + watch-library/simulator/shell.html | 368 + watch-library/simulator/watch/watch.c | 9 + watch-library/simulator/watch/watch_adc.c | 48 + watch-library/simulator/watch/watch_buzzer.c | 60 + watch-library/simulator/watch/watch_deepsleep.c | 99 + watch-library/simulator/watch/watch_extint.c | 191 + watch-library/simulator/watch/watch_gpio.c | 47 + watch-library/simulator/watch/watch_i2c.c | 51 + watch-library/simulator/watch/watch_led.c | 63 + watch-library/simulator/watch/watch_private.c | 78 + watch-library/simulator/watch/watch_rtc.c | 223 + watch-library/simulator/watch/watch_slcd.c | 115 + watch-library/simulator/watch/watch_uart.c | 65 + watch-library/startup_saml22.c | 225 - watch-library/watch/tusb_config.h | 91 - watch-library/watch/watch.c | 44 - watch-library/watch/watch.h | 83 - watch-library/watch/watch_adc.c | 179 - watch-library/watch/watch_adc.h | 157 - watch-library/watch/watch_app.h | 108 - watch-library/watch/watch_buzzer.c | 64 - watch-library/watch/watch_buzzer.h | 164 - watch-library/watch/watch_deepsleep.c | 209 - watch-library/watch/watch_deepsleep.h | 159 - watch-library/watch/watch_extint.c | 111 - watch-library/watch/watch_extint.h | 85 - watch-library/watch/watch_gpio.c | 61 - watch-library/watch/watch_gpio.h | 76 - watch-library/watch/watch_i2c.c | 93 - watch-library/watch/watch_i2c.h | 106 - watch-library/watch/watch_led.c | 69 - watch-library/watch/watch_led.h | 93 - watch-library/watch/watch_private.c | 423 - watch-library/watch/watch_private.h | 50 - watch-library/watch/watch_rtc.c | 195 - watch-library/watch/watch_rtc.h | 164 - watch-library/watch/watch_slcd.c | 318 - watch-library/watch/watch_slcd.h | 151 - watch-library/watch/watch_uart.c | 89 - watch-library/watch/watch_uart.h | 58 - watch-library/watch/watch_utility.c | 172 - watch-library/watch/watch_utility.h | 100 - 605 files changed, 146084 insertions(+), 144351 deletions(-) delete mode 100644 watch-library/config/RTE_Components.h delete mode 100644 watch-library/config/hpl_dmac_config.h delete mode 100644 watch-library/config/hpl_eic_config.h delete mode 100644 watch-library/config/hpl_gclk_config.h delete mode 100644 watch-library/config/hpl_mclk_config.h delete mode 100755 watch-library/config/hpl_nvmctrl_config.h delete mode 100644 watch-library/config/hpl_osc32kctrl_config.h delete mode 100644 watch-library/config/hpl_oscctrl_config.h delete mode 100644 watch-library/config/hpl_port_config.h delete mode 100644 watch-library/config/hpl_rtc_config.h delete mode 100644 watch-library/config/hpl_sercom_config.h delete mode 100644 watch-library/config/hpl_slcd_config.h delete mode 100644 watch-library/config/hpl_systick_config.h delete mode 100755 watch-library/config/hpl_trng_config.h delete mode 100755 watch-library/config/nv_storage_config.h delete mode 100644 watch-library/config/peripheral_clk_config.h delete mode 100644 watch-library/driver/lis2dh.c delete mode 100644 watch-library/driver/lis2dh.h delete mode 100644 watch-library/driver/lis2dw.c delete mode 100644 watch-library/driver/lis2dw.h delete mode 100644 watch-library/hal/documentation/ext_irq.rst delete mode 100755 watch-library/hal/documentation/flash.rst delete mode 100644 watch-library/hal/documentation/i2c_master_sync.rst delete mode 100755 watch-library/hal/documentation/rand_sync.rst delete mode 100644 watch-library/hal/documentation/slcd_sync.rst delete mode 100755 watch-library/hal/documentation/spi_master_sync.rst delete mode 100755 watch-library/hal/documentation/usart_sync.rst delete mode 100644 watch-library/hal/include/hal_atomic.h delete mode 100644 watch-library/hal/include/hal_calendar.h delete mode 100644 watch-library/hal/include/hal_delay.h delete mode 100644 watch-library/hal/include/hal_ext_irq.h delete mode 100755 watch-library/hal/include/hal_flash.h delete mode 100644 watch-library/hal/include/hal_gpio.h delete mode 100644 watch-library/hal/include/hal_i2c_m_sync.h delete mode 100644 watch-library/hal/include/hal_init.h delete mode 100644 watch-library/hal/include/hal_io.h delete mode 100755 watch-library/hal/include/hal_rand_sync.h delete mode 100644 watch-library/hal/include/hal_slcd_sync.h delete mode 100644 watch-library/hal/include/hal_sleep.h delete mode 100755 watch-library/hal/include/hal_spi_m_sync.h delete mode 100755 watch-library/hal/include/hal_usart_sync.h delete mode 100644 watch-library/hal/include/hpl_calendar.h delete mode 100644 watch-library/hal/include/hpl_core.h delete mode 100644 watch-library/hal/include/hpl_delay.h delete mode 100644 watch-library/hal/include/hpl_dma.h delete mode 100644 watch-library/hal/include/hpl_ext_irq.h delete mode 100755 watch-library/hal/include/hpl_flash.h delete mode 100644 watch-library/hal/include/hpl_gpio.h delete mode 100644 watch-library/hal/include/hpl_i2c_m_async.h delete mode 100644 watch-library/hal/include/hpl_i2c_m_sync.h delete mode 100644 watch-library/hal/include/hpl_i2c_s_async.h delete mode 100644 watch-library/hal/include/hpl_i2c_s_sync.h delete mode 100644 watch-library/hal/include/hpl_init.h delete mode 100644 watch-library/hal/include/hpl_irq.h delete mode 100644 watch-library/hal/include/hpl_missing_features.h delete mode 100755 watch-library/hal/include/hpl_rand_sync.h delete mode 100644 watch-library/hal/include/hpl_reset.h delete mode 100644 watch-library/hal/include/hpl_slcd.h delete mode 100644 watch-library/hal/include/hpl_slcd_sync.h delete mode 100644 watch-library/hal/include/hpl_sleep.h delete mode 100644 watch-library/hal/include/hpl_spi.h delete mode 100644 watch-library/hal/include/hpl_spi_async.h delete mode 100755 watch-library/hal/include/hpl_spi_dma.h delete mode 100644 watch-library/hal/include/hpl_spi_m_async.h delete mode 100644 watch-library/hal/include/hpl_spi_m_dma.h delete mode 100644 watch-library/hal/include/hpl_spi_m_sync.h delete mode 100644 watch-library/hal/include/hpl_spi_s_async.h delete mode 100644 watch-library/hal/include/hpl_spi_s_sync.h delete mode 100644 watch-library/hal/include/hpl_spi_sync.h delete mode 100644 watch-library/hal/include/hpl_time_measure.h delete mode 100644 watch-library/hal/include/hpl_timer.h delete mode 100644 watch-library/hal/include/hpl_usart.h delete mode 100644 watch-library/hal/include/hpl_usart_async.h delete mode 100644 watch-library/hal/include/hpl_usart_sync.h delete mode 100755 watch-library/hal/include/hpl_user_area.h delete mode 100644 watch-library/hal/src/hal_atomic.c delete mode 100644 watch-library/hal/src/hal_calendar.c delete mode 100644 watch-library/hal/src/hal_delay.c delete mode 100644 watch-library/hal/src/hal_ext_irq.c delete mode 100755 watch-library/hal/src/hal_flash.c delete mode 100644 watch-library/hal/src/hal_gpio.c delete mode 100644 watch-library/hal/src/hal_i2c_m_sync.c delete mode 100644 watch-library/hal/src/hal_init.c delete mode 100644 watch-library/hal/src/hal_io.c delete mode 100755 watch-library/hal/src/hal_rand_sync.c delete mode 100644 watch-library/hal/src/hal_slcd_sync.c delete mode 100644 watch-library/hal/src/hal_sleep.c delete mode 100755 watch-library/hal/src/hal_spi_m_sync.c delete mode 100755 watch-library/hal/src/hal_usart_sync.c delete mode 100644 watch-library/hal/utils/include/compiler.h delete mode 100644 watch-library/hal/utils/include/err_codes.h delete mode 100644 watch-library/hal/utils/include/events.h delete mode 100644 watch-library/hal/utils/include/parts.h delete mode 100644 watch-library/hal/utils/include/utils.h delete mode 100644 watch-library/hal/utils/include/utils_assert.h delete mode 100644 watch-library/hal/utils/include/utils_decrement_macro.h delete mode 100644 watch-library/hal/utils/include/utils_event.h delete mode 100644 watch-library/hal/utils/include/utils_increment_macro.h delete mode 100644 watch-library/hal/utils/include/utils_list.h delete mode 100644 watch-library/hal/utils/include/utils_recursion_macro.h delete mode 100644 watch-library/hal/utils/include/utils_repeat_macro.h delete mode 100644 watch-library/hal/utils/src/utils_assert.c delete mode 100644 watch-library/hal/utils/src/utils_event.c delete mode 100644 watch-library/hal/utils/src/utils_list.c delete mode 100644 watch-library/hal/utils/src/utils_syscalls.c create mode 100644 watch-library/hardware/hal/documentation/ext_irq.rst create mode 100755 watch-library/hardware/hal/documentation/flash.rst create mode 100644 watch-library/hardware/hal/documentation/i2c_master_sync.rst create mode 100755 watch-library/hardware/hal/documentation/rand_sync.rst create mode 100644 watch-library/hardware/hal/documentation/slcd_sync.rst create mode 100755 watch-library/hardware/hal/documentation/spi_master_sync.rst create mode 100755 watch-library/hardware/hal/documentation/usart_sync.rst create mode 100644 watch-library/hardware/hal/include/hal_atomic.h create mode 100644 watch-library/hardware/hal/include/hal_calendar.h create mode 100644 watch-library/hardware/hal/include/hal_delay.h create mode 100644 watch-library/hardware/hal/include/hal_ext_irq.h create mode 100755 watch-library/hardware/hal/include/hal_flash.h create mode 100644 watch-library/hardware/hal/include/hal_gpio.h create mode 100644 watch-library/hardware/hal/include/hal_i2c_m_sync.h create mode 100644 watch-library/hardware/hal/include/hal_init.h create mode 100644 watch-library/hardware/hal/include/hal_io.h create mode 100755 watch-library/hardware/hal/include/hal_rand_sync.h create mode 100644 watch-library/hardware/hal/include/hal_slcd_sync.h create mode 100644 watch-library/hardware/hal/include/hal_sleep.h create mode 100755 watch-library/hardware/hal/include/hal_spi_m_sync.h create mode 100755 watch-library/hardware/hal/include/hal_usart_sync.h create mode 100644 watch-library/hardware/hal/include/hpl_calendar.h create mode 100644 watch-library/hardware/hal/include/hpl_core.h create mode 100644 watch-library/hardware/hal/include/hpl_delay.h create mode 100644 watch-library/hardware/hal/include/hpl_dma.h create mode 100644 watch-library/hardware/hal/include/hpl_ext_irq.h create mode 100755 watch-library/hardware/hal/include/hpl_flash.h create mode 100644 watch-library/hardware/hal/include/hpl_gpio.h create mode 100644 watch-library/hardware/hal/include/hpl_i2c_m_async.h create mode 100644 watch-library/hardware/hal/include/hpl_i2c_m_sync.h create mode 100644 watch-library/hardware/hal/include/hpl_i2c_s_async.h create mode 100644 watch-library/hardware/hal/include/hpl_i2c_s_sync.h create mode 100644 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watch-library/simulator/watch/watch_adc.c create mode 100644 watch-library/simulator/watch/watch_buzzer.c create mode 100644 watch-library/simulator/watch/watch_deepsleep.c create mode 100644 watch-library/simulator/watch/watch_extint.c create mode 100644 watch-library/simulator/watch/watch_gpio.c create mode 100644 watch-library/simulator/watch/watch_i2c.c create mode 100644 watch-library/simulator/watch/watch_led.c create mode 100644 watch-library/simulator/watch/watch_private.c create mode 100644 watch-library/simulator/watch/watch_rtc.c create mode 100644 watch-library/simulator/watch/watch_slcd.c create mode 100644 watch-library/simulator/watch/watch_uart.c delete mode 100755 watch-library/startup_saml22.c delete mode 100644 watch-library/watch/tusb_config.h delete mode 100644 watch-library/watch/watch.c delete mode 100644 watch-library/watch/watch.h delete mode 100644 watch-library/watch/watch_adc.c delete mode 100644 watch-library/watch/watch_adc.h delete mode 100644 watch-library/watch/watch_app.h delete mode 100644 watch-library/watch/watch_buzzer.c delete mode 100644 watch-library/watch/watch_buzzer.h delete mode 100644 watch-library/watch/watch_deepsleep.c delete mode 100644 watch-library/watch/watch_deepsleep.h delete mode 100644 watch-library/watch/watch_extint.c delete mode 100644 watch-library/watch/watch_extint.h delete mode 100644 watch-library/watch/watch_gpio.c delete mode 100644 watch-library/watch/watch_gpio.h delete mode 100644 watch-library/watch/watch_i2c.c delete mode 100644 watch-library/watch/watch_i2c.h delete mode 100644 watch-library/watch/watch_led.c delete mode 100644 watch-library/watch/watch_led.h delete mode 100644 watch-library/watch/watch_private.c delete mode 100644 watch-library/watch/watch_private.h delete mode 100644 watch-library/watch/watch_rtc.c delete mode 100644 watch-library/watch/watch_rtc.h delete mode 100644 watch-library/watch/watch_slcd.c delete mode 100644 watch-library/watch/watch_slcd.h delete mode 100644 watch-library/watch/watch_uart.c delete mode 100644 watch-library/watch/watch_uart.h delete mode 100644 watch-library/watch/watch_utility.c delete mode 100644 watch-library/watch/watch_utility.h diff --git a/apps/beats-time/app.c b/apps/beats-time/app.c index 3a8c2dac..ef27ffef 100644 --- a/apps/beats-time/app.c +++ b/apps/beats-time/app.c @@ -3,7 +3,7 @@ #include #include "watch.h" -const uint8_t UTC_OFFSET = 4; // set to your current UTC offset to see correct beats time +const int8_t UTC_OFFSET = 4; // set to your current UTC offset to see correct beats time const uint8_t BEAT_REFRESH_FREQUENCY = 8; typedef enum ApplicationMode { @@ -160,7 +160,7 @@ float clock2beats(uint16_t hours, uint16_t minutes, uint16_t seconds, int16_t ut float beats = seconds + ((float)application_state.subsecond / (float)BEAT_REFRESH_FREQUENCY); beats += 60 * minutes; beats += (float)hours * 60 * 60; - beats += (utc_offset + 1) * 60 * 60; // offset from utc + 1 since beats in in UTC+1 + beats += (1 - utc_offset) * 60 * 60; // offset from utc + 1 since beats in in UTC+1 beats /= 86.4; // convert to beats while(beats > 1000) beats -= 1000; // beats %= 1000 but for a float diff --git a/make.mk b/make.mk index 1b688ae5..94d0bd82 100644 --- a/make.mk +++ b/make.mk @@ -9,17 +9,18 @@ endif ############################################################################## .PHONY: all directory clean size -CC = arm-none-eabi-gcc -OBJCOPY = arm-none-eabi-objcopy -SIZE = arm-none-eabi-size -UF2 = python $(TOP)/utils/uf2conv.py - ifeq ($(OS), Windows_NT) MKDIR = gmkdir else MKDIR = mkdir endif +ifndef EMSCRIPTEN +CC = arm-none-eabi-gcc +OBJCOPY = arm-none-eabi-objcopy +SIZE = arm-none-eabi-size +UF2 = python $(TOP)/utils/uf2conv.py + CFLAGS += -W -Wall -Wextra -Wmissing-prototypes -Wmissing-declarations CFLAGS += --std=gnu99 -Os CFLAGS += -fno-diagnostics-show-caret @@ -30,40 +31,41 @@ CFLAGS += -MD -MP -MT $(BUILD)/$(*F).o -MF $(BUILD)/$(@F).d LDFLAGS += -mcpu=cortex-m0plus -mthumb LDFLAGS += -Wl,--gc-sections -LDFLAGS += -Wl,--script=$(TOP)//watch-library/linker/saml22j18.ld +LDFLAGS += -Wl,--script=$(TOP)/watch-library/hardware/linker/saml22j18.ld LIBS += -lm INCLUDES += \ -I$(TOP)/tinyusb/src \ -I$(TOP)/boards/$(BOARD) \ - -I$(TOP)/watch-library/include \ - -I$(TOP)/watch-library/hal/ \ - -I$(TOP)/watch-library/hal/documentation/ \ - -I$(TOP)/watch-library/hal/include/ \ - -I$(TOP)/watch-library/hal/src/ \ - -I$(TOP)/watch-library/hal/utils/ \ - -I$(TOP)/watch-library/hal/utils/include/ \ - -I$(TOP)/watch-library/hal/utils/src/ \ - -I$(TOP)/watch-library/hpl/ \ - -I$(TOP)/watch-library/hpl/core/ \ - -I$(TOP)/watch-library/hpl/dmac/ \ - -I$(TOP)/watch-library/hpl/eic/ \ - -I$(TOP)/watch-library/hpl/gclk/ \ - -I$(TOP)/watch-library/hpl/mclk/ \ - -I$(TOP)/watch-library/hpl/osc32kctrl/ \ - -I$(TOP)/watch-library/hpl/oscctrl/ \ - -I$(TOP)/watch-library/hpl/pm/ \ - -I$(TOP)/watch-library/hpl/port/ \ - -I$(TOP)/watch-library/hpl/sercom/ \ - -I$(TOP)/watch-library/hpl/slcd/ \ - -I$(TOP)/watch-library/hpl/systick/ \ - -I$(TOP)/watch-library/hri/ \ - -I$(TOP)/watch-library/config/ \ - -I$(TOP)/watch-library/hw/ \ - -I$(TOP)/watch-library/watch/ \ - -I$(TOP)/watch-library/driver/ \ - -I$(TOP)/watch-library + -I$(TOP)/watch-library/shared/config/ \ + -I$(TOP)/watch-library/shared/driver/ \ + -I$(TOP)/watch-library/shared/watch/ \ + -I$(TOP)/watch-library/hardware/include \ + -I$(TOP)/watch-library/hardware/hal/ \ + -I$(TOP)/watch-library/hardware/hal/documentation/ \ + -I$(TOP)/watch-library/hardware/hal/include/ \ + -I$(TOP)/watch-library/hardware/hal/src/ \ + -I$(TOP)/watch-library/hardware/hal/utils/ \ + -I$(TOP)/watch-library/hardware/hal/utils/include/ \ + -I$(TOP)/watch-library/hardware/hal/utils/src/ \ + -I$(TOP)/watch-library/hardware/hpl/ \ + -I$(TOP)/watch-library/hardware/hpl/core/ \ + -I$(TOP)/watch-library/hardware/hpl/dmac/ \ + -I$(TOP)/watch-library/hardware/hpl/eic/ \ + -I$(TOP)/watch-library/hardware/hpl/gclk/ \ + -I$(TOP)/watch-library/hardware/hpl/mclk/ \ + -I$(TOP)/watch-library/hardware/hpl/osc32kctrl/ \ + -I$(TOP)/watch-library/hardware/hpl/oscctrl/ \ + -I$(TOP)/watch-library/hardware/hpl/pm/ \ + -I$(TOP)/watch-library/hardware/hpl/port/ \ + -I$(TOP)/watch-library/hardware/hpl/sercom/ \ + -I$(TOP)/watch-library/hardware/hpl/slcd/ \ + -I$(TOP)/watch-library/hardware/hpl/systick/ \ + -I$(TOP)/watch-library/hardware/hri/ \ + -I$(TOP)/watch-library/hardware/hw/ \ + -I$(TOP)/watch-library/hardware/watch/ \ + -I$(TOP)/watch-library/hardware \ SRCS += \ $(TOP)/tinyusb/src/tusb.c \ @@ -72,55 +74,92 @@ SRCS += \ $(TOP)/tinyusb/src/device/usbd.c \ $(TOP)/tinyusb/src/device/usbd_control.c \ $(TOP)/tinyusb/src/portable/microchip/samd/dcd_samd.c \ - $(TOP)/watch-library/main.c \ - $(TOP)/watch-library/startup_saml22.c \ - $(TOP)/watch-library/hw/driver_init.c \ - $(TOP)/watch-library/watch/watch_rtc.c \ - $(TOP)/watch-library/watch/watch_slcd.c \ - $(TOP)/watch-library/watch/watch_extint.c \ - $(TOP)/watch-library/watch/watch_led.c \ - $(TOP)/watch-library/watch/watch_buzzer.c \ - $(TOP)/watch-library/watch/watch_adc.c \ - $(TOP)/watch-library/watch/watch_gpio.c \ - $(TOP)/watch-library/watch/watch_i2c.c \ - $(TOP)/watch-library/watch/watch_uart.c \ - $(TOP)/watch-library/watch/watch_deepsleep.c \ - $(TOP)/watch-library/watch/watch_utility.c \ - $(TOP)/watch-library/watch/watch_private.c \ - $(TOP)/watch-library/watch/watch.c \ - $(TOP)/watch-library/hal/src/hal_atomic.c \ - $(TOP)/watch-library/hal/src/hal_delay.c \ - $(TOP)/watch-library/hal/src/hal_ext_irq.c \ - $(TOP)/watch-library/hal/src/hal_gpio.c \ - $(TOP)/watch-library/hal/src/hal_i2c_m_sync.c \ - $(TOP)/watch-library/hal/src/hal_spi_m_sync.c \ - $(TOP)/watch-library/hal/src/hal_init.c \ - $(TOP)/watch-library/hal/src/hal_io.c \ - $(TOP)/watch-library/hal/src/hal_slcd_sync.c \ - $(TOP)/watch-library/hal/src/hal_sleep.c \ - $(TOP)/watch-library/hal/utils/src/utils_assert.c \ - $(TOP)/watch-library/hal/utils/src/utils_event.c \ - $(TOP)/watch-library/hal/utils/src/utils_list.c \ - $(TOP)/watch-library/hal/utils/src/utils_syscalls.c \ - $(TOP)/watch-library/hpl/core/hpl_core_m0plus_base.c \ - $(TOP)/watch-library/hpl/core/hpl_init.c \ - $(TOP)/watch-library/hpl/dmac/hpl_dmac.c \ - $(TOP)/watch-library/hpl/eic/hpl_eic.c \ - $(TOP)/watch-library/hpl/gclk/hpl_gclk.c \ - $(TOP)/watch-library/hpl/mclk/hpl_mclk.c \ - $(TOP)/watch-library/hpl/osc32kctrl/hpl_osc32kctrl.c \ - $(TOP)/watch-library/hpl/oscctrl/hpl_oscctrl.c \ - $(TOP)/watch-library/hpl/pm/hpl_pm.c \ - $(TOP)/watch-library/hpl/sercom/hpl_sercom.c \ - $(TOP)/watch-library/hpl/slcd/hpl_slcd.c \ - $(TOP)/watch-library/hpl/systick/hpl_systick.c \ - $(TOP)/watch-library/driver/lis2dh.c \ - $(TOP)/watch-library/driver/lis2dw.c \ + $(TOP)/watch-library/hardware/main.c \ + $(TOP)/watch-library/hardware/startup_saml22.c \ + $(TOP)/watch-library/hardware/hw/driver_init.c \ + $(TOP)/watch-library/hardware/watch/watch_rtc.c \ + $(TOP)/watch-library/hardware/watch/watch_slcd.c \ + $(TOP)/watch-library/hardware/watch/watch_extint.c \ + $(TOP)/watch-library/hardware/watch/watch_led.c \ + $(TOP)/watch-library/hardware/watch/watch_buzzer.c \ + $(TOP)/watch-library/hardware/watch/watch_adc.c \ + $(TOP)/watch-library/hardware/watch/watch_gpio.c \ + $(TOP)/watch-library/hardware/watch/watch_i2c.c \ + $(TOP)/watch-library/hardware/watch/watch_uart.c \ + $(TOP)/watch-library/hardware/watch/watch_deepsleep.c \ + $(TOP)/watch-library/hardware/watch/watch_private.c \ + $(TOP)/watch-library/hardware/watch/watch.c \ + $(TOP)/watch-library/hardware/hal/src/hal_atomic.c \ + $(TOP)/watch-library/hardware/hal/src/hal_delay.c \ + $(TOP)/watch-library/hardware/hal/src/hal_ext_irq.c \ + $(TOP)/watch-library/hardware/hal/src/hal_gpio.c \ + $(TOP)/watch-library/hardware/hal/src/hal_i2c_m_sync.c \ + $(TOP)/watch-library/hardware/hal/src/hal_spi_m_sync.c \ + $(TOP)/watch-library/hardware/hal/src/hal_init.c \ + $(TOP)/watch-library/hardware/hal/src/hal_io.c \ + $(TOP)/watch-library/hardware/hal/src/hal_slcd_sync.c \ + $(TOP)/watch-library/hardware/hal/src/hal_sleep.c \ + $(TOP)/watch-library/hardware/hal/utils/src/utils_assert.c \ + $(TOP)/watch-library/hardware/hal/utils/src/utils_event.c \ + $(TOP)/watch-library/hardware/hal/utils/src/utils_list.c \ + $(TOP)/watch-library/hardware/hal/utils/src/utils_syscalls.c \ + $(TOP)/watch-library/hardware/hpl/core/hpl_core_m0plus_base.c \ + $(TOP)/watch-library/hardware/hpl/core/hpl_init.c \ + $(TOP)/watch-library/hardware/hpl/dmac/hpl_dmac.c \ + $(TOP)/watch-library/hardware/hpl/eic/hpl_eic.c \ + $(TOP)/watch-library/hardware/hpl/gclk/hpl_gclk.c \ + $(TOP)/watch-library/hardware/hpl/mclk/hpl_mclk.c \ + $(TOP)/watch-library/hardware/hpl/osc32kctrl/hpl_osc32kctrl.c \ + $(TOP)/watch-library/hardware/hpl/oscctrl/hpl_oscctrl.c \ + $(TOP)/watch-library/hardware/hpl/pm/hpl_pm.c \ + $(TOP)/watch-library/hardware/hpl/sercom/hpl_sercom.c \ + $(TOP)/watch-library/hardware/hpl/slcd/hpl_slcd.c \ + $(TOP)/watch-library/hardware/hpl/systick/hpl_systick.c \ + $(TOP)/watch-library/shared/driver/lis2dh.c \ + $(TOP)/watch-library/shared/driver/lis2dw.c \ + $(TOP)/watch-library/shared/watch/watch_private_display.c \ + $(TOP)/watch-library/shared/watch/watch_utility.c \ DEFINES += \ -D__SAML22J18A__ \ -DDONT_USE_CMSIS_INIT +else + +CFLAGS += -W -Wall -Wextra -Wmissing-prototypes -Wmissing-declarations +CFLAGS += -Wno-format -Wno-unused-parameter + +INCLUDES += \ + -I$(TOP)/boards/$(BOARD) \ + -I$(TOP)/watch-library/shared/driver/ \ + -I$(TOP)/watch-library/shared/config/ \ + -I$(TOP)/watch-library/shared/watch/ \ + -I$(TOP)/watch-library/simulator/hpl/port/ \ + -I$(TOP)/watch-library/hardware/include/component \ + -I$(TOP)/watch-library/hardware/hal/include/ \ + -I$(TOP)/watch-library/hardware/hal/utils/include/ \ + -I$(TOP)/watch-library/hardware/hpl/slcd/ \ + -I$(TOP)/watch-library/hardware/hw/ \ + +SRCS += \ + $(TOP)/watch-library/simulator/main.c \ + $(TOP)/watch-library/simulator/watch/watch_rtc.c \ + $(TOP)/watch-library/simulator/watch/watch_slcd.c \ + $(TOP)/watch-library/simulator/watch/watch_extint.c \ + $(TOP)/watch-library/simulator/watch/watch_led.c \ + $(TOP)/watch-library/simulator/watch/watch_buzzer.c \ + $(TOP)/watch-library/simulator/watch/watch_adc.c \ + $(TOP)/watch-library/simulator/watch/watch_gpio.c \ + $(TOP)/watch-library/simulator/watch/watch_i2c.c \ + $(TOP)/watch-library/simulator/watch/watch_uart.c \ + $(TOP)/watch-library/simulator/watch/watch_deepsleep.c \ + $(TOP)/watch-library/simulator/watch/watch_private.c \ + $(TOP)/watch-library/simulator/watch/watch.c \ + $(TOP)/watch-library/shared/watch/watch_private_display.c \ + $(TOP)/watch-library/shared/watch/watch_utility.c \ + +endif + ifeq ($(LED), BLUE) CFLAGS += -DWATCH_SWAP_LED_PINS endif diff --git a/movement/README.md b/movement/README.md index 0e1c3b40..5d5b0e2f 100644 --- a/movement/README.md +++ b/movement/README.md @@ -22,13 +22,13 @@ A fifth optional function, `watch_face_wants_background_task`, will be added to To create a new watch face, you should create a new C header and source file in the watch-faces folder (i.e. for a watch face that displays moon phases: `moon_phase_face.h`, `moon_phase_face.c`), and implement these functions with your own unique prefix (i.e. `moon_phase_face_setup`). Then declare your watch face in your header file as follows: ```c -static const watch_face_t moon_phase_face = { - moon_phase_face_setup, - moon_phase_face_activate, - moon_phase_face_loop, - moon_phase_face_resign, - NULL // or moon_phase_face_wants_background_task, if you implemented this function -}; +#define moon_phase_face ((const watch_face_t){ \ + moon_phase_face_setup, \ + moon_phase_face_activate, \ + moon_phase_face_loop, \ + moon_phase_face_resign, \ + NULL, /* or moon_phase_face_wants_background_task, if you implemented this function */ \ +}) ``` This section will go over how each function works. The section headings use the watch_face prefix, but know that you should implement each function with your own prefix as described above. @@ -96,13 +96,13 @@ void pulsometer_face_activate(movement_settings_t *settings, void *context); bool pulsometer_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void pulsometer_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t pulsometer_face = { - pulsometer_face_setup, - pulsometer_face_activate, - pulsometer_face_loop, - pulsometer_face_resign, - NULL -}; +#define pulsometer_face ((const watch_face_t){ \ + pulsometer_face_setup, \ + pulsometer_face_activate, \ + pulsometer_face_loop, \ + pulsometer_face_resign, \ + NULL, \ +}) ``` ### pulsometer_face.c diff --git a/movement/lib/TOTP-MCU/TOTP.c b/movement/lib/TOTP-MCU/TOTP.c index d977d06e..02858611 100644 --- a/movement/lib/TOTP-MCU/TOTP.c +++ b/movement/lib/TOTP-MCU/TOTP.c @@ -17,7 +17,7 @@ void setTimezone(uint8_t timezone){ _timeZoneOffset = timezone; } -uint32_t TimeStruct2Timestamp(struct tm time){ +static uint32_t TimeStruct2Timestamp(struct tm time){ //time.tm_mon -= 1; //time.tm_year -= 1900; return mktime(&(time)) - (_timeZoneOffset * 3600) - 2208988800; diff --git a/movement/lib/TOTP-MCU/sha1.c b/movement/lib/TOTP-MCU/sha1.c index 3ac14856..21a24fa5 100644 --- a/movement/lib/TOTP-MCU/sha1.c +++ b/movement/lib/TOTP-MCU/sha1.c @@ -34,11 +34,11 @@ void init(void) { bufferOffset = 0; } -uint32_t rol32(uint32_t number, uint8_t bits) { +static uint32_t rol32(uint32_t number, uint8_t bits) { return ((number << bits) | (uint32_t)(number >> (32-bits))); } -void hashBlock(void) { +static void hashBlock(void) { uint8_t i; uint32_t a,b,c,d,e,t; @@ -75,7 +75,7 @@ void hashBlock(void) { state.w[4] += e; } -void addUncounted(uint8_t data) { +static void addUncounted(uint8_t data) { buffer.b[bufferOffset ^ 3] = data; bufferOffset++; if (bufferOffset == BLOCK_LENGTH) { @@ -97,7 +97,7 @@ void writeArray(uint8_t *buffer, uint8_t size){ } } -void pad(void) { +static void pad(void) { // Implement SHA-1 padding (fips180-2 ��5.1.1) // Pad with 0x80 followed by 0x00 until the end of the block diff --git a/movement/movement.c b/movement/movement.c index 3dc1c060..d15c349f 100644 --- a/movement/movement.c +++ b/movement/movement.c @@ -29,6 +29,10 @@ #include "movement.h" #include "movement_config.h" +#if __EMSCRIPTEN__ +#include +#endif + movement_state_t movement_state; void * watch_face_contexts[MOVEMENT_NUM_FACES]; watch_date_time scheduled_tasks[MOVEMENT_NUM_FACES]; @@ -149,7 +153,16 @@ static void _movement_handle_scheduled_tasks(void) { void movement_request_tick_frequency(uint8_t freq) { if (freq == 128) return; // Movement uses the 128 Hz tick internally - RTC->MODE2.INTENCLR.reg = 0xFE; // disable all callbacks except the 128 Hz one + + // disable all callbacks except the 128 Hz one +#if __EMSCRIPTEN__ + for (int i = 1; i < 128; i = i << 1) { + watch_rtc_disable_periodic_callback(i); + } +#else + RTC->MODE2.INTENCLR.reg = 0xFE; +#endif + movement_state.subsecond = 0; movement_state.tick_frequency = freq; if (freq) watch_rtc_register_periodic_callback(cb_tick, freq); @@ -215,6 +228,18 @@ void app_init(void) { movement_state.light_ticks = -1; movement_state.alarm_ticks = -1; _movement_reset_inactivity_countdown(); + +#if __EMSCRIPTEN__ + int32_t time_zone_offset = EM_ASM_INT({ + return -new Date().getTimezoneOffset(); + }); + for (int i = 0, count = sizeof(movement_timezone_offsets) / sizeof(movement_timezone_offsets[0]); i < count; i++) { + if (movement_timezone_offsets[i] == time_zone_offset) { + movement_state.settings.bit.time_zone = i; + break; + } + } +#endif } void app_wake_from_backup(void) { diff --git a/movement/watch_faces/clock/simple_clock_face.h b/movement/watch_faces/clock/simple_clock_face.h index 98f997bf..6e8665bf 100644 --- a/movement/watch_faces/clock/simple_clock_face.h +++ b/movement/watch_faces/clock/simple_clock_face.h @@ -39,12 +39,12 @@ bool simple_clock_face_loop(movement_event_t event, movement_settings_t *setting void simple_clock_face_resign(movement_settings_t *settings, void *context); bool simple_clock_face_wants_background_task(movement_settings_t *settings, void *context); -static const watch_face_t simple_clock_face = { - simple_clock_face_setup, - simple_clock_face_activate, - simple_clock_face_loop, - simple_clock_face_resign, - simple_clock_face_wants_background_task -}; +#define simple_clock_face ((const watch_face_t){ \ + simple_clock_face_setup, \ + simple_clock_face_activate, \ + simple_clock_face_loop, \ + simple_clock_face_resign, \ + simple_clock_face_wants_background_task, \ +}) #endif // SIMPLE_CLOCK_FACE_H_ diff --git a/movement/watch_faces/clock/world_clock_face.h b/movement/watch_faces/clock/world_clock_face.h index b519bc85..36960f53 100644 --- a/movement/watch_faces/clock/world_clock_face.h +++ b/movement/watch_faces/clock/world_clock_face.h @@ -46,12 +46,12 @@ void world_clock_face_resign(movement_settings_t *settings, void *context); uint8_t world_clock_face_get_weekday(uint16_t day, uint16_t month, uint16_t year); -static const watch_face_t world_clock_face = { - world_clock_face_setup, - world_clock_face_activate, - world_clock_face_loop, - world_clock_face_resign, - NULL -}; +#define world_clock_face ((const watch_face_t){ \ + world_clock_face_setup, \ + world_clock_face_activate, \ + world_clock_face_loop, \ + world_clock_face_resign, \ + NULL, \ +}) #endif // WORLD_CLOCK_FACE_H_ diff --git a/movement/watch_faces/complications/beats_face.c b/movement/watch_faces/complications/beats_face.c index d1466b33..df31ad1c 100644 --- a/movement/watch_faces/complications/beats_face.c +++ b/movement/watch_faces/complications/beats_face.c @@ -45,7 +45,7 @@ bool beats_face_loop(movement_event_t event, movement_settings_t *settings, void state->next_subsecond_update = (event.subsecond + 1 + (BEAT_REFRESH_FREQUENCY * 2 / 3)) % BEAT_REFRESH_FREQUENCY; state->last_centibeat_displayed = centibeats; } - sprintf(buf, "bt %6ld", centibeats); + sprintf(buf, "bt %6lu", centibeats); watch_display_string(buf, 0); break; @@ -53,7 +53,7 @@ bool beats_face_loop(movement_event_t event, movement_settings_t *settings, void if (!watch_tick_animation_is_running()) watch_start_tick_animation(432); date_time = watch_rtc_get_date_time(); centibeats = clock2beats(date_time.unit.hour, date_time.unit.minute, date_time.unit.second, event.subsecond, movement_timezone_offsets[settings->bit.time_zone]); - sprintf(buf, "bt %4ld ", centibeats / 100); + sprintf(buf, "bt %4lu ", centibeats / 100); watch_display_string(buf, 0); break; diff --git a/movement/watch_faces/complications/beats_face.h b/movement/watch_faces/complications/beats_face.h index f11126d1..2bbbc26d 100644 --- a/movement/watch_faces/complications/beats_face.h +++ b/movement/watch_faces/complications/beats_face.h @@ -14,12 +14,12 @@ void beats_face_activate(movement_settings_t *settings, void *context); bool beats_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void beats_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t beats_face = { - beats_face_setup, - beats_face_activate, - beats_face_loop, - beats_face_resign, - NULL -}; +#define beats_face ((const watch_face_t){ \ + beats_face_setup, \ + beats_face_activate, \ + beats_face_loop, \ + beats_face_resign, \ + NULL, \ +}) #endif // BEATS_FACE_H_ \ No newline at end of file diff --git a/movement/watch_faces/complications/blinky_face.h b/movement/watch_faces/complications/blinky_face.h index 14f0e143..e966ab1d 100644 --- a/movement/watch_faces/complications/blinky_face.h +++ b/movement/watch_faces/complications/blinky_face.h @@ -38,12 +38,12 @@ void blinky_face_activate(movement_settings_t *settings, void *context); bool blinky_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void blinky_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t blinky_face = { - blinky_face_setup, - blinky_face_activate, - blinky_face_loop, - blinky_face_resign, - NULL -}; +#define blinky_face ((const watch_face_t){ \ + blinky_face_setup, \ + blinky_face_activate, \ + blinky_face_loop, \ + blinky_face_resign, \ + NULL, \ +}) -#endif // BLINKY_FACE_H_ \ No newline at end of file +#endif // BLINKY_FACE_H_ diff --git a/movement/watch_faces/complications/countdown_face.h b/movement/watch_faces/complications/countdown_face.h index 1a5d2c78..657c6377 100644 --- a/movement/watch_faces/complications/countdown_face.h +++ b/movement/watch_faces/complications/countdown_face.h @@ -58,12 +58,12 @@ void countdown_face_activate(movement_settings_t *settings, void *context); bool countdown_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void countdown_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t countdown_face = { - countdown_face_setup, - countdown_face_activate, - countdown_face_loop, - countdown_face_resign, - NULL -}; +#define countdown_face ((const watch_face_t){ \ + countdown_face_setup, \ + countdown_face_activate, \ + countdown_face_loop, \ + countdown_face_resign, \ + NULL, \ +}) #endif // COUNTDOWN_FACE_H_ diff --git a/movement/watch_faces/complications/day_one_face.c b/movement/watch_faces/complications/day_one_face.c index 18d02d4d..99433990 100644 --- a/movement/watch_faces/complications/day_one_face.c +++ b/movement/watch_faces/complications/day_one_face.c @@ -37,7 +37,7 @@ static void _day_one_face_update(day_one_state_t state) { watch_date_time date_time = watch_rtc_get_date_time(); uint32_t julian_date = _day_one_face_juliandaynum(date_time.unit.year + WATCH_RTC_REFERENCE_YEAR, date_time.unit.month, date_time.unit.day); uint32_t julian_birthdate = _day_one_face_juliandaynum(state.birth_year, state.birth_month, state.birth_day); - sprintf(buf, "DA %6ld", julian_date - julian_birthdate); + sprintf(buf, "DA %6lu", julian_date - julian_birthdate); watch_display_string(buf, 0); } diff --git a/movement/watch_faces/complications/day_one_face.h b/movement/watch_faces/complications/day_one_face.h index f39c7927..ab8372bf 100644 --- a/movement/watch_faces/complications/day_one_face.h +++ b/movement/watch_faces/complications/day_one_face.h @@ -44,12 +44,12 @@ void day_one_face_activate(movement_settings_t *settings, void *context); bool day_one_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void day_one_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t day_one_face = { - day_one_face_setup, - day_one_face_activate, - day_one_face_loop, - day_one_face_resign, - NULL -}; +#define day_one_face ((const watch_face_t){ \ + day_one_face_setup, \ + day_one_face_activate, \ + day_one_face_loop, \ + day_one_face_resign, \ + NULL, \ +}) #endif // DAY_ONE_FACE_H_ diff --git a/movement/watch_faces/complications/pulsometer_face.h b/movement/watch_faces/complications/pulsometer_face.h index 65188604..600201e9 100644 --- a/movement/watch_faces/complications/pulsometer_face.h +++ b/movement/watch_faces/complications/pulsometer_face.h @@ -38,12 +38,12 @@ void pulsometer_face_activate(movement_settings_t *settings, void *context); bool pulsometer_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void pulsometer_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t pulsometer_face = { - pulsometer_face_setup, - pulsometer_face_activate, - pulsometer_face_loop, - pulsometer_face_resign, - NULL -}; +#define pulsometer_face ((const watch_face_t){ \ + pulsometer_face_setup, \ + pulsometer_face_activate, \ + pulsometer_face_loop, \ + pulsometer_face_resign, \ + NULL, \ +}) -#endif // PULSOMETER_FACE_H_ \ No newline at end of file +#endif // PULSOMETER_FACE_H_ diff --git a/movement/watch_faces/complications/stopwatch_face.h b/movement/watch_faces/complications/stopwatch_face.h index ff0c1796..c6e3aadb 100644 --- a/movement/watch_faces/complications/stopwatch_face.h +++ b/movement/watch_faces/complications/stopwatch_face.h @@ -15,12 +15,12 @@ void stopwatch_face_activate(movement_settings_t *settings, void *context); bool stopwatch_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void stopwatch_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t stopwatch_face = { - stopwatch_face_setup, - stopwatch_face_activate, - stopwatch_face_loop, - stopwatch_face_resign, - NULL -}; +#define stopwatch_face ((const watch_face_t){ \ + stopwatch_face_setup, \ + stopwatch_face_activate, \ + stopwatch_face_loop, \ + stopwatch_face_resign, \ + NULL, \ +}) -#endif // STOPWATCH_FACE_H_ \ No newline at end of file +#endif // STOPWATCH_FACE_H_ diff --git a/movement/watch_faces/complications/sunrise_sunset_face.h b/movement/watch_faces/complications/sunrise_sunset_face.h index 196b9db0..826d5e95 100644 --- a/movement/watch_faces/complications/sunrise_sunset_face.h +++ b/movement/watch_faces/complications/sunrise_sunset_face.h @@ -52,12 +52,12 @@ void sunrise_sunset_face_activate(movement_settings_t *settings, void *context); bool sunrise_sunset_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void sunrise_sunset_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t sunrise_sunset_face = { - sunrise_sunset_face_setup, - sunrise_sunset_face_activate, - sunrise_sunset_face_loop, - sunrise_sunset_face_resign, - NULL -}; +#define sunrise_sunset_face ((const watch_face_t){ \ + sunrise_sunset_face_setup, \ + sunrise_sunset_face_activate, \ + sunrise_sunset_face_loop, \ + sunrise_sunset_face_resign, \ + NULL, \ +}) #endif // SUNRISE_SUNSET_FACE_H_ diff --git a/movement/watch_faces/complications/totp_face.h b/movement/watch_faces/complications/totp_face.h index 1e2c5c02..dfa4a6d0 100644 --- a/movement/watch_faces/complications/totp_face.h +++ b/movement/watch_faces/complications/totp_face.h @@ -15,12 +15,12 @@ void totp_face_activate(movement_settings_t *settings, void *context); bool totp_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void totp_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t totp_face = { - totp_face_setup, - totp_face_activate, - totp_face_loop, - totp_face_resign, - NULL -}; +#define totp_face ((const watch_face_t){ \ + totp_face_setup, \ + totp_face_activate, \ + totp_face_loop, \ + totp_face_resign, \ + NULL, \ +}) #endif // TOTP_FACE_H_ diff --git a/movement/watch_faces/demos/character_set_face.h b/movement/watch_faces/demos/character_set_face.h index a6c8e17d..82627aed 100644 --- a/movement/watch_faces/demos/character_set_face.h +++ b/movement/watch_faces/demos/character_set_face.h @@ -32,12 +32,12 @@ void character_set_face_activate(movement_settings_t *settings, void *context); bool character_set_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void character_set_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t character_set_face = { - character_set_face_setup, - character_set_face_activate, - character_set_face_loop, - character_set_face_resign, - NULL -}; +#define character_set_face ((const watch_face_t){ \ + character_set_face_setup, \ + character_set_face_activate, \ + character_set_face_loop, \ + character_set_face_resign, \ + NULL, \ +}) -#endif // CHARACTER_SET_FACE_H_ \ No newline at end of file +#endif // CHARACTER_SET_FACE_H_ diff --git a/movement/watch_faces/demos/demo_face.h b/movement/watch_faces/demos/demo_face.h index 6eb4298d..026e0d10 100644 --- a/movement/watch_faces/demos/demo_face.h +++ b/movement/watch_faces/demos/demo_face.h @@ -32,12 +32,12 @@ void demo_face_activate(movement_settings_t *settings, void *context); bool demo_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void demo_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t demo_face = { - demo_face_setup, - demo_face_activate, - demo_face_loop, - demo_face_resign, - NULL -}; +#define demo_face ((const watch_face_t){ \ + demo_face_setup, \ + demo_face_activate, \ + demo_face_loop, \ + demo_face_resign, \ + NULL, \ +}) -#endif // DEMO_FACE_H_ \ No newline at end of file +#endif // DEMO_FACE_H_ diff --git a/movement/watch_faces/demos/hello_there_face.h b/movement/watch_faces/demos/hello_there_face.h index c444e016..1140bb20 100644 --- a/movement/watch_faces/demos/hello_there_face.h +++ b/movement/watch_faces/demos/hello_there_face.h @@ -37,12 +37,12 @@ void hello_there_face_activate(movement_settings_t *settings, void *context); bool hello_there_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void hello_there_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t hello_there_face = { - hello_there_face_setup, - hello_there_face_activate, - hello_there_face_loop, - hello_there_face_resign, - NULL -}; +#define hello_there_face ((const watch_face_t){ \ + hello_there_face_setup, \ + hello_there_face_activate, \ + hello_there_face_loop, \ + hello_there_face_resign, \ + NULL, \ +}) #endif // HELLO_THERE_FACE_H_ diff --git a/movement/watch_faces/demos/lis2dh_logging_face.c b/movement/watch_faces/demos/lis2dh_logging_face.c index 08b265b6..31d1cad7 100644 --- a/movement/watch_faces/demos/lis2dh_logging_face.c +++ b/movement/watch_faces/demos/lis2dh_logging_face.c @@ -36,10 +36,11 @@ // Pressing the alarm button enters the log mode, where the main display shows the number of interrupts detected in each of the last // 24 hours (the hour is shown in the top right digit and AM/PM indicator, if the clock is set to 12 hour mode) -static void _lis2dh_logging_face_update_display(movement_settings_t *settings, lis2dh_logger_state_t *logger_state, lis2dh_interrupt_state interrupt_state, watch_date_time date_time) { +static void _lis2dh_logging_face_update_display(movement_settings_t *settings, lis2dh_logger_state_t *logger_state, lis2dh_interrupt_state interrupt_state) { char buf[14]; char time_indication_character; int8_t pos; + watch_date_time date_time; if (logger_state->log_ticks) { pos = (logger_state->data_points - 1 - logger_state->display_index) % LIS2DH_LOGGING_NUM_DATA_POINTS; @@ -58,16 +59,16 @@ static void _lis2dh_logging_face_update_display(movement_settings_t *settings, l } switch (logger_state->axis_index) { case 0: - sprintf(buf, "3A%2d%02d%4ld", date_time.unit.hour, date_time.unit.minute, logger_state->data[pos].x_interrupts + logger_state->data[pos].y_interrupts + logger_state->data[pos].z_interrupts); + sprintf(buf, "3A%2d%02d%4lu", date_time.unit.hour, date_time.unit.minute, logger_state->data[pos].x_interrupts + logger_state->data[pos].y_interrupts + logger_state->data[pos].z_interrupts); break; case 1: - sprintf(buf, "XA%2d%02d%4ld", date_time.unit.hour, date_time.unit.minute, logger_state->data[pos].x_interrupts); + sprintf(buf, "XA%2d%02d%4lu", date_time.unit.hour, date_time.unit.minute, logger_state->data[pos].x_interrupts); break; case 2: - sprintf(buf, "YA%2d%02d%4ld", date_time.unit.hour, date_time.unit.minute, logger_state->data[pos].y_interrupts); + sprintf(buf, "YA%2d%02d%4lu", date_time.unit.hour, date_time.unit.minute, logger_state->data[pos].y_interrupts); break; case 3: - sprintf(buf, "ZA%2d%02d%4ld", date_time.unit.hour, date_time.unit.minute, logger_state->data[pos].z_interrupts); + sprintf(buf, "ZA%2d%02d%4lu", date_time.unit.hour, date_time.unit.minute, logger_state->data[pos].z_interrupts); break; } } @@ -145,7 +146,6 @@ void lis2dh_logging_face_activate(movement_settings_t *settings, void *context) bool lis2dh_logging_face_loop(movement_event_t event, movement_settings_t *settings, void *context) { lis2dh_logger_state_t *logger_state = (lis2dh_logger_state_t *)context; lis2dh_interrupt_state interrupt_state = 0; - watch_date_time date_time; switch (event.event_type) { case EVENT_MODE_BUTTON_UP: @@ -157,13 +157,13 @@ bool lis2dh_logging_face_loop(movement_event_t event, movement_settings_t *setti case EVENT_LIGHT_BUTTON_DOWN: logger_state->axis_index = (logger_state->axis_index + 1) % 4; logger_state->log_ticks = 255; - _lis2dh_logging_face_update_display(settings, logger_state, interrupt_state, date_time); + _lis2dh_logging_face_update_display(settings, logger_state, interrupt_state); break; case EVENT_ALARM_BUTTON_UP: if (logger_state->log_ticks) logger_state->display_index = (logger_state->display_index + 1) % LIS2DH_LOGGING_NUM_DATA_POINTS; logger_state->log_ticks = 255; logger_state->axis_index = 0; - _lis2dh_logging_face_update_display(settings, logger_state, interrupt_state, date_time); + _lis2dh_logging_face_update_display(settings, logger_state, interrupt_state); break; case EVENT_ACTIVATE: case EVENT_TICK: @@ -182,7 +182,7 @@ bool lis2dh_logging_face_loop(movement_event_t event, movement_settings_t *setti } else { watch_clear_indicator(WATCH_INDICATOR_SIGNAL); } - _lis2dh_logging_face_update_display(settings, logger_state, interrupt_state, date_time); + _lis2dh_logging_face_update_display(settings, logger_state, interrupt_state); break; case EVENT_BACKGROUND_TASK: _lis2dh_logging_face_log_data(logger_state); diff --git a/movement/watch_faces/demos/lis2dh_logging_face.h b/movement/watch_faces/demos/lis2dh_logging_face.h index 22ecd2d9..49366542 100644 --- a/movement/watch_faces/demos/lis2dh_logging_face.h +++ b/movement/watch_faces/demos/lis2dh_logging_face.h @@ -55,12 +55,12 @@ bool lis2dh_logging_face_loop(movement_event_t event, movement_settings_t *setti void lis2dh_logging_face_resign(movement_settings_t *settings, void *context); bool lis2dh_logging_face_wants_background_task(movement_settings_t *settings, void *context); -static const watch_face_t lis2dh_logging_face = { - lis2dh_logging_face_setup, - lis2dh_logging_face_activate, - lis2dh_logging_face_loop, - lis2dh_logging_face_resign, - lis2dh_logging_face_wants_background_task -}; +#define lis2dh_logging_face ((const watch_face_t){ \ + lis2dh_logging_face_setup, \ + lis2dh_logging_face_activate, \ + lis2dh_logging_face_loop, \ + lis2dh_logging_face_resign, \ + lis2dh_logging_face_wants_background_task, \ +}) #endif // LIS2DH_LOGGING_FACE_H_ diff --git a/movement/watch_faces/demos/voltage_face.c b/movement/watch_faces/demos/voltage_face.c index 4e5fecc1..24346aa3 100644 --- a/movement/watch_faces/demos/voltage_face.c +++ b/movement/watch_faces/demos/voltage_face.c @@ -86,6 +86,6 @@ void voltage_face_resign(movement_settings_t *settings, void *context) { (void) settings; (void) context; // make sure to restore the default in the end. - watch_set_analog_reference_voltage(ADC_REFCTRL_REFSEL_INTVCC2_Val); + watch_set_analog_reference_voltage(ADC_REFERENCE_VCC); watch_disable_adc(); } diff --git a/movement/watch_faces/demos/voltage_face.h b/movement/watch_faces/demos/voltage_face.h index 07d9e473..dc5e631b 100644 --- a/movement/watch_faces/demos/voltage_face.h +++ b/movement/watch_faces/demos/voltage_face.h @@ -32,12 +32,12 @@ void voltage_face_activate(movement_settings_t *settings, void *context); bool voltage_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void voltage_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t voltage_face = { - voltage_face_setup, - voltage_face_activate, - voltage_face_loop, - voltage_face_resign, - NULL -}; +#define voltage_face ((const watch_face_t){ \ + voltage_face_setup, \ + voltage_face_activate, \ + voltage_face_loop, \ + voltage_face_resign, \ + NULL, \ +}) -#endif // VOLTAGE_FACE_H_ \ No newline at end of file +#endif // VOLTAGE_FACE_H_ diff --git a/movement/watch_faces/settings/preferences_face.h b/movement/watch_faces/settings/preferences_face.h index 11f9dc43..b178bfd2 100644 --- a/movement/watch_faces/settings/preferences_face.h +++ b/movement/watch_faces/settings/preferences_face.h @@ -32,12 +32,12 @@ void preferences_face_activate(movement_settings_t *settings, void *context); bool preferences_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void preferences_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t preferences_face = { - preferences_face_setup, - preferences_face_activate, - preferences_face_loop, - preferences_face_resign, - NULL -}; +#define preferences_face ((const watch_face_t){ \ + preferences_face_setup, \ + preferences_face_activate, \ + preferences_face_loop, \ + preferences_face_resign, \ + NULL, \ +}) -#endif // PREFERENCES_FACE_H_ \ No newline at end of file +#endif // PREFERENCES_FACE_H_ diff --git a/movement/watch_faces/settings/set_time_face.h b/movement/watch_faces/settings/set_time_face.h index ebc3d8d4..c86b6376 100644 --- a/movement/watch_faces/settings/set_time_face.h +++ b/movement/watch_faces/settings/set_time_face.h @@ -32,12 +32,12 @@ void set_time_face_activate(movement_settings_t *settings, void *context); bool set_time_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void set_time_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t set_time_face = { - set_time_face_setup, - set_time_face_activate, - set_time_face_loop, - set_time_face_resign, - NULL -}; +#define set_time_face ((const watch_face_t){ \ + set_time_face_setup, \ + set_time_face_activate, \ + set_time_face_loop, \ + set_time_face_resign, \ + NULL, \ +}) #endif // SET_TIME_FACE_H_ diff --git a/movement/watch_faces/thermistor/thermistor_logging_face.h b/movement/watch_faces/thermistor/thermistor_logging_face.h index effb8822..4ba593ec 100644 --- a/movement/watch_faces/thermistor/thermistor_logging_face.h +++ b/movement/watch_faces/thermistor/thermistor_logging_face.h @@ -48,12 +48,12 @@ bool thermistor_logging_face_loop(movement_event_t event, movement_settings_t *s void thermistor_logging_face_resign(movement_settings_t *settings, void *context); bool thermistor_logging_face_wants_background_task(movement_settings_t *settings, void *context); -static const watch_face_t thermistor_logging_face = { - thermistor_logging_face_setup, - thermistor_logging_face_activate, - thermistor_logging_face_loop, - thermistor_logging_face_resign, - thermistor_logging_face_wants_background_task -}; +#define thermistor_logging_face ((const watch_face_t){ \ + thermistor_logging_face_setup, \ + thermistor_logging_face_activate, \ + thermistor_logging_face_loop, \ + thermistor_logging_face_resign, \ + thermistor_logging_face_wants_background_task, \ +}) #endif // THERMISTOR_LOGGING_FACE_H_ diff --git a/movement/watch_faces/thermistor/thermistor_readout_face.h b/movement/watch_faces/thermistor/thermistor_readout_face.h index 5b14fc5b..7361164e 100644 --- a/movement/watch_faces/thermistor/thermistor_readout_face.h +++ b/movement/watch_faces/thermistor/thermistor_readout_face.h @@ -32,12 +32,12 @@ void thermistor_readout_face_activate(movement_settings_t *settings, void *conte bool thermistor_readout_face_loop(movement_event_t event, movement_settings_t *settings, void *context); void thermistor_readout_face_resign(movement_settings_t *settings, void *context); -static const watch_face_t thermistor_readout_face = { - thermistor_readout_face_setup, - thermistor_readout_face_activate, - thermistor_readout_face_loop, - thermistor_readout_face_resign, - NULL -}; +#define thermistor_readout_face ((const watch_face_t){ \ + thermistor_readout_face_setup, \ + thermistor_readout_face_activate, \ + thermistor_readout_face_loop, \ + thermistor_readout_face_resign, \ + NULL, \ +}) #endif // THERMISTOR_READOUT_FACE_H_ diff --git a/rules.mk b/rules.mk index f0979f3f..cd42a433 100644 --- a/rules.mk +++ b/rules.mk @@ -4,7 +4,17 @@ OBJS = $(addprefix $(BUILD)/, $(notdir %/$(subst .c,.o, $(SRCS)))) SUBMODULES = tinyusb +ifndef EMSCRIPTEN all: directory $(SUBMODULES) $(BUILD)/$(BIN).elf $(BUILD)/$(BIN).hex $(BUILD)/$(BIN).bin $(BUILD)/$(BIN).uf2 size +else +all: directory $(SUBMODULES) $(BUILD)/$(BIN).html +endif + +$(BUILD)/$(BIN).html: $(OBJS) + @echo HTML $@ + @$(CC) $(LDFLAGS) $(OBJS) $(LIBS) -o $@ \ + -s EXPORTED_FUNCTIONS=_main \ + --shell-file=$(TOP)/watch-library/simulator/shell.html $(BUILD)/$(BIN).elf: $(OBJS) @echo LD $@ diff --git a/watch-library/config/RTE_Components.h b/watch-library/config/RTE_Components.h deleted file mode 100644 index 3ba6b1ba..00000000 --- a/watch-library/config/RTE_Components.h +++ /dev/null @@ -1,54 +0,0 @@ - /** - * \file - * - * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME) - * - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \acme_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \acme_license_stop - * - * Project: My Project - * Target: ATSAML22J18A - * - **/ - - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -#define ATMEL_START - -#endif /* RTE_COMPONENTS_H */ diff --git a/watch-library/config/hpl_dmac_config.h b/watch-library/config/hpl_dmac_config.h deleted file mode 100644 index 36adb88b..00000000 --- a/watch-library/config/hpl_dmac_config.h +++ /dev/null @@ -1,3122 +0,0 @@ -/* Auto-generated config file hpl_dmac_config.h */ -#ifndef HPL_DMAC_CONFIG_H -#define HPL_DMAC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// DMAC enable -// Indicates whether dmac is enabled or not -// dmac_enable -#ifndef CONF_DMAC_ENABLE -#define CONF_DMAC_ENABLE 0 -#endif - -// Priority Level 0 -// Indicates whether Priority Level 0 is enabled or not -// dmac_lvlen0 -#ifndef CONF_DMAC_LVLEN0 -#define CONF_DMAC_LVLEN0 0 -#endif - -// Level 0 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 0 -// <1=> Round-robin arbitration scheme for channel with priority 0 -// Defines Level 0 Arbitration for DMA channels -// dmac_rrlvlen0 -#ifndef CONF_DMAC_RRLVLEN0 -#define CONF_DMAC_RRLVLEN0 0 -#endif - -// Level 0 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri0 -#ifndef CONF_DMAC_LVLPRI0 -#define CONF_DMAC_LVLPRI0 0 -#endif - -// Priority Level 1 -// Indicates whether Priority Level 1 is enabled or not -// dmac_lvlen1 -#ifndef CONF_DMAC_LVLEN1 -#define CONF_DMAC_LVLEN1 0 -#endif - -// Level 1 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 1 -// <1=> Round-robin arbitration scheme for channel with priority 1 -// Defines Level 1 Arbitration for DMA channels -// dmac_rrlvlen1 -#ifndef CONF_DMAC_RRLVLEN1 -#define CONF_DMAC_RRLVLEN1 0 -#endif - -// Level 1 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri1 -#ifndef CONF_DMAC_LVLPRI1 -#define CONF_DMAC_LVLPRI1 0 -#endif - -// Priority Level 2 -// Indicates whether Priority Level 2 is enabled or not -// dmac_lvlen2 -#ifndef CONF_DMAC_LVLEN2 -#define CONF_DMAC_LVLEN2 0 -#endif - -// Level 2 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 2 -// <1=> Round-robin arbitration scheme for channel with priority 2 -// Defines Level 2 Arbitration for DMA channels -// dmac_rrlvlen2 -#ifndef CONF_DMAC_RRLVLEN2 -#define CONF_DMAC_RRLVLEN2 0 -#endif - -// Level 2 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri2 -#ifndef CONF_DMAC_LVLPRI2 -#define CONF_DMAC_LVLPRI2 0 -#endif - -// Priority Level 3 -// Indicates whether Priority Level 3 is enabled or not -// dmac_lvlen3 -#ifndef CONF_DMAC_LVLEN3 -#define CONF_DMAC_LVLEN3 0 -#endif - -// Level 3 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 3 -// <1=> Round-robin arbitration scheme for channel with priority 3 -// Defines Level 3 Arbitration for DMA channels -// dmac_rrlvlen3 -#ifndef CONF_DMAC_RRLVLEN3 -#define CONF_DMAC_RRLVLEN3 0 -#endif - -// Level 3 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri3 -#ifndef CONF_DMAC_LVLPRI3 -#define CONF_DMAC_LVLPRI3 0 -#endif - -// Data Transfer Quality of Service -// <0=> Background (no sensitive operation) -// <1=> Sensitive bandwidth -// <2=> Sensitive latency -// <3=> Critical latency -// Defines the memory priority access during the data transfer operation -// dmac_dqos -#ifndef CONF_DMAC_DQOS -#define CONF_DMAC_DQOS 0 -#endif - -// Fetch Quality of Service -// <0=> Background (no sensitive operation) -// <1=> Sensitive bandwidth -// <2=> Sensitive latency -// <3=> Critical latency -// Defines the memory priority access during the fetch operation -// dmac_fqos -#ifndef CONF_DMAC_FQOS -#define CONF_DMAC_FQOS 0 -#endif - -// Write-Back Quality of Service -// <0=> Background (no sensitive operation) -// <1=> Sensitive bandwidth -// <2=> Sensitive latency -// <3=> Critical latency -// Defines the memory priority access during the write-back operation -// dmac_wrbqos -#ifndef CONF_DMAC_WRBQOS -#define CONF_DMAC_WRBQOS 0 -#endif - -// Debug Run -// Indicates whether Debug Run is enabled or not -// dmac_dbgrun -#ifndef CONF_DMAC_DBGRUN -#define CONF_DMAC_DBGRUN 0 -#endif - -// Channel 0 settings -// dmac_channel_0_settings -#ifndef CONF_DMAC_CHANNEL_0_SETTINGS -#define CONF_DMAC_CHANNEL_0_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 0 is enabled or not -// dmac_enable_0 -#ifndef CONF_DMAC_ENABLE_0 -#define CONF_DMAC_ENABLE_0 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 0 is running in standby mode or not -// dmac_runstdby_0 -#ifndef CONF_DMAC_RUNSTDBY_0 -#define CONF_DMAC_RUNSTDBY_0 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_0 -#ifndef CONF_DMAC_TRIGACT_0 -#define CONF_DMAC_TRIGACT_0 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_0 -#ifndef CONF_DMAC_TRIGSRC_0 -#define CONF_DMAC_TRIGSRC_0 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_0 -#ifndef CONF_DMAC_LVL_0 -#define CONF_DMAC_LVL_0 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_0 -#ifndef CONF_DMAC_EVOE_0 -#define CONF_DMAC_EVOE_0 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_0 -#ifndef CONF_DMAC_EVIE_0 -#define CONF_DMAC_EVIE_0 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_0 -#ifndef CONF_DMAC_EVACT_0 -#define CONF_DMAC_EVACT_0 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_0 -#ifndef CONF_DMAC_STEPSIZE_0 -#define CONF_DMAC_STEPSIZE_0 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_0 -#ifndef CONF_DMAC_STEPSEL_0 -#define CONF_DMAC_STEPSEL_0 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_0 -#ifndef CONF_DMAC_SRCINC_0 -#define CONF_DMAC_SRCINC_0 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_0 -#ifndef CONF_DMAC_DSTINC_0 -#define CONF_DMAC_DSTINC_0 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_0 -#ifndef CONF_DMAC_BEATSIZE_0 -#define CONF_DMAC_BEATSIZE_0 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_0 -#ifndef CONF_DMAC_BLOCKACT_0 -#define CONF_DMAC_BLOCKACT_0 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_0 -#ifndef CONF_DMAC_EVOSEL_0 -#define CONF_DMAC_EVOSEL_0 0 -#endif -// - -// Channel 1 settings -// dmac_channel_1_settings -#ifndef CONF_DMAC_CHANNEL_1_SETTINGS -#define CONF_DMAC_CHANNEL_1_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 1 is enabled or not -// dmac_enable_1 -#ifndef CONF_DMAC_ENABLE_1 -#define CONF_DMAC_ENABLE_1 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 1 is running in standby mode or not -// dmac_runstdby_1 -#ifndef CONF_DMAC_RUNSTDBY_1 -#define CONF_DMAC_RUNSTDBY_1 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_1 -#ifndef CONF_DMAC_TRIGACT_1 -#define CONF_DMAC_TRIGACT_1 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_1 -#ifndef CONF_DMAC_TRIGSRC_1 -#define CONF_DMAC_TRIGSRC_1 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_1 -#ifndef CONF_DMAC_LVL_1 -#define CONF_DMAC_LVL_1 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_1 -#ifndef CONF_DMAC_EVOE_1 -#define CONF_DMAC_EVOE_1 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_1 -#ifndef CONF_DMAC_EVIE_1 -#define CONF_DMAC_EVIE_1 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_1 -#ifndef CONF_DMAC_EVACT_1 -#define CONF_DMAC_EVACT_1 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_1 -#ifndef CONF_DMAC_STEPSIZE_1 -#define CONF_DMAC_STEPSIZE_1 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_1 -#ifndef CONF_DMAC_STEPSEL_1 -#define CONF_DMAC_STEPSEL_1 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_1 -#ifndef CONF_DMAC_SRCINC_1 -#define CONF_DMAC_SRCINC_1 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_1 -#ifndef CONF_DMAC_DSTINC_1 -#define CONF_DMAC_DSTINC_1 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_1 -#ifndef CONF_DMAC_BEATSIZE_1 -#define CONF_DMAC_BEATSIZE_1 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_1 -#ifndef CONF_DMAC_BLOCKACT_1 -#define CONF_DMAC_BLOCKACT_1 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_1 -#ifndef CONF_DMAC_EVOSEL_1 -#define CONF_DMAC_EVOSEL_1 0 -#endif -// - -// Channel 2 settings -// dmac_channel_2_settings -#ifndef CONF_DMAC_CHANNEL_2_SETTINGS -#define CONF_DMAC_CHANNEL_2_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 2 is enabled or not -// dmac_enable_2 -#ifndef CONF_DMAC_ENABLE_2 -#define CONF_DMAC_ENABLE_2 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 2 is running in standby mode or not -// dmac_runstdby_2 -#ifndef CONF_DMAC_RUNSTDBY_2 -#define CONF_DMAC_RUNSTDBY_2 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_2 -#ifndef CONF_DMAC_TRIGACT_2 -#define CONF_DMAC_TRIGACT_2 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_2 -#ifndef CONF_DMAC_TRIGSRC_2 -#define CONF_DMAC_TRIGSRC_2 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_2 -#ifndef CONF_DMAC_LVL_2 -#define CONF_DMAC_LVL_2 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_2 -#ifndef CONF_DMAC_EVOE_2 -#define CONF_DMAC_EVOE_2 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_2 -#ifndef CONF_DMAC_EVIE_2 -#define CONF_DMAC_EVIE_2 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_2 -#ifndef CONF_DMAC_EVACT_2 -#define CONF_DMAC_EVACT_2 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_2 -#ifndef CONF_DMAC_STEPSIZE_2 -#define CONF_DMAC_STEPSIZE_2 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_2 -#ifndef CONF_DMAC_STEPSEL_2 -#define CONF_DMAC_STEPSEL_2 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_2 -#ifndef CONF_DMAC_SRCINC_2 -#define CONF_DMAC_SRCINC_2 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_2 -#ifndef CONF_DMAC_DSTINC_2 -#define CONF_DMAC_DSTINC_2 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_2 -#ifndef CONF_DMAC_BEATSIZE_2 -#define CONF_DMAC_BEATSIZE_2 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_2 -#ifndef CONF_DMAC_BLOCKACT_2 -#define CONF_DMAC_BLOCKACT_2 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_2 -#ifndef CONF_DMAC_EVOSEL_2 -#define CONF_DMAC_EVOSEL_2 0 -#endif -// - -// Channel 3 settings -// dmac_channel_3_settings -#ifndef CONF_DMAC_CHANNEL_3_SETTINGS -#define CONF_DMAC_CHANNEL_3_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 3 is enabled or not -// dmac_enable_3 -#ifndef CONF_DMAC_ENABLE_3 -#define CONF_DMAC_ENABLE_3 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 3 is running in standby mode or not -// dmac_runstdby_3 -#ifndef CONF_DMAC_RUNSTDBY_3 -#define CONF_DMAC_RUNSTDBY_3 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_3 -#ifndef CONF_DMAC_TRIGACT_3 -#define CONF_DMAC_TRIGACT_3 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_3 -#ifndef CONF_DMAC_TRIGSRC_3 -#define CONF_DMAC_TRIGSRC_3 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_3 -#ifndef CONF_DMAC_LVL_3 -#define CONF_DMAC_LVL_3 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_3 -#ifndef CONF_DMAC_EVOE_3 -#define CONF_DMAC_EVOE_3 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_3 -#ifndef CONF_DMAC_EVIE_3 -#define CONF_DMAC_EVIE_3 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_3 -#ifndef CONF_DMAC_EVACT_3 -#define CONF_DMAC_EVACT_3 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_3 -#ifndef CONF_DMAC_STEPSIZE_3 -#define CONF_DMAC_STEPSIZE_3 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_3 -#ifndef CONF_DMAC_STEPSEL_3 -#define CONF_DMAC_STEPSEL_3 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_3 -#ifndef CONF_DMAC_SRCINC_3 -#define CONF_DMAC_SRCINC_3 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_3 -#ifndef CONF_DMAC_DSTINC_3 -#define CONF_DMAC_DSTINC_3 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_3 -#ifndef CONF_DMAC_BEATSIZE_3 -#define CONF_DMAC_BEATSIZE_3 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_3 -#ifndef CONF_DMAC_BLOCKACT_3 -#define CONF_DMAC_BLOCKACT_3 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_3 -#ifndef CONF_DMAC_EVOSEL_3 -#define CONF_DMAC_EVOSEL_3 0 -#endif -// - -// Channel 4 settings -// dmac_channel_4_settings -#ifndef CONF_DMAC_CHANNEL_4_SETTINGS -#define CONF_DMAC_CHANNEL_4_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 4 is enabled or not -// dmac_enable_4 -#ifndef CONF_DMAC_ENABLE_4 -#define CONF_DMAC_ENABLE_4 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 4 is running in standby mode or not -// dmac_runstdby_4 -#ifndef CONF_DMAC_RUNSTDBY_4 -#define CONF_DMAC_RUNSTDBY_4 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_4 -#ifndef CONF_DMAC_TRIGACT_4 -#define CONF_DMAC_TRIGACT_4 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_4 -#ifndef CONF_DMAC_TRIGSRC_4 -#define CONF_DMAC_TRIGSRC_4 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_4 -#ifndef CONF_DMAC_LVL_4 -#define CONF_DMAC_LVL_4 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_4 -#ifndef CONF_DMAC_EVOE_4 -#define CONF_DMAC_EVOE_4 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_4 -#ifndef CONF_DMAC_EVIE_4 -#define CONF_DMAC_EVIE_4 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_4 -#ifndef CONF_DMAC_EVACT_4 -#define CONF_DMAC_EVACT_4 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_4 -#ifndef CONF_DMAC_STEPSIZE_4 -#define CONF_DMAC_STEPSIZE_4 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_4 -#ifndef CONF_DMAC_STEPSEL_4 -#define CONF_DMAC_STEPSEL_4 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_4 -#ifndef CONF_DMAC_SRCINC_4 -#define CONF_DMAC_SRCINC_4 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_4 -#ifndef CONF_DMAC_DSTINC_4 -#define CONF_DMAC_DSTINC_4 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_4 -#ifndef CONF_DMAC_BEATSIZE_4 -#define CONF_DMAC_BEATSIZE_4 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_4 -#ifndef CONF_DMAC_BLOCKACT_4 -#define CONF_DMAC_BLOCKACT_4 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_4 -#ifndef CONF_DMAC_EVOSEL_4 -#define CONF_DMAC_EVOSEL_4 0 -#endif -// - -// Channel 5 settings -// dmac_channel_5_settings -#ifndef CONF_DMAC_CHANNEL_5_SETTINGS -#define CONF_DMAC_CHANNEL_5_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 5 is enabled or not -// dmac_enable_5 -#ifndef CONF_DMAC_ENABLE_5 -#define CONF_DMAC_ENABLE_5 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 5 is running in standby mode or not -// dmac_runstdby_5 -#ifndef CONF_DMAC_RUNSTDBY_5 -#define CONF_DMAC_RUNSTDBY_5 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_5 -#ifndef CONF_DMAC_TRIGACT_5 -#define CONF_DMAC_TRIGACT_5 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_5 -#ifndef CONF_DMAC_TRIGSRC_5 -#define CONF_DMAC_TRIGSRC_5 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_5 -#ifndef CONF_DMAC_LVL_5 -#define CONF_DMAC_LVL_5 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_5 -#ifndef CONF_DMAC_EVOE_5 -#define CONF_DMAC_EVOE_5 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_5 -#ifndef CONF_DMAC_EVIE_5 -#define CONF_DMAC_EVIE_5 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_5 -#ifndef CONF_DMAC_EVACT_5 -#define CONF_DMAC_EVACT_5 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_5 -#ifndef CONF_DMAC_STEPSIZE_5 -#define CONF_DMAC_STEPSIZE_5 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_5 -#ifndef CONF_DMAC_STEPSEL_5 -#define CONF_DMAC_STEPSEL_5 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_5 -#ifndef CONF_DMAC_SRCINC_5 -#define CONF_DMAC_SRCINC_5 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_5 -#ifndef CONF_DMAC_DSTINC_5 -#define CONF_DMAC_DSTINC_5 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_5 -#ifndef CONF_DMAC_BEATSIZE_5 -#define CONF_DMAC_BEATSIZE_5 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_5 -#ifndef CONF_DMAC_BLOCKACT_5 -#define CONF_DMAC_BLOCKACT_5 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_5 -#ifndef CONF_DMAC_EVOSEL_5 -#define CONF_DMAC_EVOSEL_5 0 -#endif -// - -// Channel 6 settings -// dmac_channel_6_settings -#ifndef CONF_DMAC_CHANNEL_6_SETTINGS -#define CONF_DMAC_CHANNEL_6_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 6 is enabled or not -// dmac_enable_6 -#ifndef CONF_DMAC_ENABLE_6 -#define CONF_DMAC_ENABLE_6 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 6 is running in standby mode or not -// dmac_runstdby_6 -#ifndef CONF_DMAC_RUNSTDBY_6 -#define CONF_DMAC_RUNSTDBY_6 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_6 -#ifndef CONF_DMAC_TRIGACT_6 -#define CONF_DMAC_TRIGACT_6 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_6 -#ifndef CONF_DMAC_TRIGSRC_6 -#define CONF_DMAC_TRIGSRC_6 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_6 -#ifndef CONF_DMAC_LVL_6 -#define CONF_DMAC_LVL_6 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_6 -#ifndef CONF_DMAC_EVOE_6 -#define CONF_DMAC_EVOE_6 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_6 -#ifndef CONF_DMAC_EVIE_6 -#define CONF_DMAC_EVIE_6 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_6 -#ifndef CONF_DMAC_EVACT_6 -#define CONF_DMAC_EVACT_6 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_6 -#ifndef CONF_DMAC_STEPSIZE_6 -#define CONF_DMAC_STEPSIZE_6 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_6 -#ifndef CONF_DMAC_STEPSEL_6 -#define CONF_DMAC_STEPSEL_6 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_6 -#ifndef CONF_DMAC_SRCINC_6 -#define CONF_DMAC_SRCINC_6 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_6 -#ifndef CONF_DMAC_DSTINC_6 -#define CONF_DMAC_DSTINC_6 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_6 -#ifndef CONF_DMAC_BEATSIZE_6 -#define CONF_DMAC_BEATSIZE_6 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_6 -#ifndef CONF_DMAC_BLOCKACT_6 -#define CONF_DMAC_BLOCKACT_6 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_6 -#ifndef CONF_DMAC_EVOSEL_6 -#define CONF_DMAC_EVOSEL_6 0 -#endif -// - -// Channel 7 settings -// dmac_channel_7_settings -#ifndef CONF_DMAC_CHANNEL_7_SETTINGS -#define CONF_DMAC_CHANNEL_7_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 7 is enabled or not -// dmac_enable_7 -#ifndef CONF_DMAC_ENABLE_7 -#define CONF_DMAC_ENABLE_7 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 7 is running in standby mode or not -// dmac_runstdby_7 -#ifndef CONF_DMAC_RUNSTDBY_7 -#define CONF_DMAC_RUNSTDBY_7 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_7 -#ifndef CONF_DMAC_TRIGACT_7 -#define CONF_DMAC_TRIGACT_7 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_7 -#ifndef CONF_DMAC_TRIGSRC_7 -#define CONF_DMAC_TRIGSRC_7 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_7 -#ifndef CONF_DMAC_LVL_7 -#define CONF_DMAC_LVL_7 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_7 -#ifndef CONF_DMAC_EVOE_7 -#define CONF_DMAC_EVOE_7 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_7 -#ifndef CONF_DMAC_EVIE_7 -#define CONF_DMAC_EVIE_7 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_7 -#ifndef CONF_DMAC_EVACT_7 -#define CONF_DMAC_EVACT_7 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_7 -#ifndef CONF_DMAC_STEPSIZE_7 -#define CONF_DMAC_STEPSIZE_7 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_7 -#ifndef CONF_DMAC_STEPSEL_7 -#define CONF_DMAC_STEPSEL_7 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_7 -#ifndef CONF_DMAC_SRCINC_7 -#define CONF_DMAC_SRCINC_7 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_7 -#ifndef CONF_DMAC_DSTINC_7 -#define CONF_DMAC_DSTINC_7 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_7 -#ifndef CONF_DMAC_BEATSIZE_7 -#define CONF_DMAC_BEATSIZE_7 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_7 -#ifndef CONF_DMAC_BLOCKACT_7 -#define CONF_DMAC_BLOCKACT_7 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_7 -#ifndef CONF_DMAC_EVOSEL_7 -#define CONF_DMAC_EVOSEL_7 0 -#endif -// - -// Channel 8 settings -// dmac_channel_8_settings -#ifndef CONF_DMAC_CHANNEL_8_SETTINGS -#define CONF_DMAC_CHANNEL_8_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 8 is enabled or not -// dmac_enable_8 -#ifndef CONF_DMAC_ENABLE_8 -#define CONF_DMAC_ENABLE_8 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 8 is running in standby mode or not -// dmac_runstdby_8 -#ifndef CONF_DMAC_RUNSTDBY_8 -#define CONF_DMAC_RUNSTDBY_8 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_8 -#ifndef CONF_DMAC_TRIGACT_8 -#define CONF_DMAC_TRIGACT_8 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_8 -#ifndef CONF_DMAC_TRIGSRC_8 -#define CONF_DMAC_TRIGSRC_8 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_8 -#ifndef CONF_DMAC_LVL_8 -#define CONF_DMAC_LVL_8 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_8 -#ifndef CONF_DMAC_EVOE_8 -#define CONF_DMAC_EVOE_8 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_8 -#ifndef CONF_DMAC_EVIE_8 -#define CONF_DMAC_EVIE_8 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_8 -#ifndef CONF_DMAC_EVACT_8 -#define CONF_DMAC_EVACT_8 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_8 -#ifndef CONF_DMAC_STEPSIZE_8 -#define CONF_DMAC_STEPSIZE_8 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_8 -#ifndef CONF_DMAC_STEPSEL_8 -#define CONF_DMAC_STEPSEL_8 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_8 -#ifndef CONF_DMAC_SRCINC_8 -#define CONF_DMAC_SRCINC_8 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_8 -#ifndef CONF_DMAC_DSTINC_8 -#define CONF_DMAC_DSTINC_8 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_8 -#ifndef CONF_DMAC_BEATSIZE_8 -#define CONF_DMAC_BEATSIZE_8 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_8 -#ifndef CONF_DMAC_BLOCKACT_8 -#define CONF_DMAC_BLOCKACT_8 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_8 -#ifndef CONF_DMAC_EVOSEL_8 -#define CONF_DMAC_EVOSEL_8 0 -#endif -// - -// Channel 9 settings -// dmac_channel_9_settings -#ifndef CONF_DMAC_CHANNEL_9_SETTINGS -#define CONF_DMAC_CHANNEL_9_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 9 is enabled or not -// dmac_enable_9 -#ifndef CONF_DMAC_ENABLE_9 -#define CONF_DMAC_ENABLE_9 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 9 is running in standby mode or not -// dmac_runstdby_9 -#ifndef CONF_DMAC_RUNSTDBY_9 -#define CONF_DMAC_RUNSTDBY_9 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_9 -#ifndef CONF_DMAC_TRIGACT_9 -#define CONF_DMAC_TRIGACT_9 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_9 -#ifndef CONF_DMAC_TRIGSRC_9 -#define CONF_DMAC_TRIGSRC_9 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_9 -#ifndef CONF_DMAC_LVL_9 -#define CONF_DMAC_LVL_9 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_9 -#ifndef CONF_DMAC_EVOE_9 -#define CONF_DMAC_EVOE_9 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_9 -#ifndef CONF_DMAC_EVIE_9 -#define CONF_DMAC_EVIE_9 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_9 -#ifndef CONF_DMAC_EVACT_9 -#define CONF_DMAC_EVACT_9 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_9 -#ifndef CONF_DMAC_STEPSIZE_9 -#define CONF_DMAC_STEPSIZE_9 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_9 -#ifndef CONF_DMAC_STEPSEL_9 -#define CONF_DMAC_STEPSEL_9 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_9 -#ifndef CONF_DMAC_SRCINC_9 -#define CONF_DMAC_SRCINC_9 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_9 -#ifndef CONF_DMAC_DSTINC_9 -#define CONF_DMAC_DSTINC_9 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_9 -#ifndef CONF_DMAC_BEATSIZE_9 -#define CONF_DMAC_BEATSIZE_9 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_9 -#ifndef CONF_DMAC_BLOCKACT_9 -#define CONF_DMAC_BLOCKACT_9 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_9 -#ifndef CONF_DMAC_EVOSEL_9 -#define CONF_DMAC_EVOSEL_9 0 -#endif -// - -// Channel 10 settings -// dmac_channel_10_settings -#ifndef CONF_DMAC_CHANNEL_10_SETTINGS -#define CONF_DMAC_CHANNEL_10_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 10 is enabled or not -// dmac_enable_10 -#ifndef CONF_DMAC_ENABLE_10 -#define CONF_DMAC_ENABLE_10 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 10 is running in standby mode or not -// dmac_runstdby_10 -#ifndef CONF_DMAC_RUNSTDBY_10 -#define CONF_DMAC_RUNSTDBY_10 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_10 -#ifndef CONF_DMAC_TRIGACT_10 -#define CONF_DMAC_TRIGACT_10 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_10 -#ifndef CONF_DMAC_TRIGSRC_10 -#define CONF_DMAC_TRIGSRC_10 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_10 -#ifndef CONF_DMAC_LVL_10 -#define CONF_DMAC_LVL_10 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_10 -#ifndef CONF_DMAC_EVOE_10 -#define CONF_DMAC_EVOE_10 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_10 -#ifndef CONF_DMAC_EVIE_10 -#define CONF_DMAC_EVIE_10 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_10 -#ifndef CONF_DMAC_EVACT_10 -#define CONF_DMAC_EVACT_10 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_10 -#ifndef CONF_DMAC_STEPSIZE_10 -#define CONF_DMAC_STEPSIZE_10 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_10 -#ifndef CONF_DMAC_STEPSEL_10 -#define CONF_DMAC_STEPSEL_10 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_10 -#ifndef CONF_DMAC_SRCINC_10 -#define CONF_DMAC_SRCINC_10 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_10 -#ifndef CONF_DMAC_DSTINC_10 -#define CONF_DMAC_DSTINC_10 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_10 -#ifndef CONF_DMAC_BEATSIZE_10 -#define CONF_DMAC_BEATSIZE_10 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_10 -#ifndef CONF_DMAC_BLOCKACT_10 -#define CONF_DMAC_BLOCKACT_10 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_10 -#ifndef CONF_DMAC_EVOSEL_10 -#define CONF_DMAC_EVOSEL_10 0 -#endif -// - -// Channel 11 settings -// dmac_channel_11_settings -#ifndef CONF_DMAC_CHANNEL_11_SETTINGS -#define CONF_DMAC_CHANNEL_11_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 11 is enabled or not -// dmac_enable_11 -#ifndef CONF_DMAC_ENABLE_11 -#define CONF_DMAC_ENABLE_11 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 11 is running in standby mode or not -// dmac_runstdby_11 -#ifndef CONF_DMAC_RUNSTDBY_11 -#define CONF_DMAC_RUNSTDBY_11 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_11 -#ifndef CONF_DMAC_TRIGACT_11 -#define CONF_DMAC_TRIGACT_11 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_11 -#ifndef CONF_DMAC_TRIGSRC_11 -#define CONF_DMAC_TRIGSRC_11 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_11 -#ifndef CONF_DMAC_LVL_11 -#define CONF_DMAC_LVL_11 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_11 -#ifndef CONF_DMAC_EVOE_11 -#define CONF_DMAC_EVOE_11 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_11 -#ifndef CONF_DMAC_EVIE_11 -#define CONF_DMAC_EVIE_11 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_11 -#ifndef CONF_DMAC_EVACT_11 -#define CONF_DMAC_EVACT_11 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_11 -#ifndef CONF_DMAC_STEPSIZE_11 -#define CONF_DMAC_STEPSIZE_11 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_11 -#ifndef CONF_DMAC_STEPSEL_11 -#define CONF_DMAC_STEPSEL_11 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_11 -#ifndef CONF_DMAC_SRCINC_11 -#define CONF_DMAC_SRCINC_11 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_11 -#ifndef CONF_DMAC_DSTINC_11 -#define CONF_DMAC_DSTINC_11 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_11 -#ifndef CONF_DMAC_BEATSIZE_11 -#define CONF_DMAC_BEATSIZE_11 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_11 -#ifndef CONF_DMAC_BLOCKACT_11 -#define CONF_DMAC_BLOCKACT_11 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_11 -#ifndef CONF_DMAC_EVOSEL_11 -#define CONF_DMAC_EVOSEL_11 0 -#endif -// - -// Channel 12 settings -// dmac_channel_12_settings -#ifndef CONF_DMAC_CHANNEL_12_SETTINGS -#define CONF_DMAC_CHANNEL_12_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 12 is enabled or not -// dmac_enable_12 -#ifndef CONF_DMAC_ENABLE_12 -#define CONF_DMAC_ENABLE_12 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 12 is running in standby mode or not -// dmac_runstdby_12 -#ifndef CONF_DMAC_RUNSTDBY_12 -#define CONF_DMAC_RUNSTDBY_12 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_12 -#ifndef CONF_DMAC_TRIGACT_12 -#define CONF_DMAC_TRIGACT_12 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_12 -#ifndef CONF_DMAC_TRIGSRC_12 -#define CONF_DMAC_TRIGSRC_12 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_12 -#ifndef CONF_DMAC_LVL_12 -#define CONF_DMAC_LVL_12 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_12 -#ifndef CONF_DMAC_EVOE_12 -#define CONF_DMAC_EVOE_12 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_12 -#ifndef CONF_DMAC_EVIE_12 -#define CONF_DMAC_EVIE_12 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_12 -#ifndef CONF_DMAC_EVACT_12 -#define CONF_DMAC_EVACT_12 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_12 -#ifndef CONF_DMAC_STEPSIZE_12 -#define CONF_DMAC_STEPSIZE_12 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_12 -#ifndef CONF_DMAC_STEPSEL_12 -#define CONF_DMAC_STEPSEL_12 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_12 -#ifndef CONF_DMAC_SRCINC_12 -#define CONF_DMAC_SRCINC_12 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_12 -#ifndef CONF_DMAC_DSTINC_12 -#define CONF_DMAC_DSTINC_12 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_12 -#ifndef CONF_DMAC_BEATSIZE_12 -#define CONF_DMAC_BEATSIZE_12 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_12 -#ifndef CONF_DMAC_BLOCKACT_12 -#define CONF_DMAC_BLOCKACT_12 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_12 -#ifndef CONF_DMAC_EVOSEL_12 -#define CONF_DMAC_EVOSEL_12 0 -#endif -// - -// Channel 13 settings -// dmac_channel_13_settings -#ifndef CONF_DMAC_CHANNEL_13_SETTINGS -#define CONF_DMAC_CHANNEL_13_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 13 is enabled or not -// dmac_enable_13 -#ifndef CONF_DMAC_ENABLE_13 -#define CONF_DMAC_ENABLE_13 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 13 is running in standby mode or not -// dmac_runstdby_13 -#ifndef CONF_DMAC_RUNSTDBY_13 -#define CONF_DMAC_RUNSTDBY_13 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_13 -#ifndef CONF_DMAC_TRIGACT_13 -#define CONF_DMAC_TRIGACT_13 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_13 -#ifndef CONF_DMAC_TRIGSRC_13 -#define CONF_DMAC_TRIGSRC_13 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_13 -#ifndef CONF_DMAC_LVL_13 -#define CONF_DMAC_LVL_13 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_13 -#ifndef CONF_DMAC_EVOE_13 -#define CONF_DMAC_EVOE_13 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_13 -#ifndef CONF_DMAC_EVIE_13 -#define CONF_DMAC_EVIE_13 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_13 -#ifndef CONF_DMAC_EVACT_13 -#define CONF_DMAC_EVACT_13 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_13 -#ifndef CONF_DMAC_STEPSIZE_13 -#define CONF_DMAC_STEPSIZE_13 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_13 -#ifndef CONF_DMAC_STEPSEL_13 -#define CONF_DMAC_STEPSEL_13 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_13 -#ifndef CONF_DMAC_SRCINC_13 -#define CONF_DMAC_SRCINC_13 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_13 -#ifndef CONF_DMAC_DSTINC_13 -#define CONF_DMAC_DSTINC_13 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_13 -#ifndef CONF_DMAC_BEATSIZE_13 -#define CONF_DMAC_BEATSIZE_13 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_13 -#ifndef CONF_DMAC_BLOCKACT_13 -#define CONF_DMAC_BLOCKACT_13 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_13 -#ifndef CONF_DMAC_EVOSEL_13 -#define CONF_DMAC_EVOSEL_13 0 -#endif -// - -// Channel 14 settings -// dmac_channel_14_settings -#ifndef CONF_DMAC_CHANNEL_14_SETTINGS -#define CONF_DMAC_CHANNEL_14_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 14 is enabled or not -// dmac_enable_14 -#ifndef CONF_DMAC_ENABLE_14 -#define CONF_DMAC_ENABLE_14 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 14 is running in standby mode or not -// dmac_runstdby_14 -#ifndef CONF_DMAC_RUNSTDBY_14 -#define CONF_DMAC_RUNSTDBY_14 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_14 -#ifndef CONF_DMAC_TRIGACT_14 -#define CONF_DMAC_TRIGACT_14 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_14 -#ifndef CONF_DMAC_TRIGSRC_14 -#define CONF_DMAC_TRIGSRC_14 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_14 -#ifndef CONF_DMAC_LVL_14 -#define CONF_DMAC_LVL_14 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_14 -#ifndef CONF_DMAC_EVOE_14 -#define CONF_DMAC_EVOE_14 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_14 -#ifndef CONF_DMAC_EVIE_14 -#define CONF_DMAC_EVIE_14 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_14 -#ifndef CONF_DMAC_EVACT_14 -#define CONF_DMAC_EVACT_14 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_14 -#ifndef CONF_DMAC_STEPSIZE_14 -#define CONF_DMAC_STEPSIZE_14 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_14 -#ifndef CONF_DMAC_STEPSEL_14 -#define CONF_DMAC_STEPSEL_14 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_14 -#ifndef CONF_DMAC_SRCINC_14 -#define CONF_DMAC_SRCINC_14 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_14 -#ifndef CONF_DMAC_DSTINC_14 -#define CONF_DMAC_DSTINC_14 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_14 -#ifndef CONF_DMAC_BEATSIZE_14 -#define CONF_DMAC_BEATSIZE_14 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_14 -#ifndef CONF_DMAC_BLOCKACT_14 -#define CONF_DMAC_BLOCKACT_14 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_14 -#ifndef CONF_DMAC_EVOSEL_14 -#define CONF_DMAC_EVOSEL_14 0 -#endif -// - -// Channel 15 settings -// dmac_channel_15_settings -#ifndef CONF_DMAC_CHANNEL_15_SETTINGS -#define CONF_DMAC_CHANNEL_15_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 15 is enabled or not -// dmac_enable_15 -#ifndef CONF_DMAC_ENABLE_15 -#define CONF_DMAC_ENABLE_15 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 15 is running in standby mode or not -// dmac_runstdby_15 -#ifndef CONF_DMAC_RUNSTDBY_15 -#define CONF_DMAC_RUNSTDBY_15 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_15 -#ifndef CONF_DMAC_TRIGACT_15 -#define CONF_DMAC_TRIGACT_15 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_15 -#ifndef CONF_DMAC_TRIGSRC_15 -#define CONF_DMAC_TRIGSRC_15 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_15 -#ifndef CONF_DMAC_LVL_15 -#define CONF_DMAC_LVL_15 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_15 -#ifndef CONF_DMAC_EVOE_15 -#define CONF_DMAC_EVOE_15 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_15 -#ifndef CONF_DMAC_EVIE_15 -#define CONF_DMAC_EVIE_15 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_15 -#ifndef CONF_DMAC_EVACT_15 -#define CONF_DMAC_EVACT_15 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_15 -#ifndef CONF_DMAC_STEPSIZE_15 -#define CONF_DMAC_STEPSIZE_15 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_15 -#ifndef CONF_DMAC_STEPSEL_15 -#define CONF_DMAC_STEPSEL_15 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_15 -#ifndef CONF_DMAC_SRCINC_15 -#define CONF_DMAC_SRCINC_15 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_15 -#ifndef CONF_DMAC_DSTINC_15 -#define CONF_DMAC_DSTINC_15 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_15 -#ifndef CONF_DMAC_BEATSIZE_15 -#define CONF_DMAC_BEATSIZE_15 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_15 -#ifndef CONF_DMAC_BLOCKACT_15 -#define CONF_DMAC_BLOCKACT_15 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_15 -#ifndef CONF_DMAC_EVOSEL_15 -#define CONF_DMAC_EVOSEL_15 0 -#endif -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_DMAC_CONFIG_H diff --git a/watch-library/config/hpl_eic_config.h b/watch-library/config/hpl_eic_config.h deleted file mode 100644 index be54c2e1..00000000 --- a/watch-library/config/hpl_eic_config.h +++ /dev/null @@ -1,736 +0,0 @@ -/* Auto-generated config file hpl_eic_config.h */ -#ifndef HPL_EIC_CONFIG_H -#define HPL_EIC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic Settings -// Clock Selection -// Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or -// either by CLK_ULP32K when power consumption is the priority. -// <0x0=> Clocked by GCLK -// <0x1=> Clocked by ULPOSC32K -// eic_arch_cksel -#ifndef CONF_EIC_CKSEL -#define CONF_EIC_CKSEL 0 -#endif - -// - -// Non-Maskable Interrupt Control -// eic_arch_nmi_ctrl -#ifndef CONF_EIC_ENABLE_NMI_CTRL -#define CONF_EIC_ENABLE_NMI_CTRL 0 -#endif - -// Non-Maskable Interrupt Filter Enable -// Indicates whether the mon-maskable interrupt filter is enabled or not -// eic_arch_nmifilten -#ifndef CONF_EIC_NMIFILTEN -#define CONF_EIC_NMIFILTEN 0 -#endif - -// Non-Maskable Interrupt Sense -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines non-maskable interrupt sense -// eic_arch_nmisense -#ifndef CONF_EIC_NMISENSE -#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// Asynchronous Edge Detection Mode -// Indicates the interrupt detection mode operated synchronously or asynchronousl -// eic_arch_nmiasynch -#ifndef CONF_EIC_NMIASYNCH -#define CONF_EIC_NMIASYNCH 0 -#endif -// - -// Interrupt 0 Settings -// eic_arch_enable_irq_setting0 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING0 -#define CONF_EIC_ENABLE_IRQ_SETTING0 0 -#endif - -// External Interrupt 0 Filter Enable -// Indicates whether the external interrupt 0 filter is enabled or not -// eic_arch_filten0 -#ifndef CONF_EIC_FILTEN0 -#define CONF_EIC_FILTEN0 1 -#endif - -// External Interrupt 0 Event Output Enable -// Indicates whether the external interrupt 0 event output is enabled or not -// eic_arch_extinteo0 -#ifndef CONF_EIC_EXTINTEO0 -#define CONF_EIC_EXTINTEO0 0 -#endif - -// Input 0 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense0 -#ifndef CONF_EIC_SENSE0 -#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 0 Asynchronous Edge Detection Mode -// Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl -// eic_arch_asynch0 -#ifndef CONF_EIC_ASYNCH0 -#define CONF_EIC_ASYNCH0 0 -#endif - -// - -// Interrupt 1 Settings -// eic_arch_enable_irq_setting1 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING1 -#define CONF_EIC_ENABLE_IRQ_SETTING1 0 -#endif - -// External Interrupt 1 Filter Enable -// Indicates whether the external interrupt 1 filter is enabled or not -// eic_arch_filten1 -#ifndef CONF_EIC_FILTEN1 -#define CONF_EIC_FILTEN1 1 -#endif - -// External Interrupt 1 Event Output Enable -// Indicates whether the external interrupt 1 event output is enabled or not -// eic_arch_extinteo1 -#ifndef CONF_EIC_EXTINTEO1 -#define CONF_EIC_EXTINTEO1 0 -#endif - -// Input 1 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense1 -#ifndef CONF_EIC_SENSE1 -#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 1 Asynchronous Edge Detection Mode -// Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl -// eic_arch_asynch1 -#ifndef CONF_EIC_ASYNCH1 -#define CONF_EIC_ASYNCH1 0 -#endif - -// - -// Interrupt 2 Settings -// eic_arch_enable_irq_setting2 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING2 -#define CONF_EIC_ENABLE_IRQ_SETTING2 0 -#endif - -// External Interrupt 2 Filter Enable -// Indicates whether the external interrupt 2 filter is enabled or not -// eic_arch_filten2 -#ifndef CONF_EIC_FILTEN2 -#define CONF_EIC_FILTEN2 1 -#endif - -// External Interrupt 2 Event Output Enable -// Indicates whether the external interrupt 2 event output is enabled or not -// eic_arch_extinteo2 -#ifndef CONF_EIC_EXTINTEO2 -#define CONF_EIC_EXTINTEO2 0 -#endif - -// Input 2 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense2 -#ifndef CONF_EIC_SENSE2 -#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 2 Asynchronous Edge Detection Mode -// Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl -// eic_arch_asynch2 -#ifndef CONF_EIC_ASYNCH2 -#define CONF_EIC_ASYNCH2 0 -#endif - -// - -// Interrupt 3 Settings -// eic_arch_enable_irq_setting3 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING3 -#define CONF_EIC_ENABLE_IRQ_SETTING3 0 -#endif - -// External Interrupt 3 Filter Enable -// Indicates whether the external interrupt 3 filter is enabled or not -// eic_arch_filten3 -#ifndef CONF_EIC_FILTEN3 -#define CONF_EIC_FILTEN3 1 -#endif - -// External Interrupt 3 Event Output Enable -// Indicates whether the external interrupt 3 event output is enabled or not -// eic_arch_extinteo3 -#ifndef CONF_EIC_EXTINTEO3 -#define CONF_EIC_EXTINTEO3 0 -#endif - -// Input 3 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense3 -#ifndef CONF_EIC_SENSE3 -#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 3 Asynchronous Edge Detection Mode -// Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl -// eic_arch_asynch3 -#ifndef CONF_EIC_ASYNCH3 -#define CONF_EIC_ASYNCH3 0 -#endif - -// - -// Interrupt 4 Settings -// eic_arch_enable_irq_setting4 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING4 -#define CONF_EIC_ENABLE_IRQ_SETTING4 0 -#endif - -// External Interrupt 4 Filter Enable -// Indicates whether the external interrupt 4 filter is enabled or not -// eic_arch_filten4 -#ifndef CONF_EIC_FILTEN4 -#define CONF_EIC_FILTEN4 1 -#endif - -// External Interrupt 4 Event Output Enable -// Indicates whether the external interrupt 4 event output is enabled or not -// eic_arch_extinteo4 -#ifndef CONF_EIC_EXTINTEO4 -#define CONF_EIC_EXTINTEO4 0 -#endif - -// Input 4 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense4 -#ifndef CONF_EIC_SENSE4 -#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 4 Asynchronous Edge Detection Mode -// Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl -// eic_arch_asynch4 -#ifndef CONF_EIC_ASYNCH4 -#define CONF_EIC_ASYNCH4 0 -#endif - -// - -// Interrupt 5 Settings -// eic_arch_enable_irq_setting5 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING5 -#define CONF_EIC_ENABLE_IRQ_SETTING5 0 -#endif - -// External Interrupt 5 Filter Enable -// Indicates whether the external interrupt 5 filter is enabled or not -// eic_arch_filten5 -#ifndef CONF_EIC_FILTEN5 -#define CONF_EIC_FILTEN5 1 -#endif - -// External Interrupt 5 Event Output Enable -// Indicates whether the external interrupt 5 event output is enabled or not -// eic_arch_extinteo5 -#ifndef CONF_EIC_EXTINTEO5 -#define CONF_EIC_EXTINTEO5 0 -#endif - -// Input 5 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense5 -#ifndef CONF_EIC_SENSE5 -#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 5 Asynchronous Edge Detection Mode -// Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl -// eic_arch_asynch5 -#ifndef CONF_EIC_ASYNCH5 -#define CONF_EIC_ASYNCH5 0 -#endif - -// - -// Interrupt 6 Settings -// eic_arch_enable_irq_setting6 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING6 -#define CONF_EIC_ENABLE_IRQ_SETTING6 0 -#endif - -// External Interrupt 6 Filter Enable -// Indicates whether the external interrupt 6 filter is enabled or not -// eic_arch_filten6 -#ifndef CONF_EIC_FILTEN6 -#define CONF_EIC_FILTEN6 1 -#endif - -// External Interrupt 6 Event Output Enable -// Indicates whether the external interrupt 6 event output is enabled or not -// eic_arch_extinteo6 -#ifndef CONF_EIC_EXTINTEO6 -#define CONF_EIC_EXTINTEO6 0 -#endif - -// Input 6 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense6 -#ifndef CONF_EIC_SENSE6 -#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 6 Asynchronous Edge Detection Mode -// Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl -// eic_arch_asynch6 -#ifndef CONF_EIC_ASYNCH6 -#define CONF_EIC_ASYNCH6 0 -#endif - -// - -// Interrupt 7 Settings -// eic_arch_enable_irq_setting7 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING7 -#define CONF_EIC_ENABLE_IRQ_SETTING7 0 -#endif - -// External Interrupt 7 Filter Enable -// Indicates whether the external interrupt 7 filter is enabled or not -// eic_arch_filten7 -#ifndef CONF_EIC_FILTEN7 -#define CONF_EIC_FILTEN7 1 -#endif - -// External Interrupt 7 Event Output Enable -// Indicates whether the external interrupt 7 event output is enabled or not -// eic_arch_extinteo7 -#ifndef CONF_EIC_EXTINTEO7 -#define CONF_EIC_EXTINTEO7 0 -#endif - -// Input 7 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense7 -#ifndef CONF_EIC_SENSE7 -#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 7 Asynchronous Edge Detection Mode -// Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl -// eic_arch_asynch7 -#ifndef CONF_EIC_ASYNCH7 -#define CONF_EIC_ASYNCH7 0 -#endif - -// - -// Interrupt 8 Settings -// eic_arch_enable_irq_setting8 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING8 -#define CONF_EIC_ENABLE_IRQ_SETTING8 0 -#endif - -// External Interrupt 8 Filter Enable -// Indicates whether the external interrupt 8 filter is enabled or not -// eic_arch_filten8 -#ifndef CONF_EIC_FILTEN8 -#define CONF_EIC_FILTEN8 0 -#endif - -// External Interrupt 8 Event Output Enable -// Indicates whether the external interrupt 8 event output is enabled or not -// eic_arch_extinteo8 -#ifndef CONF_EIC_EXTINTEO8 -#define CONF_EIC_EXTINTEO8 0 -#endif - -// Input 8 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense8 -#ifndef CONF_EIC_SENSE8 -#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 8 Asynchronous Edge Detection Mode -// Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl -// eic_arch_asynch8 -#ifndef CONF_EIC_ASYNCH8 -#define CONF_EIC_ASYNCH8 0 -#endif - -// - -// Interrupt 9 Settings -// eic_arch_enable_irq_setting9 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING9 -#define CONF_EIC_ENABLE_IRQ_SETTING9 0 -#endif - -// External Interrupt 9 Filter Enable -// Indicates whether the external interrupt 9 filter is enabled or not -// eic_arch_filten9 -#ifndef CONF_EIC_FILTEN9 -#define CONF_EIC_FILTEN9 0 -#endif - -// External Interrupt 9 Event Output Enable -// Indicates whether the external interrupt 9 event output is enabled or not -// eic_arch_extinteo9 -#ifndef CONF_EIC_EXTINTEO9 -#define CONF_EIC_EXTINTEO9 0 -#endif - -// Input 9 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense9 -#ifndef CONF_EIC_SENSE9 -#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 9 Asynchronous Edge Detection Mode -// Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl -// eic_arch_asynch9 -#ifndef CONF_EIC_ASYNCH9 -#define CONF_EIC_ASYNCH9 0 -#endif - -// - -// Interrupt 10 Settings -// eic_arch_enable_irq_setting10 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING10 -#define CONF_EIC_ENABLE_IRQ_SETTING10 0 -#endif - -// External Interrupt 10 Filter Enable -// Indicates whether the external interrupt 10 filter is enabled or not -// eic_arch_filten10 -#ifndef CONF_EIC_FILTEN10 -#define CONF_EIC_FILTEN10 0 -#endif - -// External Interrupt 10 Event Output Enable -// Indicates whether the external interrupt 10 event output is enabled or not -// eic_arch_extinteo10 -#ifndef CONF_EIC_EXTINTEO10 -#define CONF_EIC_EXTINTEO10 0 -#endif - -// Input 10 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense10 -#ifndef CONF_EIC_SENSE10 -#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 10 Asynchronous Edge Detection Mode -// Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl -// eic_arch_asynch10 -#ifndef CONF_EIC_ASYNCH10 -#define CONF_EIC_ASYNCH10 0 -#endif - -// - -// Interrupt 11 Settings -// eic_arch_enable_irq_setting11 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING11 -#define CONF_EIC_ENABLE_IRQ_SETTING11 0 -#endif - -// External Interrupt 11 Filter Enable -// Indicates whether the external interrupt 11 filter is enabled or not -// eic_arch_filten11 -#ifndef CONF_EIC_FILTEN11 -#define CONF_EIC_FILTEN11 0 -#endif - -// External Interrupt 11 Event Output Enable -// Indicates whether the external interrupt 11 event output is enabled or not -// eic_arch_extinteo11 -#ifndef CONF_EIC_EXTINTEO11 -#define CONF_EIC_EXTINTEO11 0 -#endif - -// Input 11 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense11 -#ifndef CONF_EIC_SENSE11 -#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 11 Asynchronous Edge Detection Mode -// Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl -// eic_arch_asynch11 -#ifndef CONF_EIC_ASYNCH11 -#define CONF_EIC_ASYNCH11 0 -#endif - -// - -// Interrupt 12 Settings -// eic_arch_enable_irq_setting12 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING12 -#define CONF_EIC_ENABLE_IRQ_SETTING12 0 -#endif - -// External Interrupt 12 Filter Enable -// Indicates whether the external interrupt 12 filter is enabled or not -// eic_arch_filten12 -#ifndef CONF_EIC_FILTEN12 -#define CONF_EIC_FILTEN12 0 -#endif - -// External Interrupt 12 Event Output Enable -// Indicates whether the external interrupt 12 event output is enabled or not -// eic_arch_extinteo12 -#ifndef CONF_EIC_EXTINTEO12 -#define CONF_EIC_EXTINTEO12 0 -#endif - -// Input 12 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense12 -#ifndef CONF_EIC_SENSE12 -#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 12 Asynchronous Edge Detection Mode -// Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl -// eic_arch_asynch12 -#ifndef CONF_EIC_ASYNCH12 -#define CONF_EIC_ASYNCH12 0 -#endif - -// - -// Interrupt 13 Settings -// eic_arch_enable_irq_setting13 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING13 -#define CONF_EIC_ENABLE_IRQ_SETTING13 0 -#endif - -// External Interrupt 13 Filter Enable -// Indicates whether the external interrupt 13 filter is enabled or not -// eic_arch_filten13 -#ifndef CONF_EIC_FILTEN13 -#define CONF_EIC_FILTEN13 0 -#endif - -// External Interrupt 13 Event Output Enable -// Indicates whether the external interrupt 13 event output is enabled or not -// eic_arch_extinteo13 -#ifndef CONF_EIC_EXTINTEO13 -#define CONF_EIC_EXTINTEO13 0 -#endif - -// Input 13 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense13 -#ifndef CONF_EIC_SENSE13 -#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 13 Asynchronous Edge Detection Mode -// Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl -// eic_arch_asynch13 -#ifndef CONF_EIC_ASYNCH13 -#define CONF_EIC_ASYNCH13 0 -#endif - -// - -// Interrupt 14 Settings -// eic_arch_enable_irq_setting14 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING14 -#define CONF_EIC_ENABLE_IRQ_SETTING14 0 -#endif - -// External Interrupt 14 Filter Enable -// Indicates whether the external interrupt 14 filter is enabled or not -// eic_arch_filten14 -#ifndef CONF_EIC_FILTEN14 -#define CONF_EIC_FILTEN14 0 -#endif - -// External Interrupt 14 Event Output Enable -// Indicates whether the external interrupt 14 event output is enabled or not -// eic_arch_extinteo14 -#ifndef CONF_EIC_EXTINTEO14 -#define CONF_EIC_EXTINTEO14 0 -#endif - -// Input 14 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense14 -#ifndef CONF_EIC_SENSE14 -#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 14 Asynchronous Edge Detection Mode -// Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl -// eic_arch_asynch14 -#ifndef CONF_EIC_ASYNCH14 -#define CONF_EIC_ASYNCH14 0 -#endif - -// - -// Interrupt 15 Settings -// eic_arch_enable_irq_setting15 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING15 -#define CONF_EIC_ENABLE_IRQ_SETTING15 0 -#endif - -// External Interrupt 15 Filter Enable -// Indicates whether the external interrupt 15 filter is enabled or not -// eic_arch_filten15 -#ifndef CONF_EIC_FILTEN15 -#define CONF_EIC_FILTEN15 0 -#endif - -// External Interrupt 15 Event Output Enable -// Indicates whether the external interrupt 15 event output is enabled or not -// eic_arch_extinteo15 -#ifndef CONF_EIC_EXTINTEO15 -#define CONF_EIC_EXTINTEO15 0 -#endif - -// Input 15 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense15 -#ifndef CONF_EIC_SENSE15 -#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 15 Asynchronous Edge Detection Mode -// Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl -// eic_arch_asynch15 -#ifndef CONF_EIC_ASYNCH15 -#define CONF_EIC_ASYNCH15 0 -#endif - -// - -// this is still a hack: if the user wants to use PA02 (alarm button) as an RTC interrupt pin and PB02 (9-pin A2) on the EIC, we don't support that. -// TODO item: refactor out our reliance on the ASF external interrupt driver. - joey 11/30 -#ifdef CRYSTALLESS -#define CONFIG_EIC_EXTINT_MAP {0, PIN_PB00}, {1, PIN_PB01}, {2, PIN_PA02}, {3, PIN_PB03}, {5, PIN_PB05}, {7, PIN_PA07}, -#else -#define CONFIG_EIC_EXTINT_MAP {0, PIN_PB00}, {1, PIN_PB01}, {2, PIN_PA02}, {3, PIN_PB03}, {6, PIN_PA22}, {7, PIN_PA23}, -#endif - -// <<< end of configuration section >>> - -#endif // HPL_EIC_CONFIG_H diff --git a/watch-library/config/hpl_gclk_config.h b/watch-library/config/hpl_gclk_config.h deleted file mode 100644 index ee7aace3..00000000 --- a/watch-library/config/hpl_gclk_config.h +++ /dev/null @@ -1,388 +0,0 @@ -/* Auto-generated config file hpl_gclk_config.h */ -#ifndef HPL_GCLK_CONFIG_H -#define HPL_GCLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Generic clock generator 0 configuration -// Indicates whether generic clock 0 configuration is enabled or not -// enable_gclk_gen_0 -#ifndef CONF_GCLK_GENERATOR_0_CONFIG -#define CONF_GCLK_GENERATOR_0_CONFIG 1 -#endif - -// Generic Clock Generator Control -// Generic clock generator 0 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 16MHz Internal Oscillator (OSC16M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 0 -// gclk_gen_0_oscillator -#ifndef CONF_GCLK_GEN_0_SOURCE -#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_0_runstdby -#ifndef CONF_GCLK_GEN_0_RUNSTDBY -#define CONF_GCLK_GEN_0_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_0_div_sel -#ifndef CONF_GCLK_GEN_0_DIVSEL -#define CONF_GCLK_GEN_0_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_0_oe -#ifndef CONF_GCLK_GEN_0_OE -#define CONF_GCLK_GEN_0_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_0_oov -#ifndef CONF_GCLK_GEN_0_OOV -#define CONF_GCLK_GEN_0_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_0_idc -#ifndef CONF_GCLK_GEN_0_IDC -#define CONF_GCLK_GEN_0_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_0_enable -#ifndef CONF_GCLK_GEN_0_GENEN -#define CONF_GCLK_GEN_0_GENEN 1 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 0 division <0x0000-0xFFFF> -// gclk_gen_0_div -#ifndef CONF_GCLK_GEN_0_DIV -#define CONF_GCLK_GEN_0_DIV 1 -#endif -// -// - -// Generic clock generator 1 configuration -// Indicates whether generic clock 1 configuration is enabled or not -// enable_gclk_gen_1 -#ifndef CONF_GCLK_GENERATOR_1_CONFIG -#define CONF_GCLK_GENERATOR_1_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 1 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 16MHz Internal Oscillator (OSC16M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 1 -// gclk_gen_1_oscillator -#ifndef CONF_GCLK_GEN_1_SOURCE -#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_1_runstdby -#ifndef CONF_GCLK_GEN_1_RUNSTDBY -#define CONF_GCLK_GEN_1_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_1_div_sel -#ifndef CONF_GCLK_GEN_1_DIVSEL -#define CONF_GCLK_GEN_1_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_1_oe -#ifndef CONF_GCLK_GEN_1_OE -#define CONF_GCLK_GEN_1_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_1_oov -#ifndef CONF_GCLK_GEN_1_OOV -#define CONF_GCLK_GEN_1_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_1_idc -#ifndef CONF_GCLK_GEN_1_IDC -#define CONF_GCLK_GEN_1_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_1_enable -#ifndef CONF_GCLK_GEN_1_GENEN -#define CONF_GCLK_GEN_1_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 1 division <0x0000-0xFFFF> -// gclk_gen_1_div -#ifndef CONF_GCLK_GEN_1_DIV -#define CONF_GCLK_GEN_1_DIV 1 -#endif -// -// - -// Generic clock generator 2 configuration -// Indicates whether generic clock 2 configuration is enabled or not -// enable_gclk_gen_2 -#ifndef CONF_GCLK_GENERATOR_2_CONFIG -#define CONF_GCLK_GENERATOR_2_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 2 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 16MHz Internal Oscillator (OSC16M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 2 -// gclk_gen_2_oscillator -#ifndef CONF_GCLK_GEN_2_SOURCE -#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_2_runstdby -#ifndef CONF_GCLK_GEN_2_RUNSTDBY -#define CONF_GCLK_GEN_2_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_2_div_sel -#ifndef CONF_GCLK_GEN_2_DIVSEL -#define CONF_GCLK_GEN_2_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_2_oe -#ifndef CONF_GCLK_GEN_2_OE -#define CONF_GCLK_GEN_2_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_2_oov -#ifndef CONF_GCLK_GEN_2_OOV -#define CONF_GCLK_GEN_2_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_2_idc -#ifndef CONF_GCLK_GEN_2_IDC -#define CONF_GCLK_GEN_2_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_2_enable -#ifndef CONF_GCLK_GEN_2_GENEN -#define CONF_GCLK_GEN_2_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 2 division <0x0000-0xFFFF> -// gclk_gen_2_div -#ifndef CONF_GCLK_GEN_2_DIV -#define CONF_GCLK_GEN_2_DIV 1 -#endif -// -// - -// Generic clock generator 3 configuration -// Indicates whether generic clock 3 configuration is enabled or not -// enable_gclk_gen_3 -#ifndef CONF_GCLK_GENERATOR_3_CONFIG -#define CONF_GCLK_GENERATOR_3_CONFIG 1 -#endif - -// Generic Clock Generator Control -// Generic clock generator 3 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 16MHz Internal Oscillator (OSC16M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 3 -// gclk_gen_3_oscillator -#ifndef CONF_GCLK_GEN_3_SOURCE -#ifdef CRYSTALLESS -#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_OSCULP32K -#else -#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K -#endif - -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_3_runstdby -#ifndef CONF_GCLK_GEN_3_RUNSTDBY -#define CONF_GCLK_GEN_3_RUNSTDBY 1 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_3_div_sel -#ifndef CONF_GCLK_GEN_3_DIVSEL -#define CONF_GCLK_GEN_3_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_3_oe -#ifndef CONF_GCLK_GEN_3_OE -#define CONF_GCLK_GEN_3_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_3_oov -#ifndef CONF_GCLK_GEN_3_OOV -#define CONF_GCLK_GEN_3_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_3_idc -#ifndef CONF_GCLK_GEN_3_IDC -#define CONF_GCLK_GEN_3_IDC 1 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_3_enable -#ifndef CONF_GCLK_GEN_3_GENEN -#define CONF_GCLK_GEN_3_GENEN 1 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 3 division <0x0000-0xFFFF> -// gclk_gen_3_div -#ifndef CONF_GCLK_GEN_3_DIV -#define CONF_GCLK_GEN_3_DIV 1 -#endif -// -// - -// Generic clock generator 4 configuration -// Indicates whether generic clock 4 configuration is enabled or not -// enable_gclk_gen_4 -#ifndef CONF_GCLK_GENERATOR_4_CONFIG -#define CONF_GCLK_GENERATOR_4_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 4 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 16MHz Internal Oscillator (OSC16M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 4 -// gclk_gen_4_oscillator -#ifndef CONF_GCLK_GEN_4_SOURCE -#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_4_runstdby -#ifndef CONF_GCLK_GEN_4_RUNSTDBY -#define CONF_GCLK_GEN_4_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_4_div_sel -#ifndef CONF_GCLK_GEN_4_DIVSEL -#define CONF_GCLK_GEN_4_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_4_oe -#ifndef CONF_GCLK_GEN_4_OE -#define CONF_GCLK_GEN_4_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_4_oov -#ifndef CONF_GCLK_GEN_4_OOV -#define CONF_GCLK_GEN_4_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_4_idc -#ifndef CONF_GCLK_GEN_4_IDC -#define CONF_GCLK_GEN_4_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_4_enable -#ifndef CONF_GCLK_GEN_4_GENEN -#define CONF_GCLK_GEN_4_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 4 division <0x0000-0xFFFF> -// gclk_gen_4_div -#ifndef CONF_GCLK_GEN_4_DIV -#define CONF_GCLK_GEN_4_DIV 1 -#endif -// -// - -// <<< end of configuration section >>> - -#endif // HPL_GCLK_CONFIG_H diff --git a/watch-library/config/hpl_mclk_config.h b/watch-library/config/hpl_mclk_config.h deleted file mode 100644 index 3358edcf..00000000 --- a/watch-library/config/hpl_mclk_config.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Auto-generated config file hpl_mclk_config.h */ -#ifndef HPL_MCLK_CONFIG_H -#define HPL_MCLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -// System Configuration -// Indicates whether configuration for system is enabled or not -// enable_cpu_clock -#ifndef CONF_SYSTEM_CONFIG -#define CONF_SYSTEM_CONFIG 1 -#endif - -// Basic settings -// CPU Clock source -// Generic clock generator 0 -// This defines the clock source for the CPU -// cpu_clock_source -#ifndef CONF_CPU_SRC -#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// CPU Clock Division Factor -// 1 -// 2 -// 4 -// 8 -// 16 -// 32 -// 64 -// 128 -// Prescalar for CPU clock -// cpu_div -#ifndef CONF_MCLK_CPUDIV -#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val -#endif - -// Backup Clock Division -// Divide by 1 -// Divide by 2 -// Divide by 4 -// Divide by 8 -// Divide by 16 -// Divide by 32 -// Divide by 64 -// Divide by 128 -// mclk_arch_bupdiv -#ifndef CONF_MCLK_BUPDIV -#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV1_Val -#endif -// - -// NVM Settings -// NVM Wait States -// These bits select the number of wait states for a read operation. -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 -// <8=> 8 -// <9=> 9 -// <10=> 10 -// <11=> 11 -// <12=> 12 -// <13=> 13 -// <14=> 14 -// <15=> 15 -// nvm_wait_states -#ifndef CONF_NVM_WAIT_STATE -#define CONF_NVM_WAIT_STATE 0 -#endif - -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_MCLK_CONFIG_H diff --git a/watch-library/config/hpl_nvmctrl_config.h b/watch-library/config/hpl_nvmctrl_config.h deleted file mode 100755 index 76d49bac..00000000 --- a/watch-library/config/hpl_nvmctrl_config.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Auto-generated config file hpl_nvmctrl_config.h */ -#ifndef HPL_NVMCTRL_CONFIG_H -#define HPL_NVMCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic Settings - -// Read Mode Selection -// <0x00=> No Miss Penalty -// <0x01=> Low Power -// <0x02=> Deterministic -// nvm_arch_read_mode -#ifndef CONF_NVM_READ_MODE -#define CONF_NVM_READ_MODE 1 -#endif - -// Power Reduction Mode During Sleep -// <0x00=> Wake On Access -// <0x01=> Wake Up Instant -// <0x03=> Disabled -// nvm_arch_sleepprm -#ifndef CONF_NVM_SLEEPPRM -#define CONF_NVM_SLEEPPRM 0 -#endif - -// Cache Disable -// Indicate whether cache is disable or not -// nvm_arch_cache -#ifndef CONF_NVM_CACHE -#define CONF_NVM_CACHE 0 -#endif - -// - -// <<< end of configuration section >>> - -#endif // HPL_NVMCTRL_CONFIG_H diff --git a/watch-library/config/hpl_osc32kctrl_config.h b/watch-library/config/hpl_osc32kctrl_config.h deleted file mode 100644 index 540f1c60..00000000 --- a/watch-library/config/hpl_osc32kctrl_config.h +++ /dev/null @@ -1,177 +0,0 @@ -/* Auto-generated config file hpl_osc32kctrl_config.h */ -#ifndef HPL_OSC32KCTRL_CONFIG_H -#define HPL_OSC32KCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// RTC Source configuration -// enable_rtc_source -#ifndef CONF_RTCCTRL_CONFIG -#define CONF_RTCCTRL_CONFIG 0 -#endif - -// RTC source control -// RTC Clock Source Selection -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// This defines the clock source for RTC -// rtc_source_oscillator -#ifndef CONF_RTCCTRL_SRC -#ifdef CRYSTALLESS -#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K -#else -#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K -#endif -#endif - -// Use 1 kHz output -// rtc_1khz_selection -#ifndef CONF_RTCCTRL_1KHZ - -#define CONF_RTCCTRL_1KHZ 1 - -#endif - -#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K -#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) -#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K -#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) -#else -#error unexpected CONF_RTCCTRL_SRC -#endif - -// -// -// SLCD Source configuration -// enable_slcd_source -#ifndef CONF_SLCDCTRL_CONFIG -#define CONF_SLCDCTRL_CONFIG 0 -#endif - -// SLCD source control -// SLCD Clock Source Selection -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// This defines the clock source for SLCD -// slcd_source_oscillator -#ifndef CONF_SLCDCTRL_SRC -#define CONF_SLCDCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K -#endif - -// -// -// 32kHz External Crystal Oscillator Configuration -// Indicates whether configuration for External 32K Osc is enabled or not -// enable_xosc32k -#ifndef CONF_XOSC32K_CONFIG -#define CONF_XOSC32K_CONFIG 1 -#endif - -// 32kHz External Crystal Oscillator Control -// Oscillator enable -// Indicates whether 32kHz External Crystal Oscillator is enabled or not -// xosc32k_arch_enable -#ifndef CONF_XOSC32K_ENABLE -#define CONF_XOSC32K_ENABLE 1 -#endif - -// Start-Up Time -// <0x0=>62592us -// <0x1=>125092us -// <0x2=>500092us -// <0x3=>1000092us -// <0x4=>2000092us -// <0x5=>4000092us -// <0x6=>8000092us -// xosc32k_arch_startup -#ifndef CONF_XOSC32K_STARTUP -#define CONF_XOSC32K_STARTUP 0x3 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// xosc32k_arch_ondemand -#ifndef CONF_XOSC32K_ONDEMAND -#define CONF_XOSC32K_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// xosc32k_arch_runstdby -#ifndef CONF_XOSC32K_RUNSTDBY -#define CONF_XOSC32K_RUNSTDBY 1 -#endif - -// 1kHz Output Enable -// Indicates whether 1kHz Output is enabled or not -// xosc32k_arch_en1k -#ifndef CONF_XOSC32K_EN1K -#define CONF_XOSC32K_EN1K 1 -#endif - -// 32kHz Output Enable -// Indicates whether 32kHz Output is enabled or not -// xosc32k_arch_en32k -#ifndef CONF_XOSC32K_EN32K -#define CONF_XOSC32K_EN32K 1 -#endif - -// Clock Switch Back -// Indicates whether Clock Switch Back is enabled or not -// xosc32k_arch_swben -#ifndef CONF_XOSC32K_SWBEN -#define CONF_XOSC32K_SWBEN 0 -#endif - -// Clock Failure Detector -// Indicates whether Clock Failure Detector is enabled or not -// xosc32k_arch_cfden -#ifndef CONF_XOSC32K_CFDEN -#define CONF_XOSC32K_CFDEN 0 -#endif - -// Clock Failure Detector Event Out -// Indicates whether Clock Failure Detector Event Out is enabled or not -// xosc32k_arch_cfdeo -#ifndef CONF_XOSC32K_CFDEO -#define CONF_XOSC32K_CFDEO 0 -#endif - -// Crystal connected to XIN32/XOUT32 Enable -// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// xosc32k_arch_xtalen -#ifndef CONF_XOSC32K_XTALEN -#define CONF_XOSC32K_XTALEN 1 -#endif - -// -// - -// 32kHz Ultra Low Power Internal Oscillator Configuration -// Indicates whether configuration for OSCULP32K is enabled or not -// enable_osculp32k -#ifndef CONF_OSCULP32K_CONFIG -#define CONF_OSCULP32K_CONFIG 1 -#endif - -// 32kHz Ultra Low Power Internal Oscillator Control - -// Oscillator Calibration Control -// Indicates whether Oscillator Calibration is enabled or not -// osculp32k_calib_enable -#ifndef CONF_OSCULP32K_CALIB_ENABLE -#define CONF_OSCULP32K_CALIB_ENABLE 0 -#endif - -// Oscillator Calibration <0x0-0x1F> -// osculp32k_calib -#ifndef CONF_OSCULP32K_CALIB -#define CONF_OSCULP32K_CALIB 0x0 -#endif - -// -// - -// <<< end of configuration section >>> - -#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/watch-library/config/hpl_oscctrl_config.h b/watch-library/config/hpl_oscctrl_config.h deleted file mode 100644 index ba2d42e6..00000000 --- a/watch-library/config/hpl_oscctrl_config.h +++ /dev/null @@ -1,483 +0,0 @@ -/* Auto-generated config file hpl_oscctrl_config.h */ -#ifndef HPL_OSCCTRL_CONFIG_H -#define HPL_OSCCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// External Multipurpose Crystal Oscillator Configuration -// Indicates whether configuration for XOSC is enabled or not -// enable_xosc -#ifndef CONF_XOSC_CONFIG -#define CONF_XOSC_CONFIG 0 -#endif - -// Frequency <400000-32000000> -// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. -// xosc_frequency -#ifndef CONF_XOSC_FREQUENCY -#define CONF_XOSC_FREQUENCY 400000 -#endif - -// External Multipurpose Crystal Oscillator Control -// Oscillator enable -// Indicates whether External Multipurpose Crystal Oscillator is enabled or not -// xosc_arch_enable -#ifndef CONF_XOSC_ENABLE -#define CONF_XOSC_ENABLE 0 -#endif - -// Start-Up Time -// <0x0=>31us -// <0x1=>61us -// <0x2=>122us -// <0x3=>244us -// <0x4=>488us -// <0x5=>977us -// <0x6=>1953us -// <0x7=>3906us -// <0x8=>7813us -// <0x9=>15625us -// <0xA=>31250us -// <0xB=>62500us -// <0xC=>125000us -// <0xD=>250000us -// <0xE=>500000us -// <0xF=>1000000us -// xosc_arch_startup -#ifndef CONF_XOSC_STARTUP -#define CONF_XOSC_STARTUP 0x0 -#endif - -// Automatic Amplitude Gain Control -// Indicates whether Automatic Amplitude Gain Control is enabled or not -// xosc_arch_ampgc -#ifndef CONF_XOSC_AMPGC -#define CONF_XOSC_AMPGC 0 -#endif - -// External Multipurpose Crystal Oscillator Gain -// <0x0=>2MHz -// <0x1=>4MHz -// <0x2=>8MHz -// <0x3=>16MHz -// <0x4=>30MHz -// xosc_arch_gain -#ifndef CONF_XOSC_GAIN -#define CONF_XOSC_GAIN 0x0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// xosc_arch_ondemand -#ifndef CONF_XOSC_ONDEMAND -#define CONF_XOSC_ONDEMAND 1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// xosc_arch_runstdby -#ifndef CONF_XOSC_RUNSTDBY -#define CONF_XOSC_RUNSTDBY 0 -#endif - -// Clock Switch Back -// Indicates whether Clock Switch Back is enabled or not -// xosc_arch_swben -#ifndef CONF_XOSC_SWBEN -#define CONF_XOSC_SWBEN 0 -#endif - -// Clock Failure Detector -// Indicates whether Clock Failure Detector is enabled or not -// xosc_arch_cfden -#ifndef CONF_XOSC_CFDEN -#define CONF_XOSC_CFDEN 0 -#endif - -// Clock Failure Detector Event Out -// Indicates whether Clock Failure Detector Event Out is enabled or not -// xosc_arch_cfdeo -#ifndef CONF_XOSC_CFDEO -#define CONF_XOSC_CFDEO 0 -#endif - -// Crystal connected to XIN/XOUT Enable -// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// xosc_arch_xtalen -#ifndef CONF_XOSC_XTALEN -#define CONF_XOSC_XTALEN 0 -#endif -// -// - -// 16MHz Internal Oscillator Configuration -// Indicates whether configuration for OSC8M is enabled or not -// enable_osc16m -#ifndef CONF_OSC16M_CONFIG -#define CONF_OSC16M_CONFIG 1 -#endif - -// 16MHz Internal Oscillator Control -// Enable -// Indicates whether 16MHz Internal Oscillator is enabled or not -// osc16m_arch_enable -#ifndef CONF_OSC16M_ENABLE -#define CONF_OSC16M_ENABLE 1 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// osc16m_arch_ondemand -#ifndef CONF_OSC16M_ONDEMAND -#define CONF_OSC16M_ONDEMAND 1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// osc16m_arch_runstdby -#ifndef CONF_OSC16M_RUNSTDBY -#define CONF_OSC16M_RUNSTDBY 0 -#endif - -// Oscillator Frequency Selection(Mhz) -// 4 -// 8 -// 12 -// 16 -// This defines the oscillator frequency (Mhz) -// osc16m_freq -#ifndef CONF_OSC16M_FSEL -#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val -#endif - -// Oscillator Calibration Control -// Indicates whether Oscillator Calibration is enabled or not -// osc16m_arch_calib_enable -#ifndef CONF_OSC16M_CALIB_ENABLE -#define CONF_OSC16M_CALIB_ENABLE 0 -#endif - -// 4MHz Frequency Calibration <0x0-0x3F> -// osc16m_arch_4m_fcal -#ifndef CONF_OSC16M_FCAL -#define CONF_OSC16M_4M_FCAL 0 -#endif - -// 4MHz Temperature Calibration <0x0-0x3F> -// osc16m_arch_4m_tcal -#ifndef CONF_OSC16M_TCAL -#define CONF_OSC16M_4M_TCAL 0 -#endif - -// 8MHz Frequency Calibration <0x0-0x3F> -// osc16m_arch_8m_fcal -#ifndef CONF_OSC16M_FCAL -#define CONF_OSC16M_8M_FCAL 0 -#endif - -// 8MHz Temperature Calibration <0x0-0x3F> -// osc16m_arch_8m_tcal -#ifndef CONF_OSC16M_TCAL -#define CONF_OSC16M_8M_TCAL 0 -#endif - -// 12MHz Frequency Calibration <0x0-0x3F> -// osc16m_arch_12m_fcal -#ifndef CONF_OSC16M_FCAL -#define CONF_OSC16M_12M_FCAL 0 -#endif - -// 12MHz Temperature Calibration <0x0-0x3F> -// osc16m_arch_12m_tcal -#ifndef CONF_OSC16M_TCAL -#define CONF_OSC16M_12M_TCAL 0 -#endif - -// 16MHz Frequency Calibration <0x0-0x3F> -// osc16m_arch_fcal -#ifndef CONF_OSC16M_FCAL -#define CONF_OSC16M_16M_FCAL 0 -#endif - -// 16MHz Temperature Calibration <0x0-0x3F> -// osc16m_arch_16m_tcal -#ifndef CONF_OSC16M_TCAL -#define CONF_OSC16M_16M_TCAL 0 -#endif -// -// - -// DFLL Configuration -// Indicates whether configuration for DFLL is enabled or not -// enable_dfll48m -#ifndef CONF_DFLL_CONFIG -#define CONF_DFLL_CONFIG 0 -#endif - -// Reference Clock Source -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Select the clock source. -// dfll48m_ref_clock -#ifndef CONF_DFLL_GCLK -#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -// Digital Frequency Locked Loop Control -// DFLL Enable -// Indicates whether DFLL is enabled or not -// dfll48m_arch_enable -#ifndef CONF_DFLL_ENABLE -#define CONF_DFLL_ENABLE 0 -#endif - -// Wait Lock -// Indicates whether Wait Lock is enabled or not -// dfll_arch_waitlock -#ifndef CONF_DFLL_WAITLOCK -#define CONF_DFLL_WAITLOCK 0 -#endif - -// Bypass Coarse Lock -// Indicates whether Bypass Coarse Lock is enabled or not -// dfll_arch_bplckc -#ifndef CONF_DFLL_BPLCKC -#define CONF_DFLL_BPLCKC 0 -#endif - -// Quick Lock Disable -// Indicates whether Quick Lock Disable is enabled or not -// dfll_arch_qldis -#ifndef CONF_DFLL_QLDIS -#define CONF_DFLL_QLDIS 0 -#endif - -// Chill Cycle Disable -// Indicates whether Chill Cycle Disable is enabled or not -// dfll_arch_ccdis -#ifndef CONF_DFLL_CCDIS -#define CONF_DFLL_CCDIS 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// dfll_arch_ondemand -#ifndef CONF_DFLL_ONDEMAND -#define CONF_DFLL_ONDEMAND 1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// dfll_arch_runstdby -#ifndef CONF_DFLL_RUNSTDBY -#define CONF_DFLL_RUNSTDBY 0 -#endif - -// USB Clock Recovery Mode -// Indicates whether USB Clock Recovery Mode is enabled or not -// dfll_arch_usbcrm -#ifndef CONF_DFLL_USBCRM -#define CONF_DFLL_USBCRM 0 -#endif - -// Lose Lock After Wake -// Indicates whether Lose Lock After Wake is enabled or not -// dfll_arch_llaw -#ifndef CONF_DFLL_LLAW -#define CONF_DFLL_LLAW 0 -#endif - -// Stable DFLL Frequency -// Indicates whether Stable DFLL Frequency is enabled or not -// dfll_arch_stable -#ifndef CONF_DFLL_STABLE -#define CONF_DFLL_STABLE 0 -#endif - -// Operating Mode Selection -// <0=>Open Loop Mode -// <1=>Closed Loop Mode -// dfll48m_mode -#ifndef CONF_DFLL_MODE -#define CONF_DFLL_MODE 0 -#endif - -// Coarse Maximum Step <0x0-0x1F> -// dfll_arch_cstep -#ifndef CONF_DFLL_CSTEP -#define CONF_DFLL_CSTEP 1 -#endif - -// Fine Maximum Step <0x0-0x3FF> -// dfll_arch_fstep -#ifndef CONF_DFLL_FSTEP -#define CONF_DFLL_FSTEP 1 -#endif - -// DFLL Multiply Factor <0x0-0xFFFF> -// dfll48m_mul -#ifndef CONF_DFLL_MUL -#define CONF_DFLL_MUL 0 -#endif - -// DFLL Calibration Overwrite -// Indicates whether Overwrite Calibration value of DFLL -// dfll_arch_calibration -#ifndef CONF_DFLL_OVERWRITE_CALIBRATION -#define CONF_DFLL_OVERWRITE_CALIBRATION 0 -#endif - -// Coarse Value <0x0-0x3F> -// dfll_arch_coarse -#ifndef CONF_DFLL_COARSE -#define CONF_DFLL_COARSE (0x1f / 4) -#endif - -// Fine Value <0x0-0x3FF> -// dfll_arch_fine -#ifndef CONF_DFLL_FINE -#define CONF_DFLL_FINE (0x200) -#endif - -// - -// - -// - -// DPLL Configuration -// Indicates whether configuration for DPLL is enabled or not -// enable_fdpll96m -#ifndef CONF_DPLL_CONFIG -#define CONF_DPLL_CONFIG 0 -#endif - -// Reference Clock Source -// 32kHz External Crystal Oscillator (XOSC32K) -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Select the clock source. -// fdpll96m_ref_clock -#ifndef CONF_DPLL_GCLK -#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K - -#endif - -// Digital Phase Locked Loop Control -// Enable -// Indicates whether Digital Phase Locked Loop is enabled or not -// fdpll96m_arch_enable -#ifndef CONF_DPLL_ENABLE -#define CONF_DPLL_ENABLE 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// fdpll96m_arch_ondemand -#ifndef CONF_DPLL_ONDEMAND -#define CONF_DPLL_ONDEMAND 1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// fdpll96m_arch_runstdby -#ifndef CONF_DPLL_RUNSTDBY -#define CONF_DPLL_RUNSTDBY 0 -#endif - -// Loop Divider Ratio Fractional Part <0x0-0xF> -// fdpll96m_ldrfrac -#ifndef CONF_DPLL_LDRFRAC -#define CONF_DPLL_LDRFRAC 0xd -#endif - -// Loop Divider Ratio Integer Part <0x0-0xFFF> -// fdpll96m_ldr -#ifndef CONF_DPLL_LDR -#define CONF_DPLL_LDR 0x5b7 -#endif - -// Clock Divider <0x0-0x3FF> -// fdpll96m_clock_div -#ifndef CONF_DPLL_DIV -#define CONF_DPLL_DIV 0 -#endif - -// Lock Bypass -// Indicates whether Lock Bypass is enabled or not -// fdpll96m_arch_lbypass -#ifndef CONF_DPLL_LBYPASS -#define CONF_DPLL_LBYPASS 0 -#endif - -// Lock Time -// <0=>No time-out, automatic lock -// <4=>The Time-out if no lock within 8 ms -// <5=>The Time-out if no lock within 9 ms -// <6=>The Time-out if no lock within 10 ms -// <7=>The Time-out if no lock within 11 ms -// fdpll96m_arch_ltime -#ifndef CONF_DPLL_LTIME -#define CONF_DPLL_LTIME 0 -#endif - -// Reference Clock Selection -// <0=>XOSC32K clock reference -// <1=>XOSC clock reference -// <2=>GCLK clock reference -// fdpll96m_arch_refclk -#ifndef CONF_DPLL_REFCLK -#define CONF_DPLL_REFCLK 0 -#endif - -// Wake Up Fast -// Indicates whether Wake Up Fast is enabled or not -// fdpll96m_arch_wuf -#ifndef CONF_DPLL_WUF -#define CONF_DPLL_WUF 0 -#endif - -// Low-Power Enable -// Indicates whether Low-Power Enable is enabled or not -// fdpll96m_arch_lpen -#ifndef CONF_DPLL_LPEN -#define CONF_DPLL_LPEN 0 -#endif - -// Reference Clock Selection -// <0=>Default filter mode -// <1=>Low bandwidth filter -// <2=>High bandwidth filter -// <3=>High damping filter -// fdpll96m_arch_filter -#ifndef CONF_DPLL_FILTER -#define CONF_DPLL_FILTER 0 -#endif - -// Output Clock Prescaler -// 1 -// 2 -// 4 -// fdpll96m_presc -#ifndef CONF_DPLL_PRESC -#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val -#endif -// -// - -// <<< end of configuration section >>> - -#endif // HPL_OSCCTRL_CONFIG_H diff --git a/watch-library/config/hpl_port_config.h b/watch-library/config/hpl_port_config.h deleted file mode 100644 index 1efce33e..00000000 --- a/watch-library/config/hpl_port_config.h +++ /dev/null @@ -1,284 +0,0 @@ -/* Auto-generated config file hpl_port_config.h */ -#ifndef HPL_PORT_CONFIG_H -#define HPL_PORT_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// PORT Input Event 0 configuration -// enable_port_input_event_0 -#ifndef CONF_PORT_EVCTRL_PORT_0 -#define CONF_PORT_EVCTRL_PORT_0 0 -#endif - -// PORT Input Event 0 configuration on PORT A - -// PORTA Input Event 0 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled -// porta_input_event_enable_0 -#ifndef CONF_PORTA_EVCTRL_PORTEI_0 -#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 -#endif - -// PORTA Event 0 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_0 -#ifndef CONF_PORTA_EVCTRL_PID_0 -#define CONF_PORTA_EVCTRL_PID_0 0x0 -#endif - -// PORTA Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 0 -// porta_event_action_0 -#ifndef CONF_PORTA_EVCTRL_EVACT_0 -#define CONF_PORTA_EVCTRL_EVACT_0 0 -#endif - -// -// PORT Input Event 0 configuration on PORT B - -// PORTB Input Event 0 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled -// portb_input_event_enable_0 -#ifndef CONF_PORTB_EVCTRL_PORTEI_0 -#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 -#endif - -// PORTB Event 0 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_0 -#ifndef CONF_PORTB_EVCTRL_PID_0 -#define CONF_PORTB_EVCTRL_PID_0 0x0 -#endif - -// PORTB Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 0 -// portb_event_action_0 -#ifndef CONF_PORTB_EVCTRL_EVACT_0 -#define CONF_PORTB_EVCTRL_EVACT_0 0 -#endif - -// - -// - -// PORT Input Event 1 configuration -// enable_port_input_event_1 -#ifndef CONF_PORT_EVCTRL_PORT_1 -#define CONF_PORT_EVCTRL_PORT_1 0 -#endif - -// PORT Input Event 1 configuration on PORT A - -// PORTA Input Event 1 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled -// porta_input_event_enable_1 -#ifndef CONF_PORTA_EVCTRL_PORTEI_1 -#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 -#endif - -// PORTA Event 1 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_1 -#ifndef CONF_PORTA_EVCTRL_PID_1 -#define CONF_PORTA_EVCTRL_PID_1 0x0 -#endif - -// PORTA Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 1 -// porta_event_action_1 -#ifndef CONF_PORTA_EVCTRL_EVACT_1 -#define CONF_PORTA_EVCTRL_EVACT_1 0 -#endif - -// -// PORT Input Event 1 configuration on PORT B - -// PORTB Input Event 1 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled -// portb_input_event_enable_1 -#ifndef CONF_PORTB_EVCTRL_PORTEI_1 -#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 -#endif - -// PORTB Event 1 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_1 -#ifndef CONF_PORTB_EVCTRL_PID_1 -#define CONF_PORTB_EVCTRL_PID_1 0x0 -#endif - -// PORTB Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 1 -// portb_event_action_1 -#ifndef CONF_PORTB_EVCTRL_EVACT_1 -#define CONF_PORTB_EVCTRL_EVACT_1 0 -#endif - -// - -// - -// PORT Input Event 2 configuration -// enable_port_input_event_2 -#ifndef CONF_PORT_EVCTRL_PORT_2 -#define CONF_PORT_EVCTRL_PORT_2 0 -#endif - -// PORT Input Event 2 configuration on PORT A - -// PORTA Input Event 2 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled -// porta_input_event_enable_2 -#ifndef CONF_PORTA_EVCTRL_PORTEI_2 -#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 -#endif - -// PORTA Event 2 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_2 -#ifndef CONF_PORTA_EVCTRL_PID_2 -#define CONF_PORTA_EVCTRL_PID_2 0x0 -#endif - -// PORTA Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 2 -// porta_event_action_2 -#ifndef CONF_PORTA_EVCTRL_EVACT_2 -#define CONF_PORTA_EVCTRL_EVACT_2 0 -#endif - -// -// PORT Input Event 2 configuration on PORT B - -// PORTB Input Event 2 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled -// portb_input_event_enable_2 -#ifndef CONF_PORTB_EVCTRL_PORTEI_2 -#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 -#endif - -// PORTB Event 2 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_2 -#ifndef CONF_PORTB_EVCTRL_PID_2 -#define CONF_PORTB_EVCTRL_PID_2 0x0 -#endif - -// PORTB Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 2 -// portb_event_action_2 -#ifndef CONF_PORTB_EVCTRL_EVACT_2 -#define CONF_PORTB_EVCTRL_EVACT_2 0 -#endif - -// - -// - -// PORT Input Event 3 configuration -// enable_port_input_event_3 -#ifndef CONF_PORT_EVCTRL_PORT_3 -#define CONF_PORT_EVCTRL_PORT_3 0 -#endif - -// PORT Input Event 3 configuration on PORT A - -// PORTA Input Event 3 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled -// porta_input_event_enable_3 -#ifndef CONF_PORTA_EVCTRL_PORTEI_3 -#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 -#endif - -// PORTA Event 3 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_3 -#ifndef CONF_PORTA_EVCTRL_PID_3 -#define CONF_PORTA_EVCTRL_PID_3 0x0 -#endif - -// PORTA Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 3 -// porta_event_action_3 -#ifndef CONF_PORTA_EVCTRL_EVACT_3 -#define CONF_PORTA_EVCTRL_EVACT_3 0 -#endif - -// -// PORT Input Event 3 configuration on PORT B - -// PORTB Input Event 3 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled -// portb_input_event_enable_3 -#ifndef CONF_PORTB_EVCTRL_PORTEI_3 -#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 -#endif - -// PORTB Event 3 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_3 -#ifndef CONF_PORTB_EVCTRL_PID_3 -#define CONF_PORTB_EVCTRL_PID_3 0x0 -#endif - -// PORTB Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 3 -// portb_event_action_3 -#ifndef CONF_PORTB_EVCTRL_EVACT_3 -#define CONF_PORTB_EVCTRL_EVACT_3 0 -#endif - -// - -// - -#define CONF_PORTA_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ - | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ - | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) -#define CONF_PORTB_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ - | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ - | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) - -// <<< end of configuration section >>> - -#endif // HPL_PORT_CONFIG_H diff --git a/watch-library/config/hpl_rtc_config.h b/watch-library/config/hpl_rtc_config.h deleted file mode 100644 index 9085ca37..00000000 --- a/watch-library/config/hpl_rtc_config.h +++ /dev/null @@ -1,318 +0,0 @@ -/* Auto-generated config file hpl_rtc_config.h */ -#ifndef HPL_RTC_CONFIG_H -#define HPL_RTC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic settings - -#ifndef CONF_RTC_ENABLE -#define CONF_RTC_ENABLE 1 -#endif - -// Force reset RTC on initialization -// Force RTC to reset on initialization. -// Note that the previous power down data in RTC is lost if it's enabled. -// rtc_arch_init_reset -#ifndef CONF_RTC_INIT_RESET -#define CONF_RTC_INIT_RESET 0 -#endif - -// Prescaler configuration -// <0x0=>OFF(Peripheral clock divided by 1) -// <0x1=>Peripheral clock divided by 1 -// <0x2=>Peripheral clock divided by 2 -// <0x3=>Peripheral clock divided by 4 -// <0x4=>Peripheral clock divided by 8 -// <0x5=>Peripheral clock divided by 16 -// <0x6=>Peripheral clock divided by 32 -// <0x7=>Peripheral clock divided by 64 -// <0x8=>Peripheral clock divided by 128 -// <0x9=>Peripheral clock divided by 256 -// <0xA=>Peripheral clock divided by 512 -// <0xB=>Peripheral clock divided by 1024 -// These bits define the RTC clock relative to the peripheral clock -// rtc_arch_prescaler -#ifndef CONF_RTC_PRESCALER - -#define CONF_RTC_PRESCALER 0xb - -#endif - -#ifndef CONF_RTC_COMP_VAL - -#define CONF_RTC_COMP_VAL 0 - -#endif - -// RTC Tamper Input 0 settings -// tamper_input_0_settings -#ifndef CONF_TAMPER_INPUT_0_SETTINGS -#define CONF_TAMPER_INPUT_0_SETTINGS 0 -#endif - -// Tamper Level Settings -// Indicates Tamper input 0 level -// tamper_level_0 -#ifndef CONF_RTC_TAMP_LVL_0 -#define CONF_RTC_TAMP_LVL_0 0 -#endif - -// RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// These bits define the RTC Tamper Input Action to be performed -// rtc_tamper_input_action_0 -#ifndef CONF_RTC_TAMPER_INACT_0 -#define CONF_RTC_TAMPER_INACT_0 0 -#endif - -// Debounce Enable for Tamper Input -// Indicates Debounce should be enabled for Tamper input 0 -// tamper_debounce_enable_0 -#ifndef CONF_RTC_TAMP_DEBNC_0 -#define CONF_RTC_TAMP_DEBNC_0 0 -#endif - -// - -// RTC Tamper Input 1 settings -// tamper_input_1_settings -#ifndef CONF_TAMPER_INPUT_1_SETTINGS -#define CONF_TAMPER_INPUT_1_SETTINGS 0 -#endif - -// Tamper Level Settings -// Indicates Tamper input 1 level -// tamper_level_1 -#ifndef CONF_RTC_TAMP_LVL_1 -#define CONF_RTC_TAMP_LVL_1 0 -#endif - -// RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// These bits define the RTC Tamper Input Action to be performed -// rtc_tamper_input_action_1 -#ifndef CONF_RTC_TAMPER_INACT_1 -#define CONF_RTC_TAMPER_INACT_1 0 -#endif - -// Debounce Enable for Tamper Input -// Indicates Debounce should be enabled for Tamper input 1 -// tamper_debounce_enable_1 -#ifndef CONF_RTC_TAMP_DEBNC_1 -#define CONF_RTC_TAMP_DEBNC_1 0 -#endif - -// - -// RTC Tamper Input 2 settings -// tamper_input_2_settings -#ifndef CONF_TAMPER_INPUT_2_SETTINGS -#define CONF_TAMPER_INPUT_2_SETTINGS 0 -#endif - -// Tamper Level Settings -// Indicates Tamper input 2 level -// tamper_level_2 -#ifndef CONF_RTC_TAMP_LVL_2 -#define CONF_RTC_TAMP_LVL_2 0 -#endif - -// RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// These bits define the RTC Tamper Input Action to be performed -// rtc_tamper_input_action_2 -#ifndef CONF_RTC_TAMPER_INACT_2 -#define CONF_RTC_TAMPER_INACT_2 0 -#endif - -// Debounce Enable for Tamper Input -// Indicates Debounce should be enabled for Tamper input 2 -// tamper_debounce_enable_2 -#ifndef CONF_RTC_TAMP_DEBNC_2 -#define CONF_RTC_TAMP_DEBNC_2 0 -#endif - -// - -// RTC Tamper Input 3 settings -// tamper_input_3_settings -#ifndef CONF_TAMPER_INPUT_3_SETTINGS -#define CONF_TAMPER_INPUT_3_SETTINGS 0 -#endif - -// Tamper Level Settings -// Indicates Tamper input 3 level -// tamper_level_3 -#ifndef CONF_RTC_TAMP_LVL_3 -#define CONF_RTC_TAMP_LVL_3 0 -#endif - -// RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// These bits define the RTC Tamper Input Action to be performed -// rtc_tamper_input_action_3 -#ifndef CONF_RTC_TAMPER_INACT_3 -#define CONF_RTC_TAMPER_INACT_3 0 -#endif - -// Debounce Enable for Tamper Input -// Indicates Debounce should be enabled for Tamper input 3 -// tamper_debounce_enable_3 -#ifndef CONF_RTC_TAMP_DEBNC_3 -#define CONF_RTC_TAMP_DEBNC_3 0 -#endif - -// - -// RTC Tamper Input 4 settings -// tamper_input_4_settings -#ifndef CONF_TAMPER_INPUT_4_SETTINGS -#define CONF_TAMPER_INPUT_4_SETTINGS 0 -#endif - -// Tamper Level Settings -// Indicates Tamper input 4 level -// tamper_level_4 -#ifndef CONF_RTC_TAMP_LVL_4 -#define CONF_RTC_TAMP_LVL_4 0 -#endif - -// RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// These bits define the RTC Tamper Input Action to be performed -// rtc_tamper_input_action_4 -#ifndef CONF_RTC_TAMPER_INACT_4 -#define CONF_RTC_TAMPER_INACT_4 0 -#endif - -// Debounce Enable for Tamper Input -// Indicates Debounce should be enabled for Tamper input 4 -// tamper_debounce_enable_4 -#ifndef CONF_RTC_TAMP_DEBNC_4 -#define CONF_RTC_TAMP_DEBNC_4 0 -#endif - -// - -// RTC Tamper Active Layer Frequency Prescalar -// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2 -// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4 -// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8 -// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16 -// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32 -// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64 -// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128 -// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256 -// These bits define the RTC Tamper Active Layer Frequecny Prescalar -// rtc_tamper_active_layer_frequency_prescalar -#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES -#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0 -#endif - -// RTC Tamper Debounce Frequency Prescalar -// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2 -// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4 -// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8 -// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16 -// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32 -// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64 -// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128 -// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256 -// These bits define the RTC Debounce Frequency Prescalar -// rtc_tamper_debounce_frequency_prescalar -#ifndef CONF_RTC_TAMP_DEBF_PRES -#define CONF_RTC_TAMP_DEBF_PRES 0 -#endif - -// Event control -// rtc_event_control -#ifndef CONF_RTC_EVENT_CONTROL_ENABLE -#define CONF_RTC_EVENT_CONTROL_ENABLE 0 -#endif - -// Periodic Interval 0 Event Output -// This bit indicates whether Periodic interval 0 event is enabled and will be generated -// rtc_pereo0 -#ifndef CONF_RTC_PEREO0 -#define CONF_RTC_PEREO0 0 -#endif -// Periodic Interval 1 Event Output -// This bit indicates whether Periodic interval 1 event is enabled and will be generated -// rtc_pereo1 -#ifndef CONF_RTC_PEREO1 -#define CONF_RTC_PEREO1 0 -#endif -// Periodic Interval 2 Event Output -// This bit indicates whether Periodic interval 2 event is enabled and will be generated -// rtc_pereo2 -#ifndef CONF_RTC_PEREO2 -#define CONF_RTC_PEREO2 0 -#endif -// Periodic Interval 3 Event Output -// This bit indicates whether Periodic interval 3 event is enabled and will be generated -// rtc_pereo3 -#ifndef CONF_RTC_PEREO3 -#define CONF_RTC_PEREO3 0 -#endif -// Periodic Interval 4 Event Output -// This bit indicates whether Periodic interval 4 event is enabled and will be generated -// rtc_pereo4 -#ifndef CONF_RTC_PEREO4 -#define CONF_RTC_PEREO4 0 -#endif -// Periodic Interval 5 Event Output -// This bit indicates whether Periodic interval 5 event is enabled and will be generated -// rtc_pereo5 -#ifndef CONF_RTC_PEREO5 -#define CONF_RTC_PEREO5 0 -#endif -// Periodic Interval 6 Event Output -// This bit indicates whether Periodic interval 6 event is enabled and will be generated -// rtc_pereo6 -#ifndef CONF_RTC_PEREO6 -#define CONF_RTC_PEREO6 0 -#endif -// Periodic Interval 7 Event Output -// This bit indicates whether Periodic interval 7 event is enabled and will be generated -// rtc_pereo7 -#ifndef CONF_RTC_PEREO7 -#define CONF_RTC_PEREO7 0 -#endif - -// Compare 0 Event Output -// This bit indicates whether Compare O event is enabled and will be generated -// rtc_cmpeo0 -#ifndef CONF_RTC_COMPE0 -#define CONF_RTC_COMPE0 0 -#endif - -// Overflow Event Output -// This bit indicates whether Overflow event is enabled and will be generated -// rtc_ovfeo -#ifndef CONF_RTC_OVFEO -#define CONF_RTC_OVFEO 0 -#endif - -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_RTC_CONFIG_H diff --git a/watch-library/config/hpl_sercom_config.h b/watch-library/config/hpl_sercom_config.h deleted file mode 100644 index 6df4b08e..00000000 --- a/watch-library/config/hpl_sercom_config.h +++ /dev/null @@ -1,303 +0,0 @@ -/* Auto-generated config file hpl_sercom_config.h */ -#ifndef HPL_SERCOM_CONFIG_H -#define HPL_SERCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER -#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) -#endif - -#ifndef CONF_SERCOM_1_I2CM_ENABLE -#define CONF_SERCOM_1_I2CM_ENABLE 1 -#endif - -// Basic - -// I2C Bus clock speed (Hz) <1-400000> -// I2C Bus clock (SCL) speed measured in Hz -// i2c_master_baud_rate -#ifndef CONF_SERCOM_1_I2CM_BAUD -#define CONF_SERCOM_1_I2CM_BAUD 100000 -#endif - -// - -// Advanced -// i2c_master_advanced -#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG -#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0 -#endif - -// TRise (ns) <0-300> -// Determined by the bus impedance, check electric characteristics in the datasheet -// Standard Fast Mode: typical 215ns, max 300ns -// Fast Mode +: typical 60ns, max 100ns -// High Speed Mode: typical 20ns, max 40ns -// i2c_master_arch_trise - -#ifndef CONF_SERCOM_1_I2CM_TRISE -#define CONF_SERCOM_1_I2CM_TRISE 215 -#endif - -// Master SCL Low Extended Time-Out (MEXTTOEN) -// This enables the master SCL low extend time-out -// i2c_master_arch_mexttoen -#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN -#define CONF_SERCOM_1_I2CM_MEXTTOEN 0 -#endif - -// Slave SCL Low Extend Time-Out (SEXTTOEN) -// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine -// i2c_master_arch_sexttoen -#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN -#define CONF_SERCOM_1_I2CM_SEXTTOEN 0 -#endif - -// SCL Low Time-Out (LOWTOUT) -// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold -// i2c_master_arch_lowtout -#ifndef CONF_SERCOM_1_I2CM_LOWTOUT -#define CONF_SERCOM_1_I2CM_LOWTOUT 0 -#endif - -// Inactive Time-Out (INACTOUT) -// <0x0=>Disabled -// <0x1=>5-6 SCL cycle time-out(50-60us) -// <0x2=>10-11 SCL cycle time-out(100-110us) -// <0x3=>20-21 SCL cycle time-out(200-210us) -// Defines if inactivity time-out should be enabled, and how long the time-out should be -// i2c_master_arch_inactout -#ifndef CONF_SERCOM_1_I2CM_INACTOUT -#define CONF_SERCOM_1_I2CM_INACTOUT 0x0 -#endif - -// SDA Hold Time (SDAHOLD) -// <0=>Disabled -// <1=>50-100ns hold time -// <2=>300-600ns hold time -// <3=>400-800ns hold time -// Defines the SDA hold time with respect to the negative edge of SCL -// i2c_master_arch_sdahold -#ifndef CONF_SERCOM_1_I2CM_SDAHOLD -#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2 -#endif - -// Run in stand-by -// Determine if the module shall run in standby sleep mode -// i2c_master_arch_runstdby -#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY -#define CONF_SERCOM_1_I2CM_RUNSTDBY 0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. -// <0=>Keep running -// <1=>Halt -// i2c_master_arch_dbgstop -#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE -#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0 -#endif - -// - -#ifndef CONF_SERCOM_1_I2CM_SPEED -#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode -#endif -#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300 -#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns -#undef CONF_SERCOM_1_I2CM_TRISE -#define CONF_SERCOM_1_I2CM_TRISE 215U -#endif - -// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) -// BAUD + BAUDLOW = -------------------------------------------------------------------- -// i2c_scl_freq -// BAUD: register value low [7:0] -// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW -#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ - - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ - / 1000U)) \ - * 10U \ - + 5U) \ - / (CONF_SERCOM_1_I2CM_BAUD * 10U)) -#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE -#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) -#warning Requested I2C baudrate too low, please check -#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF -#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1 -#warning Requested I2C baudrate too high, please check -#define CONF_SERCOM_1_I2CM_BAUD_RATE 1 -#else -#define CONF_SERCOM_1_I2CM_BAUD_RATE \ - ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) -#endif -#endif - -#include - -// Enable configuration of module -#ifndef CONF_SERCOM_3_SPI_ENABLE -#define CONF_SERCOM_3_SPI_ENABLE 1 -#endif - -// Set module in SPI Master mode -#ifndef CONF_SERCOM_3_SPI_MODE -#define CONF_SERCOM_3_SPI_MODE 0x03 -#endif - -// Basic Configuration - -// Receive buffer enable -// Enable receive buffer to receive data from slave (RXEN) -// spi_master_rx_enable -#ifndef CONF_SERCOM_3_SPI_RXEN -#define CONF_SERCOM_3_SPI_RXEN 0x1 -#endif - -// Character Size -// Bit size for all characters sent over the SPI bus (CHSIZE) -// <0x0=>8 bits -// <0x1=>9 bits -// spi_master_character_size -#ifndef CONF_SERCOM_3_SPI_CHSIZE -#define CONF_SERCOM_3_SPI_CHSIZE 0x0 -#endif -// Baud rate <1-12000000> -// The SPI data transfer rate -// spi_master_baud_rate -#ifndef CONF_SERCOM_3_SPI_BAUD -#define CONF_SERCOM_3_SPI_BAUD 50000 -#endif - -// - -// Advanced Configuration -// spi_master_advanced -#ifndef CONF_SERCOM_3_SPI_ADVANCED -#define CONF_SERCOM_3_SPI_ADVANCED 1 -#endif - -// Dummy byte <0x00-0x1ff> -// spi_master_dummybyte -// Dummy byte used when reading data from the slave without sending any data -#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE -#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff -#endif - -// Data Order -// <0=>MSB first -// <1=>LSB first -// I least significant or most significant bit is shifted out first (DORD) -// spi_master_arch_dord -#ifndef CONF_SERCOM_3_SPI_DORD -#define CONF_SERCOM_3_SPI_DORD 0x0 -#endif - -// Clock Polarity -// <0=>SCK is low when idle -// <1=>SCK is high when idle -// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) -// spi_master_arch_cpol -#ifndef CONF_SERCOM_3_SPI_CPOL -#define CONF_SERCOM_3_SPI_CPOL 0x0 -#endif - -// Clock Phase -// <0x0=>Sample input on leading edge -// <0x1=>Sample input on trailing edge -// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) -// spi_master_arch_cpha -#ifndef CONF_SERCOM_3_SPI_CPHA -#define CONF_SERCOM_3_SPI_CPHA 0x0 -#endif - -// Immediate Buffer Overflow Notification -// Controls when OVF is asserted (IBON) -// <0x0=>In data stream -// <0x1=>On buffer overflow -// spi_master_arch_ibon -#ifndef CONF_SERCOM_3_SPI_IBON -#define CONF_SERCOM_3_SPI_IBON 0x0 -#endif - -// Run in stand-by -// Module stays active in stand-by sleep mode. (RUNSTDBY) -// spi_master_arch_runstdby -#ifndef CONF_SERCOM_3_SPI_RUNSTDBY -#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) -// <0=>Keep running -// <1=>Halt -// spi_master_arch_dbgstop -#ifndef CONF_SERCOM_3_SPI_DBGSTOP -#define CONF_SERCOM_3_SPI_DBGSTOP 0 -#endif - -// - -// Address mode disabled in master mode -#ifndef CONF_SERCOM_3_SPI_AMODE_EN -#define CONF_SERCOM_3_SPI_AMODE_EN 0 -#endif - -#ifndef CONF_SERCOM_3_SPI_AMODE -#define CONF_SERCOM_3_SPI_AMODE 0 -#endif - -#ifndef CONF_SERCOM_3_SPI_ADDR -#define CONF_SERCOM_3_SPI_ADDR 0 -#endif - -#ifndef CONF_SERCOM_3_SPI_ADDRMASK -#define CONF_SERCOM_3_SPI_ADDRMASK 0 -#endif - -#ifndef CONF_SERCOM_3_SPI_SSDE -#define CONF_SERCOM_3_SPI_SSDE 0 -#endif - -#ifndef CONF_SERCOM_3_SPI_MSSEN -#define CONF_SERCOM_3_SPI_MSSEN 0x0 -#endif - -#ifndef CONF_SERCOM_3_SPI_PLOADEN -#define CONF_SERCOM_3_SPI_PLOADEN 0 -#endif - -// Receive Data Pinout -// <0x0=>PAD[0] -// <0x1=>PAD[1] -// <0x2=>PAD[2] -// <0x3=>PAD[3] -// spi_master_rxpo -#ifndef CONF_SERCOM_3_SPI_RXPO -#define CONF_SERCOM_3_SPI_RXPO 2 -#endif - -// Transmit Data Pinout -// <0x0=>PAD[0,1]_DO_SCK -// <0x1=>PAD[2,3]_DO_SCK -// <0x2=>PAD[3,1]_DO_SCK -// <0x3=>PAD[0,3]_DO_SCK -// spi_master_txpo -#ifndef CONF_SERCOM_3_SPI_TXPO -#define CONF_SERCOM_3_SPI_TXPO 3 -#endif - -// Calculate baud register value from requested baudrate value -#ifndef CONF_SERCOM_3_SPI_BAUD_RATE -#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1 -#endif - -// <<< end of configuration section >>> - -#endif // HPL_SERCOM_CONFIG_H diff --git a/watch-library/config/hpl_slcd_config.h b/watch-library/config/hpl_slcd_config.h deleted file mode 100644 index d78e3391..00000000 --- a/watch-library/config/hpl_slcd_config.h +++ /dev/null @@ -1,239 +0,0 @@ -/* Auto-generated config file hpl_slcd_config.h */ -#ifndef HPL_SLCD_CONFIG_H -#define HPL_SLCD_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include -#include -#include "pins.h" - -// Standard configuration - -// Number of COM Lines -// Number of COM Lines -// <0=>1 -// <1=>2 -// <2=>3 -// <3=>4 -// <4=>6 -// <5=>8 -// slcd_arch_com_num -#ifndef CONF_SLCD_COM_NUM -#define CONF_SLCD_COM_NUM 2 -#endif - -// Number of Segment Lines <1-44> -// Number of Segment Lines -// slcd_arch_seg_num -#ifndef CONF_SLCD_SEG_NUM -#define CONF_SLCD_SEG_NUM 24 -#endif - -#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_SIXTH_Val && CONF_SLCD_SEG_NUM > 42 -#warning Segment number should less than or equals to 42 -#endif -#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_EIGHT_Val && CONF_SLCD_SEG_NUM > 40 -#warning Segment number should less than or equals to 40 -#endif - -// Bias -// Bias Settting -// <0=>STATIC -// <1=>HALF -// <2=>THIRD -// <3=>FOURTH -// slcd_arch_bias -#ifndef CONF_SLCD_BIAS -#define CONF_SLCD_BIAS 2 -#endif - -#if CONF_SLCD_COM_NUM == 0 && CONF_SLCD_BIAS != 0 -#warning Recommended Bias for 1 common terminal is STATIC -#elif CONF_SLCD_COM_NUM == 1 && CONF_SLCD_BIAS != 1 -#warning Recommended Bias for 2 Common Terminals is HALF -#elif CONF_SLCD_COM_NUM <= 4 && CONF_SLCD_BIAS != 2 -#warning Recommended Bias for 3/4/6 Common Terminals is THIRD -#elif CONF_SLCD_COM_NUM == 5 && CONF_SLCD_BIAS != 3 -#warning Recommended Bias for 8 Common Terminals is FOURTH -#endif - -// Bias Buffer Enable -// Enable Bias Buffer -// slcd_arch_bben -#ifndef CONF_SLCD_BBEN -#define CONF_SLCD_BBEN 1 -#endif - -// Bias Buffer Enable Duration <1-16> -// Configure the enable duration of the bias buffer, unit is cycle of SLCD OSC clock source -// slcd_arch_bbd -#ifndef CONF_SLCD_BBD -#define CONF_SLCD_BBD 2 -#endif - -// Clock Prescaler -// Setting for LCD frame frequency -// <0=>16 -// <1=>32 -// <2=>64 -// <3=>128 -// slcd_arch_presc -#ifndef CONF_SLCD_PRESC -#define CONF_SLCD_PRESC 1 -#endif - -// Clock Divider -// Setting for LCD frame frequency -// <0=>1 -// <1=>2 -// <2=>3 -// <3=>4 -// <4=>5 -// <5=>6 -// <6=>7 -// <7=>8 -// slcd_arch_ckdiv -#ifndef CONF_SLCD_CKDIV -#define CONF_SLCD_CKDIV 5 -#endif - -/* TODO add frame frequency check */ - -// Reference Refresh Frequency -// Setting for Reference Refresh Frequency -// <0=>2kHz -// <1=>1kHz -// <2=>500Hz -// <3=>250Hz -// <4=>125Hz -// <5=>62.5Hz -// slcd_arch_rrf -#ifndef CONF_SLCD_RRF -#define CONF_SLCD_RRF 0 -#endif - -// Power Refresh Frequency -// Setting for Charge pump Refresh Frequency -// <0=>2kHz -// <1=>1kHz -// <2=>500Hz -// <3=>250Hz -// slcd_arch_prf -#ifndef CONF_SLCD_PRF -#define CONF_SLCD_PRF 3 -#endif - -// External VLCD -// Setting for how VLCD is generated -// slcd_arch_xvlcd -#ifndef CONF_SLCD_XVLCD -#define CONF_SLCD_XVLCD 0 -#endif - -// Waveform Mode -// Setting for Waveform Mode -// <0=>Low Power Waveform(frame-inversion) -// <1=>Standard Waveform Mode(bit-inversion) -// slcd_arch_wmod -#ifndef CONF_SLCD_WMOD -#define CONF_SLCD_WMOD 0 -#endif - -// Contrast Adjustment -// The contrast of the LCD is determined by the value of VLCD voltage. -// The higher the VLCD voltage, the higher is the contrast. -// The software contrast adjustment is only possible in internal supply mode. -// <0=>2.5056V -// <1=>2.5731V -// <2=>2.6379V -// <3=>2.7054V -// <4=>2.7729V -// <5=>2.8404V -// <6=>2.9052V -// <7=>2.9727V -// <8=>3.0402V -// <9=>3.1077V -// <10=>3.1725V -// <11=>3.24V -// <12=>3.3075V -// <13=>3.375V -// <14=>3.4398V -// <15=>3.5073V -// slcd_arch_contrast_adjust -#ifndef CONF_SLCD_CONTRAST_ADJUST -#define CONF_SLCD_CONTRAST_ADJUST 14 -#endif - -// - -// Advanced configuration -// slcd_arch_advanced_settings -#ifndef CONF_SLCD_ADVANCED_SETTINGS -#define CONF_SLCD_ADVANCED_SETTINGS 1 -#endif - -// Run in standby -// Indicates whether the SLCD will continue running in standby sleep mode or not -// slcd_arch_runstdby -#ifndef CONF_SLCD_RUNSTDBY -#define CONF_SLCD_RUNSTDBY 1 -#endif - -// - -#if SLCD_FRAME_FREQUENCY < 30 || SLCD_FRAME_FREQUENCY > 100 -#warning The optimal frame frequency should be in range from 30Hz up to 100Hz to avoid flickering and ghosting effect. -#endif - -#define SLCD_FC_MAX_MS (((0x1F + 1) * 8) * (1000 / SLCD_FRAME_FREQUENCY)) -#define SLCD_FC_MIN_MS (1000 / SLCD_FRAME_FREQUENCY) -#define SLCD_FC_BYPASS_MAX_MS ((0x1F + 1) * (1000 / SLCD_FRAME_FREQUENCY)) - -// Character Mapping Setting -// slcd_arch_cm_setting -#ifndef CONF_SLCD_CM_ENABLE -#define CONF_SLCD_CM_ENABLE 0 -#endif - -/** - * character lookup table - */ -#ifndef CONF_SLCD_LPENL -#define CONF_SLCD_LPENL (\ - (uint32_t)1 << 0 | \ - (uint32_t)1 << 1 | \ - (uint32_t)1 << 2 | \ - (uint32_t)1 << 3 | \ - (uint32_t)1 << 4 | \ - (uint32_t)1 << 5 | \ - (uint32_t)1 << 6 | \ - (uint32_t)1 << 7 | \ - (uint32_t)1 << 11 | \ - (uint32_t)1 << 12 | \ - (uint32_t)1 << 13 | \ - (uint32_t)1 << 14 | \ - (uint32_t)1 << 21 | \ - (uint32_t)1 << 22 | \ - (uint32_t)1 << 23 | \ - (uint32_t)1 << 24 | \ - (uint32_t)1 << 25 | \ - (uint32_t)1 << 28 | \ - (uint32_t)1 << 29 | \ - (uint32_t)1 << 30 | \ - (uint32_t)1 << 31 | 0) -#endif // CONF_SLCD_LPENL - -#ifndef CONF_SLCD_LPENH -#define CONF_SLCD_LPENH (\ - (uint32_t)1 << (32 - 32) | \ - (uint32_t)1 << (33 - 32) | \ - (uint32_t)1 << (34 - 32) | \ - (uint32_t)1 << (35 - 32) | \ - (uint32_t)1 << (42 - 32) | \ - (uint32_t)1 << (43 - 32) | 0) -#endif // CONF_SLCD_LPENH - -// <<< end of configuration section >>> - -#endif // HPL_SLCD_CONFIG_H diff --git a/watch-library/config/hpl_systick_config.h b/watch-library/config/hpl_systick_config.h deleted file mode 100644 index a7f2f362..00000000 --- a/watch-library/config/hpl_systick_config.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Auto-generated config file hpl_systick_config.h */ -#ifndef HPL_SYSTICK_CONFIG_H -#define HPL_SYSTICK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Advanced settings -// SysTick exception request -// Indicates whether the generation of SysTick exception is enabled or not -// systick_arch_tickint -#ifndef CONF_SYSTICK_TICKINT -#define CONF_SYSTICK_TICKINT 0 -#endif -// - -// <<< end of configuration section >>> - -#endif // HPL_SYSTICK_CONFIG_H diff --git a/watch-library/config/hpl_trng_config.h b/watch-library/config/hpl_trng_config.h deleted file mode 100755 index ba901498..00000000 --- a/watch-library/config/hpl_trng_config.h +++ /dev/null @@ -1,27 +0,0 @@ -/* Auto-generated config file hpl_trng_config.h */ -#ifndef HPL_TRNG_CONFIG_H -#define HPL_TRNG_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Advanced configurations - -// Run In Standby -// Indicates whether the TRNG works in standby mode -// trng_runstdby -#ifndef CONF_TRNG_RUNSTDBY -#define CONF_TRNG_RUNSTDBY 0 -#endif - -// Data Ready Event Output Enable -// Indicates whether the TRNG generates event on Data Ready -// trng_datardyeo -#ifndef CONF_TRNG_DATARDYEO -#define CONF_TRNG_DATARDYEO 0 -#endif - -// - -// <<< end of configuration section >>> - -#endif // HPL_TRNG_CONFIG_H diff --git a/watch-library/config/nv_storage_config.h b/watch-library/config/nv_storage_config.h deleted file mode 100755 index 4888d1bd..00000000 --- a/watch-library/config/nv_storage_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Auto-generated config file nv_storage_config.h */ -#ifndef NV_STORAGE_CONFIG_H -#define NV_STORAGE_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Storage start address <0x00000000-0xFFFFFFFF> -// This defines the start address of device flash for storage. -// The start address should be in device flash area. -// The start address and (start address + Item Number * Sector size) cannot beyond device flash area. -// conf_storage_memory_start -#ifndef CONF_STORAGE_MEMORY_START -#define CONF_STORAGE_MEMORY_START 0x10000 -#endif - -// Item number <0-65535> -// This defines the maximum number of elements stored in persistent storage -// conf_max_item_number -#ifndef CONF_MAX_ITEM_NUMBER -#define CONF_MAX_ITEM_NUMBER 10 -#endif - -// Sector size <0-65535> -// This defines the size of one storage sector in bytes -// conf_sector_size -#ifndef CONF_SECTOR_SIZE -#define CONF_SECTOR_SIZE 4096 -#endif - -/** - * Check If the Storage configuration out of the flash area. - */ -#ifdef FLASH_SIZE -#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > FLASH_SIZE -#error Invalidate storage configuration, make sure the configuration with \ -the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \ -are located within the device flash size. -#endif -#endif - -#ifdef IFLASH_SIZE -#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > IFLASH_SIZE -#error Invalidate storage configuration, make sure the configuration with \ -the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \ -are located within the device flash size. -#endif -#endif - -// <<< end of configuration section >>> - -#endif // NV_STORAGE_CONFIG_H diff --git a/watch-library/config/peripheral_clk_config.h b/watch-library/config/peripheral_clk_config.h deleted file mode 100644 index 523b036c..00000000 --- a/watch-library/config/peripheral_clk_config.h +++ /dev/null @@ -1,266 +0,0 @@ -/* Auto-generated config file peripheral_clk_config.h */ -#ifndef PERIPHERAL_CLK_CONFIG_H -#define PERIPHERAL_CLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// ADC Clock Source -// adc_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Select the clock source for ADC. -#ifndef CONF_GCLK_ADC_SRC -#define CONF_GCLK_ADC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_ADC_FREQUENCY - * \brief ADC's Clock frequency - */ -#ifndef CONF_GCLK_ADC_FREQUENCY -#define CONF_GCLK_ADC_FREQUENCY 4000000 -#endif - -// EIC Clock Source -// eic_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Select the clock source for EIC. -#ifndef CONF_GCLK_EIC_SRC -#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_EIC_FREQUENCY - * \brief EIC's Clock frequency - */ -#ifndef CONF_GCLK_EIC_FREQUENCY -#define CONF_GCLK_EIC_FREQUENCY 32768 -#endif - -/** - * \def CONF_CPU_FREQUENCY - * \brief CPU's Clock frequency - */ -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 4000000 -#endif - -// RTC Clock Source -// rtc_clk_selection -// RTC source -// Select the clock source for RTC. -#ifndef CONF_GCLK_RTC_SRC -#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE -#endif - -/** - * \def CONF_GCLK_RTC_FREQUENCY - * \brief RTC's Clock frequency - */ -#ifndef CONF_GCLK_RTC_FREQUENCY -#define CONF_GCLK_RTC_FREQUENCY 1024 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM1_CORE_SRC -#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM1_SLOW_SRC -#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY - * \brief SERCOM1's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY -#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 4000000 -#endif - -/** - * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY - * \brief SERCOM1's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM3_CORE_SRC -#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM3_SLOW_SRC -#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY - * \brief SERCOM3's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY -#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 4000000 -#endif - -/** - * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY - * \brief SERCOM3's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 -#endif - -// TC Clock Source -// tc_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Select the clock source for TC. -#ifndef CONF_GCLK_TC3_SRC -#define CONF_GCLK_TC3_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_TC3_FREQUENCY - * \brief TC3's Clock frequency - */ -#ifndef CONF_GCLK_TC3_FREQUENCY -#define CONF_GCLK_TC3_FREQUENCY 32768 -#endif - -// TCC Clock Source -// tcc_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Select the clock source for TCC. -#ifndef CONF_GCLK_TCC0_SRC -#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_TCC0_FREQUENCY - * \brief TCC0's Clock frequency - */ -#ifndef CONF_GCLK_TCC0_FREQUENCY -#define CONF_GCLK_TCC0_FREQUENCY 16000000 -#endif - -#include - -// SLCD Clock Source -// slcd_clk_selection -// SLCD source -// Select the clock source for SLCD. -#ifndef CONF_GCLK_SLCD_SRC -#define CONF_GCLK_SLCD_SRC SLCD_CLOCK_SOURCE -#endif - -/** - * \def CONF_GCLK_SLCD_FREQUENCY - * \brief SLCD's Clock frequency - */ -#ifndef CONF_GCLK_SLCD_FREQUENCY -#define CONF_GCLK_SLCD_FREQUENCY 32768 -#endif - -#ifndef SLCD_FRAME_FREQUENCY -#define SLCD_FRAME_FREQUENCY \ - (CONF_GCLK_SLCD_FREQUENCY \ - / (((CONF_SLCD_PRESC + 1) * 16) * (CONF_SLCD_CKDIV + 1) \ - * ((CONF_SLCD_COM_NUM == 4) ? 6 : ((CONF_SLCD_COM_NUM == 5) ? 8 : (CONF_SLCD_COM_NUM + 1))))) -#endif - -// <<< end of configuration section >>> - -#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/watch-library/driver/lis2dh.c b/watch-library/driver/lis2dh.c deleted file mode 100644 index 20702bf5..00000000 --- a/watch-library/driver/lis2dh.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2021 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "lis2dh.h" -#include "watch.h" - -bool lis2dh_begin(void) { - if (lis2dh_get_device_id() != LIS2DH_WHO_AM_I_VAL) { - return false; - } - // Enable all axes, start at lowest possible data rate - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1, LIS2DH_CTRL1_VAL_XEN | - LIS2DH_CTRL1_VAL_YEN | - LIS2DH_CTRL1_VAL_ZEN | - LIS2DH_CTRL1_VAL_ODR_1HZ); - // Set range to ±2G and enable block data update (output registers not updated until MSB and LSB have been read) - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4, LIS2DH_CTRL4_VAL_BDU | LIS2DH_RANGE_2_G); - - return true; -} - -uint8_t lis2dh_get_device_id(void) { - return watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_WHO_AM_I); -} - -bool lis2dh_have_new_data(void) { - uint8_t retval = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_STATUS); - return !!retval; // return true if any bit is set -} - -lis2dh_reading lis2dh_get_raw_reading(void) { - uint8_t buffer[6]; - uint8_t reg = LIS2DH_REG_OUT_X_L | 0x80; // set high bit for consecutive reads - lis2dh_reading retval; - - watch_i2c_send(LIS2DH_ADDRESS, ®, 1); - watch_i2c_receive(LIS2DH_ADDRESS, (uint8_t *)&buffer, 6); - - retval.x = buffer[0]; - retval.x |= ((uint16_t)buffer[1]) << 8; - retval.y = buffer[2]; - retval.y |= ((uint16_t)buffer[3]) << 8; - retval.z = buffer[4]; - retval.z |= ((uint16_t)buffer[5]) << 8; - - return retval; -} - - lis2dh_acceleration_measurement lis2dh_get_acceleration_measurement(lis2dh_reading *out_reading) { - lis2dh_reading reading = lis2dh_get_raw_reading(); - uint8_t range = lis2dh_get_range(); - if (out_reading != NULL) *out_reading = reading; - - // this bit is cribbed from Adafruit's LIS3DH driver; from their notes, the magic number below - // converts from 16-bit lsb to 10-bit and divides by 1k to convert from milli-gs. - // final value is raw_lsb => 10-bit lsb -> milli-gs -> gs - uint8_t lsb_value = 1; - if (range == LIS2DH_RANGE_2_G) lsb_value = 4; - if (range == LIS2DH_RANGE_4_G) lsb_value = 8; - if (range == LIS2DH_RANGE_8_G) lsb_value = 16; - if (range == LIS2DH_RANGE_16_G) lsb_value = 48; - - lis2dh_acceleration_measurement retval; - - retval.x = lsb_value * ((float)reading.x / 64000.0); - retval.y = lsb_value * ((float)reading.y / 64000.0); - retval.z = lsb_value * ((float)reading.z / 64000.0); - - return retval; -} - -void lis2dh_set_range(lis2dh_range_t range) { - uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4) & 0xCF; - uint8_t bits = range << 4; - - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4, val | bits); -} - -lis2dh_range_t lis2dh_get_range(void) { - uint8_t retval = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4) & 0x30; - retval >>= 4; - return (lis2dh_range_t)retval; -} - - -void lis2dh_set_data_rate(lis2dh_data_rate_t dataRate) { - uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1) & 0x0F; - uint8_t bits = dataRate << 4; - - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1, val | bits); -} - -lis2dh_data_rate_t lis2dh_get_data_rate(void) { - return watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1) >> 4; -} - -void lis2dh_configure_aoi_int1(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch) { - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL3, LIS2DH_CTRL3_VAL_I1_AOI1); - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_CFG, configuration); - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_THS, threshold); - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_DUR, duration); - uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5) & 0xF7; - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5, val | latch ? LIS2DH_CTRL5_VAL_LIR_INT1 : 0); -} - -lis2dh_interrupt_state lis2dh_get_int1_state(void) { - return (lis2dh_interrupt_state) watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_SRC); -} - -void lis2dh_configure_aoi_int2(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch) { - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL6, LIS2DH_CTRL6_VAL_I2_INT2); - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_CFG, configuration); - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_THS, threshold); - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_DUR, duration); - uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5) & 0xFD; - watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5, val | latch ? LIS2DH_CTRL5_VAL_LIR_INT2 : 0); -} - -lis2dh_interrupt_state lis2dh_get_int2_state(void) { - return (lis2dh_interrupt_state) watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_SRC); -} - diff --git a/watch-library/driver/lis2dh.h b/watch-library/driver/lis2dh.h deleted file mode 100644 index 68831519..00000000 --- a/watch-library/driver/lis2dh.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2021 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#ifndef LIS2DH_H -#define LIS2DH_H - -#include -#include - -typedef struct { - int16_t x; - int16_t y; - int16_t z; -} lis2dh_reading; - -typedef struct { - float x; - float y; - float z; -} lis2dh_acceleration_measurement; - -typedef enum { - LIS2DH_RANGE_16_G = 0b11, // +/- 16g - LIS2DH_RANGE_8_G = 0b10, // +/- 8g - LIS2DH_RANGE_4_G = 0b01, // +/- 4g - LIS2DH_RANGE_2_G = 0b00 // +/- 2g (default value) -} lis2dh_range_t; - -typedef enum { - LIS2DH_DATA_RATE_POWERDOWN = 0, - LIS2DH_DATA_RATE_1_HZ = 0b0001, - LIS2DH_DATA_RATE_10_HZ = 0b0010, - LIS2DH_DATA_RATE_25_HZ = 0b0011, - LIS2DH_DATA_RATE_50_HZ = 0b0100, - LIS2DH_DATA_RATE_100_HZ = 0b0101, - LIS2DH_DATA_RATE_200_HZ = 0b0110, - LIS2DH_DATA_RATE_400_HZ = 0b0111, - LIS2DH_DATA_RATE_LP1620HZ = 0b1000, - LIS2DH_DATA_RATE_LP5376HZ = 0b1001, - -} lis2dh_data_rate_t; - -typedef enum { - LIS2DH_INTERRUPT_CONFIGURATION_OR = 0b00000000, - LIS2DH_INTERRUPT_CONFIGURATION_AND = 0b10000000, - LIS2DH_INTERRUPT_CONFIGURATION_6D_MOVEMENT = 0b01000000, - LIS2DH_INTERRUPT_CONFIGURATION_6D_POSITION = 0b11000000, // in 6D mode, these have an alternate meaning: - LIS2DH_INTERRUPT_CONFIGURATION_Z_HIGH_ENABLE = 0b00100000, // Z up enable - LIS2DH_INTERRUPT_CONFIGURATION_Z_LOW_ENABLE = 0b00010000, // Z down enable - LIS2DH_INTERRUPT_CONFIGURATION_Y_HIGH_ENABLE = 0b00001000, // Y up enable - LIS2DH_INTERRUPT_CONFIGURATION_Y_LOW_ENABLE = 0b00000100, // Y down enable - LIS2DH_INTERRUPT_CONFIGURATION_X_HIGH_ENABLE = 0b00000010, // X up enable - LIS2DH_INTERRUPT_CONFIGURATION_X_LOW_ENABLE = 0b00000001, // X down enable -} lis2dh_interrupt_configuration; - -typedef enum { - LIS2DH_INTERRUPT_STATE_ACTIVE = 0b01000000, - LIS2DH_INTERRUPT_STATE_Z_HIGH = 0b00100000, // Z up - LIS2DH_INTERRUPT_STATE_Z_LOW = 0b00010000, // Z down - LIS2DH_INTERRUPT_STATE_Y_HIGH = 0b00001000, // Y up - LIS2DH_INTERRUPT_STATE_Y_LOW = 0b00000100, // Y down - LIS2DH_INTERRUPT_STATE_X_HIGH = 0b00000010, // X up - LIS2DH_INTERRUPT_STATE_X_LOW = 0b00000001, // X down -} lis2dh_interrupt_state; - -bool lis2dh_begin(void); - -uint8_t lis2dh_get_device_id(void); - -bool lis2dh_have_new_data(void); - -lis2dh_reading lis2dh_get_raw_reading(void); - -lis2dh_acceleration_measurement lis2dh_get_acceleration_measurement(lis2dh_reading *out_reading); - -void lis2dh_set_range(lis2dh_range_t range); - -lis2dh_range_t lis2dh_get_range(void); - -void lis2dh_set_data_rate(lis2dh_data_rate_t dataRate); - -lis2dh_data_rate_t lis2dh_get_data_rate(void); - -void lis2dh_configure_aoi_int1(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch); - -lis2dh_interrupt_state lis2dh_get_int1_state(void); - -void lis2dh_configure_aoi_int2(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch); - -lis2dh_interrupt_state lis2dh_get_int2_state(void); - -// Assumes SA0 is high; if low, its 0x18 -#define LIS2DH_ADDRESS (0x19) - -#define LIS2DH_REG_STATUS_AUX 0x07 ///< Auxiliary status register -#define LIS2DH_REG_STATUS_AUX_TDA (1 << 2) ///< Temperature data available -#define LIS2DH_REG_STATUS_AUX_TOR (1 << 6) ///< Temperature data overrun - -#define LIS2DH_REG_OUT_TEMP_L 0x0C ///< Temperature data low bit -#define LIS2DH_REG_OUT_TEMP_H 0x0D ///< Temperature data high bit - -#define LIS2DH_REG_INT_COUNTER 0x0E - -#define LIS2DH_REG_WHO_AM_I 0x0F ///< Device identification, will read 0x33 -#define LIS2DH_WHO_AM_I_VAL 0x33 ///< Expected value of the WHO_AM_I register - -#define LIS2DH_REG_TEMP_CFG 0x1F ///< Temperature configuration; 0 to disable, 0xC0 to enable. -#define LIS2DH_TEMP_CFG_VAL_ENABLE 0xC0 ///< Value for LIS2DH_REG_TEMP_CFG that enables temperature sensing. -#define LIS2DH_TEMP_CFG_VAL_DISABLE 0x00 ///< Value for LIS2DH_REG_TEMP_CFG that disables temperature sensing. - -#define LIS2DH_REG_CTRL1 0x20 ///< CTRL_REG1 in the data sheet. -#define LIS2DH_CTRL1_VAL_XEN 0b00000001 ///< Enable X-axis -#define LIS2DH_CTRL1_VAL_YEN 0b00000010 ///< Enable Y-axis -#define LIS2DH_CTRL1_VAL_ZEN 0b00000100 ///< Enable Z-axis -#define LIS2DH_CTRL1_VAL_LPEN 0b00001000 ///< Enable low power mode -#define LIS2DH_CTRL1_VAL_ODR_POWERDOWN 0 ///< Power down -#define LIS2DH_CTRL1_VAL_ODR_1HZ (LIS2DH_DATA_RATE_1_HZ << 4) -#define LIS2DH_CTRL1_VAL_ODR_10HZ (LIS2DH_DATA_RATE_10_HZ << 4) -#define LIS2DH_CTRL1_VAL_ODR_25HZ (LIS2DH_DATA_RATE_25_HZ << 4) -#define LIS2DH_CTRL1_VAL_ODR_50HZ (LIS2DH_DATA_RATE_50_HZ << 4) -#define LIS2DH_CTRL1_VAL_ODR_100HZ (LIS2DH_DATA_RATE_100_HZ << 4) -#define LIS2DH_CTRL1_VAL_ODR_200HZ (LIS2DH_DATA_RATE_200_HZ << 4) -#define LIS2DH_CTRL1_VAL_ODR_400HZ (LIS2DH_DATA_RATE_400_HZ << 4) -#define LIS2DH_CTRL1_VAL_ODR_LP1620HZ (LIS2DH_DATA_RATE_LP1620HZ << 4) -#define LIS2DH_CTRL1_VAL_ODR_LP5376HZ (LIS2DH_DATA_RATE_LP5376HZ << 4) - -#define LIS2DH_REG_CTRL2 0x21 - -#define LIS2DH_REG_CTRL3 0x22 -#define LIS2DH_CTRL3_VAL_I1_CLICK 0b10000000 -#define LIS2DH_CTRL3_VAL_I1_AOI1 0b01000000 -#define LIS2DH_CTRL3_VAL_I1_AOI2 0b00100000 -#define LIS2DH_CTRL3_VAL_I1_DRDY1 0b00010000 -#define LIS2DH_CTRL3_VAL_I1_DRDY2 0b00001000 -#define LIS2DH_CTRL3_VAL_I1_WTM 0b00000100 -#define LIS2DH_CTRL3_VAL_I1_OVERRUN 0b00000010 - -#define LIS2DH_REG_CTRL4 0x23 -#define LIS2DH_CTRL4_VAL_BDU 0b10000000 -#define LIS2DH_CTRL4_VAL_BLE 0b01000000 -#define LIS2DH_CTRL4_VAL_RANGE_2G (LIS2DH_RANGE_2_G << 4) -#define LIS2DH_CTRL4_VAL_RANGE_4G (LIS2DH_RANGE_4_G << 4) -#define LIS2DH_CTRL4_VAL_RANGE_8G (LIS2DH_RANGE_8_G << 4) -#define LIS2DH_CTRL4_VAL_RANGE_16G (LIS2DH_RANGE_16_G << 4) -#define LIS2DH_CTRL4_VAL_HR 0b00001000 -#define LIS2DH_CTRL4_VAL_ST0 0b00000000 -#define LIS2DH_CTRL4_VAL_ST1 0b00000000 - -#define LIS2DH_REG_CTRL5 0x24 -#define LIS2DH_CTRL5_VAL_BOOT 0b10000000 -#define LIS2DH_CTRL5_VAL_FIFO_EN 0b01000000 -#define LIS2DH_CTRL5_VAL_LIR_INT1 0b00001000 -#define LIS2DH_CTRL5_VAL_D4D_INT1 0b00000100 -#define LIS2DH_CTRL5_VAL_LIR_INT2 0b00000010 -#define LIS2DH_CTRL5_VAL_D4D_INT2 0b00000001 - -#define LIS2DH_REG_CTRL6 0x25 -#define LIS2DH_CTRL6_VAL_I2_CLICK 0b10000000 -#define LIS2DH_CTRL6_VAL_I2_INT1 0b01000000 -#define LIS2DH_CTRL6_VAL_I2_INT2 0b00100000 -#define LIS2DH_CTRL6_VAL_BOOT_I2 0b00010000 -#define LIS2DH_CTRL6_VAL_P2_ACT 0b00001000 -#define LIS2DH_CTRL6_VAL_H_L_ACTIVE 0b00000000 - -#define LIS2DH_REG_REFERENCE 0x26 - -#define LIS2DH_REG_STATUS 0x27 -#define LIS2DH_STATUS_VAL_ZYXOR 0b10000000 -#define LIS2DH_STATUS_VAL_ZOR 0b01000000 -#define LIS2DH_STATUS_VAL_YOR 0b00100000 -#define LIS2DH_STATUS_VAL_XOR 0b00010000 -#define LIS2DH_STATUS_VAL_ZYXDA 0b00001000 -#define LIS2DH_STATUS_VAL_ZDA 0b00000100 -#define LIS2DH_STATUS_VAL_YDA 0b00000010 -#define LIS2DH_STATUS_VAL_XDA 0b00000001 - -#define LIS2DH_REG_OUT_X_L 0x28 -#define LIS2DH_REG_OUT_X_H 0x29 -#define LIS2DH_REG_OUT_Y_L 0x2A -#define LIS2DH_REG_OUT_Y_H 0x2B -#define LIS2DH_REG_OUT_Z_L 0x2C -#define LIS2DH_REG_OUT_Z_H 0x2D - -#define LIS2DH_REG_FIFO_CTRL 0x2E -#define LIS2DH_REG_FIFO_SRC 0x2F -#define LIS2DH_REG_INT1_CFG 0x30 -#define LIS2DH_REG_INT1_SRC 0x31 -#define LIS2DH_REG_INT1_THS 0x32 -#define LIS2DH_REG_INT1_DUR 0x33 -#define LIS2DH_REG_INT2_CFG 0x34 -#define LIS2DH_REG_INT2_SRC 0x35 -#define LIS2DH_REG_INT2_THS 0x36 -#define LIS2DH_REG_INT2_DUR 0x37 -#define LIS2DH_REG_CLICK_CFG 0x38 -#define LIS2DH_REG_CLICK_SRC 0x39 -#define LIS2DH_REG_CLICK_THS 0x3A -#define LIS2DH_REG_TIME_LIMIT 0x3B -#define LIS2DH_REG_TIME_LATENCY 0x3C -#define LIS2DH_REG_TIME_WINDOW 0x3D - -#endif // LIS2DH_H diff --git a/watch-library/driver/lis2dw.c b/watch-library/driver/lis2dw.c deleted file mode 100644 index 6e1ac56d..00000000 --- a/watch-library/driver/lis2dw.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2021 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "lis2dw.h" -#include "watch.h" - -bool lis2dw_begin(void) { - if (lis2dw_get_device_id() != LIS2DW_WHO_AM_I_VAL) { - return false; - } - watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL2, LIS2DW_CTRL2_VAL_BOOT); - watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL2, LIS2DW_CTRL2_VAL_SOFT_RESET); - // Start at lowest possible data rate and lowest possible power mode - watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, LIS2DW_CTRL1_VAL_ODR_LOWEST | LIS2DW_CTRL1_VAL_MODE_LOW_POWER | LIS2DW_CTRL1_VAL_LPMODE_1); - // Enable block data update (output registers not updated until MSB and LSB have been read) and address autoincrement - watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL2, LIS2DW_CTRL2_VAL_BDU | LIS2DW_CTRL2_VAL_IF_ADD_INC); - // Set range to ±2G - watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6, LIS2DW_CTRL6_VAL_RANGE_2G); - - return true; -} - -uint8_t lis2dw_get_device_id(void) { - return watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_WHO_AM_I); -} - -bool lis2dw_have_new_data(void) { - uint8_t retval = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_STATUS); - return retval & LIS2DW_STATUS_VAL_DRDY; -} - -lis2dw_reading lis2dw_get_raw_reading(void) { - uint8_t buffer[6]; - uint8_t reg = LIS2DW_REG_OUT_X_L | 0x80; // set high bit for consecutive reads - lis2dw_reading retval; - - watch_i2c_send(LIS2DW_ADDRESS, ®, 1); - watch_i2c_receive(LIS2DW_ADDRESS, (uint8_t *)&buffer, 6); - - retval.x = buffer[0]; - retval.x |= ((uint16_t)buffer[1]) << 8; - retval.y = buffer[2]; - retval.y |= ((uint16_t)buffer[3]) << 8; - retval.z = buffer[4]; - retval.z |= ((uint16_t)buffer[5]) << 8; - - return retval; -} - - lis2dw_acceleration_measurement lis2dw_get_acceleration_measurement(lis2dw_reading *out_reading) { - lis2dw_reading reading = lis2dw_get_raw_reading(); - uint8_t range = lis2dw_get_range(); - if (out_reading != NULL) *out_reading = reading; - - // this bit is cribbed from Adafruit's LIS3DH driver; from their notes, the magic number below - // converts from 16-bit lsb to 10-bit and divides by 1k to convert from milli-gs. - // final value is raw_lsb => 10-bit lsb -> milli-gs -> gs - uint8_t lsb_value = 1; - if (range == LIS2DW_RANGE_2_G) lsb_value = 4; - if (range == LIS2DW_RANGE_4_G) lsb_value = 8; - if (range == LIS2DW_RANGE_8_G) lsb_value = 16; - if (range == LIS2DW_RANGE_16_G) lsb_value = 48; - - lis2dw_acceleration_measurement retval; - - retval.x = lsb_value * ((float)reading.x / 64000.0); - retval.y = lsb_value * ((float)reading.y / 64000.0); - retval.z = lsb_value * ((float)reading.z / 64000.0); - - return retval; -} - -void lis2dw_set_range(lis2dw_range_t range) { - uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6) & ~(LIS2DW_RANGE_16_G << 4); - uint8_t bits = range << 4; - - watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6, val | bits); -} - -lis2dw_range_t lis2dw_get_range(void) { - uint8_t retval = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6) & (LIS2DW_RANGE_16_G << 4); - retval >>= 4; - return (lis2dw_range_t)retval; -} - - -void lis2dw_set_data_rate(lis2dw_data_rate_t dataRate) { - uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & ~(0b1111 << 4); - uint8_t bits = dataRate << 4; - - watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, val | bits); -} - -lis2dw_data_rate_t lis2dw_get_data_rate(void) { - return watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) >> 4; -} - -void lis2dw_set_low_power_mode(lis2dw_low_power_mode_t mode) { - uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & ~(0b11); - uint8_t bits = mode & 0b11; - - watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, val | bits); -} - -lis2dw_low_power_mode_t lis2dw_get_low_power_mode(void) { - return watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & 0b11; -} - -void lis2dw_set_low_noise_mode(bool on) { - uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & ~(LIS2DW_CTRL6_VAL_LOW_NOISE); - uint8_t bits = on ? LIS2DW_CTRL6_VAL_LOW_NOISE : 0; - - watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, val | bits); -} - -bool lis2dw_get_low_noise_mode(void) { - return (watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & LIS2DW_CTRL6_VAL_LOW_NOISE) != 0; -} diff --git a/watch-library/driver/lis2dw.h b/watch-library/driver/lis2dw.h deleted file mode 100644 index 22b4484f..00000000 --- a/watch-library/driver/lis2dw.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2021 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#ifndef LIS2DW_H -#define LIS2DW_H - -#include -#include - -typedef struct { - int16_t x; - int16_t y; - int16_t z; -} lis2dw_reading; - -typedef struct { - float x; - float y; - float z; -} lis2dw_acceleration_measurement; - -typedef enum { - LIS2DW_DATA_RATE_POWERDOWN = 0, - LIS2DW_DATA_RATE_LOWEST = 0b0001, // 12.5 Hz in high performance mode, 1.6 Hz in low power - LIS2DW_DATA_RATE_12_5_HZ = 0b0010, - LIS2DW_DATA_RATE_25_HZ = 0b0011, - LIS2DW_DATA_RATE_50_HZ = 0b0100, - LIS2DW_DATA_RATE_100_HZ = 0b0101, - LIS2DW_DATA_RATE_200_HZ = 0b0110, - LIS2DW_DATA_RATE_HP_400_HZ = 0b0111, - LIS2DW_DATA_RATE_HP_800_HZ = 0b1000, - LIS2DW_DATA_RATE_HP_1600_HZ = 0b1001, - -} lis2dw_data_rate_t; - -typedef enum { - LIS2DW_MODE_LOW_POWER = 0b00, - LIS2DW_MODE_HIGH_PERFORMANCE = 0b01, - LIS2DW_MODE_ON_DEMAND = 0b10, -} lis2dw_mode_t; - -typedef enum { - LIS2DW_LP_MODE_1 = 0b00, // 12-bit - LIS2DW_LP_MODE_2 = 0b01, // 14-bit - LIS2DW_LP_MODE_3 = 0b10, // 14-bit - LIS2DW_LP_MODE_4 = 0b11, // 14-bit -} lis2dw_low_power_mode_t; - -typedef enum { - LIS2DW_BANDWIDTH_FILTER_DIV2 = 0b00, - LIS2DW_BANDWIDTH_FILTER_DIV4 = 0b01, - LIS2DW_BANDWIDTH_FILTER_DIV10 = 0b10, - LIS2DW_BANDWIDTH_FILTER_DIV20 = 0b11, -} lis2dw_bandwidth_filtering_mode_t; - -typedef enum { - LIS2DW_RANGE_16_G = 0b11, // +/- 16g - LIS2DW_RANGE_8_G = 0b10, // +/- 8g - LIS2DW_RANGE_4_G = 0b01, // +/- 4g - LIS2DW_RANGE_2_G = 0b00 // +/- 2g (default value) -} lis2dw_range_t; - -// Assumes SA0 is high; if low, its 0x18 -#define LIS2DW_ADDRESS (0x19) - -#define LIS2DW_REG_OUT_TEMP_L 0x0D ///< Temperature data low bit -#define LIS2DW_REG_OUT_TEMP_H 0x0E ///< Temperature data high bit - -#define LIS2DW_REG_WHO_AM_I 0x0F ///< Device identification, will read 0x44 -#define LIS2DW_WHO_AM_I_VAL 0x44 ///< Expected value of the WHO_AM_I register - -#define LIS2DW_REG_CTRL1 0x20 ///< CTRL_REG1 in the data sheet. -#define LIS2DW_CTRL1_VAL_ODR_POWERDOWN 0 -#define LIS2DW_CTRL1_VAL_ODR_LOWEST (LIS2DW_DATA_RATE_LOWEST << 4) -#define LIS2DW_CTRL1_VAL_ODR_12_5HZ (LIS2DW_DATA_RATE_12_5_HZ << 4) -#define LIS2DW_CTRL1_VAL_ODR_25HZ (LIS2DW_DATA_RATE_25_HZ << 4) -#define LIS2DW_CTRL1_VAL_ODR_50HZ (LIS2DW_DATA_RATE_50_HZ << 4) -#define LIS2DW_CTRL1_VAL_ODR_100HZ (LIS2DW_DATA_RATE_100_HZ << 4) -#define LIS2DW_CTRL1_VAL_ODR_200HZ (LIS2DW_DATA_RATE_200_HZ << 4) -#define LIS2DW_CTRL1_VAL_ODR_HP_400_HZ (LIS2DW_DATA_RATE_HP_400_HZ << 4) -#define LIS2DW_CTRL1_VAL_ODR_HP_800_HZ (LIS2DW_DATA_RATE_HP_800_HZ << 4) -#define LIS2DW_CTRL1_VAL_ODR_HP_1600_HZ (LIS2DW_DATA_RATE_HP_1600_HZ << 4) -#define LIS2DW_CTRL1_VAL_MODE_LOW_POWER (LIS2DW_MODE_LOW_POWER << 2) -#define LIS2DW_CTRL1_VAL_MODE_HIGH_PERFORMANCE (LIS2DW_MODE_HIGH_PERFORMANCE << 2) -#define LIS2DW_CTRL1_VAL_MODE_ON_DEMAND (LIS2DW_MODE_ON_DEMAND << 2) -#define LIS2DW_CTRL1_VAL_LPMODE_1 (LIS2DW_LP_MODE_1 << 0) -#define LIS2DW_CTRL1_VAL_LPMODE_2 (LIS2DW_LP_MODE_2 << 0) -#define LIS2DW_CTRL1_VAL_LPMODE_3 (LIS2DW_LP_MODE_3 << 0) -#define LIS2DW_CTRL1_VAL_LPMODE_4 (LIS2DW_LP_MODE_4 << 0) - -#define LIS2DW_REG_CTRL2 0x21 -#define LIS2DW_CTRL2_VAL_BOOT 0b10000000 -#define LIS2DW_CTRL2_VAL_SOFT_RESET 0b01000000 -#define LIS2DW_CTRL2_VAL_CS_PU_DISC 0b00010000 -#define LIS2DW_CTRL2_VAL_BDU 0b00001000 -#define LIS2DW_CTRL2_VAL_IF_ADD_INC 0b00000100 - -#define LIS2DW_REG_CTRL3 0x22 -#define LIS2DW_CTRL4_VAL_SELF_TEST_POS 0b10000000 -#define LIS2DW_CTRL4_VAL_SELF_TEST_NEG 0b01000000 -#define LIS2DW_CTRL3_VAL_PP_OD 0b00100000 -#define LIS2DW_CTRL3_VAL_LIR 0b00010000 -#define LIS2DW_CTRL3_VAL_H_L_ACTIVE 0b00001000 -#define LIS2DW_CTRL3_VAL_SLP_MODE_SEL 0b00000010 -#define LIS2DW_CTRL3_VAL_SLP_MODE_1 0b00000001 - -#define LIS2DW_REG_CTRL4 0x23 -#define LIS2DW_CTRL4_INT1_6D 0b10000000 -#define LIS2DW_CTRL4_INT1_SINGLE_TAP 0b01000000 -#define LIS2DW_CTRL4_INT1_WU 0b00100000 -#define LIS2DW_CTRL4_INT1_FF 0b00010000 -#define LIS2DW_CTRL4_INT1_TAP 0b00001000 -#define LIS2DW_CTRL4_INT1_DIFF5 0b00000100 -#define LIS2DW_CTRL4_INT1_FTH 0b00000010 -#define LIS2DW_CTRL4_INT1_DRDY 0b00000001 - -#define LIS2DW_REG_CTRL5 0x24 -#define LIS2DW_CTRL5_INT2_SLEEP_STATE 0b10000000 -#define LIS2DW_CTRL5_INT2_SLEEP_CHG 0b01000000 -#define LIS2DW_CTRL5_INT2_BOOT 0b00100000 -#define LIS2DW_CTRL5_INT2_DRDY_T 0b00010000 -#define LIS2DW_CTRL5_INT2_OVR 0b00001000 -#define LIS2DW_CTRL5_INT2_DIFF5 0b00000100 -#define LIS2DW_CTRL5_INT2_FTH 0b00000010 -#define LIS2DW_CTRL5_INT2_DRDY 0b00000001 - -#define LIS2DW_REG_CTRL6 0x25 -#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV2 (LIS2DW_BANDWIDTH_FILTER_DIV2 << 6) -#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV4 (LIS2DW_BANDWIDTH_FILTER_DIV4 << 6) -#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV10 (LIS2DW_BANDWIDTH_FILTER_DIV10 << 6) -#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV20 (LIS2DW_BANDWIDTH_FILTER_DIV20 << 6) -#define LIS2DW_CTRL6_VAL_RANGE_2G (LIS2DW_RANGE_2_G << 4) -#define LIS2DW_CTRL6_VAL_RANGE_4G (LIS2DW_RANGE_4_G << 4) -#define LIS2DW_CTRL6_VAL_RANGE_8G (LIS2DW_RANGE_8_G << 4) -#define LIS2DW_CTRL6_VAL_RANGE_16G (LIS2DW_RANGE_16_G << 4) -#define LIS2DW_CTRL6_VAL_FDS 0b00001000 -#define LIS2DW_CTRL6_VAL_LOW_NOISE 0b00000100 - -#define LIS2DW_REG_OUT_TEMP 0x26 - -#define LIS2DW_REG_STATUS 0x27 -#define LIS2DW_STATUS_VAL_FIFO_THS 0b10000000 -#define LIS2DW_STATUS_VAL_WU_IA 0b01000000 -#define LIS2DW_STATUS_VAL_SLEEP_STATE 0b00100000 -#define LIS2DW_STATUS_VAL_DOUBLE_TAP 0b00010000 -#define LIS2DW_STATUS_VAL_SINGLE_TAP 0b00001000 -#define LIS2DW_STATUS_VAL_6D_IA 0b00000100 -#define LIS2DW_STATUS_VAL_FF_IA 0b00000010 -#define LIS2DW_STATUS_VAL_DRDY 0b00000001 - -#define LIS2DW_REG_OUT_X_L 0x28 -#define LIS2DW_REG_OUT_X_H 0x29 -#define LIS2DW_REG_OUT_Y_L 0x2A -#define LIS2DW_REG_OUT_Y_H 0x2B -#define LIS2DW_REG_OUT_Z_L 0x2C -#define LIS2DW_REG_OUT_Z_H 0x2D - -#define LIS2DW_REG_FIFO_CTRL 0x2E -#define LIS2DW_REG_FIFO_SRC 0x2F - -#define LIS2DW_REG_TAP_THS_X 0x30 -#define LIS2DW_REG_TAP_THS_Y 0x31 -#define LIS2DW_REG_TAP_THS_Z 0x32 -#define LIS2DW_REG_INT1_DUR 0x33 -#define LIS2DW_REG_WAKE_UP_THS 0x34 -#define LIS2DW_REG_WAKE_UP_DUR 0x35 -#define LIS2DW_REG_FREE_FALL 0x36 -#define LIS2DW_REG_STATUS_DUP 0x37 - -#define LIS2DW_REG_WAKE_UP_SRC 0x38 -#define LIS2DW_WAKE_UP_SRC_VAL_FF_IA 0b00100000 -#define LIS2DW_WAKE_UP_SRC_VAL_SLEEP_STATE_IA 0b00010000 -#define LIS2DW_WAKE_UP_SRC_VAL_WU_IA 0b00001000 -#define LIS2DW_WAKE_UP_SRC_VAL_X_WU 0b00000100 -#define LIS2DW_WAKE_UP_SRC_VAL_Y_WU 0b00000010 -#define LIS2DW_WAKE_UP_SRC_VAL_Z_WU 0b00000001 - -#define LIS2DW_REG_TAP_SRC 0x39 -#define LIS2DW_TAP_SRC_VAL_TAP_IA 0b01000000 -#define LIS2DW_TAP_SRC_VAL_SINGLE_TAP 0b00100000 -#define LIS2DW_TAP_SRC_VAL_DOUBLE_TAP 0b00010000 -#define LIS2DW_TAP_SRC_VAL_TAP_SIGN 0b00001000 -#define LIS2DW_TAP_SRC_VAL_X_TAP 0b00000100 -#define LIS2DW_TAP_SRC_VAL_Y_TAP 0b00000010 -#define LIS2DW_TAP_SRC_VAL_Z_TAP 0b00000001 - -#define LIS2DW_REG_SIXD_SRC 0x3A -#define LIS2DW_WAKE_UP_SRC_VAL_6D_IA 0b01000000 -#define LIS2DW_WAKE_UP_SRC_VAL_ZH 0b00100000 -#define LIS2DW_WAKE_UP_SRC_VAL_ZL 0b00010000 -#define LIS2DW_WAKE_UP_SRC_VAL_YH 0b00001000 -#define LIS2DW_WAKE_UP_SRC_VAL_YL 0b00000100 -#define LIS2DW_WAKE_UP_SRC_VAL_XH 0b00000010 -#define LIS2DW_WAKE_UP_SRC_VAL_XL 0b00000001 - -#define LIS2DW_REG_ALL_INT_SRC 0x3B -#define LIS2DW_REG_ALL_INT_SRC_SLEEP_CHANGE_IA 0b00100000 -#define LIS2DW_REG_ALL_INT_SRC_6D_IA 0b00010000 -#define LIS2DW_REG_ALL_INT_SRC_DOUBLE_TAP 0b00001000 -#define LIS2DW_REG_ALL_INT_SRC_SINGLE_TAP 0b00000100 -#define LIS2DW_REG_ALL_INT_SRC_WU_IA 0b00000010 -#define LIS2DW_REG_ALL_INT_SRC_FF_IA 0b00000001 - -#define LIS2DW_REG_X_OFS_USR 0x3C -#define LIS2DW_REG_Y_OFS_USR 0x3D -#define LIS2DW_REG_Z_OFS_USR 0x3E - -#define LIS2DW_REG_CTRL7 0x3F -#define LIS2DW_CTRL7_VAL_DRDY_PULSED 0b10000000 -#define LIS2DW_CTRL7_VAL_INT2_ON_INT1 0b01000000 -#define LIS2DW_CTRL7_VAL_INTERRUPTS_ENABLE 0b00100000 -#define LIS2DW_CTRL7_VAL_USR_OFF_ON_OUT 0b00010000 -#define LIS2DW_CTRL7_VAL_USR_OFF_ON_WU 0b00001000 -#define LIS2DW_CTRL7_VAL_USR_OFF_W 0b00000100 -#define LIS2DW_CTRL7_VAL_HP_REF_MODE 0b00000010 -#define LIS2DW_CTRL7_VAL_LPASS_ON6D 0b00000001 - -bool lis2dw_begin(void); - -uint8_t lis2dw_get_device_id(void); - -bool lis2dw_have_new_data(void); - -lis2dw_reading lis2dw_get_raw_reading(void); - -lis2dw_acceleration_measurement lis2dw_get_acceleration_measurement(lis2dw_reading *out_reading); - -void lis2dw_set_range(lis2dw_range_t range); - -lis2dw_range_t lis2dw_get_range(void); - -void lis2dw_set_data_rate(lis2dw_data_rate_t dataRate); - -lis2dw_data_rate_t lis2dw_get_data_rate(void); - -void lis2dw_set_low_power_mode(lis2dw_low_power_mode_t mode); - -lis2dw_low_power_mode_t lis2dw_get_low_power_mode(void); - -void lis2dw_set_low_noise_mode(bool on); - -bool lis2dw_get_low_noise_mode(void); - -#endif // LIS2DW_H diff --git a/watch-library/hal/documentation/ext_irq.rst b/watch-library/hal/documentation/ext_irq.rst deleted file mode 100644 index 7dcdc7c5..00000000 --- a/watch-library/hal/documentation/ext_irq.rst +++ /dev/null @@ -1,39 +0,0 @@ -============== -EXT IRQ driver -============== - -The External Interrupt driver allows external pins to be -configured as interrupt lines. Each interrupt line can be -individually masked and can generate an interrupt on rising, -falling or both edges, or on high or low levels. Some of -external pin can also be configured to wake up the device -from sleep modes where all clocks have been disabled. -External pins can also generate an event. - -Features --------- -* Initialization and de-initialization -* Enabling and disabling -* Detect external pins interrupt - -Applications ------------- -* Generate an interrupt on rising, falling or both edges, - or on high or low levels. - -Dependencies ------------- -* GPIO hardware - -Concurrency ------------ -N/A - -Limitations ------------ -N/A - -Knows issues and workarounds ----------------------------- -N/A - diff --git a/watch-library/hal/documentation/flash.rst b/watch-library/hal/documentation/flash.rst deleted file mode 100755 index fcc86e63..00000000 --- a/watch-library/hal/documentation/flash.rst +++ /dev/null @@ -1,52 +0,0 @@ -The Flash Driver -================ - -Flash is a re-programmable memory that retains program and data -storage even with power off. - -User can write or read several bytes from any valid address in a flash. - -As to the erase/lock/unlock command, the input parameter of address should -be a bytes address aligned with the page start, otherwise, the command will fail -to be executed. At the meantime, the number of pages that can be locked or unlocked -at once depends on region size of the flash. User can get the real number -from the function return value which could be different for the different devices. - -Features --------- - -* Initialization/de-initialization -* Writing/Reading bytes -* Locking/Unlocking/Erasing pages -* Notifications about errors or being ready for a new command - -Applications ------------- - -* Mini disk which can retain program and data storage -* Boot loader -* Non volatile storage - -Dependencies ------------- - -The peripheral which controls a re-programmable flash memory. - -Concurrency ------------ - -N/A - -Limitations ------------ - -User should pay attention to set a proper stack size in their application, -since the driver manages a temporary buffer in stack to cache unchanged data -when calling flash write and erase function. -Due to flash memory architecture of SAMD21/D20/L21/L22/C20/C21/D09/D10/D11/R21, -write operation erazes row content before each write. - -Known issues and workarounds ----------------------------- - -N/A diff --git a/watch-library/hal/documentation/i2c_master_sync.rst b/watch-library/hal/documentation/i2c_master_sync.rst deleted file mode 100644 index 77b4f6e9..00000000 --- a/watch-library/hal/documentation/i2c_master_sync.rst +++ /dev/null @@ -1,87 +0,0 @@ -============================= -I2C Master synchronous driver -============================= - -I2C (Inter-Integrated Circuit) is a two wire serial interface usually used -for on-board low-speed bi-directional communication between controllers and -peripherals. The master device is responsible for initiating and controlling -all transfers on the I2C bus. Only one master device can be active on the I2C -bus at the time, but the master role can be transferred between devices on the -same I2C bus. I2C uses only two bidirectional open-drain lines, usually -designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up -resistors. - -The stop condition is automatically controlled by the driver if the I/O write and -read functions are used, but can be manually controlled by using the -i2c_m_sync_transfer function. - -Often a master accesses different information in the slave by accessing -different registers in the slave. This is done by first sending a message to -the target slave containing the register address, followed by a repeated start -condition (no stop condition between) ending with transferring register data. -This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read -function, but limited to 8-bit register addresses. - -I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in -Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to -stick within the SCL clock frequency range supported by the selected mode. -The requested SCL clock frequency is not validated by the -i2c_m_sync_set_baudrate function against the selected I2C mode. - -Features --------- - - * I2C Master support - * Initialization and de-initialization - * Enabling and disabling - * Run-time bus speed configuration - * Write and read I2C messages - * Slave register access functions (limited to 8-bit address) - * Manual or automatic stop condition generation - * 10- and 7- bit addressing - * I2C Modes supported - +----------------------+-------------------+ - |* Standard/Fast mode | (SCL: 1 - 400kHz) | - +----------------------+-------------------+ - |* Fastmode+ | (SCL: 1 - 1000kHz)| - +----------------------+-------------------+ - |* Highspeed mode | (SCL: 1 - 3400kHz)| - +----------------------+-------------------+ - -Applications ------------- - -* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals -* Data communication between micro controllers -* Controlling displays - -Dependencies ------------- - -* I2C Master capable hardware - -Concurrency ------------ - -N/A - -Limitations ------------ - -General -^^^^^^^ - - * System Managmenet Bus (SMBus) not supported. - * Power Management Bus (PMBus) not supported. - -Clock considerations -^^^^^^^^^^^^^^^^^^^^ - -The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected. - -Known issues and workarounds ----------------------------- - -N/A - - diff --git a/watch-library/hal/documentation/rand_sync.rst b/watch-library/hal/documentation/rand_sync.rst deleted file mode 100755 index 19ec1d36..00000000 --- a/watch-library/hal/documentation/rand_sync.rst +++ /dev/null @@ -1,43 +0,0 @@ -========================================== -Random Number Generator Synchronous driver -========================================== - -Random Number Generator (RAND) generates a sequence of numbers that can not -be reasonably predicted better than by a random chance. - -In some implementation cases, seed is required for the Random Number Generator -to generate random numbers. rand_sync_set_seed is used to update the seed. -If it's actually not required by the generator implementation, the function just -returns ERR_UNSUPPORTED_OP. - -Features --------- - -* Initialization and de-initialization -* Enabling and Disabling -* Setting seed -* 8-bit and 32-bit random data/data array generation - -Applications ------------- - -* Generate random keys for data encryption - -Dependencies ------------- - -* Random number generation hardware/software - -Concurrency ------------ -N/A - -Limitations ------------ - -N/A - -Known issues and workarounds ----------------------------- -N/A - diff --git a/watch-library/hal/documentation/slcd_sync.rst b/watch-library/hal/documentation/slcd_sync.rst deleted file mode 100644 index e18aa9dd..00000000 --- a/watch-library/hal/documentation/slcd_sync.rst +++ /dev/null @@ -1,82 +0,0 @@ - -SLCD Synchronous driver -======================= - -An LCD display is made of several segments (pixels or complete symbols) which -can be block light or let light through. In each segment is one electrode -connected to the common terminal (COM pin) and one is connected to the segment -terminal (SEG pin). When a voltage above a certain threshold level is applied -across the liquid crystal, it will change orientation and either let light -through or block it. - -The driver supports segment on/off/blink, animation and character display. - -Each segment has a unique int32 segment id which is used by the driver. The id is -combined by common number(COM) and segment number(SEG), the COM and SEG start from 0. -The unique segment id is calculated by this formula: (COM << 16) | SEG -For example a 8(coms)*8(segments)SLCD, the unique segment id for segment should be - - +-----+-----+---------+ - | COM | SEG | ID | - +-----+-----+---------+ - | 0 | 0 | 0x00000 | - +-----+-----+---------+ - | 1 | 0 | 0x10000 | - +-----+-----+---------+ - | 7 | 7 | 0x70007 | - +-----+-----+---------+ - -Segment ID can be calculated using the pre-defined macro SLCD_SEGID(com, seg). - -For character display, the "segment character mapping table" and "character mapping table" -should be setup in configuration. The driver have no API to setup/change those -mapping setting. -There are two pre-defined "segment character mapping table" in this driver, 7 segments -and 14 segments. The 7 segment character mapping can display 0-9 and a-f, the 14 -segments character mapping can display 0-9, A-Z and some special ASCII, for more -details please refer to hpl_slcd_cm_7_seg_mapping.h and hpl_slcd_cm_14_seg_mapping.h. -Application can also adjust this mapping table in the configuration header file, -to add more character mapping or remove some unused character. - -The "character mapping" is used to setup each character in SLCD display screen. -The driver supports multiple character mapping, the max number varies on different -MCU/MPU. For example if an LCD display screen has five "7-segments character" and -eight "14-segments character", and the MCU support max 44 characters setting, then -the 13 character should be setup in configuration. Application can select any -position from those 44 characters setting to save those 13 character. -The index of character setting will be used in the driver API. For example: -five "7-segments character" setting to 0 to 4 and eight "14-segments character" setting -to 10 to 17. Then the application can use index from 0 to 4 to display the -"7-segments character" and use index from 10 to 14 to display "14-segments character". - -Features --------- - -* Initialization and de-initialization -* Enabling and Disabling -* Switching segment on/off -* Set segment blink -* Autonomous animation -* Character display - -Applications ------------- -* SLCD display control, segment on/off/blink -* Play battery animation, running wheel, wifi signal, etc. -* Display Time Clock by 7 segments character mapping -* Display ASCII character by 14 segments character mapping - -Dependencies ------------- -* SLCD capable hardware - -Concurrency ------------ -N/A - -Limitations ------------ - -Known issues and workarounds ----------------------------- -N/A diff --git a/watch-library/hal/documentation/spi_master_sync.rst b/watch-library/hal/documentation/spi_master_sync.rst deleted file mode 100755 index 4fbe45e2..00000000 --- a/watch-library/hal/documentation/spi_master_sync.rst +++ /dev/null @@ -1,51 +0,0 @@ -The SPI Master Synchronous Driver -================================= - -The serial peripheral interface (SPI) is a synchronous serial communication -interface. - -SPI devices communicate in full duplex mode using a master-slave -architecture with a single master. The master device originates the frame for -reading and writing. Multiple slave devices are supported through selection -with individual slave select (SS) lines. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* Control of the following settings: - - * Baudrate - * SPI mode - * Character size - * Data order -* Data transfer: transmission, reception and full-duplex - -Applications ------------- - -Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card, -LCD controller, etc. - -Dependencies ------------- - -SPI master capable hardware - -Concurrency ------------ - -N/A - -Limitations ------------ - -The slave select (SS) is not automatically inserted during read/write/transfer, -user must use I/O to control the devices' SS. - -Known issues and workarounds ----------------------------- - -N/A - diff --git a/watch-library/hal/documentation/usart_sync.rst b/watch-library/hal/documentation/usart_sync.rst deleted file mode 100755 index 15e4b138..00000000 --- a/watch-library/hal/documentation/usart_sync.rst +++ /dev/null @@ -1,58 +0,0 @@ -The USART Synchronous Driver -============================ - -The universal synchronous and asynchronous receiver and transmitter -(USART) is usually used to transfer data from one device to the other. - -User can set action for flow control pins by function usart_set_flow_control, -if the flow control is enabled. All the available states are defined in union -usart_flow_control_state. - -Note that user can set state of flow control pins only if automatic support of -the flow control is not supported by the hardware. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* Control of the following settings: - - * Baudrate - * UART or USRT communication mode - * Character size - * Data order - * Flow control -* Data transfer: transmission, reception - -Applications ------------- - -They are commonly used in a terminal application or low-speed communication -between devices. - -Dependencies ------------- - -USART capable hardware. - -Concurrency ------------ - -Write buffer should not be changed while data is being sent. - - -Limitations ------------ - -* The driver does not support 9-bit character size. -* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. - And the SCK pin can't be set directly. Application can use a GCLK output PIN - to generate SCK. For example to communicate with a SMARTCARD with ISO7816 - (F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be - config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. - -Known issues and workarounds ----------------------------- - -N/A diff --git a/watch-library/hal/include/hal_atomic.h b/watch-library/hal/include/hal_atomic.h deleted file mode 100644 index 82151fc5..00000000 --- a/watch-library/hal/include/hal_atomic.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * \file - * - * \brief Critical sections related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_ATOMIC_H_INCLUDED -#define _HAL_ATOMIC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_atomic - * - *@{ - */ - -/** - * \brief Type for the register holding global interrupt enable flag - */ -typedef uint32_t hal_atomic_t; - -/** - * \brief Helper macro for entering critical sections - * - * This macro is recommended to be used instead of a direct call - * hal_enterCritical() function to enter critical - * sections. No semicolon is required after the macro. - * - * \section atomic_usage Usage Example - * \code - * CRITICAL_SECTION_ENTER() - * Critical code - * CRITICAL_SECTION_LEAVE() - * \endcode - */ -#define CRITICAL_SECTION_ENTER() \ - { \ - volatile hal_atomic_t __atomic; \ - atomic_enter_critical(&__atomic); - -/** - * \brief Helper macro for leaving critical sections - * - * This macro is recommended to be used instead of a direct call - * hal_leaveCritical() function to leave critical - * sections. No semicolon is required after the macro. - */ -#define CRITICAL_SECTION_LEAVE() \ - atomic_leave_critical(&__atomic); \ - } - -/** - * \brief Disable interrupts, enter critical section - * - * Disables global interrupts. Supports nested critical sections, - * so that global interrupts are only re-enabled - * upon leaving the outermost nested critical section. - * - * \param[out] atomic The pointer to a variable to store the value of global - * interrupt enable flag - */ -void atomic_enter_critical(hal_atomic_t volatile *atomic); - -/** - * \brief Exit atomic section - * - * Enables global interrupts. Supports nested critical sections, - * so that global interrupts are only re-enabled - * upon leaving the outermost nested critical section. - * - * \param[in] atomic The pointer to a variable, which stores the latest stored - * value of the global interrupt enable flag - */ -void atomic_leave_critical(hal_atomic_t volatile *atomic); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t atomic_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/watch-library/hal/include/hal_calendar.h b/watch-library/hal/include/hal_calendar.h deleted file mode 100644 index e69de29b..00000000 diff --git a/watch-library/hal/include/hal_delay.h b/watch-library/hal/include/hal_delay.h deleted file mode 100644 index 9d4aa5c1..00000000 --- a/watch-library/hal/include/hal_delay.h +++ /dev/null @@ -1,89 +0,0 @@ -/** - * \file - * - * \brief HAL delay related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -#ifndef _HAL_DELAY_H_INCLUDED -#define _HAL_DELAY_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_delay Delay Driver - * - *@{ - */ - -/** - * \brief Initialize Delay driver - * - * \param[in] hw The pointer to hardware instance - */ -void delay_init(void *const hw); - -/** - * \brief Perform delay in us - * - * This function performs delay for the given amount of microseconds. - * - * \param[in] us The amount delay in us - */ -void delay_us(const uint16_t us); - -/** - * \brief Perform delay in ms - * - * This function performs delay for the given amount of milliseconds. - * - * \param[in] ms The amount delay in ms - */ -void delay_ms(const uint16_t ms); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t delay_get_version(void); - -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/watch-library/hal/include/hal_ext_irq.h b/watch-library/hal/include/hal_ext_irq.h deleted file mode 100644 index a7c26005..00000000 --- a/watch-library/hal/include/hal_ext_irq.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * \file - * - * \brief External interrupt functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_EXT_IRQ_H_INCLUDED -#define _HAL_EXT_IRQ_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_ext_irq - * - * @{ - */ - -/** - * \brief External IRQ callback type - */ -typedef void (*ext_irq_cb_t)(void); - -/** - * \brief Initialize external IRQ component, if any - * - * \return Initialization status. - * \retval -1 External IRQ module is already initialized - * \retval 0 The initialization is completed successfully - */ -int32_t ext_irq_init(void); - -/** - * \brief Deinitialize external IRQ, if any - * - * \return De-initialization status. - * \retval -1 External IRQ module is already deinitialized - * \retval 0 The de-initialization is completed successfully - */ -int32_t ext_irq_deinit(void); - -/** - * \brief Register callback for the given external interrupt - * - * \param[in] pin Pin to enable external IRQ on - * \param[in] cb Callback function - * - * \return Registration status. - * \retval -1 Passed parameters were invalid - * \retval 0 The callback registration is completed successfully - */ -int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb); - -/** - * \brief Enable external IRQ - * - * \param[in] pin Pin to enable external IRQ on - * - * \return Enabling status. - * \retval -1 Passed parameters were invalid - * \retval 0 The enabling is completed successfully - */ -int32_t ext_irq_enable(const uint32_t pin); - -/** - * \brief Disable external IRQ - * - * \param[in] pin Pin to enable external IRQ on - * - * \return Disabling status. - * \retval -1 Passed parameters were invalid - * \retval 0 The disabling is completed successfully - */ -int32_t ext_irq_disable(const uint32_t pin); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t ext_irq_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_EXT_IRQ_H_INCLUDED */ diff --git a/watch-library/hal/include/hal_flash.h b/watch-library/hal/include/hal_flash.h deleted file mode 100755 index 8216afde..00000000 --- a/watch-library/hal/include/hal_flash.h +++ /dev/null @@ -1,209 +0,0 @@ -/** - * \file - * - * \brief Flash related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_FLASH_H_INCLUDED -#define _HAL_FLASH_H_INCLUDED - -#include - -/** - * \addtogroup doc_driver_hal_flash - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Forward declaration of flash_descriptor. */ -struct flash_descriptor; - -/** The callback types */ -enum flash_cb_type { - /** Callback type for ready to accept a new command */ - FLASH_CB_READY, - /** Callback type for error */ - FLASH_CB_ERROR, - FLASH_CB_N -}; - -/** \brief Prototype of callback on FLASH - * - */ -typedef void (*flash_cb_t)(struct flash_descriptor *const descr); - -/** \brief FLASH HAL callbacks - * - */ -struct flash_callbacks { - /** Callback invoked when ready to accept a new command */ - flash_cb_t cb_ready; - /** Callback invoked when error occurs */ - flash_cb_t cb_error; -}; - -/** \brief FLASH HAL driver struct for asynchronous access - */ -struct flash_descriptor { - /** Pointer to FLASH device instance */ - struct _flash_device dev; - /** Callbacks for asynchronous transfer */ - struct flash_callbacks callbacks; -}; - -/** \brief Initialize the FLASH HAL instance and hardware for callback mode - * - * Initialize FLASH HAL with interrupt mode (uses callbacks). - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] hw Pointer to the hardware base. - * \return Initialize status. - */ -int32_t flash_init(struct flash_descriptor *flash, void *const hw); - -/** \brief Deinitialize the FLASH HAL instance - * - * Abort transfer, disable and reset FLASH, and deinitialize software. - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \return Deinitialze status. - */ -int32_t flash_deinit(struct flash_descriptor *flash); - -/** \brief Writes a number of bytes to a page in the internal Flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address to write into flash - * \param[in] buffer Pointer to a buffer where the content - * will be written to the flash - * \param[in] length Number of bytes to write - * \return Write status. - */ -int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); - -/** \brief Appends a number of bytes to a page in the internal Flash - * - * This functions never erases the flash before writing. - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address to write to flash - * \param[in] buffer Pointer to a buffer with data to write to flash - * \param[in] length Number of bytes to append - * \return Append status. - */ -int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); - -/** \brief Reads a number of bytes to a page in the internal Flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] src_addr Source bytes address to read from flash - * \param[out] buffer Pointer to a buffer where the content - * of the read pages will be stored - * \param[in] length Number of bytes to read - * \return Read status. - */ -int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length); - -/** \brief Register a function as FLASH transfer completion callback - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] type Callback type (\ref flash_cb_type). - * \param[in] func Pointer to callback function. - * \retval 0 Success - * \retval -1 Error - */ -int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func); - -/** \brief Execute lock in the internal flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address aligned with page - * start to be locked - * \param[in] page_nums Number of pages to be locked - * - * \return Real locked numbers of pages. - */ -int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); - -/** \brief Execute unlock in the internal flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address aligned with page - * start to be unlocked - * \param[in] page_nums Number of pages to be unlocked - * - * \return Real unlocked numbers of pages. - */ -int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); - -/** \brief Execute erase in the internal flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address aligned with page - * start to be erased - * \param[in] page_nums Number of pages to be erased - * \retval 0 Success - * \retval -1 Error - */ -int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); - -/** - * \brief Get the flash page size - * - * \param[in, out] flash Pointer to the HAL FLASH instance - * - * \return The flash page size - */ -uint32_t flash_get_page_size(struct flash_descriptor *flash); - -/** - * \brief Get the number of flash page - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * - * \return The flash total page numbers - */ -uint32_t flash_get_total_pages(struct flash_descriptor *flash); - -/** \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t flash_get_version(void); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* ifndef _HAL_FLASH_H_INCLUDED */ diff --git a/watch-library/hal/include/hal_gpio.h b/watch-library/hal/include/hal_gpio.h deleted file mode 100644 index fbfa2d4a..00000000 --- a/watch-library/hal/include/hal_gpio.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - * \file - * - * \brief Port - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - */ -#ifndef _HAL_GPIO_INCLUDED_ -#define _HAL_GPIO_INCLUDED_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Set gpio pull mode - * - * Set pin pull mode, non existing pull modes throws an fatal assert - * - * \param[in] pin The pin number for device - * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor - * GPIO_PULL_UP = Pull pin high with internal resistor - * GPIO_PULL_OFF = Disable pin pull mode - */ -static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) -{ - _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); -} - -/** - * \brief Set pin function - * - * Select which function a pin will be used for - * - * \param[in] pin The pin number for device - * \param[in] function The pin function is given by a 32-bit wide bitfield - * found in the header files for the device - * - */ -static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) -{ - _gpio_set_pin_function(pin, function); -} - -/** - * \brief Set port data direction - * - * Select if the pin data direction is input, output or disabled. - * If disabled state is not possible, this function throws an assert. - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to the - * corresponding pin - * \param[in] direction GPIO_DIRECTION_IN = Data direction in - * GPIO_DIRECTION_OUT = Data direction out - * GPIO_DIRECTION_OFF = Disables the pin - * (low power state) - */ -static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction) -{ - _gpio_set_direction(port, mask, direction); -} - -/** - * \brief Set gpio data direction - * - * Select if the pin data direction is input, output or disabled. - * If disabled state is not possible, this function throws an assert. - * - * \param[in] pin The pin number for device - * \param[in] direction GPIO_DIRECTION_IN = Data direction in - * GPIO_DIRECTION_OUT = Data direction out - * GPIO_DIRECTION_OFF = Disables the pin - * (low power state) - */ -static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) -{ - _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); -} - -/** - * \brief Set port level - * - * Sets output level on the pins defined by the bit mask - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply port level to the corresponding - * pin - * \param[in] level true = Pin levels set to "high" state - * false = Pin levels set to "low" state - */ -static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) -{ - _gpio_set_level(port, mask, level); -} - -/** - * \brief Set gpio level - * - * Sets output level on a pin - * - * \param[in] pin The pin number for device - * \param[in] level true = Pin level set to "high" state - * false = Pin level set to "low" state - */ -static inline void gpio_set_pin_level(const uint8_t pin, const bool level) -{ - _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); -} - -/** - * \brief Toggle out level on pins - * - * Toggle the pin levels on pins defined by bit mask - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding - * pin - */ -static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) -{ - _gpio_toggle_level(port, mask); -} - -/** - * \brief Toggle output level on pin - * - * Toggle the pin levels on pins defined by bit mask - * - * \param[in] pin The pin number for device - */ -static inline void gpio_toggle_pin_level(const uint8_t pin) -{ - _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); -} - -/** - * \brief Get input level on pins - * - * Read the input level on pins connected to a port - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - */ -static inline uint32_t gpio_get_port_level(const enum gpio_port port) -{ - return _gpio_get_level(port); -} - -/** - * \brief Get level on pin - * - * Reads the level on pins connected to a port - * - * \param[in] pin The pin number for device - */ -static inline bool gpio_get_pin_level(const uint8_t pin) -{ - return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); -} -/** - * \brief Get current driver version - */ -uint32_t gpio_get_version(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/watch-library/hal/include/hal_i2c_m_sync.h b/watch-library/hal/include/hal_i2c_m_sync.h deleted file mode 100644 index f7772483..00000000 --- a/watch-library/hal/include/hal_i2c_m_sync.h +++ /dev/null @@ -1,244 +0,0 @@ -/** - * \file - * - * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_I2C_M_SYNC_H_INCLUDED -#define _HAL_I2C_M_SYNC_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_i2c_controller_sync - * - * @{ - */ - -#define I2C_M_MAX_RETRY 1 - -/** - * \brief I2C descriptor structure, embed i2c_device & i2c_interface - */ -struct i2c_m_sync_desc { - struct _i2c_m_sync_device device; - struct io_descriptor io; - uint16_t periph_addr; -}; - -/** - * \brief Initialize synchronous I2C interface - * - * This function initializes the given I/O descriptor to be used as a - * synchronous I2C interface descriptor. - * It checks if the given hardware is not initialized and if the given hardware - * is permitted to be initialized. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - * \retval -1 The passed parameters were invalid or the interface is already initialized - * \retval 0 The initialization is completed successfully - */ -int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw); - -/** - * \brief Deinitialize I2C interface - * - * This function deinitializes the given I/O descriptor. - * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Uninitialization status. - * \retval -1 The passed parameters were invalid or the interface is already deinitialized - * \retval 0 The de-initialization is completed successfully - */ -int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c); - -/** - * \brief Set the peripheral device address - * - * This function sets the next transfer target peripheral I2C device address. - * It takes no effect to any already started access. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] addr The peripheral address to access - * \param[in] addr_len The peripheral address length, can be I2C_M_TEN or I2C_M_SEVEN - * - * \return Masked peripheral address. The mask is a maximum 10-bit address, and 10th - * bit is set if a 10-bit address is used - */ -int32_t i2c_m_sync_set_periphaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len); - -/** - * \brief Set baudrate - * - * This function sets the I2C device to the specified baudrate. - * It only takes effect when the hardware is disabled. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] clkrate Unused parameter. Should always be 0 - * \param[in] baudrate The baudrate value set to controller - * - * \return Whether successfully set the baudrate - * \retval -1 The passed parameters were invalid or the device is already enabled - * \retval 0 The baudrate set is completed successfully - */ -int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Sync version of enable hardware - * - * This function enables the I2C device, and then waits for this enabling operation to be done - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Whether successfully enable the device - * \retval -1 The passed parameters were invalid or the device enable failed - * \retval 0 The hardware enabling is completed successfully - */ -int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c); - -/** - * \brief Sync version of disable hardware - * - * This function disables the I2C device and then waits for this disabling operation to be done - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Whether successfully disable the device - * \retval -1 The passed parameters were invalid or the device disable failed - * \retval 0 The hardware disabling is completed successfully - */ -int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c); - -/** - * \brief Sync version of write command to I2C peripheral - * - * This function will write the value to a specified register in the I2C peripheral device and - * then wait for this operation to be done. - * - * The sequence of this routine is - * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] reg The internal address/register of the I2C peripheral device - * \param[in] buffer The buffer holding data to write to the I2C peripheral device - * \param[in] length The length (in bytes) to write to the I2C peripheral device - * - * \return Whether successfully write to the device - * \retval <0 The passed parameters were invalid or write fail - * \retval 0 Writing to register is completed successfully - */ -int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); - -/** - * \brief Sync version of read register value from I2C peripheral - * - * This function will read a byte value from a specified register in the I2C peripheral device and - * then wait for this operation to be done. - * - * The sequence of this routine is - * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] reg The internal address/register of the I2C peripheral device - * \param[in] buffer The buffer to hold the read data from the I2C peripheral device - * \param[in] length The length (in bytes) to read from the I2C peripheral device - * - * \return Whether successfully read from the device - * \retval <0 The passed parameters were invalid or read fail - * \retval 0 Reading from register is completed successfully - */ -int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); - -/** - * \brief Sync version of transfer message to/from the I2C peripheral - * - * This function will transfer a message between the I2C peripheral and the controller. - * This function will wait for the operation to be done. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] msg An i2c_m_msg struct - * - * \return The status of the operation - * \retval 0 Operation completed successfully - * \retval <0 Operation failed - */ -int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg); - -/** - * \brief Sync version of send stop condition on the i2c bus - * - * This function will create a stop condition on the i2c bus to release the bus - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return The status of the operation - * \retval 0 Operation completed successfully - * \retval <0 Operation failed - */ -int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c); - -/** - * \brief Return I/O descriptor for this I2C instance - * - * This function will return a I/O instance for this I2C driver instance - * - * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C - * \param[in] io_descriptor A pointer to an I/O descriptor pointer type - * - * \return Error code - * \retval 0 No error detected - * \retval <0 Error code - */ -int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t i2c_m_sync_get_version(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/watch-library/hal/include/hal_init.h b/watch-library/hal/include/hal_init.h deleted file mode 100644 index d7bc6fe2..00000000 --- a/watch-library/hal/include/hal_init.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * \file - * - * \brief HAL initialization related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_INIT_H_INCLUDED -#define _HAL_INIT_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_init Init Driver - * - *@{ - */ - -/** - * \brief Initialize the hardware abstraction layer - * - * This function calls the various initialization functions. - * Currently the following initialization functions are supported: - * - System clock initialization - */ -static inline void init_mcu(void) -{ - _init_chip(); -} - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t init_get_version(void); - -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/watch-library/hal/include/hal_io.h b/watch-library/hal/include/hal_io.h deleted file mode 100644 index f50401d7..00000000 --- a/watch-library/hal/include/hal_io.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - * \file - * - * \brief I/O related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_IO_INCLUDED -#define _HAL_IO_INCLUDED - -/** - * \addtogroup doc_driver_hal_helper_io I/O Driver - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief I/O descriptor - * - * The I/O descriptor forward declaration. - */ -struct io_descriptor; - -/** - * \brief I/O write function pointer type - */ -typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O read function pointer type - */ -typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O descriptor - */ -struct io_descriptor { - io_write_t write; /*! The write function pointer. */ - io_read_t read; /*! The read function pointer. */ -}; - -/** - * \brief I/O write interface - * - * This function writes up to \p length of bytes to a given I/O descriptor. - * It returns the number of bytes actually write. - * - * \param[in] descr An I/O descriptor to write - * \param[in] buf The buffer pointer to story the write data - * \param[in] length The number of bytes to write - * - * \return The number of bytes written - */ -int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O read interface - * - * This function reads up to \p length bytes from a given I/O descriptor, and - * stores it in the buffer pointed to by \p buf. It returns the number of bytes - * actually read. - * - * \param[in] descr An I/O descriptor to read - * \param[in] buf The buffer pointer to story the read data - * \param[in] length The number of bytes to read - * - * \return The number of bytes actually read. This number can be less than the - * requested length. E.g., in a driver that uses ring buffer for - * reception, it may depend on the availability of data in the - * ring buffer. - */ -int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HAL_IO_INCLUDED */ diff --git a/watch-library/hal/include/hal_rand_sync.h b/watch-library/hal/include/hal_rand_sync.h deleted file mode 100755 index 9f8cc31e..00000000 --- a/watch-library/hal/include/hal_rand_sync.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - * \file - * - * \brief Generic Random Number Generator (RAND) functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_RAND_SYNC_H_INCLUDED -#define _HAL_RAND_SYNC_H_INCLUDED - -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_rand_sync - * - *@{ - */ - -/** Random Number Generator polling device. */ -struct rand_sync_desc { - struct _rand_sync_dev dev; -}; - -/** - * \brief Initialize the Random Number Generator Driver - * \param[out] desc Pointer to the device descriptor instance struct - * \param[in, out] hw Pointer to the hardware for device instance - * \return Initialization operation result status, ERR_NONE (0) for OK. - */ -int32_t rand_sync_init(struct rand_sync_desc *const desc, void *const hw); - -/** - * \brief Deinitialize the Random Number Generator Driver - * \param[out] desc Pointer to the device descriptor instance struct - */ -void rand_sync_deinit(struct rand_sync_desc *const desc); - -/** - * \brief Enable the Random Number Generator Driver - * \param[out] desc Pointer to the device descriptor instance struct - * \return Enable operation result status, ERR_NONE (0) for OK. - */ -int32_t rand_sync_enable(struct rand_sync_desc *const desc); - -/** - * \brief Disable the Random Number Generator Driver - * \param[out] desc Pointer to the device descriptor instance struct - */ -void rand_sync_disable(struct rand_sync_desc *const desc); - -/** - * \brief Set seed for the Random Number Generator Driver - * \param[out] desc Pointer to the device descriptor instance struct - */ -int32_t rand_sync_set_seed(struct rand_sync_desc *const desc, const uint32_t seed); - -/** - * \brief Read the 8-bit Random Number - * \param[in] desc Pointer to the device descriptor instance struct - * \return The random number generated - */ -uint8_t rand_sync_read8(const struct rand_sync_desc *const desc); - -/** - * \brief Read the 32-bit Random Number - * \param[in] desc Pointer to the device descriptor instance struct - * \return The random number generated - */ -uint32_t rand_sync_read32(const struct rand_sync_desc *const desc); - -/** - * \brief Read the 8-bit Random Number Sequence into a buffer - * \param[in] desc Pointer to the device descriptor instance struct - * \param[out] buf Pointer to the buffer to fill an array of generated numbers - * \param[in] len Number of random numbers to read - */ -void rand_sync_read_buf8(const struct rand_sync_desc *const desc, uint8_t *buf, uint32_t len); - -/** - * \brief Read the 32-bit Random Number Sequence into a buffer - * \param[in] desc Pointer to the device descriptor instance struct - * \param[out] buf Pointer to the buffer to fill an array of generated numbers - * \param[in] len Number of random numbers to read - */ -void rand_sync_read_buf32(const struct rand_sync_desc *const desc, uint32_t *buf, uint32_t len); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t rand_sync_get_version(void); - -/* I/O read will be used to get random data. */ - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_RAND_SYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hal_slcd_sync.h b/watch-library/hal/include/hal_slcd_sync.h deleted file mode 100644 index 84c4e1f9..00000000 --- a/watch-library/hal/include/hal_slcd_sync.h +++ /dev/null @@ -1,168 +0,0 @@ -/** - * \file - * - * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality - * declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef HAL_SLCD_SYNC_H_INCLUDED -#define HAL_SLCD_SYNC_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_slcd_sync - * - *@{ - */ - -struct slcd_sync_descriptor { - struct _slcd_sync_device dev; /*!< SLCD HPL device descriptor */ -}; - -/** - * \brief Initialize SLCD Descriptor - * - * \param[in] descr SLCD descriptor to be initialized - * \param[in] hw The pointer to hardware instance - */ -int32_t slcd_sync_init(struct slcd_sync_descriptor *const descr, void *const hw); - -/** - * \brief Deinitialize SLCD Descriptor - * - * \param[in] descr SLCD descriptor to be deinitialized - */ -int32_t slcd_sync_deinit(struct slcd_sync_descriptor *const descr); - -/** - * \brief Enable SLCD driver - * - * \param[in] descr SLCD descriptor to be initialized - */ -int32_t slcd_sync_enable(struct slcd_sync_descriptor *const descr); - -/** - * \brief Disable SLCD driver - * - * \param[in] descr SLCD descriptor to be disabled - */ -int32_t slcd_sync_disable(struct slcd_sync_descriptor *const descr); - -/** - * \brief Turn on a Segment - * - * \param[in] descr SLCD descriptor to be enabled - * \param[in] seg Segment index. The segment index is by the combination - * of common and segment terminal index. The - * SLCD_SEGID(com, seg) macro can generate the index. - */ -int32_t slcd_sync_seg_on(struct slcd_sync_descriptor *const descr, uint32_t seg); - -/** - * \brief Turn off a Segment - * - * \param[in] descr SLCD descriptor - * \param[in] seg Segment index - * value is "(common terminals << 16 | segment terminal)" - */ -int32_t slcd_sync_seg_off(struct slcd_sync_descriptor *const descr, uint32_t seg); - -/** - * \brief Blink a Segment - * - * \param[in] descr SLCD descriptor - * \param[in] seg Segment index - * value is "(common terminals << 16 | segment terminal)" - * \param[in] period Blink period, unit is millisecond - */ -int32_t slcd_sync_seg_blink(struct slcd_sync_descriptor *const descr, uint32_t seg, const uint32_t period); - -/** - * \brief Displays a character - * - * \param[in] descr SLCD descriptor - * \param[in] character Character to be displayed - * \param[in] index Index of the character Mapping Group - */ -int32_t slcd_sync_write_char(struct slcd_sync_descriptor *const descr, const uint8_t character, uint32_t index); - -/** - * \brief Displays character string string - * - * \param[in] descr SLCD descriptor - * \param[in] str String to be displayed, 0 will turn off the - * corresponding char to display - * \param[in] len Length of the string array - * \param[in] index Index of the character Mapping Group - */ -int32_t slcd_sync_write_string(struct slcd_sync_descriptor *const descr, uint8_t *const str, uint32_t len, - uint32_t index); - -/** - * \brief Start animation play by a segment array - * - * \param[in] descr SLCD descriptor - * \param[in] segs Segment array - * \param[in] len Length of the segment array - * \param[in] period Period (milliseconds) of each segment to animation - */ -int32_t slcd_sync_start_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len, - const uint32_t period); - -/** - * \brief Stop animation play by a segment array - * - * \param[in] descr SLCD descriptor - * \param[in] segs Segment array - * \param[in] len Length of the segment array - */ -int32_t slcd_sync_stop_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len); - -/** - * \brief Set animation Frequency - * - * \param[in] descr SLCD descriptor - * \param[in] period Period (million second) of each segment to animation - */ -int32_t slcd_sync_set_animation_period(struct slcd_sync_descriptor *const descr, const uint32_t period); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/watch-library/hal/include/hal_sleep.h b/watch-library/hal/include/hal_sleep.h deleted file mode 100644 index b90ef6a5..00000000 --- a/watch-library/hal/include/hal_sleep.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SLEEP_H_INCLUDED -#define _HAL_SLEEP_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_sleep - * - *@{ - */ - -/** - * \brief Set the sleep mode of the device and put the MCU to sleep - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see the data sheet. - * - * \param[in] mode Sleep mode to use - * - * \return The status of a sleep request - * \retval -1 The requested sleep mode was invalid or not available - * \retval 0 The operation completed successfully, returned after leaving the - * sleep - */ -int sleep(const uint8_t mode); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t sleep_get_version(void); -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/watch-library/hal/include/hal_spi_m_sync.h b/watch-library/hal/include/hal_spi_m_sync.h deleted file mode 100755 index 5d040558..00000000 --- a/watch-library/hal/include/hal_spi_m_sync.h +++ /dev/null @@ -1,221 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SPI_M_SYNC_H_INCLUDED -#define _HAL_SPI_M_SYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup doc_driver_hal_spi_master_sync - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** \brief SPI HAL driver struct for polling mode - * - */ -struct spi_m_sync_descriptor { - struct _spi_m_sync_hpl_interface *func; - /** SPI device instance */ - struct _spi_sync_dev dev; - /** I/O read/write */ - struct io_descriptor io; - /** Flags for HAL driver */ - uint16_t flags; -}; - -/** \brief Set the SPI HAL instance function pointer for HPL APIs. - * - * Set SPI HAL instance function pointer for HPL APIs. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] func Pointer to the HPL api structure. - * - */ -void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func); - -/** \brief Initialize SPI HAL instance and hardware for polling mode - * - * Initialize SPI HAL with polling mode. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] hw Pointer to the hardware base. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_INVALID_DATA Error, initialized. - */ -int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw); - -/** \brief Deinitialize the SPI HAL instance and hardware - * - * Abort transfer, disable and reset SPI, deinit software. - * - * \param[in] spi Pointer to the HAL SPI instance. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval <0 Error code. - */ -void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi); - -/** \brief Enable SPI - * - * \param[in] spi Pointer to the HAL SPI instance. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval <0 Error code. - */ -void spi_m_sync_enable(struct spi_m_sync_descriptor *spi); - -/** \brief Disable SPI - * - * \param[in] spi Pointer to the HAL SPI instance. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval <0 Error code. - */ -void spi_m_sync_disable(struct spi_m_sync_descriptor *spi); - -/** \brief Set SPI baudrate - * - * Works if SPI is initialized as master, it sets the baudrate. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] baud_val The target baudrate value - * (see "baudrate calculation" for calculating the value). - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The baudrate is not supported. - */ -int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val); - -/** \brief Set SPI mode - * - * Set the SPI transfer mode (\ref spi_transfer_mode), - * which controls the clock polarity and clock phase: - * - Mode 0: leading edge is rising edge, data sample on leading edge. - * - Mode 1: leading edge is rising edge, data sample on trailing edge. - * - Mode 2: leading edge is falling edge, data sample on leading edge. - * - Mode 3: leading edge is falling edge, data sample on trailing edge. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] mode The mode (0~3). - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The mode is not supported. - */ -int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode); - -/** \brief Set SPI transfer character size in number of bits - * - * The character size (\ref spi_char_size) influence the way the data is - * sent/received. - * For char size <= 8-bit, data is stored byte by byte. - * For char size between 9-bit ~ 16-bit, data is stored in 2-byte length. - * Note that the default and recommended char size is 8-bit since it's - * supported by all system. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] char_size The char size (~16, recommended 8). - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The char size is not supported. - */ -int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size); - -/** \brief Set SPI transfer data order - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] dord The data order: send LSB/MSB first. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The data order is not supported. - */ -int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord); - -/** \brief Perform the SPI data transfer (TX and RX) in polling way - * - * Activate CS, do TX and RX and deactivate CS. It blocks. - * - * \param[in, out] spi Pointer to the HAL SPI instance. - * \param[in] xfer Pointer to the transfer information (\ref spi_xfer). - * - * \retval size Success. - * \retval >=0 Timeout, with number of characters transferred. - * \retval ERR_BUSY SPI is busy - */ -int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer); - -/** - * \brief Return the I/O descriptor for this SPI instance - * - * This function will return an I/O instance for this SPI driver instance. - * - * \param[in] spi An SPI master descriptor, which is used to communicate through - * SPI - * \param[in, out] io A pointer to an I/O descriptor pointer type - * - * \retval ERR_NONE - */ -int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io); - -/** \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t spi_m_sync_get_version(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hal_usart_sync.h b/watch-library/hal/include/hal_usart_sync.h deleted file mode 100755 index 1ef22fc6..00000000 --- a/watch-library/hal/include/hal_usart_sync.h +++ /dev/null @@ -1,247 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SYNC_USART_H_INCLUDED -#define _HAL_SYNC_USART_H_INCLUDED - -#include "hal_io.h" -#include - -/** - * \addtogroup doc_driver_hal_usart_sync - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Synchronous USART descriptor - */ -struct usart_sync_descriptor { - struct io_descriptor io; - struct _usart_sync_device device; -}; - -/** - * \brief Initialize USART interface - * - * This function initializes the given I/O descriptor to be used - * as USART interface descriptor. - * It checks if the given hardware is not initialized and - * if the given hardware is permitted to be initialized. - * - * \param[out] descr A USART descriptor which is used to communicate via USART - * \param[in] hw The pointer to hardware instance - * \param[in] func The pointer to as set of functions pointers - * - * \return Initialization status. - */ -int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); - -/** - * \brief Deinitialize USART interface - * - * This function deinitializes the given I/O descriptor. - * It checks if the given hardware is initialized and - * if the given hardware is permitted to be deinitialized. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return De-initialization status. - */ -int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); - -/** - * \brief Enable USART interface - * - * Enables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Enabling status. - */ -int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); - -/** - * \brief Disable USART interface - * - * Disables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Disabling status. - */ -int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); - -/** - * \brief Retrieve I/O descriptor - * - * This function retrieves the I/O descriptor of the given USART descriptor. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] io An I/O descriptor to retrieve - * - * \return The status of the I/O descriptor retrieving. - */ -int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); - -/** - * \brief Specify action for flow control pins - * - * This function sets the action (or state) for the flow control pins - * if the flow control is enabled. - * It sets the state of flow control pins only if the automatic support of - * the flow control is not supported by the hardware. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] state A state to set the flow control pins - * - * \return The status of flow control action setup. - */ -int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, - const union usart_flow_control_state state); - -/** - * \brief Set USART baud rate - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] baud_rate A baud rate to set - * - * \return The status of baud rate setting. - */ -int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); - -/** - * \brief Set USART data order - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] data_order A data order to set - * - * \return The status of data order setting. - */ -int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); - -/** - * \brief Set USART mode - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] mode A mode to set - * - * \return The status of mode setting. - */ -int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); - -/** - * \brief Set USART parity - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] parity A parity to set - * - * \return The status of parity setting. - */ -int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); - -/** - * \brief Set USART stop bits - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] stop_bits Stop bits to set - * - * \return The status of stop bits setting. - */ -int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); - -/** - * \brief Set USART character size - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] size A character size to set - * - * \return The status of character size setting. - */ -int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins - * if the flow control is enabled. - * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case - * if the flow control is done by the hardware - * and the pins state cannot be read out. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] state The state of flow control pins - * - * \return The status of flow control state reading. - */ -int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, - union usart_flow_control_state *const state); - -/** - * \brief Check if the USART transmitter is empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of USART TX empty checking. - * \retval 0 The USART transmitter is not empty - * \retval 1 The USART transmitter is empty - */ -int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); - -/** - * \brief Check if the USART receiver is not empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of USART RX empty checking. - * \retval 1 The USART receiver is not empty - * \retval 0 The USART receiver is empty - */ -int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t usart_sync_get_version(void); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_calendar.h b/watch-library/hal/include/hpl_calendar.h deleted file mode 100644 index 0dce40fd..00000000 --- a/watch-library/hal/include/hpl_calendar.h +++ /dev/null @@ -1,75 +0,0 @@ -/** - * \file - * - * \brief Generic CALENDAR functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_CALENDER_H_INCLUDED -#define _HPL_CALENDER_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Time struct for calendar - */ -struct calendar_time { - /*range from 0 to 59*/ - uint8_t sec; - /*range from 0 to 59*/ - uint8_t min; - /*range from 0 to 23*/ - uint8_t hour; -}; - -/** - * \brief Time struct for calendar - */ -struct calendar_date { - /*range from 1 to 28/29/30/31*/ - uint8_t day; - /*range from 1 to 12*/ - uint8_t month; - /*absolute year>= 1970(such as 2000)*/ - uint16_t year; -}; - -/** \brief Date&Time struct for calendar - */ -struct calendar_date_time { - struct calendar_time time; - struct calendar_date date; -}; - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_RTC_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_core.h b/watch-library/hal/include/hpl_core.h deleted file mode 100644 index 9324c43e..00000000 --- a/watch-library/hal/include/hpl_core.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * \file - * - * \brief CPU core related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_CORE_H_INCLUDED -#define _HPL_CORE_H_INCLUDED - -/** - * \addtogroup HPL Core - * - * \section hpl_core_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_core_port.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_delay.h b/watch-library/hal/include/hpl_delay.h deleted file mode 100644 index a0f1ac81..00000000 --- a/watch-library/hal/include/hpl_delay.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * \file - * - * \brief Delay related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_DELAY_H_INCLUDED -#define _HPL_DELAY_H_INCLUDED - -/** - * \addtogroup HPL Delay - * - * \section hpl_delay_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ - -/** - * \brief Initialize delay functionality - * - * \param[in] hw The pointer to hardware instance - */ -void _delay_init(void *const hw); - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - * - * \param[in] us The amount of us to delay for - * - * \return The amount of cycles - */ -uint32_t _get_cycles_for_us(const uint16_t us); - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - * - * \param[in] ms The amount of ms to delay for - * - * \return The amount of cycles - */ -uint32_t _get_cycles_for_ms(const uint16_t ms); - -/** - * \brief Delay loop to delay n number of cycles - * - * \param[in] hw The pointer to hardware instance - * \param[in] cycles The amount of cycles to delay for - */ -void _delay_cycles(void *const hw, uint32_t cycles); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_dma.h b/watch-library/hal/include/hpl_dma.h deleted file mode 100644 index 1e08434a..00000000 --- a/watch-library/hal/include/hpl_dma.h +++ /dev/null @@ -1,176 +0,0 @@ -/** - * \file - * - * \brief DMA related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_DMA_H_INCLUDED -#define _HPL_DMA_H_INCLUDED - -/** - * \addtogroup HPL DMA - * - * \section hpl_dma_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct _dma_resource; - -/** - * \brief DMA callback types - */ -enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; - -/** - * \brief DMA interrupt callbacks - */ -struct _dma_callbacks { - void (*transfer_done)(struct _dma_resource *resource); - void (*error)(struct _dma_resource *resource); -}; - -/** - * \brief DMA resource structure - */ -struct _dma_resource { - struct _dma_callbacks dma_cb; - void * back; -}; - -/** - * \brief Initialize DMA - * - * This function does low level DMA configuration. - * - * \return initialize status - */ -int32_t _dma_init(void); - -/** - * \brief Set destination address - * - * \param[in] channel DMA channel to set destination address for - * \param[in] dst Destination address - * - * \return setting status - */ -int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); - -/** - * \brief Set source address - * - * \param[in] channel DMA channel to set source address for - * \param[in] src Source address - * - * \return setting status - */ -int32_t _dma_set_source_address(const uint8_t channel, const void *const src); - -/** - * \brief Set next descriptor address - * - * \param[in] current_channel Current DMA channel to set next descriptor address - * \param[in] next_channel Next DMA channel used as next descriptor - * - * \return setting status - */ -int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); - -/** - * \brief Enable/disable source address incrementation during DMA transaction - * - * \param[in] channel DMA channel to set source address for - * \param[in] enable True to enable, false to disable - * - * \return status of operation - */ -int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); - -/** - * \brief Enable/disable Destination address incrementation during DMA transaction - * - * \param[in] channel DMA channel to set destination address for - * \param[in] enable True to enable, false to disable - * - * \return status of operation - */ -int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); -/** - * \brief Set the amount of data to be transfered per transaction - * - * \param[in] channel DMA channel to set data amount for - * \param[in] amount Data amount - * - * \return status of operation - */ -int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); - -/** - * \brief Trigger DMA transaction on the given channel - * - * \param[in] channel DMA channel to trigger transaction on - * - * \return status of operation - */ -int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); - -/** - * \brief Retrieves DMA resource structure - * - * \param[out] resource The resource to be retrieved - * \param[in] channel DMA channel to retrieve structure for - * - * \return status of operation - */ -int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); - -/** - * \brief Enable/disable DMA interrupt - * - * \param[in] channel DMA channel to enable/disable interrupt for - * \param[in] type The type of interrupt to disable/enable if applicable - * \param[in] state Enable or disable - */ -void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); - -#ifdef __cplusplus -} -#endif - -#endif /* HPL_DMA_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_ext_irq.h b/watch-library/hal/include/hpl_ext_irq.h deleted file mode 100644 index 3a169b69..00000000 --- a/watch-library/hal/include/hpl_ext_irq.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * \file - * - * \brief External IRQ related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_EXT_IRQ_H_INCLUDED -#define _HPL_EXT_IRQ_H_INCLUDED - -/** - * \addtogroup HPL EXT IRQ - * - * \section hpl_ext_irq_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize external interrupt module - * - * This function does low level external interrupt configuration. - * - * \param[in] cb The pointer to callback function from external interrupt - * - * \return Initialization status. - * \retval -1 External irq module is already initialized - * \retval 0 The initialization is completed successfully - */ -int32_t _ext_irq_init(void (*cb)(const uint32_t pin)); - -/** - * \brief Deinitialize external interrupt module - * - * \return Initialization status. - * \retval -1 External irq module is already deinitialized - * \retval 0 The de-initialization is completed successfully - */ -int32_t _ext_irq_deinit(void); - -/** - * \brief Enable / disable external irq - * - * \param[in] pin Pin to enable external irq on - * \param[in] enable True to enable, false to disable - * - * \return Status of external irq enabling / disabling - * \retval -1 External irq module can't be enabled / disabled - * \retval 0 External irq module is enabled / disabled successfully - */ -int32_t _ext_irq_enable(const uint32_t pin, const bool enable); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_EXT_IRQ_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_flash.h b/watch-library/hal/include/hpl_flash.h deleted file mode 100755 index 3a42c448..00000000 --- a/watch-library/hal/include/hpl_flash.h +++ /dev/null @@ -1,265 +0,0 @@ -/** - * \file - * - * \brief FLASH related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_FLASH_H_INCLUDED -#define _HPL_FLASH_H_INCLUDED - -/** - * \addtogroup hpl__flash__group FLASH HPL APIs - * - */ - -/**@{*/ - -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief FLASH device structure - * - * The FLASH device structure forward declaration. - */ -struct _flash_device; - -/** The callback types */ -enum _flash_cb_type { FLASH_DEVICE_CB_READY, FLASH_DEVICE_CB_ERROR, FLASH_DEVICE_CB_N }; - -/** - * \brief FLASH interrupt handlers structure - */ -struct _flash_callback { - /** Ready to accept new command handler */ - void (*ready_cb)(struct _flash_device *device); - /** Error handler */ - void (*error_cb)(struct _flash_device *device); -}; - -/** - * \brief FLASH descriptor device structure. - */ -struct _flash_device { - struct _flash_callback flash_cb; /*!< Interrupt handers */ - struct _irq_descriptor irq; /*!< Interrupt descriptor */ - void * hw; /*!< Hardware module instance handler */ -}; - -/** - * \brief Initialize FLASH. - * - * This function does low level FLASH configuration. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialize status. - */ -int32_t _flash_init(struct _flash_device *const device, void *const hw); - -/** - * \brief Deinitialize FLASH. - * - * \param[in] device The pointer to FLASH device instance - */ -void _flash_deinit(struct _flash_device *const device); - -/** - * \brief Reads a number of bytes in the internal Flash. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] src_addr Source bytes address to read from flash - * \param[out] buffer Pointer to a buffer where the content - * of the read page will be stored - * \param[in] length Number of bytes to read - */ -void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length); - -/** - * \brief Writes a number of bytes in the internal Flash. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address to write into flash - * \param[in] buffer Pointer to buffer where the data to - * write is stored - * \param[in] length Number of bytes to write - */ -void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); - -/** - * \brief Appends a number of bytes in the internal Flash. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address to write into flash - * \param[in] buffer Pointer to buffer with data to write to flash - * \param[in] length Number of bytes to write - */ -void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); - -/** \brief Execute lock in the internal flash - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address aligned with page - * start to be locked - * \param[in] page_nums Number of pages to be locked - * - * \return Real locked numbers of pages. - */ -int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); - -/** \brief Execute unlock in the internal flash - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address aligned with page - * start to be unlocked - * \param[in] page_nums Number of pages to be unlocked - * - * \return Real unlocked numbers of pages. - */ -int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); - -/** \brief check whether the region which is pointed by address - * is locked - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address to check - * - * \return The lock status of assigned address. - */ -bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr); - -/** \brief Execute erase in the internal flash - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address aligned with page - * start to be erased - * \param[in] page_nums Number of pages to be erased - */ -void _flash_erase(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); - -/** - * \brief Get the flash page size. - * - * \param[in] device The pointer to FLASH device instance - * - * \return The flash page size - */ -uint32_t _flash_get_page_size(struct _flash_device *const device); - -/** - * \brief Get the numbers of flash page. - * - * \param[in] device The pointer to FLASH device instance - * - * \return The flash total page numbers - */ -uint32_t _flash_get_total_pages(struct _flash_device *const device); - -/** - * \brief Get the number of wait states for read and write operations. - * - * \param[in] device The pointer to FLASH device instance - * - * \return The number of wait states for read and write operations - */ -uint8_t _flash_get_wait_state(struct _flash_device *const device); - -/** - * \brief Set the number of wait states for read and write operations. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] state The number of wait states - * - */ -void _flash_set_wait_state(struct _flash_device *const device, uint8_t state); - -/** - * \brief Enable/disable Flash interrupt - * - * param[in] device The pointer to Flash device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state); - -/* - * Below RWW flash APIs are only available for device which has RWWEE - * flash array, such as SAM C20/C21/D21/L21/L22/R30/DA1/HA1 etc. - */ -/** - * \brief Get the RWWEE flash page size. - * - * \param[in] device The pointer to FLASH device instance - * - * \return The flash page size - */ -uint32_t _rww_flash_get_page_size(struct _flash_device *const device); - -/** - * \brief Get the total page numbers of RWWEE flash. - * - * \param[in] device The pointer to FLASH device instance - * - * \return The flash total page numbers - */ -uint32_t _rww_flash_get_total_pages(struct _flash_device *const device); - -/** - * \brief Reads a number of bytes in the internal RWWEE Flash. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] src_addr Source bytes address to read from flash - * \param[out] buffer Pointer to a buffer where the content - * of the read page will be stored - * \param[in] length Number of bytes to read - * - * \return Read status, ERR_NONE for successful read. - */ -int32_t _rww_flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length); - -/** - * \brief Writes a number of bytes in the internal RWWEE Flash. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address to write into flash - * \param[in] buffer Pointer to buffer where the data to - * write is stored - * \param[in] length Number of bytes to write - * - * \return Write status, ERR_NONE for successful write. - */ -int32_t _rww_flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); -#ifdef __cplusplus -} -#endif - -/**@}*/ - -#endif /* _HPL_FLASH_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_gpio.h b/watch-library/hal/include/hpl_gpio.h deleted file mode 100644 index 5cdd387b..00000000 --- a/watch-library/hal/include/hpl_gpio.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - * \file - * - * \brief Port related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_GPIO_H_INCLUDED -#define _HPL_GPIO_H_INCLUDED - -/** - * \addtogroup HPL Port - * - * \section hpl_port_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif -/** - * \brief Macros for the pin and port group, lower 5 - * bits stands for pin number in the group, higher 3 - * bits stands for port group - */ -#define GPIO_PIN(n) (((n)&0x1Fu) << 0) -#define GPIO_PORT(n) ((n) >> 5) -#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) -#define GPIO_PIN_FUNCTION_OFF 0xffffffff - -/** - * \brief PORT pull mode settings - */ -enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; - -/** - * \brief PORT direction settins - */ -enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; - -/** - * \brief PORT group abstraction - */ - -enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Port initialization function - * - * Port initialization function should setup the port module based - * on a static configuration file, this function should normally - * not be called directly, but is a part of hal_init() - */ -void _gpio_init(void); - -/** - * \brief Set direction on port with mask - * - * Set data direction for each pin, or disable the pin - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to the - * corresponding pin - * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input - * and disable input buffer to disable the pin - * GPIO_DIRECTION_IN = set pin direction to input - * and enable input buffer to enable the pin - * GPIO_DIRECTION_OUT = set pin direction to output - * and disable input buffer - */ -static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction); - -/** - * \brief Set output level on port with mask - * - * Sets output state on pin to high or low with pin masking - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to - * the corresponding pin - * \param[in] level true = pin level is set to 1 - * false = pin level is set to 0 - */ -static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); - -/** - * \brief Change output level to the opposite with mask - * - * Change pin output level to the opposite with pin masking - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to - * the corresponding pin - */ -static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); - -/** - * \brief Get input levels on all port pins - * - * Get input level on all port pins, will read IN register if configured to - * input and OUT register if configured as output - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - */ -static inline uint32_t _gpio_get_level(const enum gpio_port port); - -/** - * \brief Set pin pull mode - * - * Set pull mode on a single pin - * - * \notice This function will automatically change pin direction to input - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] pin The pin in the group that pull mode should be selected - * for - * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled - * GPIO_PULL_DOWN = pull resistor on pin will pull pin - * level to ground level - * GPIO_PULL_UP = pull resistor on pin will pull pin - * level to VCC - */ -static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, - const enum gpio_pull_mode pull_mode); - -/** - * \brief Set gpio function - * - * Select which function a gpio is used for - * - * \param[in] gpio The gpio to set function for - * \param[in] function The gpio function is given by a 32-bit wide bitfield - * found in the header files for the device - * - */ -static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); - -#include -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_i2c_m_async.h b/watch-library/hal/include/hpl_i2c_m_async.h deleted file mode 100644 index 8a9491de..00000000 --- a/watch-library/hal/include/hpl_i2c_m_async.h +++ /dev/null @@ -1,205 +0,0 @@ -/** - * \file - * - * \brief I2C Master Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED -#define _HPL_I2C_M_ASYNC_H_INCLUDED - -#include "hpl_i2c_m_sync.h" -#include "hpl_irq.h" -#include "utils.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c master callback names - */ -enum _i2c_m_async_callback_type { - I2C_M_ASYNC_DEVICE_ERROR, - I2C_M_ASYNC_DEVICE_TX_COMPLETE, - I2C_M_ASYNC_DEVICE_RX_COMPLETE -}; - -struct _i2c_m_async_device; - -typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); -typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); - -/** - * \brief i2c callback pointers structure - */ -struct _i2c_m_async_callback { - _i2c_error_cb_t error; - _i2c_complete_cb_t tx_complete; - _i2c_complete_cb_t rx_complete; -}; - -/** - * \brief i2c device structure - */ -struct _i2c_m_async_device { - struct _i2c_m_service service; - void * hw; - struct _i2c_m_async_callback cb; - struct _irq_descriptor irq; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize I2C in interrupt mode - * - * This function does low level I2C configuration. - * - * \param[in] i2c_dev The pointer to i2c interrupt device structure - * \param[in] hw The pointer to hardware instance - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); - -/** - * \brief Deinitialize I2C in interrupt mode - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Transfer data by I2C - * - * This function does low level I2C data transfer. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] msg The pointer to i2c msg structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); - -/** - * \brief Set baud rate of I2C - * - * This function does low level I2C set baud rate. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] clkrate The clock rate(KHz) input to i2c module - * \param[in] baudrate The demand baud rate(KHz) of i2c module - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Register callback to I2C - * - * This function does low level I2C callback register. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] cb_type The callback type request - * \param[in] func The callback function pointer - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, - FUNC_PTR func); - -/** - * \brief Generate stop condition on the I2C bus - * - * This function will generate a stop condition on the I2C bus - * - * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C - * - * \return Operation status - * \retval 0 Operation executed successfully - * \retval <0 Operation failed - */ -int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Returns the number of bytes left or not used in the I2C message buffer - * - * This function will return the number of bytes left (not written to the bus) or still free - * (not received from the bus) in the message buffer, depending on direction of transmission. - * - * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C - * - * \return Number of bytes or error code - * \retval >0 Positive number indicating bytes left - * \retval 0 Buffer is full/empty depending on direction - * \retval <0 Error code - */ -int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Enable/disable I2C master interrupt - * - * param[in] device The pointer to I2C master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, - const bool state); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/watch-library/hal/include/hpl_i2c_m_sync.h b/watch-library/hal/include/hpl_i2c_m_sync.h deleted file mode 100644 index ce173ae2..00000000 --- a/watch-library/hal/include/hpl_i2c_m_sync.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - * \file - * - * \brief I2C Master Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_M_SYNC_H_INCLUDED -#define _HPL_I2C_M_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c flags - */ -#define I2C_M_RD 0x0001 /* read data, from slave to master */ -#define I2C_M_BUSY 0x0100 -#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ -#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ -#define I2C_M_FAIL 0x1000 -#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ - -/** - * \brief i2c Return codes - */ -#define I2C_OK 0 /* Operation successful */ -#define I2C_ACK -1 /* Received ACK from device on I2C bus */ -#define I2C_NACK -2 /* Received NACK from device on I2C bus */ -#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ -#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ -#define I2C_ERR_BUS -5 /* Bus error */ -#define I2C_ERR_BUSY -6 /* Device busy */ -#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ - -/** - * \brief i2c I2C Modes - */ -#define I2C_STANDARD_MODE 0x00 -#define I2C_FASTMODE 0x01 -#define I2C_HIGHSPEED_MODE 0x02 - -/** - * \brief i2c master message structure - */ -struct _i2c_m_msg { - uint16_t addr; - volatile uint16_t flags; - int32_t len; - uint8_t * buffer; -}; - -/** - * \brief i2c master service - */ -struct _i2c_m_service { - struct _i2c_m_msg msg; - uint16_t mode; - uint16_t trise; -}; - -/** - * \brief i2c sync master device structure - */ -struct _i2c_m_sync_device { - struct _i2c_m_service service; - void * hw; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize I2C - * - * This function does low level I2C configuration. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] hw The pointer to hardware instance - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); - -/** - * \brief Deinitialize I2C - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Transfer data by I2C - * - * This function does low level I2C data transfer. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] msg The pointer to i2c msg structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); - -/** - * \brief Set baud rate of I2C - * - * This function does low level I2C set baud rate. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] clkrate The clock rate(KHz) input to i2c module - * \param[in] baudrate The demand baud rate(KHz) of i2c module - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Send send condition on the I2C bus - * - * This function will generate a stop condition on the I2C bus - * - * \param[in] i2c_dev The pointer to i2c device struct - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/watch-library/hal/include/hpl_i2c_s_async.h b/watch-library/hal/include/hpl_i2c_s_async.h deleted file mode 100644 index 92a5765d..00000000 --- a/watch-library/hal/include/hpl_i2c_s_async.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - * \file - * - * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED -#define _HPL_I2C_S_ASYNC_H_INCLUDED - -#include "hpl_i2c_s_sync.h" -#include "hpl_irq.h" -#include "utils.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c callback types - */ -enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; - -/** - * \brief Forward declaration of I2C Slave device - */ -struct _i2c_s_async_device; - -/** - * \brief i2c slave callback function type - */ -typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); - -/** - * \brief i2c slave callback pointers structure - */ -struct _i2c_s_async_callback { - void (*error)(struct _i2c_s_async_device *const device); - void (*tx)(struct _i2c_s_async_device *const device); - void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); -}; - -/** - * \brief i2c slave device structure - */ -struct _i2c_s_async_device { - void * hw; - struct _i2c_s_async_callback cb; - struct _irq_descriptor irq; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize asynchronous I2C slave - * - * This function does low level I2C configuration. - * - * \param[in] device The pointer to i2c interrupt device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); - -/** - * \brief Deinitialize asynchronous I2C in interrupt mode - * - * \param[in] device The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); - -/** - * \brief Check if 10-bit addressing mode is on - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Cheking status - * \retval 1 10-bit addressing mode is on - * \retval 0 10-bit addressing mode is off - */ -int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); - -/** - * \brief Set I2C slave address - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] address Address to set - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); - -/** - * \brief Write a byte to the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] data Data to write - */ -void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); - -/** - * \brief Retrieve I2C slave status - * - * \param[in] device The pointer to i2c slave device structure - * - *\return I2C slave status - */ -i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); - -/** - * \brief Abort data transmission - * - * \param[in] device The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); - -/** - * \brief Enable/disable I2C slave interrupt - * - * param[in] device The pointer to I2C slave device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] disable Enable or disable - */ -int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, - const bool disable); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_i2c_s_sync.h b/watch-library/hal/include/hpl_i2c_s_sync.h deleted file mode 100644 index 93b59345..00000000 --- a/watch-library/hal/include/hpl_i2c_s_sync.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - * \file - * - * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_S_SYNC_H_INCLUDED -#define _HPL_I2C_S_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief I2C Slave status type - */ -typedef uint32_t i2c_s_status_t; - -/** - * \brief i2c slave device structure - */ -struct _i2c_s_sync_device { - void *hw; -}; - -#include - -/** - * \name HPL functions - */ - -/** - * \brief Initialize synchronous I2C slave - * - * This function does low level I2C configuration. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize synchronous I2C slave - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); - -/** - * \brief Check if 10-bit addressing mode is on - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Cheking status - * \retval 1 10-bit addressing mode is on - * \retval 0 10-bit addressing mode is off - */ -int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); - -/** - * \brief Set I2C slave address - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] address Address to set - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); - -/** - * \brief Write a byte to the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] data Data to write - */ -void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); - -/** - * \brief Retrieve I2C slave status - * - * \param[in] device The pointer to i2c slave device structure - * - *\return I2C slave status - */ -i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); - -/** - * \brief Clear the Data Ready interrupt flag - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); - -/** - * \brief Read a byte from the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Data received via I2C interface. - */ -uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); - -/** - * \brief Check if I2C is ready to send next byte - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Status of the ready check. - * \retval true if the I2C is ready to send next byte - * \retval false if the I2C is not ready to send next byte - */ -bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); - -/** - * \brief Check if there is data received by I2C - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Status of the data received check. - * \retval true if the I2C has received a byte - * \retval false if the I2C has not received a byte - */ -bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_init.h b/watch-library/hal/include/hpl_init.h deleted file mode 100644 index 71bf49c9..00000000 --- a/watch-library/hal/include/hpl_init.h +++ /dev/null @@ -1,124 +0,0 @@ -/** - * \file - * - * \brief Init related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_INIT_H_INCLUDED -#define _HPL_INIT_H_INCLUDED - -/** - * \addtogroup HPL Init - * - * \section hpl_init_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initializes clock sources - */ -void _sysctrl_init_sources(void); - -/** - * \brief Initializes Power Manager - */ -void _pm_init(void); - -/** - * \brief Initialize generators - */ -void _gclk_init_generators(void); - -/** - * \brief Initialize 32 kHz clock sources - */ -void _osc32kctrl_init_sources(void); - -/** - * \brief Initialize clock sources - */ -void _oscctrl_init_sources(void); - -/** - * \brief Initialize clock sources that need input reference clocks - */ -void _sysctrl_init_referenced_generators(void); - -/** - * \brief Initialize clock sources that need input reference clocks - */ -void _oscctrl_init_referenced_generators(void); - -/** - * \brief Initialize master clock generator - */ -void _mclk_init(void); - -/** - * \brief Initialize clock generator - */ -void _lpmcu_misc_regs_init(void); - -/** - * \brief Initialize clock generator - */ -void _pmc_init(void); - -/** - * \brief Set performance level - * - * \param[in] level The performance level to set - */ -void _set_performance_level(const uint8_t level); - -/** - * \brief Initialize the chip - */ -void _init_chip(void); - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_irq.h b/watch-library/hal/include/hpl_irq.h deleted file mode 100644 index 2894944a..00000000 --- a/watch-library/hal/include/hpl_irq.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - * \file - * - * \brief IRQ related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_IRQ_H_INCLUDED -#define _HPL_IRQ_H_INCLUDED - -/** - * \addtogroup HPL IRQ - * - * \section hpl_irq_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief IRQ descriptor - */ -struct _irq_descriptor { - void (*handler)(void *parameter); - void *parameter; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Retrieve current IRQ number - * - * \return The current IRQ number - */ -uint8_t _irq_get_current(void); - -/** - * \brief Disable the given IRQ - * - * \param[in] n The number of IRQ to disable - */ -void _irq_disable(uint8_t n); - -/** - * \brief Set the given IRQ - * - * \param[in] n The number of IRQ to set - */ -void _irq_set(uint8_t n); - -/** - * \brief Clear the given IRQ - * - * \param[in] n The number of IRQ to clear - */ -void _irq_clear(uint8_t n); - -/** - * \brief Enable the given IRQ - * - * \param[in] n The number of IRQ to enable - */ -void _irq_enable(uint8_t n); - -/** - * \brief Register IRQ handler - * - * \param[in] number The number registered IRQ - * \param[in] irq The pointer to irq handler to register - * - * \return The status of IRQ handler registering - * \retval -1 Passed parameters were invalid - * \retval 0 The registering is completed successfully - */ -void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_missing_features.h b/watch-library/hal/include/hpl_missing_features.h deleted file mode 100644 index 7071db29..00000000 --- a/watch-library/hal/include/hpl_missing_features.h +++ /dev/null @@ -1,37 +0,0 @@ -/** - * \file - * - * \brief Family-dependent missing features expected by HAL - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_MISSING_FEATURES -#define _HPL_MISSING_FEATURES - -#endif /* _HPL_MISSING_FEATURES */ diff --git a/watch-library/hal/include/hpl_rand_sync.h b/watch-library/hal/include/hpl_rand_sync.h deleted file mode 100755 index 5fdf1340..00000000 --- a/watch-library/hal/include/hpl_rand_sync.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * \file - * - * \brief Random Number Generator (RAND) related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_RAND_SYNC_H_INCLUDED -#define _HPL_RAND_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** Random Number Generator polling device. */ -struct _rand_sync_dev { - /** Pointer to private data or hardware base */ - void *prvt; - /** Number of bits generated for each read operation */ - uint8_t n_bits; -}; - -/** - * \brief Initialize the Random Number Generator Driver - * \param[out] dev Pointer to the device instance struct - * \param[in, out] hw Pointer to the hardware for device instance - * \return Initialization operation result status, 0 for OK. - */ -int32_t _rand_sync_init(struct _rand_sync_dev *const dev, void *const hw); - -/** - * \brief Deinitialize the Random Number Generator Driver - * \param[in, out] dev Pointer to the device instance struct - */ -void _rand_sync_deinit(struct _rand_sync_dev *const dev); - -/** - * \brief Enable the Random Number Generator Driver - * \param[out] dev Pointer to the device instance struct - * \return Enable operation result status, 0 for OK. - */ -int32_t _rand_sync_enable(struct _rand_sync_dev *const dev); - -/** - * \brief Disable the Random Number Generator Driver - * \param[out] dev Pointer to the device instance struct - */ -void _rand_sync_disable(struct _rand_sync_dev *const dev); - -/** - * \brief Set seed for the Random Number Generator Driver - * \param[out] dev Pointer to the device instance struct - * \param[in] seed The seed to set - * \return Operation result - * \retval ERR_NONE Operation complete success - * \retval ERR_UNSUPPORTED_OP Seed not supported - */ -int32_t _rand_sync_set_seed(struct _rand_sync_dev *const dev, const uint32_t seed); - -/** - * \brief Polling random number until it's read back - * \param[in] dev Pointer to the device instance struct - * \return The random number value - */ -uint32_t _rand_sync_read_one(const struct _rand_sync_dev *const dev); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_RAND_SYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_reset.h b/watch-library/hal/include/hpl_reset.h deleted file mode 100644 index 75738b6f..00000000 --- a/watch-library/hal/include/hpl_reset.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - * \file - * - * \brief Reset related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_RESET_H_INCLUDED -#define _HPL_RESET_H_INCLUDED - -/** - * \addtogroup HPL Reset - * - * \section hpl_reset_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Reset reason enumeration - * - * The list of possible reset reasons. - */ -enum reset_reason { - RESET_REASON_POR = 1, - RESET_REASON_BOD12 = 2, - RESET_REASON_BOD33 = 4, - RESET_REASON_EXT = 16, - RESET_REASON_WDT = 32, - RESET_REASON_SYST = 64, - RESET_REASON_BACKUP = 128 -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Retrieve the reset reason - * - * Retrieves the reset reason of the last MCU reset. - * - *\return An enum value indicating the reason of the last reset. - */ -enum reset_reason _get_reset_reason(void); - -/** - * \brief Reset MCU - */ -void _reset_mcu(void); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_slcd.h b/watch-library/hal/include/hpl_slcd.h deleted file mode 100644 index f3ccbbcd..00000000 --- a/watch-library/hal/include/hpl_slcd.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * \file - * - * \brief SLCD common declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef HPL_SLCD_H_INCLUDED -#define HPL_SLCD_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#define SLCD_SEGID(com, seg) (((com) << 16) | (seg)) -#define SLCD_COMNUM(segid) (((segid) >> 16) & 0xFF) -#define SLCD_SEGNUM(segid) ((segid)&0xFF) - -#ifdef __cplusplus -} -#endif - -#endif /* HPL_SLCD_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_slcd_sync.h b/watch-library/hal/include/hpl_slcd_sync.h deleted file mode 100644 index 2f5a05d7..00000000 --- a/watch-library/hal/include/hpl_slcd_sync.h +++ /dev/null @@ -1,154 +0,0 @@ -/** - * \file - * - * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality - * declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef HPL_SLCD_SYNC_H_INCLUDED -#define HPL_SLCD_SYNC_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief SLCD sync device structure - * - * The SLCD device structure forward declaration. - */ -struct _slcd_sync_device; - -struct _slcd_sync_device { - void *hw; /*!< Hardware module instance handler */ -}; - -/** - * \brief Initialize SLCD Device Descriptor - * - * \param[in] desc SLCD descriptor to be initialized - * \param[in] hw The pointer to hardware instance - */ -int32_t _slcd_sync_init(struct _slcd_sync_device *const dev, void *const hw); - -/** - * \brief Deinitialize SLCD Device Descriptor - * - * \param[in] desc SLCD device descriptor to be deinitialized - */ -int32_t _slcd_sync_deinit(struct _slcd_sync_device *const dev); - -/** - * \brief Enable SLCD driver - * - * \param[in] dev SLCD device descriptor to be enabled - */ -int32_t _slcd_sync_enable(struct _slcd_sync_device *const dev); - -/** - * \brief Disable SLCD driver - * - * \param[in] dev SLCD Device descriptor to be disabled - */ -int32_t _slcd_sync_disable(struct _slcd_sync_device *const dev); - -/** - * \brief Turn on a Segment - * - * \param[in] dev SLCD Device descriptor - * \param[in] seg Segment id - * value is (common terminals << 16 | segment terminal) - */ -int32_t _slcd_sync_seg_on(struct _slcd_sync_device *const dev, uint32_t seg); - -/** - * \brief Turn off a Segment - * - * \param[in] dev SLCD Device descriptor - * \param[in] seg Segment id - * value is (common terminals << 16 | segment terminal) - */ -int32_t _slcd_sync_seg_off(struct _slcd_sync_device *const dev, uint32_t seg); - -/** - * \brief Blink a Segment - * - * \param[in] dev SLCD Device descriptor - * \param[in] seg Segment index - * value is (common terminals << 16 | segment terminal) - * \param[in] period Blink period, unit is million second - */ -int32_t _slcd_sync_seg_blink(struct _slcd_sync_device *const dev, uint32_t seg, const uint32_t period); - -/** - * \brief Displays a character - * - * \param[in] dev SLCD Device descriptor - * \param[in] character Character to be displayed - * \param[in] index Index of Character Mapping Group - */ -int32_t _slcd_sync_write_char(struct _slcd_sync_device *const dev, const uint8_t character, uint32_t index); - -/** - * \brief Start animation play by a segment array - * - * \param[in] dev SLCD Device descriptor - * \param[in] segs Segment array - * \param[in] len Length of the segment array - * \param[in] period Period(milliseconds) of the each segment to animation - */ -int32_t _slcd_sync_start_animation(struct _slcd_sync_device *const dev, const uint32_t segs[], uint32_t len, - const uint32_t period); - -/** - * \brief Stop animation play by a segment array - * - * \param[in] dev SLCD device descriptor - * \param[in] segs Segment array - * \param[in] len Length of the segment array - */ -int32_t _slcd_sync_stop_animation(struct _slcd_sync_device *const dev, const uint32_t segs[], uint32_t len); - -/** - * \brief Set animation Frequency - * - * \param[in] dev SLCD Device descriptor - * \param[in] period Period(million second) of the each segment to animation - */ -int32_t _slcd_sync_set_animation_period(struct _slcd_sync_device *const dev, const uint32_t period); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/watch-library/hal/include/hpl_sleep.h b/watch-library/hal/include/hpl_sleep.h deleted file mode 100644 index 6731ec30..00000000 --- a/watch-library/hal/include/hpl_sleep.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SLEEP_H_INCLUDED -#define _HPL_SLEEP_H_INCLUDED - -/** - * \addtogroup HPL Sleep - * - * \section hpl_sleep_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Set the sleep mode for the device - * - * This function sets the sleep mode for the device. - * For an overview of which systems are disabled in sleep for the different - * sleep modes see datasheet. - * - * \param[in] mode Sleep mode to use - * - * \return the status of a sleep request - * \retval -1 The requested sleep mode was invalid - * \retval 0 The operation completed successfully, sleep mode is set - */ -int32_t _set_sleep_mode(const uint8_t mode); - -/** - * \brief Reset MCU - */ -void _reset_mcu(void); - -/** - * \brief Put MCU to sleep - */ -void _go_to_sleep(void); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_spi.h b/watch-library/hal/include/hpl_spi.h deleted file mode 100644 index a5652e50..00000000 --- a/watch-library/hal/include/hpl_spi.h +++ /dev/null @@ -1,163 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_H_INCLUDED -#define _HPL_SPI_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief SPI Dummy char is used when reading data from the SPI slave - */ -#define SPI_DUMMY_CHAR 0x1ff - -/** - * \brief SPI message to let driver to process - */ -//@{ -struct spi_msg { - /** Pointer to the output data buffer */ - uint8_t *txbuf; - /** Pointer to the input data buffer */ - uint8_t *rxbuf; - /** Size of the message data in SPI characters */ - uint32_t size; -}; -//@} - -/** - * \brief SPI transfer modes - * SPI transfer mode controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - */ -enum spi_transfer_mode { - /** Leading edge is rising edge, data sample on leading edge. */ - SPI_MODE_0, - /** Leading edge is rising edge, data sample on trailing edge. */ - SPI_MODE_1, - /** Leading edge is falling edge, data sample on leading edge. */ - SPI_MODE_2, - /** Leading edge is falling edge, data sample on trailing edge. */ - SPI_MODE_3 -}; - -/** - * \brief SPI character sizes - * The character size influence the way the data is sent/received. - * For char size <= 8 data is stored byte by byte. - * For char size between 9 ~ 16 data is stored in 2-byte length. - * Note that the default and recommended char size is 8 bit since it's - * supported by all system. - */ -enum spi_char_size { - /** Character size is 8 bit. */ - SPI_CHAR_SIZE_8 = 0, - /** Character size is 9 bit. */ - SPI_CHAR_SIZE_9 = 1, - /** Character size is 10 bit. */ - SPI_CHAR_SIZE_10 = 2, - /** Character size is 11 bit. */ - SPI_CHAR_SIZE_11 = 3, - /** Character size is 12 bit. */ - SPI_CHAR_SIZE_12 = 4, - /** Character size is 13 bit. */ - SPI_CHAR_SIZE_13 = 5, - /** Character size is 14 bit. */ - SPI_CHAR_SIZE_14 = 6, - /** Character size is 15 bit. */ - SPI_CHAR_SIZE_15 = 7, - /** Character size is 16 bit. */ - SPI_CHAR_SIZE_16 = 8 -}; - -/** - * \brief SPI data order - */ -enum spi_data_order { - /** MSB goes first. */ - SPI_DATA_ORDER_MSB_1ST = 0, - /** LSB goes first. */ - SPI_DATA_ORDER_LSB_1ST = 1 -}; - -/** \brief Transfer descriptor for SPI - * Transfer descriptor holds TX and RX buffers - */ -struct spi_xfer { - /** Pointer to data buffer to TX */ - uint8_t *txbuf; - /** Pointer to data buffer to RX */ - uint8_t *rxbuf; - /** Size of data characters to TX & RX */ - uint32_t size; -}; - -/** SPI generic driver. */ -struct spi_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Reference start of sync/async variables */ - uint32_t sync_async_misc[1]; -}; - -/** - * \brief Calculate the baudrate value for hardware to use to set baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] clk Clock frequency (Hz) for baudrate generation. - * \param[in] baud Target baudrate (bps). - * \return Error or baudrate value. - * \retval >0 Baudrate value. - * \retval ERR_INVALID_ARG Calculation fail. - */ -int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_spi_async.h b/watch-library/hal/include/hpl_spi_async.h deleted file mode 100644 index 8e5a8485..00000000 --- a/watch-library/hal/include/hpl_spi_async.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * \file - * - * \brief Common SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_ASYNC_H_INCLUDED -#define _HPL_SPI_ASYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Callbacks the SPI driver must offer in async mode - */ -//@{ -/** The callback types */ -enum _spi_async_dev_cb_type { - /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ - SPI_DEV_CB_TX, - /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ - SPI_DEV_CB_RX, - /** Callback type for \ref _spi_async_dev_cb_complete_t. */ - SPI_DEV_CB_COMPLETE, - /** Callback type for error */ - SPI_DEV_CB_ERROR, - /** Number of callbacks. */ - SPI_DEV_CB_N -}; - -struct _spi_async_dev; - -/** \brief The prototype for callback on SPI transfer error. - * If status code is zero, it indicates the normal completion, that is, - * SS deactivation. - * If status code belows zero, it indicates complete. - */ -typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); - -/** \brief The prototype for callback on SPI transmit/receive event - * For TX, the callback is invoked when transmit is done or ready to start - * transmit. - * For RX, the callback is invoked when receive is done or ready to read data, - * see \ref _spi_async_dev_read_one_t on data reading. - * Without DMA enabled, the callback is invoked on each character event. - * With DMA enabled, the callback is invoked on DMA buffer done. - */ -typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); - -/** - * \brief The callbacks offered by SPI driver - */ -struct _spi_async_dev_callbacks { - /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ - _spi_async_dev_cb_xfer_t tx; - /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ - _spi_async_dev_cb_xfer_t rx; - /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ - _spi_async_dev_cb_xfer_t complete; - /** Error callback, see \ref */ - _spi_async_dev_cb_error_t err; -}; -//@} - -/** - * \brief SPI async driver - */ -//@{ - -/** SPI driver to support async HAL */ -struct _spi_async_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Data size, number of bytes for each character */ - uint8_t char_size; - /** Dummy byte used in master mode when reading the slave */ - uint16_t dummy_byte; - - /** \brief Pointer to callback functions, ignored for polling mode - * Pointer to the callback functions so that initialize the driver to - * handle interrupts. - */ - struct _spi_async_dev_callbacks callbacks; - /** IRQ instance for SPI device. */ - struct _irq_descriptor irq; -}; -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_spi_dma.h b/watch-library/hal/include/hpl_spi_dma.h deleted file mode 100755 index 04a30158..00000000 --- a/watch-library/hal/include/hpl_spi_dma.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \file - * - * \brief Common SPI DMA related functionality declaration. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_DMA_H_INCLUDED -#define _HPL_SPI_DMA_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** The callback types */ -enum _spi_dma_dev_cb_type { - /** Callback type for DMA transmit. */ - SPI_DEV_CB_DMA_TX, - /** Callback type for DMA receive. */ - SPI_DEV_CB_DMA_RX, - /** Callback type for DMA error. */ - SPI_DEV_CB_DMA_ERROR, - /** Number of callbacks. */ - SPI_DEV_CB_DMA_N -}; - -struct _spi_dma_dev; - -/** - * \brief The prototype for callback on SPI DMA. - */ -typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource); - -/** - * \brief The callbacks offered by SPI driver - */ -struct _spi_dma_dev_callbacks { - _spi_dma_cb_t tx; - _spi_dma_cb_t rx; - _spi_dma_cb_t error; -}; - -/** SPI driver to support DMA HAL */ -struct _spi_dma_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Pointer to callback functions */ - struct _spi_dma_dev_callbacks callbacks; - /** IRQ instance for SPI device. */ - struct _irq_descriptor irq; - /** DMA resource */ - struct _dma_resource *resource; -}; - -#ifdef __cplusplus -} -#endif - -#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_spi_m_async.h b/watch-library/hal/include/hpl_spi_m_async.h deleted file mode 100644 index 8d3555ed..00000000 --- a/watch-library/hal/include/hpl_spi_m_async.h +++ /dev/null @@ -1,243 +0,0 @@ -/** - * \file - * - * \brief SPI Slave Async related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED -#define _HPL_SPI_M_ASYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_m_async_dev _spi_async_dev - -#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type - -/** Uses common SPI async device driver complete callback type. */ -#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t - -/** Uses common SPI async device driver transfer callback type. */ -#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on after data transmission complate - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); - -/** - * \brief Register the SPI device callback - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, - const FUNC_PTR func); - -/** - * \brief Enable/disable SPI master interrupt - * - * param[in] device The pointer to SPI master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, - const bool state); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_spi_m_dma.h b/watch-library/hal/include/hpl_spi_m_dma.h deleted file mode 100644 index 2b48300e..00000000 --- a/watch-library/hal/include/hpl_spi_m_dma.h +++ /dev/null @@ -1,182 +0,0 @@ -/** - * \file - * - * \brief SPI Master DMA related functionality declaration. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_DMA_H_INCLUDED -#define _HPL_SPI_M_DMA_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI dma device driver. */ -#define _spi_m_dma_dev _spi_dma_dev - -#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); - -/** - * \brief Register the SPI device callback - * \param[in] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); - -/** \brief Do SPI data transfer (TX & RX) with DMA - * Log the TX & RX buffers and transfer them in background. It never blocks. - * - * \param[in] dev Pointer to the SPI device instance. - * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). - * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). - * \param[in] length spi transfer data length. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy. - */ -int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, - const uint16_t length); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_spi_m_sync.h b/watch-library/hal/include/hpl_spi_m_sync.h deleted file mode 100644 index 38df15b4..00000000 --- a/watch-library/hal/include/hpl_spi_m_sync.h +++ /dev/null @@ -1,166 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_SYNC_H_INCLUDED -#define _HPL_SPI_M_SYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI sync device driver. */ -#define _spi_m_sync_dev _spi_sync_dev - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); - -/** - * \brief Deinitialize SPI - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); - -/** - * \brief Enable SPI for access without interrupts - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI char size - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); - -/** - * \brief Transfer the whole message without interrupt - * Transfer the message, it will keep waiting until the message finish or - * error. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] msg Pointer to the message instance to process. - * \return Error or number of characters transferred. - * \retval ERR_BUSY SPI hardware is not ready to start transfer (not - * enabled, busy applying settings, ...). - * \retval SPI_ERR_OVERFLOW Overflow error. - * \retval >=0 Number of characters transferred. - */ -int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_spi_s_async.h b/watch-library/hal/include/hpl_spi_s_async.h deleted file mode 100644 index 56472439..00000000 --- a/watch-library/hal/include/hpl_spi_s_async.h +++ /dev/null @@ -1,232 +0,0 @@ -/** - * \file - * - * \brief SPI Slave Async related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED -#define _HPL_SPI_S_ASYNC_H_INCLUDED - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_s_async_dev _spi_async_dev - -#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type - -/** Uses common SPI async device driver complete callback type. */ -#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t - -/** Uses common SPI async device driver transfer callback type. */ -#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on Slave Select (SS) rising - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); - -/** - * \brief Register the SPI device callback - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, - const FUNC_PTR func); - -/** - * \brief Enable/disable SPI slave interrupt - * - * param[in] device The pointer to SPI slave device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, - const bool state); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_spi_s_sync.h b/watch-library/hal/include/hpl_spi_s_sync.h deleted file mode 100644 index ff4c811a..00000000 --- a/watch-library/hal/include/hpl_spi_s_sync.h +++ /dev/null @@ -1,232 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_S_SYNC_H_INCLUDED -#define _HPL_SPI_S_SYNC_H_INCLUDED - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI sync device driver. */ -#define _spi_s_sync_dev _spi_sync_dev - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); - -/** - * \brief Enable SPI for access without interrupts - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retval 0 OK Status - */ -int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); - -/** - * \brief Check if TX ready - * - * \param[in] dev Pointer to the SPI device instance - * - * \return TX ready state - * \retval true TX ready - * \retval false TX not ready - */ -bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if RX character ready - * - * \param[in] dev Pointer to the SPI device instance - * - * \return RX character ready state - * \retval true RX character ready - * \retval false RX character not ready - */ -bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if SS deactiviation detected - * - * \param[in] dev Pointer to the SPI device instance - * - * \return SS deactiviation state - * \retval true SS deactiviation detected - * \retval false SS deactiviation not detected - */ -bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if error is detected - * - * \param[in] dev Pointer to the SPI device instance - * - * \return Error detection state - * \retval true Error detected - * \retval false Error not detected - */ -bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_spi_sync.h b/watch-library/hal/include/hpl_spi_sync.h deleted file mode 100644 index dc88648f..00000000 --- a/watch-library/hal/include/hpl_spi_sync.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * \file - * - * \brief Common SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_SYNC_H_INCLUDED -#define _HPL_SPI_SYNC_H_INCLUDED - -#include -#include - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * \section hpl_spi_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** SPI driver to support sync HAL */ -struct _spi_sync_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Data size, number of bytes for each character */ - uint8_t char_size; - /** Dummy byte used in master mode when reading the slave */ - uint16_t dummy_byte; -}; - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_time_measure.h b/watch-library/hal/include/hpl_time_measure.h deleted file mode 100644 index 5d688df5..00000000 --- a/watch-library/hal/include/hpl_time_measure.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - * \file - * - * \brief Time measure related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_TIME_MEASURE_H_INCLUDED -#define _HPL_TIME_MEASURE_H_INCLUDED - -/** - * \addtogroup HPL Time measure - * - * \section hpl_time_measure_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief System time type - */ -typedef uint32_t system_time_t; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize system time module - * - * \param[in] hw The pointer to hardware instance to initialize - */ -void _system_time_init(void *const hw); - -/** - * \brief Deinitialize system time module - * - * \param[in] hw The pointer to hardware instance to initialize - */ -void _system_time_deinit(void *const hw); - -/** - * \brief Get system time - * - * \param[in] hw The pointer to hardware instance to initialize - */ -system_time_t _system_time_get(const void *const hw); - -/** - * \brief Get maximum possible system time - * - * \param[in] hw The pointer to hardware instance to initialize - */ -system_time_t _system_time_get_max_time_value(const void *const hw); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_TIME_MEASURE_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_timer.h b/watch-library/hal/include/hpl_timer.h deleted file mode 100644 index 9bdfbb77..00000000 --- a/watch-library/hal/include/hpl_timer.h +++ /dev/null @@ -1,160 +0,0 @@ -/** - * \file - * - * \brief Timer related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_TIMER_H_INCLUDED -#define _HPL_TIMER_H_INCLUDED - -/** - * \addtogroup HPL Timer - * - * \section hpl_timer_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Timer device structure - * - * The Timer device structure forward declaration. - */ -struct _timer_device; - -/** - * \brief Timer interrupt callbacks - */ -struct _timer_callbacks { - void (*period_expired)(struct _timer_device *device); -}; - -/** - * \brief Timer device structure - */ -struct _timer_device { - struct _timer_callbacks timer_cb; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \brief Timer functions, pointers to low-level functions - */ -struct _timer_hpl_interface { - int32_t (*init)(struct _timer_device *const device, void *const hw); - void (*deinit)(struct _timer_device *const device); - void (*start_timer)(struct _timer_device *const device); - void (*stop_timer)(struct _timer_device *const device); - void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); - uint32_t (*get_period)(const struct _timer_device *const device); - bool (*is_timer_started)(const struct _timer_device *const device); - void (*set_timer_irq)(struct _timer_device *const device); -}; -/** - * \brief Initialize TCC - * - * This function does low level TCC configuration. - * - * \param[in] device The pointer to timer device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - */ -int32_t _timer_init(struct _timer_device *const device, void *const hw); - -/** - * \brief Deinitialize TCC - * - * \param[in] device The pointer to timer device instance - */ -void _timer_deinit(struct _timer_device *const device); - -/** - * \brief Start hardware timer - * - * \param[in] device The pointer to timer device instance - */ -void _timer_start(struct _timer_device *const device); - -/** - * \brief Stop hardware timer - * - * \param[in] device The pointer to timer device instance - */ -void _timer_stop(struct _timer_device *const device); - -/** - * \brief Set timer period - * - * \param[in] device The pointer to timer device instance - */ -void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); - -/** - * \brief Retrieve timer period - * - * \param[in] device The pointer to timer device instance - * - * \return Timer period - */ -uint32_t _timer_get_period(const struct _timer_device *const device); - -/** - * \brief Check if timer is running - * - * \param[in] device The pointer to timer device instance - * - * \return Check status. - * \retval true The given timer is running - * \retval false The given timer is not running - */ -bool _timer_is_started(const struct _timer_device *const device); - -/** - * \brief Set timer IRQ - * - * \param[in] device The pointer to timer device instance - */ -void _timer_set_irq(struct _timer_device *const device); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_usart.h b/watch-library/hal/include/hpl_usart.h deleted file mode 100644 index 0e09501d..00000000 --- a/watch-library/hal/include/hpl_usart.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USART_H_INCLUDED -#define _HPL_USART_H_INCLUDED - -/** - * \addtogroup HPL USART SYNC - * - * \section hpl_usart_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART flow control state - */ -union usart_flow_control_state { - struct { - uint8_t cts : 1; - uint8_t rts : 1; - uint8_t unavailable : 1; - uint8_t reserved : 5; - } bit; - uint8_t value; -}; - -/** - * \brief USART baud rate mode - */ -enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; - -/** - * \brief USART data order - */ -enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; - -/** - * \brief USART mode - */ -enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; - -/** - * \brief USART parity - */ -enum usart_parity { - USART_PARITY_EVEN = 0, - USART_PARITY_ODD = 1, - USART_PARITY_NONE = 2, - USART_PARITY_SPACE = 3, - USART_PARITY_MARK = 4 -}; - -/** - * \brief USART stop bits mode - */ -enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; - -/** - * \brief USART character size - */ -enum usart_character_size { - USART_CHARACTER_SIZE_8BITS = 0, - USART_CHARACTER_SIZE_9BITS = 1, - USART_CHARACTER_SIZE_5BITS = 5, - USART_CHARACTER_SIZE_6BITS = 6, - USART_CHARACTER_SIZE_7BITS = 7 -}; - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_usart_async.h b/watch-library/hal/include/hpl_usart_async.h deleted file mode 100644 index 3f833d1a..00000000 --- a/watch-library/hal/include/hpl_usart_async.h +++ /dev/null @@ -1,270 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USART_ASYNC_H_INCLUDED -#define _HPL_USART_ASYNC_H_INCLUDED - -/** - * \addtogroup HPL USART - * - * \section hpl_usart_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_usart.h" -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART callback types - */ -enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; - -/** - * \brief USART device structure - * - * The USART device structure forward declaration. - */ -struct _usart_async_device; - -/** - * \brief USART interrupt callbacks - */ -struct _usart_async_callbacks { - void (*tx_byte_sent)(struct _usart_async_device *device); - void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); - void (*tx_done_cb)(struct _usart_async_device *device); - void (*error_cb)(struct _usart_async_device *device); -}; - -/** - * \brief USART descriptor device structure - */ -struct _usart_async_device { - struct _usart_async_callbacks usart_cb; - struct _irq_descriptor irq; - void * hw; -}; -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize asynchronous USART - * - * This function does low level USART configuration. - * - * \param[in] device The pointer to USART device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); - -/** - * \brief Deinitialize USART - * - * This function closes the given USART by disabling its clock. - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_deinit(struct _usart_async_device *const device); - -/** - * \brief Enable usart module - * - * This function will enable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable(struct _usart_async_device *const device); - -/** - * \brief Disable usart module - * - * This function will disable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_disable(struct _usart_async_device *const device); - -/** - * \brief Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); - -/** - * \brief Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); - -/** - * \brief Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); - -/** - * \brief Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); - -/** - * \brief Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); - -/** - * \brief Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); - -/** - * \brief Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); - -/** - * \brief Retrieve usart status - * - * \param[in] device The pointer to USART device instance - */ -uint32_t _usart_async_get_status(const struct _usart_async_device *const device); - -/** - * \brief Write a byte to the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - */ -void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); - -/** - * \brief Check if USART is ready to send next byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART is ready to send next byte - * \retval false if the USART is not ready to send next byte - */ -bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); - -/** - * \brief Set the state of flow control pins - * - * \param[in] device The pointer to USART device instance - * \param[in] state - A state of flow control pins to set - */ -void _usart_async_set_flow_control_state(struct _usart_async_device *const device, - const union usart_flow_control_state state); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins. - * - * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. - */ -union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); - -/** - * \brief Enable data register empty interrupt - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); - -/** - * \brief Enable transmission complete interrupt - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); - -/** - * \brief Retrieve ordinal number of the given USART hardware instance - * - * \param[in] device The pointer to USART device instance - * - * \return The ordinal number of the given USART hardware instance - */ -uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); - -/** - * \brief Enable/disable USART interrupt - * - * param[in] device The pointer to USART device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, - const bool state); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_usart_sync.h b/watch-library/hal/include/hpl_usart_sync.h deleted file mode 100644 index abc7264f..00000000 --- a/watch-library/hal/include/hpl_usart_sync.h +++ /dev/null @@ -1,254 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SYNC_USART_H_INCLUDED -#define _HPL_SYNC_USART_H_INCLUDED - -/** - * \addtogroup HPL USART SYNC - * - * \section hpl_usart_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART descriptor device structure - */ -struct _usart_sync_device { - void *hw; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize synchronous USART - * - * This function does low level USART configuration. - * - * \param[in] device The pointer to USART device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize USART - * - * This function closes the given USART by disabling its clock. - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_deinit(struct _usart_sync_device *const device); - -/** - * \brief Enable usart module - * - * This function will enable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_enable(struct _usart_sync_device *const device); - -/** - * \brief Disable usart module - * - * This function will disable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_disable(struct _usart_sync_device *const device); - -/** - * \brief Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); - -/** - * \brief Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); - -/** - * \brief Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); - -/** - * \brief Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); - -/** - * \brief Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); - -/** - * \brief Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); - -/** - * \brief Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); - -/** - * \brief Retrieve usart status - * - * \param[in] device The pointer to USART device instance - */ -uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); - -/** - * \brief Write a byte to the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - */ -void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); - -/** - * \brief Read a byte from the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - * - * \return Data received via USART interface. - */ -uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); - -/** - * \brief Check if USART is ready to send next byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART is ready to send next byte - * \retval false if the USART is not ready to send next byte - */ -bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); - -/** - * \brief Check if USART transmitter has sent the byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART transmitter has sent the byte - * \retval false if the USART transmitter has not send the byte - */ -bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); - -/** - * \brief Check if there is data received by USART - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the data received check. - * \retval true if the USART has received a byte - * \retval false if the USART has not received a byte - */ -bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); - -/** - * \brief Set the state of flow control pins - * - * \param[in] device The pointer to USART device instance - * \param[in] state - A state of flow control pins to set - */ -void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, - const union usart_flow_control_state state); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins. - * - * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. - */ -union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); - -/** - * \brief Retrieve ordinal number of the given USART hardware instance - * - * \param[in] device The pointer to USART device instance - * - * \return The ordinal number of the given USART hardware instance - */ -uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/watch-library/hal/include/hpl_user_area.h b/watch-library/hal/include/hpl_user_area.h deleted file mode 100755 index 1f14098d..00000000 --- a/watch-library/hal/include/hpl_user_area.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * \file - * - * \brief Special user data area access - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USER_DATA_H_INCLUDED -#define _HPL_USER_DATA_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Read data from user data area - * - * The user data area could be the area that stores user data that is not erased - * with the flash contents, e.g., - * - NVM Software Calibration Area of SAM D/L/C family - * - User Signature of SAM E/S/V 70 - * - * \param[in] base The base address of the user area - * \param[in] offset The byte offset of the data to be read inside the area - * \param[out] buf Pointer to buffer to place the read data - * \param[in] size Size of data in number of bytes - * - * \return Operation status or bytes read. - * \retval ERR_NONE Data read successfully - * \retval ERR_UNSUPPORTED_OP base address not in any supported user area - * \retval ERR_BAD_ADDRESS offset not in right area - * \retval ERR_INVALID_ARG offset and size exceeds the right area - */ -int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, const uint32_t size); - -/** - * \brief Read no more than 32 bits data from user data area - * - * When reading bits, the bitfield can cross 32-bis boundaries. - * - * \param[in] base The base address of the user area - * \param[in] bit_offset Offset in number of bits - * \param[in] n_bits Number of bits to read - * \return data read, assert if anything wrong (address not in user area - * offset, size error, etc.). - */ -uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits); - -/** - * \brief Write data to user data area - * - * The user data area could be the area that stores user data that is not erased - * with the flash contents, e.g., - * - NVM Software Calibration Area of SAM D/L/C family - * - User Signature of SAM E/S/V 70 - * - * When assigned offset and size exceeds the data area, error is reported. - * - * \param[out] base The base address of the user area - * \param[in] offset The offset of the data to be written inside the area - * \param[in] buf Pointer to buffer to place the written data - * \param[in] size Size of data in number of bytes - * - * \return Operation status or bytes writting. - * \retval ERR_NONE Data written successfully - * \retval ERR_UNSUPPORTED_OP base address not in any supported user area - * \retval ERR_DENIED Security bit is set - * \retval ERR_BAD_ADDRESS offset not in right area - * \retval ERR_INVALID_ARG offset and size exceeds the right area - */ -int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size); - -/** - * \brief Write no more than 32 bits data to user data area - * - * When writting bits, the bitfield can cross 32-bis boundaries. - * - * \param[out] base The base address of the user area - * \param[in] bit_offset Offset in number of bits - * \param[in] bits The data content - * \param[in] n_bits Number of bits to write - * \return Operation result - * \retval ERR_NONE Data written successfully - * \retval ERR_UNSUPPORTED_OP base address not in any supported user area - * \retval ERR_DENIED Security bit is set - * \retval ERR_BAD_ADDRESS offset not in right area - * \retval ERR_INVALID_ARG offset and size exceeds the right area - */ -int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_USER_DATA_H_INCLUDED */ diff --git a/watch-library/hal/src/hal_atomic.c b/watch-library/hal/src/hal_atomic.c deleted file mode 100644 index f56418ee..00000000 --- a/watch-library/hal/src/hal_atomic.c +++ /dev/null @@ -1,66 +0,0 @@ -/** - * \file - * - * \brief Critical sections related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_atomic.h" - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Disable interrupts, enter critical section - */ -void atomic_enter_critical(hal_atomic_t volatile *atomic) -{ - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); -} - -/** - * \brief Exit atomic section - */ -void atomic_leave_critical(hal_atomic_t volatile *atomic) -{ - __DMB(); - __set_PRIMASK(*atomic); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t atomic_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/watch-library/hal/src/hal_calendar.c b/watch-library/hal/src/hal_calendar.c deleted file mode 100644 index e69de29b..00000000 diff --git a/watch-library/hal/src/hal_delay.c b/watch-library/hal/src/hal_delay.c deleted file mode 100644 index 6f77cc70..00000000 --- a/watch-library/hal/src/hal_delay.c +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * \brief HAL delay related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include "hal_delay.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief The pointer to a hardware instance used by the driver. - */ -static void *hardware; - -/** - * \brief Initialize Delay driver - */ -void delay_init(void *const hw) -{ - _delay_init(hardware = hw); -} - -/** - * \brief Perform delay in us - */ -void delay_us(const uint16_t us) -{ - _delay_cycles(hardware, _get_cycles_for_us(us)); -} - -/** - * \brief Perform delay in ms - */ -void delay_ms(const uint16_t ms) -{ - _delay_cycles(hardware, _get_cycles_for_ms(ms)); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t delay_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/watch-library/hal/src/hal_ext_irq.c b/watch-library/hal/src/hal_ext_irq.c deleted file mode 100644 index 2c383b4b..00000000 --- a/watch-library/hal/src/hal_ext_irq.c +++ /dev/null @@ -1,188 +0,0 @@ -/** - * \file - * - * \brief External interrupt functionality imkplementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_ext_irq.h" - -#define EXT_IRQ_AMOUNT 6 - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief External IRQ struct - */ -struct ext_irq { - ext_irq_cb_t cb; - uint32_t pin; -}; - -/* Remove KEIL compiling error in case no IRQ line selected */ -#if EXT_IRQ_AMOUNT == 0 -#undef EXT_IRQ_AMOUNT -#define EXT_IRQ_AMOUNT 1 -#endif - -/** - * \brief Array of external IRQs callbacks - */ -static struct ext_irq ext_irqs[EXT_IRQ_AMOUNT]; - -static void process_ext_irq(const uint32_t pin); - -/** - * \brief Initialize external irq component if any - */ -int32_t ext_irq_init(void) -{ - uint16_t i; - - for (i = 0; i < EXT_IRQ_AMOUNT; i++) { - ext_irqs[i].pin = 0xFFFFFFFF; - ext_irqs[i].cb = NULL; - } - - return _ext_irq_init(process_ext_irq); -} - -/** - * \brief Deinitialize external irq if any - */ -int32_t ext_irq_deinit(void) -{ - return _ext_irq_deinit(); -} - -/** - * \brief Register callback for the given external interrupt - */ -int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb) -{ - uint8_t i = 0, j = 0; - bool found = false; - - for (; i < EXT_IRQ_AMOUNT; i++) { - if (ext_irqs[i].pin == pin) { - ext_irqs[i].cb = cb; - found = true; - break; - } - } - - if (NULL == cb) { - if (!found) { - return ERR_INVALID_ARG; - } - return _ext_irq_enable(pin, false); - } - - if (!found) { - for (i = 0; i < EXT_IRQ_AMOUNT; i++) { - if (NULL == ext_irqs[i].cb) { - ext_irqs[i].cb = cb; - ext_irqs[i].pin = pin; - found = true; - break; - } - } - for (; (j < EXT_IRQ_AMOUNT) && (i < EXT_IRQ_AMOUNT); j++) { - if ((ext_irqs[i].pin < ext_irqs[j].pin) && (ext_irqs[j].pin != 0xFFFFFFFF)) { - struct ext_irq tmp = ext_irqs[j]; - - ext_irqs[j] = ext_irqs[i]; - ext_irqs[i] = tmp; - } - } - } - - if (!found) { - return ERR_INVALID_ARG; - } - - return _ext_irq_enable(pin, true); -} - -/** - * \brief Enable external irq - */ -int32_t ext_irq_enable(const uint32_t pin) -{ - return _ext_irq_enable(pin, true); -} - -/** - * \brief Disable external irq - */ -int32_t ext_irq_disable(const uint32_t pin) -{ - return _ext_irq_enable(pin, false); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t ext_irq_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \brief Interrupt processing routine - * - * \param[in] pin The pin which triggered the interrupt - */ -static void process_ext_irq(const uint32_t pin) -{ - uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; - - while (upper >= lower) { - middle = (upper + lower) >> 1; - if (middle >= EXT_IRQ_AMOUNT) { - return; - } - - if (ext_irqs[middle].pin == pin) { - if (ext_irqs[middle].cb) { - ext_irqs[middle].cb(); - } - return; - } - - if (ext_irqs[middle].pin < pin) { - lower = middle + 1; - } else { - upper = middle - 1; - } - } -} diff --git a/watch-library/hal/src/hal_flash.c b/watch-library/hal/src/hal_flash.c deleted file mode 100755 index b1a58b71..00000000 --- a/watch-library/hal/src/hal_flash.c +++ /dev/null @@ -1,314 +0,0 @@ -/** - * \file - * - * \brief Flash functionality implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_flash.h" -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -static void flash_ready(struct _flash_device *device); -static void flash_error(struct _flash_device *device); - -static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr); - -/** - * \brief Initialize the FLASH HAL instance and hardware for callback mode. - */ -int32_t flash_init(struct flash_descriptor *flash, void *const hw) -{ - int32_t rc; - - ASSERT(flash && hw); - - rc = _flash_init(&flash->dev, hw); - if (rc) { - return rc; - } - - flash->dev.flash_cb.ready_cb = flash_ready; - flash->dev.flash_cb.error_cb = flash_error; - - return ERR_NONE; -} - -/** - * \brief Deinitialize the FLASH HAL instance. - */ -int32_t flash_deinit(struct flash_descriptor *flash) -{ - ASSERT(flash); - - _flash_deinit(&flash->dev); - - return ERR_NONE; -} - -/** - * \brief Reads a number of bytes to a page in the internal Flash - */ -int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length) -{ - ASSERT(flash && buffer && length); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - - /* Check if the address is valid */ - if ((src_addr > page_size * total_pages) || (src_addr + length > page_size * total_pages)) { - return ERR_BAD_ADDRESS; - } - - _flash_read(&flash->dev, src_addr, buffer, length); - - return ERR_NONE; -} - -/** - * \brief Updates several bytes to the internal Flash - */ -int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) -{ - ASSERT(flash && buffer && length); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - - /* Check if the address is valid */ - if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { - return ERR_BAD_ADDRESS; - } - - if (_flash_is_locked(&flash->dev, dst_addr)) { - return ERR_DENIED; - } - - _flash_write(&flash->dev, dst_addr, buffer, length); - - return ERR_NONE; -} - -/** - * \brief Appends a number of bytes to a page in the internal Flash - */ -int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) -{ - ASSERT(flash && buffer && length); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - - /* Check if the address is valid */ - if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { - return ERR_BAD_ADDRESS; - } - - if (_flash_is_locked(&flash->dev, dst_addr)) { - return ERR_DENIED; - } - - _flash_append(&flash->dev, dst_addr, buffer, length); - - return ERR_NONE; -} - -/** - * \brief Execute erase in the internal flash - */ -int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) -{ - ASSERT(flash && page_nums); - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - int32_t rc; - - rc = flash_is_address_aligned(flash, dst_addr); - if (rc) { - return rc; - } - - if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { - return ERR_INVALID_ARG; - } - - _flash_erase(&flash->dev, dst_addr, page_nums); - - return ERR_NONE; -} - -/** - * \brief Register a function as FLASH transfer completion callback - */ -int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func) -{ - ASSERT(flash); - - switch (type) { - case FLASH_CB_READY: - flash->callbacks.cb_ready = func; - break; - - case FLASH_CB_ERROR: - flash->callbacks.cb_error = func; - break; - - default: - return ERR_INVALID_ARG; - } - - _flash_set_irq_state(&flash->dev, (enum _flash_cb_type)type, NULL != func); - - return ERR_NONE; -} - -/** - * \brief Execute lock in the internal flash - */ -int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) -{ - ASSERT(flash && page_nums); - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - int32_t rc; - - rc = flash_is_address_aligned(flash, dst_addr); - if (rc) { - return rc; - } - - if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { - return ERR_INVALID_ARG; - } - - return _flash_lock(&flash->dev, dst_addr, page_nums); -} - -/** - * \brief Execute unlock in the internal flash - */ -int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) -{ - ASSERT(flash && page_nums); - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - int32_t rc; - - rc = flash_is_address_aligned(flash, dst_addr); - if (rc) { - return rc; - } - - if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { - return ERR_INVALID_ARG; - } - - return _flash_unlock(&flash->dev, dst_addr, page_nums); -} - -/** - * \brief Get the flash page size. - */ -uint32_t flash_get_page_size(struct flash_descriptor *flash) -{ - ASSERT(flash); - return _flash_get_page_size(&flash->dev); -} - -/** - * \brief Get the numbers of flash page. - */ -uint32_t flash_get_total_pages(struct flash_descriptor *flash) -{ - ASSERT(flash); - return _flash_get_total_pages(&flash->dev); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t flash_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \internal check the address whether it is aligned - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] flash_addr address to be check in flash - * - * \return whether it is valid - * \retval 0 Valid. - * \retval -1 Error, invalid. - */ -static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr) -{ - ASSERT(flash); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - - /* Check if the read address not aligned to the start of a page */ - if (flash_addr & (page_size - 1)) { - return ERR_BAD_ADDRESS; - } - return ERR_NONE; -} - -/** - * \internal Ready for a new flash command - * - * \param[in] device The pointer to flash device structure - */ -static void flash_ready(struct _flash_device *device) -{ - struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); - if (descr->callbacks.cb_ready) { - descr->callbacks.cb_ready(descr); - } -} - -/** - * \internal Error occurs in flash command - * - * \param[in] device The pointer to flash device structure - */ -static void flash_error(struct _flash_device *device) -{ - struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); - if (descr->callbacks.cb_error) { - descr->callbacks.cb_error(descr); - } -} diff --git a/watch-library/hal/src/hal_gpio.c b/watch-library/hal/src/hal_gpio.c deleted file mode 100644 index 00dfea6f..00000000 --- a/watch-library/hal/src/hal_gpio.c +++ /dev/null @@ -1,44 +0,0 @@ -/** - * \file - * - * \brief Port - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_gpio.h" - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -uint32_t gpio_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/watch-library/hal/src/hal_i2c_m_sync.c b/watch-library/hal/src/hal_i2c_m_sync.c deleted file mode 100644 index 9be16be4..00000000 --- a/watch-library/hal/src/hal_i2c_m_sync.c +++ /dev/null @@ -1,258 +0,0 @@ -/** - * \file - * - * \brief I/O I2C related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Sync version of I2C I/O read - */ -static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n) -{ - struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->periph_addr; - msg.len = n; - msg.flags = I2C_M_STOP | I2C_M_RD; - msg.buffer = buf; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret) { - return ret; - } - - return n; -} - -/** - * \brief Sync version of I2C I/O write - */ -static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) -{ - struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->periph_addr; - msg.len = n; - msg.flags = I2C_M_STOP; - msg.buffer = (uint8_t *)buf; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret) { - return ret; - } - - return n; -} - -/** - * \brief Sync version of i2c initialize - */ -int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) -{ - int32_t init_status; - ASSERT(i2c); - - init_status = _i2c_m_sync_init(&i2c->device, hw); - if (init_status) { - return init_status; - } - - /* Init I/O */ - i2c->io.read = i2c_m_sync_read; - i2c->io.write = i2c_m_sync_write; - - return ERR_NONE; -} - -/** - * \brief deinitialize - */ -int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c) -{ - int32_t status; - ASSERT(i2c); - - status = _i2c_m_sync_deinit(&i2c->device); - if (status) { - return status; - } - - i2c->io.read = NULL; - i2c->io.write = NULL; - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c enable - */ -int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c) -{ - return _i2c_m_sync_enable(&i2c->device); -} - -/** - * \brief Sync version of i2c disable - */ -int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c) -{ - return _i2c_m_sync_disable(&i2c->device); -} - -/** - * \brief Sync version of i2c set peripheral address - */ -int32_t i2c_m_sync_set_periphaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len) -{ - return i2c->periph_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN); -} - -/** - * \brief Sync version of i2c set baudrate - */ -int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate) -{ - return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate); -} - -/** - * \brief Sync version of i2c write command - */ -int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) -{ - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->periph_addr; - msg.len = 1; - msg.flags = 0; - msg.buffer = ® - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - msg.flags = I2C_M_STOP; - msg.buffer = buffer; - msg.len = length; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c read command - */ -int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) -{ - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->periph_addr; - msg.len = 1; - msg.flags = 0; - msg.buffer = ® - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - msg.flags = I2C_M_STOP | I2C_M_RD; - msg.buffer = buffer; - msg.len = length; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c transfer command - */ -int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg) -{ - return _i2c_m_sync_transfer(&i2c->device, msg); -} - -/** - * \brief Sync version of i2c send stop condition command - */ -int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c) -{ - return _i2c_m_sync_send_stop(&i2c->device); -} - -/** - * \brief Retrieve I/O descriptor - */ -int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io) -{ - *io = &i2c->io; - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t i2c_m_sync_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/watch-library/hal/src/hal_init.c b/watch-library/hal/src/hal_init.c deleted file mode 100644 index fb65341f..00000000 --- a/watch-library/hal/src/hal_init.c +++ /dev/null @@ -1,47 +0,0 @@ -/** - * \file - * - * \brief HAL initialization related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_init.h" - -/** - * \brief Driver version - */ -#define HAL_INIT_VERSION 0x00000001u - -/** - * \brief Retrieve the current driver version - */ -uint32_t init_get_version(void) -{ - return HAL_INIT_VERSION; -} diff --git a/watch-library/hal/src/hal_io.c b/watch-library/hal/src/hal_io.c deleted file mode 100644 index ae787d42..00000000 --- a/watch-library/hal/src/hal_io.c +++ /dev/null @@ -1,58 +0,0 @@ -/** - * \file - * - * \brief I/O functionality implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief I/O write interface - */ -int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) -{ - ASSERT(io_descr && buf); - return io_descr->write(io_descr, buf, length); -} - -/** - * \brief I/O read interface - */ -int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) -{ - ASSERT(io_descr && buf); - return io_descr->read(io_descr, buf, length); -} diff --git a/watch-library/hal/src/hal_rand_sync.c b/watch-library/hal/src/hal_rand_sync.c deleted file mode 100755 index 8b29ed1b..00000000 --- a/watch-library/hal/src/hal_rand_sync.c +++ /dev/null @@ -1,122 +0,0 @@ -/** - * \file - * - * \brief Generic Random Number Generator (RNG) functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include "hal_rand_sync.h" - -#define HAL_RNG_SYNC_VERSION 0x00000001u - -int32_t rand_sync_init(struct rand_sync_desc *const desc, void *const hw) -{ - ASSERT(desc); - - return _rand_sync_init(&desc->dev, hw); -} - -void rand_sync_deinit(struct rand_sync_desc *const desc) -{ - ASSERT(desc); - _rand_sync_deinit(&desc->dev); -} - -int32_t rand_sync_enable(struct rand_sync_desc *const desc) -{ - ASSERT(desc); - return _rand_sync_enable(&desc->dev); -} - -void rand_sync_disable(struct rand_sync_desc *const desc) -{ - ASSERT(desc); - _rand_sync_disable(&desc->dev); -} - -int32_t rand_sync_set_seed(struct rand_sync_desc *const desc, const uint32_t seed) -{ - ASSERT(desc); - return _rand_sync_set_seed(&desc->dev, seed); -} - -/** - * \brief Read data bits - */ -static uint32_t _rand_sync_read_data(const struct _rand_sync_dev *dev, const uint8_t n_bits) -{ - uint8_t r_bits = (dev->n_bits < 1) ? 32 : dev->n_bits; - if (r_bits < n_bits) { - uint8_t i; - uint32_t d = 0; - /* Join read bits */ - for (i = 0; i < n_bits; i += r_bits) { - d |= (uint32_t)(_rand_sync_read_one(dev) << i); - } - return d; - } else { - return _rand_sync_read_one(dev); - } -} - -uint8_t rand_sync_read8(const struct rand_sync_desc *const desc) -{ - ASSERT(desc); - return (uint8_t)_rand_sync_read_data(&desc->dev, 8); -} - -uint32_t rand_sync_read32(const struct rand_sync_desc *const desc) -{ - ASSERT(desc); - return (uint32_t)_rand_sync_read_data(&desc->dev, 32); -} - -void rand_sync_read_buf8(const struct rand_sync_desc *const desc, uint8_t *buf, uint32_t len) -{ - uint32_t i; - ASSERT(desc && (buf && len)); - for (i = 0; i < len; i++) { - buf[i] = (uint8_t)_rand_sync_read_data(&desc->dev, 8); - } -} - -void rand_sync_read_buf32(const struct rand_sync_desc *const desc, uint32_t *buf, uint32_t len) -{ - uint32_t i; - ASSERT(desc && (buf && len)); - for (i = 0; i < len; i++) { - buf[i] = (uint32_t)_rand_sync_read_data(&desc->dev, 32); - } -} - -uint32_t rand_sync_get_version(void) -{ - return HAL_RNG_SYNC_VERSION; -} diff --git a/watch-library/hal/src/hal_slcd_sync.c b/watch-library/hal/src/hal_slcd_sync.c deleted file mode 100644 index 573eb0e2..00000000 --- a/watch-library/hal/src/hal_slcd_sync.c +++ /dev/null @@ -1,150 +0,0 @@ -/** - * \file - * - * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality - * declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Initialize SLCD Descriptor - */ -int32_t slcd_sync_init(struct slcd_sync_descriptor *const descr, void *const hw) -{ - ASSERT(descr && hw); - return _slcd_sync_init(&descr->dev, hw); -} - -/** - * \brief Deinitialize SLCD Descriptor - */ -int32_t slcd_sync_deinit(struct slcd_sync_descriptor *const descr) -{ - ASSERT(descr); - return _slcd_sync_deinit(&descr->dev); -} - -/** - * \brief Enable SLCD driver - * - */ -int32_t slcd_sync_enable(struct slcd_sync_descriptor *const descr) -{ - ASSERT(descr); - return _slcd_sync_enable(&descr->dev); -} -/** - * \brief Disable SLCD driver - * - */ -int32_t slcd_sync_disable(struct slcd_sync_descriptor *const descr) -{ - ASSERT(descr); - return _slcd_sync_disable(&descr->dev); -} -/** - * \brief Turn on a Segment - */ -int32_t slcd_sync_seg_on(struct slcd_sync_descriptor *const descr, uint32_t seg) -{ - ASSERT(descr); - return _slcd_sync_seg_on(&descr->dev, seg); -} -/** - * \brief Turn off a Segment - */ -int32_t slcd_sync_seg_off(struct slcd_sync_descriptor *const descr, uint32_t seg) -{ - ASSERT(descr); - return _slcd_sync_seg_off(&descr->dev, seg); -} -/** - * \brief Blink a Segment - */ -int32_t slcd_sync_seg_blink(struct slcd_sync_descriptor *const descr, uint32_t seg, const uint32_t period) -{ - ASSERT(descr && period); - return _slcd_sync_seg_blink(&descr->dev, seg, period); -} - -/** - * \brief Displays a character - */ -int32_t slcd_sync_write_char(struct slcd_sync_descriptor *const descr, const uint8_t character, uint32_t index) -{ - ASSERT(descr); - return _slcd_sync_write_char(&descr->dev, character, index); -} - -/** - * \brief Displays character string string - */ -int32_t slcd_sync_write_string(struct slcd_sync_descriptor *const descr, uint8_t *const str, uint32_t len, - uint32_t index) -{ - uint32_t i; - ASSERT(descr && len); - - for (i = 0; i < len; i++) { - if (_slcd_sync_write_char(&descr->dev, *(str + i), index + i) != ERR_NONE) { - return ERR_INVALID_ARG; - } - } - return ERR_NONE; -} -/** - * \brief Start animation play by a segment array - */ -int32_t slcd_sync_start_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len, - const uint32_t period) -{ - ASSERT(descr && segs && len && period); - return _slcd_sync_start_animation(&descr->dev, segs, len, period); -} - -/** - * \brief Stop animation play by a segment array - */ -int32_t slcd_sync_stop_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len) -{ - ASSERT(descr && segs && len); - return _slcd_sync_stop_animation(&descr->dev, segs, len); -} - -/** - * \brief Set animation Frequency - */ -int32_t slcd_sync_set_animation_period(struct slcd_sync_descriptor *const descr, const uint32_t period) -{ - ASSERT(descr && period); - return _slcd_sync_set_animation_period(&descr->dev, period); -} diff --git a/watch-library/hal/src/hal_sleep.c b/watch-library/hal/src/hal_sleep.c deleted file mode 100644 index 89472f15..00000000 --- a/watch-library/hal/src/hal_sleep.c +++ /dev/null @@ -1,73 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_sleep.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Set the sleep mode of the device and put the MCU to sleep - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see the data sheet. - * - * \param[in] mode Sleep mode to use - * - * \return The status of a sleep request - * \retval -1 The requested sleep mode was invalid or not available - * \retval 0 The operation completed successfully, returned after leaving the - * sleep - */ -int sleep(const uint8_t mode) -{ - if (ERR_NONE != _set_sleep_mode(mode)) - return ERR_INVALID_ARG; - - _go_to_sleep(); - - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version - */ -uint32_t sleep_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/watch-library/hal/src/hal_spi_m_sync.c b/watch-library/hal/src/hal_spi_m_sync.c deleted file mode 100755 index 1a64296a..00000000 --- a/watch-library/hal/src/hal_spi_m_sync.c +++ /dev/null @@ -1,201 +0,0 @@ -/** - * \file - * - * \brief I/O SPI related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_spi_m_sync.h" -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Driver version - */ -#define SPI_M_SYNC_DRIVER_VERSION 0x00000001u - -#define SPI_DEACTIVATE_NEXT 0x8000 - -static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length); -static int32_t _spi_m_sync_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length); - -/** - * \brief Initialize the SPI HAL instance function pointer for HPL APIs. - */ -void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func) -{ - ASSERT(spi); - spi->func = (struct _spi_m_sync_hpl_interface *)func; -} - -int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw) -{ - int32_t rc = 0; - ASSERT(spi && hw); - spi->dev.prvt = (void *)hw; - rc = _spi_m_sync_init(&spi->dev, hw); - - if (rc < 0) { - return rc; - } - - spi->flags = SPI_DEACTIVATE_NEXT; - spi->io.read = _spi_m_sync_io_read; - spi->io.write = _spi_m_sync_io_write; - - return ERR_NONE; -} - -void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi) -{ - ASSERT(spi); - _spi_m_sync_deinit(&spi->dev); -} - -void spi_m_sync_enable(struct spi_m_sync_descriptor *spi) -{ - ASSERT(spi); - _spi_m_sync_enable(&spi->dev); -} - -void spi_m_sync_disable(struct spi_m_sync_descriptor *spi) -{ - ASSERT(spi); - _spi_m_sync_disable(&spi->dev); -} - -int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val) -{ - ASSERT(spi); - return _spi_m_sync_set_baudrate(&spi->dev, baud_val); -} - -int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode) -{ - ASSERT(spi); - return _spi_m_sync_set_mode(&spi->dev, mode); -} - -int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size) -{ - ASSERT(spi); - return _spi_m_sync_set_char_size(&spi->dev, char_size); -} - -int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord) -{ - ASSERT(spi); - return _spi_m_sync_set_data_order(&spi->dev, dord); -} - -/** \brief Do SPI read in polling way - * For SPI master, activate CS, do send 0xFFs and read data, deactivate CS. - * - * It blocks until all data read or error. - * - * \param[in, out] spi Pointer to the HAL SPI instance. - * \param[out] buf Pointer to the buffer to store read data. - * \param[in] size Size of the data in number of characters. - * \return Operation status. - * \retval size Success. - * \retval >=0 Time out, with number of characters read. - */ -static int32_t _spi_m_sync_io_read(struct io_descriptor *io, uint8_t *buf, const uint16_t length) -{ - ASSERT(io); - - struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); - struct spi_xfer xfer; - - xfer.rxbuf = buf; - xfer.txbuf = 0; - xfer.size = length; - - return spi_m_sync_transfer(spi, &xfer); -} - -/** \brief Do SPI data write in polling way - * For SPI master, activate CS, do buffer send and deactivate CS. The data back - * is discarded. - * - * The data read back is discarded. - * - * It blocks until all data sent or error. - * - * \param[in, out] spi Pointer to the HAL SPI instance. - * \param[in] p_xfer Pointer to the transfer information (\ref spi_transfer). - * \return Operation status. - * \retval size Success. - * \retval >=0 Timeout, with number of characters transferred. - */ -static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length) -{ - ASSERT(io); - - struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); - struct spi_xfer xfer; - - xfer.rxbuf = 0; - xfer.txbuf = (uint8_t *)buf; - xfer.size = length; - - return spi_m_sync_transfer(spi, &xfer); -} - -int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer) -{ - struct spi_msg msg; - - ASSERT(spi && p_xfer); - - msg.txbuf = p_xfer->txbuf; - msg.rxbuf = p_xfer->rxbuf; - msg.size = p_xfer->size; - return _spi_m_sync_trans(&spi->dev, &msg); -} - -int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io) -{ - ASSERT(spi && io); - *io = &spi->io; - return 0; -} - -uint32_t spi_m_sync_get_version(void) -{ - return SPI_M_SYNC_DRIVER_VERSION; -} - -#ifdef __cplusplus -} -#endif diff --git a/watch-library/hal/src/hal_usart_sync.c b/watch-library/hal/src/hal_usart_sync.c deleted file mode 100755 index ab99c1d1..00000000 --- a/watch-library/hal/src/hal_usart_sync.c +++ /dev/null @@ -1,276 +0,0 @@ -/** - * \file - * - * \brief I/O USART related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_usart_sync.h" -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); -static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -/** - * \brief Initialize usart interface - */ -int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) -{ - int32_t init_status; - ASSERT(descr && hw); - init_status = _usart_sync_init(&descr->device, hw); - if (init_status) { - return init_status; - } - - descr->io.read = usart_sync_read; - descr->io.write = usart_sync_write; - - return ERR_NONE; -} - -/** - * \brief Uninitialize usart interface - */ -int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_deinit(&descr->device); - - descr->io.read = NULL; - descr->io.write = NULL; - - return ERR_NONE; -} - -/** - * \brief Enable usart interface - */ -int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_enable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Disable usart interface - */ -int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_disable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Retrieve I/O descriptor - */ -int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) -{ - ASSERT(descr && io); - - *io = &descr->io; - return ERR_NONE; -} - -/** - * \brief Specify action for flow control pins - */ -int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, - const union usart_flow_control_state state) -{ - ASSERT(descr); - _usart_sync_set_flow_control_state(&descr->device, state); - - return ERR_NONE; -} - -/** - * \brief Set usart baud rate - */ -int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) -{ - ASSERT(descr); - _usart_sync_set_baud_rate(&descr->device, baud_rate); - - return ERR_NONE; -} - -/** - * \brief Set usart data order - */ -int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) -{ - ASSERT(descr); - _usart_sync_set_data_order(&descr->device, data_order); - - return ERR_NONE; -} - -/** - * \brief Set usart mode - */ -int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) -{ - ASSERT(descr); - _usart_sync_set_mode(&descr->device, mode); - - return ERR_NONE; -} - -/** - * \brief Set usart parity - */ -int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) -{ - ASSERT(descr); - _usart_sync_set_parity(&descr->device, parity); - - return ERR_NONE; -} - -/** - * \brief Set usart stop bits - */ -int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) -{ - ASSERT(descr); - _usart_sync_set_stop_bits(&descr->device, stop_bits); - - return ERR_NONE; -} - -/** - * \brief Set usart character size - */ -int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) -{ - ASSERT(descr); - _usart_sync_set_character_size(&descr->device, size); - - return ERR_NONE; -} - -/** - * \brief Retrieve the state of flow control pins - */ -int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, - union usart_flow_control_state *const state) -{ - ASSERT(descr && state); - *state = _usart_sync_get_flow_control_state(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Check if the usart transmitter is empty - */ -int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - return _usart_sync_is_ready_to_send(&descr->device); -} - -/** - * \brief Check if the usart receiver is not empty - */ -int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - return _usart_sync_is_byte_received(&descr->device); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t usart_sync_get_version(void) -{ - return DRIVER_VERSION; -} - -/* - * \internal Write the given data to usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf Data to write to usart - * \param[in] length The number of bytes to write - * - * \return The number of bytes written. - */ -static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) -{ - uint32_t offset = 0; - struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); - - ASSERT(io_descr && buf && length); - while (!_usart_sync_is_ready_to_send(&descr->device)) - ; - do { - _usart_sync_write_byte(&descr->device, buf[offset]); - while (!_usart_sync_is_ready_to_send(&descr->device)) - ; - } while (++offset < length); - while (!_usart_sync_is_transmit_done(&descr->device)) - ; - return (int32_t)offset; -} - -/* - * \internal Read data from usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf A buffer to read data to - * \param[in] length The size of a buffer - * - * \return The number of bytes read. - */ -static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) -{ - uint32_t offset = 0; - struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); - - ASSERT(io_descr && buf && length); - do { - while (!_usart_sync_is_byte_received(&descr->device)) - ; - buf[offset] = _usart_sync_read_byte(&descr->device); - } while (++offset < length); - - return (int32_t)offset; -} diff --git a/watch-library/hal/utils/include/compiler.h b/watch-library/hal/utils/include/compiler.h deleted file mode 100644 index f35db3df..00000000 --- a/watch-library/hal/utils/include/compiler.h +++ /dev/null @@ -1,64 +0,0 @@ -/** - * \file - * - * \brief Header - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Microchip Support - */ - -/****************************************************************************** - * compiler.h - * - * Created: 05.05.2014 - * Author: N. Fomin - ******************************************************************************/ - -#ifndef _COMPILER_H -#define _COMPILER_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -#ifndef _UNIT_TEST_ -#include "parts.h" -#endif -#include "err_codes.h" - -#ifdef __cplusplus -} -#endif - -#endif /* _COMPILER_H */ diff --git a/watch-library/hal/utils/include/err_codes.h b/watch-library/hal/utils/include/err_codes.h deleted file mode 100644 index a7aff018..00000000 --- a/watch-library/hal/utils/include/err_codes.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - * \file - * - * \brief Error code definitions. - * - * This file defines various status codes returned by functions, - * indicating success or failure as well as what kind of failure. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef ERROR_CODES_H_INCLUDED -#define ERROR_CODES_H_INCLUDED - -#define ERR_NONE 0 -#define ERR_INVALID_DATA -1 -#define ERR_NO_CHANGE -2 -#define ERR_ABORTED -3 -#define ERR_BUSY -4 -#define ERR_SUSPEND -5 -#define ERR_IO -6 -#define ERR_REQ_FLUSHED -7 -#define ERR_TIMEOUT -8 -#define ERR_BAD_DATA -9 -#define ERR_NOT_FOUND -10 -#define ERR_UNSUPPORTED_DEV -11 -#define ERR_NO_MEMORY -12 -#define ERR_INVALID_ARG -13 -#define ERR_BAD_ADDRESS -14 -#define ERR_BAD_FORMAT -15 -#define ERR_BAD_FRQ -16 -#define ERR_DENIED -17 -#define ERR_ALREADY_INITIALIZED -18 -#define ERR_OVERFLOW -19 -#define ERR_NOT_INITIALIZED -20 -#define ERR_SAMPLERATE_UNAVAILABLE -21 -#define ERR_RESOLUTION_UNAVAILABLE -22 -#define ERR_BAUDRATE_UNAVAILABLE -23 -#define ERR_PACKET_COLLISION -24 -#define ERR_PROTOCOL -25 -#define ERR_PIN_MUX_INVALID -26 -#define ERR_UNSUPPORTED_OP -27 -#define ERR_NO_RESOURCE -28 -#define ERR_NOT_READY -29 -#define ERR_FAILURE -30 -#define ERR_WRONG_LENGTH -31 - -#endif diff --git a/watch-library/hal/utils/include/events.h b/watch-library/hal/utils/include/events.h deleted file mode 100644 index 3ee891a7..00000000 --- a/watch-library/hal/utils/include/events.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * \file - * - * \brief Events declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _EVENTS_H_INCLUDED -#define _EVENTS_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * \brief List of events. Must start with 0, be unique and follow numerical order. - */ -#define EVENT_IS_READY_TO_SLEEP_ID 0 -#define EVENT_PREPARE_TO_SLEEP_ID 1 -#define EVENT_WOKEN_UP_ID 2 - -#ifdef __cplusplus -} -#endif - -#endif /* _EVENTS_H_INCLUDED */ diff --git a/watch-library/hal/utils/include/parts.h b/watch-library/hal/utils/include/parts.h deleted file mode 100644 index df30040f..00000000 --- a/watch-library/hal/utils/include/parts.h +++ /dev/null @@ -1,41 +0,0 @@ -/** - * \file - * - * \brief Atmel part identification macros - * - * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef ATMEL_PARTS_H -#define ATMEL_PARTS_H - -#include "saml22.h" - -#include "hri_l22.h" - -#endif /* ATMEL_PARTS_H */ diff --git a/watch-library/hal/utils/include/utils.h b/watch-library/hal/utils/include/utils.h deleted file mode 100644 index 1cf26996..00000000 --- a/watch-library/hal/utils/include/utils.h +++ /dev/null @@ -1,368 +0,0 @@ -/** - * \file - * - * \brief Different macros. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef UTILS_H_INCLUDED -#define UTILS_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_utils_macro - * - * @{ - */ - -/** - * \brief Retrieve pointer to parent structure - */ -#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) - -/** - * \brief Retrieve array size - */ -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) - -/** - * \brief Emit the compiler pragma \a arg. - * - * \param[in] arg The pragma directive as it would appear after \e \#pragma - * (i.e. not stringified). - */ -#define COMPILER_PRAGMA(arg) _Pragma(#arg) - -/** - * \def COMPILER_PACK_SET(alignment) - * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. - */ -#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) - -/** - * \def COMPILER_PACK_RESET() - * \brief Set default alignment for subsequent struct and union definitions. - */ -#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) - -/** - * \brief Set aligned boundary. - */ -#if defined __GNUC__ -#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#elif defined __ICCARM__ -#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) -#elif defined __CC_ARM -#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#endif - -/** - * \brief Flash located data macros - */ -#if defined __GNUC__ -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#elif defined __ICCARM__ -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#elif defined __CC_ARM -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#endif - -/** - * \brief Optimization - */ -#if defined __GNUC__ -#define OPTIMIZE_HIGH __attribute__((optimize(s))) -#elif defined __CC_ARM -#define OPTIMIZE_HIGH _Pragma("O3") -#elif defined __ICCARM__ -#define OPTIMIZE_HIGH _Pragma("optimize=high") -#endif - -/** - * \brief RAM located function attribute - */ -#if defined(__CC_ARM) /* Keil ?Vision 4 */ -#define RAMFUNC __attribute__((section(".ramfunc"))) -#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ -#define RAMFUNC __ramfunc -#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ -#define RAMFUNC __attribute__((section(".ramfunc"))) -#endif - -/** - * \brief No-init section. - * Place a data object or a function in a no-init section. - */ -#if defined(__CC_ARM) -#define NO_INIT(a) __attribute__((zero_init)) -#elif defined(__ICCARM__) -#define NO_INIT(a) __no_init -#elif defined(__GNUC__) -#define NO_INIT(a) __attribute__((section(".no_init"))) -#endif - -/** - * \brief Set user-defined section. - * Place a data object or a function in a user-defined section. - */ -#if defined(__CC_ARM) -#define COMPILER_SECTION(a) __attribute__((__section__(a))) -#elif defined(__ICCARM__) -#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) -#elif defined(__GNUC__) -#define COMPILER_SECTION(a) __attribute__((__section__(a))) -#endif - -/** - * \brief Define WEAK attribute. - */ -#if defined(__CC_ARM) /* Keil ?Vision 4 */ -#define WEAK __attribute__((weak)) -#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ -#define WEAK __weak -#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ -#define WEAK __attribute__((weak)) -#endif - -/** - * \brief Pointer to function - */ -typedef void (*FUNC_PTR)(void); - -#define LE_BYTE0(a) ((uint8_t)(a)) -#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) -#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) -#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) - -#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) -#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) - -/** \name Zero-Bit Counting - * - * Under GCC, __builtin_clz and __builtin_ctz behave like macros when - * applied to constant expressions (values known at compile time), so they are - * more optimized than the use of the corresponding assembly instructions and - * they can be used as constant expressions e.g. to initialize objects having - * static storage duration, and like the corresponding assembly instructions - * when applied to non-constant expressions (values unknown at compile time), so - * they are more optimized than an assembly periphrasis. Hence, clz and ctz - * ensure a possible and optimized behavior for both constant and non-constant - * expressions. - * - * @{ */ - -/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the leading zero bits. - * - * \return The count of leading zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -#define clz(u) __builtin_clz(u) -#else -#define clz(u) \ - ( \ - ((u) == 0) \ - ? 32 \ - : ((u) & (1ul << 31)) \ - ? 0 \ - : ((u) & (1ul << 30)) \ - ? 1 \ - : ((u) & (1ul << 29)) \ - ? 2 \ - : ((u) & (1ul << 28)) \ - ? 3 \ - : ((u) & (1ul << 27)) \ - ? 4 \ - : ((u) & (1ul << 26)) \ - ? 5 \ - : ((u) & (1ul << 25)) \ - ? 6 \ - : ((u) & (1ul << 24)) \ - ? 7 \ - : ((u) & (1ul << 23)) \ - ? 8 \ - : ((u) & (1ul << 22)) \ - ? 9 \ - : ((u) & (1ul << 21)) \ - ? 10 \ - : ((u) & (1ul << 20)) \ - ? 11 \ - : ((u) & (1ul << 19)) \ - ? 12 \ - : ((u) & (1ul << 18)) \ - ? 13 \ - : ((u) & (1ul << 17)) ? 14 \ - : ((u) & (1ul << 16)) ? 15 \ - : ((u) & (1ul << 15)) ? 16 \ - : ((u) & (1ul << 14)) ? 17 \ - : ((u) & (1ul << 13)) ? 18 \ - : ((u) & (1ul << 12)) ? 19 \ - : ((u) \ - & (1ul \ - << 11)) \ - ? 20 \ - : ((u) \ - & (1ul \ - << 10)) \ - ? 21 \ - : ((u) \ - & (1ul \ - << 9)) \ - ? 22 \ - : ((u) \ - & (1ul \ - << 8)) \ - ? 23 \ - : ((u) & (1ul << 7)) ? 24 \ - : ((u) & (1ul << 6)) ? 25 \ - : ((u) \ - & (1ul \ - << 5)) \ - ? 26 \ - : ((u) & (1ul << 4)) ? 27 \ - : ((u) & (1ul << 3)) ? 28 \ - : ((u) & (1ul << 2)) ? 29 \ - : ( \ - (u) & (1ul << 1)) \ - ? 30 \ - : 31) -#endif - -/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the trailing zero bits. - * - * \return The count of trailing zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -#define ctz(u) __builtin_ctz(u) -#else -#define ctz(u) \ - ( \ - (u) & (1ul << 0) \ - ? 0 \ - : (u) & (1ul << 1) \ - ? 1 \ - : (u) & (1ul << 2) \ - ? 2 \ - : (u) & (1ul << 3) \ - ? 3 \ - : (u) & (1ul << 4) \ - ? 4 \ - : (u) & (1ul << 5) \ - ? 5 \ - : (u) & (1ul << 6) \ - ? 6 \ - : (u) & (1ul << 7) \ - ? 7 \ - : (u) & (1ul << 8) \ - ? 8 \ - : (u) & (1ul << 9) \ - ? 9 \ - : (u) & (1ul << 10) \ - ? 10 \ - : (u) & (1ul << 11) \ - ? 11 \ - : (u) & (1ul << 12) \ - ? 12 \ - : (u) & (1ul << 13) \ - ? 13 \ - : (u) & (1ul << 14) \ - ? 14 \ - : (u) & (1ul << 15) \ - ? 15 \ - : (u) & (1ul << 16) \ - ? 16 \ - : (u) & (1ul << 17) \ - ? 17 \ - : (u) & (1ul << 18) \ - ? 18 \ - : (u) & (1ul << 19) ? 19 \ - : (u) & (1ul << 20) ? 20 \ - : (u) & (1ul << 21) ? 21 \ - : (u) & (1ul << 22) ? 22 \ - : (u) & (1ul << 23) ? 23 \ - : (u) & (1ul << 24) ? 24 \ - : (u) & (1ul << 25) ? 25 \ - : (u) & (1ul << 26) ? 26 \ - : (u) & (1ul << 27) ? 27 \ - : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) -#endif -/** @} */ - -/** - * \brief Counts the number of bits in a mask (no more than 32 bits) - * \param[in] mask Mask of which to count the bits. - */ -#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) - -/** - * \brief Retrieve the start position of bits mask (no more than 32 bits) - * \param[in] mask Mask of which to retrieve the start position. - */ -#define pos_of_mask(mask) ctz(mask) - -/** - * \brief Return division result of a/b and round up the result to the closest - * number divisible by "b" - */ -#define round_up(a, b) (((a)-1) / (b) + 1) - -/** - * \brief Get the minimum of x and y - */ -#define min(x, y) ((x) > (y) ? (y) : (x)) - -/** - * \brief Get the maximum of x and y - */ -#define max(x, y) ((x) > (y) ? (x) : (y)) - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* UTILS_H_INCLUDED */ diff --git a/watch-library/hal/utils/include/utils_assert.h b/watch-library/hal/utils/include/utils_assert.h deleted file mode 100644 index c2328d6c..00000000 --- a/watch-library/hal/utils/include/utils_assert.h +++ /dev/null @@ -1,93 +0,0 @@ -/** - * \file - * - * \brief Asserts related functionality. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _ASSERT_H_INCLUDED -#define _ASSERT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#ifndef USE_SIMPLE_ASSERT -//# define USE_SIMPLE_ASSERT -#endif - -/** - * \brief Assert macro - * - * This macro is used to throw asserts. It can be mapped to different function - * based on debug level. - * - * \param[in] condition A condition to be checked; - * assert is thrown if the given condition is false - */ -#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) - -#ifdef DEBUG - -#ifdef USE_SIMPLE_ASSERT -#define ASSERT_IMPL(condition, file, line) \ - if (!(condition)) \ - __asm("BKPT #0"); -#else -#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) -#endif - -#else /* DEBUG */ - -#ifdef USE_SIMPLE_ASSERT -#define ASSERT_IMPL(condition, file, line) ((void)0) -#else -#define ASSERT_IMPL(condition, file, line) ((void)0) -#endif - -#endif /* DEBUG */ - -/** - * \brief Assert function - * - * This function is used to throw asserts. - * - * \param[in] condition A condition to be checked; assert is thrown if the given - * condition is false - * \param[in] file File name - * \param[in] line Line number - */ -void assert(const bool condition, const char *const file, const int line); - -#ifdef __cplusplus -} -#endif -#endif /* _ASSERT_H_INCLUDED */ diff --git a/watch-library/hal/utils/include/utils_decrement_macro.h b/watch-library/hal/utils/include/utils_decrement_macro.h deleted file mode 100644 index 2b524699..00000000 --- a/watch-library/hal/utils/include/utils_decrement_macro.h +++ /dev/null @@ -1,309 +0,0 @@ -/** - * \file - * - * \brief Decrement macro. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_DECREMENT_MACRO_H -#define _UTILS_DECREMENT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Compile time decrement, result value is entire integer literal - * - * \param[in] val - value to be decremented - */ -#define DEC_VALUE(val) DEC_##val - -// Preprocessor increment implementation -#define DEC_256 255 -#define DEC_255 254 -#define DEC_254 253 -#define DEC_253 252 -#define DEC_252 251 -#define DEC_251 250 -#define DEC_250 249 -#define DEC_249 248 -#define DEC_248 247 -#define DEC_247 246 -#define DEC_246 245 -#define DEC_245 244 -#define DEC_244 243 -#define DEC_243 242 -#define DEC_242 241 -#define DEC_241 240 -#define DEC_240 239 -#define DEC_239 238 -#define DEC_238 237 -#define DEC_237 236 -#define DEC_236 235 -#define DEC_235 234 -#define DEC_234 233 -#define DEC_233 232 -#define DEC_232 231 -#define DEC_231 230 -#define DEC_230 229 -#define DEC_229 228 -#define DEC_228 227 -#define DEC_227 226 -#define DEC_226 225 -#define DEC_225 224 -#define DEC_224 223 -#define DEC_223 222 -#define DEC_222 221 -#define DEC_221 220 -#define DEC_220 219 -#define DEC_219 218 -#define DEC_218 217 -#define DEC_217 216 -#define DEC_216 215 -#define DEC_215 214 -#define DEC_214 213 -#define DEC_213 212 -#define DEC_212 211 -#define DEC_211 210 -#define DEC_210 209 -#define DEC_209 208 -#define DEC_208 207 -#define DEC_207 206 -#define DEC_206 205 -#define DEC_205 204 -#define DEC_204 203 -#define DEC_203 202 -#define DEC_202 201 -#define DEC_201 200 -#define DEC_200 199 -#define DEC_199 198 -#define DEC_198 197 -#define DEC_197 196 -#define DEC_196 195 -#define DEC_195 194 -#define DEC_194 193 -#define DEC_193 192 -#define DEC_192 191 -#define DEC_191 190 -#define DEC_190 189 -#define DEC_189 188 -#define DEC_188 187 -#define DEC_187 186 -#define DEC_186 185 -#define DEC_185 184 -#define DEC_184 183 -#define DEC_183 182 -#define DEC_182 181 -#define DEC_181 180 -#define DEC_180 179 -#define DEC_179 178 -#define DEC_178 177 -#define DEC_177 176 -#define DEC_176 175 -#define DEC_175 174 -#define DEC_174 173 -#define DEC_173 172 -#define DEC_172 171 -#define DEC_171 170 -#define DEC_170 169 -#define DEC_169 168 -#define DEC_168 167 -#define DEC_167 166 -#define DEC_166 165 -#define DEC_165 164 -#define DEC_164 163 -#define DEC_163 162 -#define DEC_162 161 -#define DEC_161 160 -#define DEC_160 159 -#define DEC_159 158 -#define DEC_158 157 -#define DEC_157 156 -#define DEC_156 155 -#define DEC_155 154 -#define DEC_154 153 -#define DEC_153 152 -#define DEC_152 151 -#define DEC_151 150 -#define DEC_150 149 -#define DEC_149 148 -#define DEC_148 147 -#define DEC_147 146 -#define DEC_146 145 -#define DEC_145 144 -#define DEC_144 143 -#define DEC_143 142 -#define DEC_142 141 -#define DEC_141 140 -#define DEC_140 139 -#define DEC_139 138 -#define DEC_138 137 -#define DEC_137 136 -#define DEC_136 135 -#define DEC_135 134 -#define DEC_134 133 -#define DEC_133 132 -#define DEC_132 131 -#define DEC_131 130 -#define DEC_130 129 -#define DEC_129 128 -#define DEC_128 127 -#define DEC_127 126 -#define DEC_126 125 -#define DEC_125 124 -#define DEC_124 123 -#define DEC_123 122 -#define DEC_122 121 -#define DEC_121 120 -#define DEC_120 119 -#define DEC_119 118 -#define DEC_118 117 -#define DEC_117 116 -#define DEC_116 115 -#define DEC_115 114 -#define DEC_114 113 -#define DEC_113 112 -#define DEC_112 111 -#define DEC_111 110 -#define DEC_110 109 -#define DEC_109 108 -#define DEC_108 107 -#define DEC_107 106 -#define DEC_106 105 -#define DEC_105 104 -#define DEC_104 103 -#define DEC_103 102 -#define DEC_102 101 -#define DEC_101 100 -#define DEC_100 99 -#define DEC_99 98 -#define DEC_98 97 -#define DEC_97 96 -#define DEC_96 95 -#define DEC_95 94 -#define DEC_94 93 -#define DEC_93 92 -#define DEC_92 91 -#define DEC_91 90 -#define DEC_90 89 -#define DEC_89 88 -#define DEC_88 87 -#define DEC_87 86 -#define DEC_86 85 -#define DEC_85 84 -#define DEC_84 83 -#define DEC_83 82 -#define DEC_82 81 -#define DEC_81 80 -#define DEC_80 79 -#define DEC_79 78 -#define DEC_78 77 -#define DEC_77 76 -#define DEC_76 75 -#define DEC_75 74 -#define DEC_74 73 -#define DEC_73 72 -#define DEC_72 71 -#define DEC_71 70 -#define DEC_70 69 -#define DEC_69 68 -#define DEC_68 67 -#define DEC_67 66 -#define DEC_66 65 -#define DEC_65 64 -#define DEC_64 63 -#define DEC_63 62 -#define DEC_62 61 -#define DEC_61 60 -#define DEC_60 59 -#define DEC_59 58 -#define DEC_58 57 -#define DEC_57 56 -#define DEC_56 55 -#define DEC_55 54 -#define DEC_54 53 -#define DEC_53 52 -#define DEC_52 51 -#define DEC_51 50 -#define DEC_50 49 -#define DEC_49 48 -#define DEC_48 47 -#define DEC_47 46 -#define DEC_46 45 -#define DEC_45 44 -#define DEC_44 43 -#define DEC_43 42 -#define DEC_42 41 -#define DEC_41 40 -#define DEC_40 39 -#define DEC_39 38 -#define DEC_38 37 -#define DEC_37 36 -#define DEC_36 35 -#define DEC_35 34 -#define DEC_34 33 -#define DEC_33 32 -#define DEC_32 31 -#define DEC_31 30 -#define DEC_30 29 -#define DEC_29 28 -#define DEC_28 27 -#define DEC_27 26 -#define DEC_26 25 -#define DEC_25 24 -#define DEC_24 23 -#define DEC_23 22 -#define DEC_22 21 -#define DEC_21 20 -#define DEC_20 19 -#define DEC_19 18 -#define DEC_18 17 -#define DEC_17 16 -#define DEC_16 15 -#define DEC_15 14 -#define DEC_14 13 -#define DEC_13 12 -#define DEC_12 11 -#define DEC_11 10 -#define DEC_10 9 -#define DEC_9 8 -#define DEC_8 7 -#define DEC_7 6 -#define DEC_6 5 -#define DEC_5 4 -#define DEC_4 3 -#define DEC_3 2 -#define DEC_2 1 -#define DEC_1 0 - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_DECREMENT_MACRO_H */ diff --git a/watch-library/hal/utils/include/utils_event.h b/watch-library/hal/utils/include/utils_event.h deleted file mode 100644 index 13067c4f..00000000 --- a/watch-library/hal/utils/include/utils_event.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Events declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_EVENT_H_INCLUDED -#define _UTILS_EVENT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * \brief The maximum amount of events - */ -#define EVENT_MAX_AMOUNT 8 - -/** - * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the - * closest number divisible by 8. - */ -#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) - -/** - * \brief The type of event ID. IDs should start with 0 and be in numerical order. - */ -typedef uint8_t event_id_t; - -/** - * \brief The type of returned parameter. This type is big enough to contain - * pointer to data on any platform. - */ -typedef uintptr_t event_data_t; - -/** - * \brief The type of returned parameter. This type is big enough to contain - * pointer to data on any platform. - */ -typedef void (*event_cb_t)(event_id_t id, event_data_t data); - -/** - * \brief Event structure - */ -struct event { - struct list_element elem; /*! The pointer to next event */ - uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ - event_cb_t cb; /*! Callback to be called when an event occurs */ -}; - -/** - * \brief Subscribe to event - * - * \param[in] event The pointer to event structure - * \param[in] id The event ID to subscribe to - * \param[in] cb The callback function to call when the given event occurs - * - * \return The status of subscription - */ -int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); - -/** - * \brief Remove event from subscription - * - * \param[in] event The pointer to event structure - * \param[in] id The event ID to remove subscription from - * - * \return The status of subscription removing - */ -int32_t event_unsubscribe(struct event *const event, const event_id_t id); - -/** - * \brief Post event - * - * \param[in] id The event ID to post - * \param[in] data The event data to be passed to event subscribers - */ -void event_post(const event_id_t id, const event_data_t data); - -#ifdef __cplusplus -} -#endif - -#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/watch-library/hal/utils/include/utils_increment_macro.h b/watch-library/hal/utils/include/utils_increment_macro.h deleted file mode 100644 index 464c6cbb..00000000 --- a/watch-library/hal/utils/include/utils_increment_macro.h +++ /dev/null @@ -1,308 +0,0 @@ -/** - * \file - * - * \brief Increment macro. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_INCREMENT_MACRO_H -#define _UTILS_INCREMENT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Compile time increment, result value is entire integer literal - * - * \param[in] val - value to be incremented (254 max) - */ -#define INC_VALUE(val) SP_INC_##val - -// Preprocessor increment implementation -#define SP_INC_0 1 -#define SP_INC_1 2 -#define SP_INC_2 3 -#define SP_INC_3 4 -#define SP_INC_4 5 -#define SP_INC_5 6 -#define SP_INC_6 7 -#define SP_INC_7 8 -#define SP_INC_8 9 -#define SP_INC_9 10 -#define SP_INC_10 11 -#define SP_INC_11 12 -#define SP_INC_12 13 -#define SP_INC_13 14 -#define SP_INC_14 15 -#define SP_INC_15 16 -#define SP_INC_16 17 -#define SP_INC_17 18 -#define SP_INC_18 19 -#define SP_INC_19 20 -#define SP_INC_20 21 -#define SP_INC_21 22 -#define SP_INC_22 23 -#define SP_INC_23 24 -#define SP_INC_24 25 -#define SP_INC_25 26 -#define SP_INC_26 27 -#define SP_INC_27 28 -#define SP_INC_28 29 -#define SP_INC_29 30 -#define SP_INC_30 31 -#define SP_INC_31 32 -#define SP_INC_32 33 -#define SP_INC_33 34 -#define SP_INC_34 35 -#define SP_INC_35 36 -#define SP_INC_36 37 -#define SP_INC_37 38 -#define SP_INC_38 39 -#define SP_INC_39 40 -#define SP_INC_40 41 -#define SP_INC_41 42 -#define SP_INC_42 43 -#define SP_INC_43 44 -#define SP_INC_44 45 -#define SP_INC_45 46 -#define SP_INC_46 47 -#define SP_INC_47 48 -#define SP_INC_48 49 -#define SP_INC_49 50 -#define SP_INC_50 51 -#define SP_INC_51 52 -#define SP_INC_52 53 -#define SP_INC_53 54 -#define SP_INC_54 55 -#define SP_INC_55 56 -#define SP_INC_56 57 -#define SP_INC_57 58 -#define SP_INC_58 59 -#define SP_INC_59 60 -#define SP_INC_60 61 -#define SP_INC_61 62 -#define SP_INC_62 63 -#define SP_INC_63 64 -#define SP_INC_64 65 -#define SP_INC_65 66 -#define SP_INC_66 67 -#define SP_INC_67 68 -#define SP_INC_68 69 -#define SP_INC_69 70 -#define SP_INC_70 71 -#define SP_INC_71 72 -#define SP_INC_72 73 -#define SP_INC_73 74 -#define SP_INC_74 75 -#define SP_INC_75 76 -#define SP_INC_76 77 -#define SP_INC_77 78 -#define SP_INC_78 79 -#define SP_INC_79 80 -#define SP_INC_80 81 -#define SP_INC_81 82 -#define SP_INC_82 83 -#define SP_INC_83 84 -#define SP_INC_84 85 -#define SP_INC_85 86 -#define SP_INC_86 87 -#define SP_INC_87 88 -#define SP_INC_88 89 -#define SP_INC_89 90 -#define SP_INC_90 91 -#define SP_INC_91 92 -#define SP_INC_92 93 -#define SP_INC_93 94 -#define SP_INC_94 95 -#define SP_INC_95 96 -#define SP_INC_96 97 -#define SP_INC_97 98 -#define SP_INC_98 99 -#define SP_INC_99 100 -#define SP_INC_100 101 -#define SP_INC_101 102 -#define SP_INC_102 103 -#define SP_INC_103 104 -#define SP_INC_104 105 -#define SP_INC_105 106 -#define SP_INC_106 107 -#define SP_INC_107 108 -#define SP_INC_108 109 -#define SP_INC_109 110 -#define SP_INC_110 111 -#define SP_INC_111 112 -#define SP_INC_112 113 -#define SP_INC_113 114 -#define SP_INC_114 115 -#define SP_INC_115 116 -#define SP_INC_116 117 -#define SP_INC_117 118 -#define SP_INC_118 119 -#define SP_INC_119 120 -#define SP_INC_120 121 -#define SP_INC_121 122 -#define SP_INC_122 123 -#define SP_INC_123 124 -#define SP_INC_124 125 -#define SP_INC_125 126 -#define SP_INC_126 127 -#define SP_INC_127 128 -#define SP_INC_128 129 -#define SP_INC_129 130 -#define SP_INC_130 131 -#define SP_INC_131 132 -#define SP_INC_132 133 -#define SP_INC_133 134 -#define SP_INC_134 135 -#define SP_INC_135 136 -#define SP_INC_136 137 -#define SP_INC_137 138 -#define SP_INC_138 139 -#define SP_INC_139 140 -#define SP_INC_140 141 -#define SP_INC_141 142 -#define SP_INC_142 143 -#define SP_INC_143 144 -#define SP_INC_144 145 -#define SP_INC_145 146 -#define SP_INC_146 147 -#define SP_INC_147 148 -#define SP_INC_148 149 -#define SP_INC_149 150 -#define SP_INC_150 151 -#define SP_INC_151 152 -#define SP_INC_152 153 -#define SP_INC_153 154 -#define SP_INC_154 155 -#define SP_INC_155 156 -#define SP_INC_156 157 -#define SP_INC_157 158 -#define SP_INC_158 159 -#define SP_INC_159 160 -#define SP_INC_160 161 -#define SP_INC_161 162 -#define SP_INC_162 163 -#define SP_INC_163 164 -#define SP_INC_164 165 -#define SP_INC_165 166 -#define SP_INC_166 167 -#define SP_INC_167 168 -#define SP_INC_168 169 -#define SP_INC_169 170 -#define SP_INC_170 171 -#define SP_INC_171 172 -#define SP_INC_172 173 -#define SP_INC_173 174 -#define SP_INC_174 175 -#define SP_INC_175 176 -#define SP_INC_176 177 -#define SP_INC_177 178 -#define SP_INC_178 179 -#define SP_INC_179 180 -#define SP_INC_180 181 -#define SP_INC_181 182 -#define SP_INC_182 183 -#define SP_INC_183 184 -#define SP_INC_184 185 -#define SP_INC_185 186 -#define SP_INC_186 187 -#define SP_INC_187 188 -#define SP_INC_188 189 -#define SP_INC_189 190 -#define SP_INC_190 191 -#define SP_INC_191 192 -#define SP_INC_192 193 -#define SP_INC_193 194 -#define SP_INC_194 195 -#define SP_INC_195 196 -#define SP_INC_196 197 -#define SP_INC_197 198 -#define SP_INC_198 199 -#define SP_INC_199 200 -#define SP_INC_200 201 -#define SP_INC_201 202 -#define SP_INC_202 203 -#define SP_INC_203 204 -#define SP_INC_204 205 -#define SP_INC_205 206 -#define SP_INC_206 207 -#define SP_INC_207 208 -#define SP_INC_208 209 -#define SP_INC_209 210 -#define SP_INC_210 211 -#define SP_INC_211 212 -#define SP_INC_212 213 -#define SP_INC_213 214 -#define SP_INC_214 215 -#define SP_INC_215 216 -#define SP_INC_216 217 -#define SP_INC_217 218 -#define SP_INC_218 219 -#define SP_INC_219 220 -#define SP_INC_220 221 -#define SP_INC_221 222 -#define SP_INC_222 223 -#define SP_INC_223 224 -#define SP_INC_224 225 -#define SP_INC_225 226 -#define SP_INC_226 227 -#define SP_INC_227 228 -#define SP_INC_228 229 -#define SP_INC_229 230 -#define SP_INC_230 231 -#define SP_INC_231 232 -#define SP_INC_232 233 -#define SP_INC_233 234 -#define SP_INC_234 235 -#define SP_INC_235 236 -#define SP_INC_236 237 -#define SP_INC_237 238 -#define SP_INC_238 239 -#define SP_INC_239 240 -#define SP_INC_240 241 -#define SP_INC_241 242 -#define SP_INC_242 243 -#define SP_INC_243 244 -#define SP_INC_244 245 -#define SP_INC_245 246 -#define SP_INC_246 247 -#define SP_INC_247 248 -#define SP_INC_248 249 -#define SP_INC_249 250 -#define SP_INC_250 251 -#define SP_INC_251 252 -#define SP_INC_252 253 -#define SP_INC_253 254 -#define SP_INC_254 255 - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/watch-library/hal/utils/include/utils_list.h b/watch-library/hal/utils/include/utils_list.h deleted file mode 100644 index 977e8cca..00000000 --- a/watch-library/hal/utils/include/utils_list.h +++ /dev/null @@ -1,164 +0,0 @@ -/** - * \file - * - * \brief List declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_LIST_H_INCLUDED -#define _UTILS_LIST_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_utils_list - * - * @{ - */ - -#include - -/** - * \brief List element type - */ -struct list_element { - struct list_element *next; -}; - -/** - * \brief List head type - */ -struct list_descriptor { - struct list_element *head; -}; - -/** - * \brief Reset list - * - * \param[in] list The pointer to a list descriptor - */ -static inline void list_reset(struct list_descriptor *const list) -{ - list->head = NULL; -} - -/** - * \brief Retrieve list head - * - * \param[in] list The pointer to a list descriptor - * - * \return A pointer to the head of the given list or NULL if the list is - * empty - */ -static inline void *list_get_head(const struct list_descriptor *const list) -{ - return (void *)list->head; -} - -/** - * \brief Retrieve next list head - * - * \param[in] list The pointer to a list element - * - * \return A pointer to the next list element or NULL if there is not next - * element - */ -static inline void *list_get_next_element(const void *const element) -{ - return element ? ((struct list_element *)element)->next : NULL; -} - -/** - * \brief Insert an element as list head - * - * \param[in] list The pointer to a list element - * \param[in] element An element to insert to the given list - */ -void list_insert_as_head(struct list_descriptor *const list, void *const element); - -/** - * \brief Insert an element after the given list element - * - * \param[in] after An element to insert after - * \param[in] element Element to insert to the given list - */ -void list_insert_after(void *const after, void *const element); - -/** - * \brief Insert an element at list end - * - * \param[in] after An element to insert after - * \param[in] element Element to insert to the given list - */ -void list_insert_at_end(struct list_descriptor *const list, void *const element); - -/** - * \brief Check whether an element belongs to a list - * - * \param[in] list The pointer to a list - * \param[in] element An element to check - * - * \return The result of checking - * \retval true If the given element is an element of the given list - * \retval false Otherwise - */ -bool is_list_element(const struct list_descriptor *const list, const void *const element); - -/** - * \brief Removes list head - * - * This function removes the list head and sets the next element after the list - * head as a new list head. - * - * \param[in] list The pointer to a list - * - * \return The pointer to the new list head of NULL if the list head is NULL - */ -void *list_remove_head(struct list_descriptor *const list); - -/** - * \brief Removes the list element - * - * \param[in] list The pointer to a list - * \param[in] element An element to remove - * - * \return The result of element removing - * \retval true The given element is removed from the given list - * \retval false The given element is not an element of the given list - */ -bool list_delete_element(struct list_descriptor *const list, const void *const element); - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/watch-library/hal/utils/include/utils_recursion_macro.h b/watch-library/hal/utils/include/utils_recursion_macro.h deleted file mode 100644 index 294314c4..00000000 --- a/watch-library/hal/utils/include/utils_recursion_macro.h +++ /dev/null @@ -1,69 +0,0 @@ -/** - * \file - * - * \brief Recursion macro. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_RECURSION_MACRO_H -#define _UTILS_RECURSION_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * \brief Macro recursion - * - * \param[in] macro Macro to be repeated recursively - * \param[in] arg A recursive threshold, building on this to decline by times - * defined with parameter n - * \param[in] n The number of repetitious calls to macro - */ -#define RECURSION_MACRO(macro, arg, n) RECURSION_MACRO_I(macro, arg, n) - -/* - * \brief Second level is needed to get integer literal from "n" if it is - * defined as macro - */ -#define RECURSION_MACRO_I(macro, arg, n) RECURSION##n(macro, arg) - -#define RECURSION0(macro, arg) -#define RECURSION1(macro, arg) RECURSION0(macro, DEC_VALUE(arg)) macro(arg, 0) -#define RECURSION2(macro, arg) RECURSION1(macro, DEC_VALUE(arg)) macro(arg, 1) -#define RECURSION3(macro, arg) RECURSION2(macro, DEC_VALUE(arg)) macro(arg, 2) -#define RECURSION4(macro, arg) RECURSION3(macro, DEC_VALUE(arg)) macro(arg, 3) -#define RECURSION5(macro, arg) RECURSION4(macro, DEC_VALUE(arg)) macro(arg, 4) - -#ifdef __cplusplus -} -#endif - -#include -#endif /* _UTILS_RECURSION_MACRO_H */ diff --git a/watch-library/hal/utils/include/utils_repeat_macro.h b/watch-library/hal/utils/include/utils_repeat_macro.h deleted file mode 100644 index 89e6f52d..00000000 --- a/watch-library/hal/utils/include/utils_repeat_macro.h +++ /dev/null @@ -1,322 +0,0 @@ -/** - * \file - * - * \brief Repeat macro. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_REPEAT_MACRO_H -#define _UTILS_REPEAT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * \brief Sequently repeates specified macro for n times (255 max). - * - * Specified macro shall have two arguments: macro(arg, i) - * arg - user defined argument, which have the same value for all iterations. - * i - iteration number; numbering begins from zero and increments on each - * iteration. - * - * \param[in] macro - macro to be repeated - * \param[in] arg - user defined argument for repeated macro - * \param[in] n - total number of iterations (255 max) - */ -#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) - -/* - * \brief Second level is needed to get integer literal from "n" if it is - * defined as macro - */ -#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) - -#define REPEAT1(macro, arg, n) macro(arg, n) -#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) -#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) -#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) -#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) -#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) -#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) -#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) -#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) -#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) -#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) -#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) -#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) -#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) -#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) -#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) -#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) -#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) -#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) -#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) -#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) -#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) -#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) -#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) -#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) -#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) -#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) -#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) -#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) -#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) -#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) -#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) -#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) -#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) -#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) -#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) -#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) -#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) -#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) -#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) -#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) -#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) -#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) -#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) -#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) -#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) -#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) -#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) -#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) -#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) -#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) -#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) -#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) -#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) -#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) -#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) -#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) -#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) -#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) -#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) -#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) -#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) -#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) -#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) -#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) -#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) -#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) -#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) -#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) -#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) -#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) -#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) -#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) -#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) -#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) -#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) -#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) -#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) -#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) -#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) -#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) -#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) -#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) -#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) -#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) -#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) -#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) -#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) -#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) -#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) -#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) -#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) -#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) -#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) -#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) -#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) -#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) -#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) -#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) -#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) -#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) -#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) -#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) -#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) -#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) -#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) -#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) -#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) -#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) -#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) -#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) -#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) -#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) -#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) -#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) -#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) -#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) -#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) -#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) -#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) -#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) -#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) -#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) -#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) -#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) -#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) -#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) -#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) -#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) -#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) -#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) -#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) -#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) -#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) -#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) -#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) -#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) -#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) -#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) -#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) -#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) -#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) -#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) -#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) -#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) -#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) -#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) -#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) -#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) -#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) -#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) -#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) -#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) -#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) -#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) -#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) -#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) -#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) -#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) -#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) -#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) -#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) -#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) -#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) -#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) -#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) -#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) -#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) -#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) -#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) -#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) -#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) -#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) -#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) -#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) -#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) -#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) -#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) -#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) -#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) -#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) -#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) -#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) -#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) -#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) -#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) -#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) -#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) -#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) -#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) -#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) -#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) -#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) -#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) -#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) -#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) -#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) -#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) -#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) -#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) -#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) -#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) -#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) -#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) -#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) -#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) -#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) -#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) -#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) -#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) -#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) -#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) -#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) -#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) -#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) -#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) -#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) -#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) -#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) -#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) -#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) -#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) -#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) -#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) -#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) -#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) -#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) -#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) -#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) -#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) -#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) -#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) -#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) -#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) -#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) -#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) -#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) -#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) -#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) -#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) -#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) -#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) -#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) -#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) -#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) -#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) -#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) -#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) -#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) -#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) -#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) -#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) -#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) -#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) -#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) - -#ifdef __cplusplus -} -#endif - -#include -#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/watch-library/hal/utils/src/utils_assert.c b/watch-library/hal/utils/src/utils_assert.c deleted file mode 100644 index b376c970..00000000 --- a/watch-library/hal/utils/src/utils_assert.c +++ /dev/null @@ -1,46 +0,0 @@ -/** - * \file - * - * \brief Asserts related functionality. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include - -/** - * \brief Assert function - */ -void assert(const bool condition, const char *const file, const int line) -{ - if (!(condition)) { - __asm("BKPT #0"); - } - (void)file; - (void)line; -} diff --git a/watch-library/hal/utils/src/utils_event.c b/watch-library/hal/utils/src/utils_event.c deleted file mode 100644 index d1af9d0c..00000000 --- a/watch-library/hal/utils/src/utils_event.c +++ /dev/null @@ -1,125 +0,0 @@ -/** - * \file - * - * \brief Events implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) - -static struct list_descriptor events; -static uint8_t subscribed[EVENT_MASK_SIZE]; - -int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - - ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); - - if (event->mask[position] & mask) { - return ERR_NO_CHANGE; /* Already subscribed */ - } - - if (!is_list_element(&events, event)) { - memset(event->mask, 0, EVENT_MASK_SIZE); - list_insert_as_head(&events, event); - } - event->cb = cb; - event->mask[position] |= mask; - - subscribed[position] |= mask; - - return ERR_NONE; -} - -int32_t event_unsubscribe(struct event *const event, const event_id_t id) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - const struct event *current; - uint8_t i; - - ASSERT(event && (id < EVENT_MAX_AMOUNT)); - - if (!(event->mask[position] & mask)) { - return ERR_NO_CHANGE; /* Already unsubscribed */ - } - - event->mask[position] &= ~mask; - - /* Check if there are more subscribers */ - for ((current = (const struct event *)list_get_head(&events)); current; - current = (const struct event *)list_get_next_element(current)) { - if (current->mask[position] & mask) { - break; - } - } - if (!current) { - subscribed[position] &= ~mask; - } - - /* Remove event from the list. Can be unsave, document it! */ - for (i = 0; i < ARRAY_SIZE(event->mask); i++) { - if (event->mask[i]) { - return ERR_NONE; - } - } - list_delete_element(&events, event); - - return ERR_NONE; -} - -void event_post(const event_id_t id, const event_data_t data) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - const struct event *current; - - ASSERT((id < EVENT_MAX_AMOUNT)); - - if (!(subscribed[position] & mask)) { - return; /* No subscribers */ - } - - /* Find all subscribers */ - for ((current = (const struct event *)list_get_head(&events)); current; - current = (const struct event *)list_get_next_element(current)) { - if (current->mask[position] & mask) { - current->cb(id, data); - } - } -} diff --git a/watch-library/hal/utils/src/utils_list.c b/watch-library/hal/utils/src/utils_list.c deleted file mode 100644 index 4006a019..00000000 --- a/watch-library/hal/utils/src/utils_list.c +++ /dev/null @@ -1,136 +0,0 @@ -/** - * \file - * - * \brief List functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Check whether element belongs to list - */ -bool is_list_element(const struct list_descriptor *const list, const void *const element) -{ - struct list_element *it; - for (it = list->head; it; it = it->next) { - if (it == element) { - return true; - } - } - - return false; -} - -/** - * \brief Insert an element as list head - */ -void list_insert_as_head(struct list_descriptor *const list, void *const element) -{ - ASSERT(!is_list_element(list, element)); - - ((struct list_element *)element)->next = list->head; - list->head = (struct list_element *)element; -} - -/** - * \brief Insert an element after the given list element - */ -void list_insert_after(void *const after, void *const element) -{ - ((struct list_element *)element)->next = ((struct list_element *)after)->next; - ((struct list_element *)after)->next = (struct list_element *)element; -} - -/** - * \brief Insert an element at list end - */ -void list_insert_at_end(struct list_descriptor *const list, void *const element) -{ - struct list_element *it = list->head; - - ASSERT(!is_list_element(list, element)); - - if (!list->head) { - list->head = (struct list_element *)element; - ((struct list_element *)element)->next = NULL; - return; - } - - while (it->next) { - it = it->next; - } - it->next = (struct list_element *)element; - ((struct list_element *)element)->next = NULL; -} - -/** - * \brief Removes list head - */ -void *list_remove_head(struct list_descriptor *const list) -{ - if (list->head) { - struct list_element *tmp = list->head; - - list->head = list->head->next; - return (void *)tmp; - } - - return NULL; -} - -/** - * \brief Removes list element - */ -bool list_delete_element(struct list_descriptor *const list, const void *const element) -{ - if (!element) { - return false; - } - - if (list->head == element) { - list->head = list->head->next; - return true; - } else { - struct list_element *it = list->head; - - while (it && it->next != element) { - it = it->next; - } - if (it) { - it->next = ((struct list_element *)element)->next; - return true; - } - } - - return false; -} - -//@} diff --git a/watch-library/hal/utils/src/utils_syscalls.c b/watch-library/hal/utils/src/utils_syscalls.c deleted file mode 100644 index 79e2f1fe..00000000 --- a/watch-library/hal/utils/src/utils_syscalls.c +++ /dev/null @@ -1,152 +0,0 @@ -/** - * \file - * - * \brief Syscalls for SAM0 (GCC). - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#undef errno -extern int errno; -extern int _end; - -extern caddr_t _sbrk(int incr); -extern int link(char *old, char *_new); -extern int _close(int file); -extern int _fstat(int file, struct stat *st); -extern int _isatty(int file); -extern int _lseek(int file, int ptr, int dir); -extern void _exit(int status); -extern void _kill(int pid, int sig); -extern int _getpid(void); - -/** - * \brief Replacement of C library of _sbrk - */ -extern caddr_t _sbrk(int incr) -{ - static unsigned char *heap = NULL; - unsigned char * prev_heap; - - if (heap == NULL) { - heap = (unsigned char *)&_end; - } - prev_heap = heap; - - heap += incr; - - return (caddr_t)prev_heap; -} - -/** - * \brief Replacement of C library of link - */ -extern int link(char *old, char *_new) -{ - (void)old, (void)_new; - return -1; -} - -/** - * \brief Replacement of C library of _close - */ -extern int _close(int file) -{ - (void)file; - return -1; -} - -/** - * \brief Replacement of C library of _fstat - */ -extern int _fstat(int file, struct stat *st) -{ - (void)file; - st->st_mode = S_IFCHR; - - return 0; -} - -/** - * \brief Replacement of C library of _isatty - */ -extern int _isatty(int file) -{ - (void)file; - return 1; -} - -/** - * \brief Replacement of C library of _lseek - */ -extern int _lseek(int file, int ptr, int dir) -{ - (void)file, (void)ptr, (void)dir; - return 0; -} - -/** - * \brief Replacement of C library of _exit - */ -extern void _exit(int status) -{ - printf("Exiting with status %d.\n", status); - - for (;;) - ; -} - -/** - * \brief Replacement of C library of _kill - */ -extern void _kill(int pid, int sig) -{ - (void)pid, (void)sig; - return; -} - -/** - * \brief Replacement of C library of _getpid - */ -extern int _getpid(void) -{ - return -1; -} - -#ifdef __cplusplus -} -#endif diff --git a/watch-library/hardware/hal/documentation/ext_irq.rst b/watch-library/hardware/hal/documentation/ext_irq.rst new file mode 100644 index 00000000..7dcdc7c5 --- /dev/null +++ b/watch-library/hardware/hal/documentation/ext_irq.rst @@ -0,0 +1,39 @@ +============== +EXT IRQ driver +============== + +The External Interrupt driver allows external pins to be +configured as interrupt lines. Each interrupt line can be +individually masked and can generate an interrupt on rising, +falling or both edges, or on high or low levels. Some of +external pin can also be configured to wake up the device +from sleep modes where all clocks have been disabled. +External pins can also generate an event. + +Features +-------- +* Initialization and de-initialization +* Enabling and disabling +* Detect external pins interrupt + +Applications +------------ +* Generate an interrupt on rising, falling or both edges, + or on high or low levels. + +Dependencies +------------ +* GPIO hardware + +Concurrency +----------- +N/A + +Limitations +----------- +N/A + +Knows issues and workarounds +---------------------------- +N/A + diff --git a/watch-library/hardware/hal/documentation/flash.rst b/watch-library/hardware/hal/documentation/flash.rst new file mode 100755 index 00000000..fcc86e63 --- /dev/null +++ b/watch-library/hardware/hal/documentation/flash.rst @@ -0,0 +1,52 @@ +The Flash Driver +================ + +Flash is a re-programmable memory that retains program and data +storage even with power off. + +User can write or read several bytes from any valid address in a flash. + +As to the erase/lock/unlock command, the input parameter of address should +be a bytes address aligned with the page start, otherwise, the command will fail +to be executed. At the meantime, the number of pages that can be locked or unlocked +at once depends on region size of the flash. User can get the real number +from the function return value which could be different for the different devices. + +Features +-------- + +* Initialization/de-initialization +* Writing/Reading bytes +* Locking/Unlocking/Erasing pages +* Notifications about errors or being ready for a new command + +Applications +------------ + +* Mini disk which can retain program and data storage +* Boot loader +* Non volatile storage + +Dependencies +------------ + +The peripheral which controls a re-programmable flash memory. + +Concurrency +----------- + +N/A + +Limitations +----------- + +User should pay attention to set a proper stack size in their application, +since the driver manages a temporary buffer in stack to cache unchanged data +when calling flash write and erase function. +Due to flash memory architecture of SAMD21/D20/L21/L22/C20/C21/D09/D10/D11/R21, +write operation erazes row content before each write. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/watch-library/hardware/hal/documentation/i2c_master_sync.rst b/watch-library/hardware/hal/documentation/i2c_master_sync.rst new file mode 100644 index 00000000..77b4f6e9 --- /dev/null +++ b/watch-library/hardware/hal/documentation/i2c_master_sync.rst @@ -0,0 +1,87 @@ +============================= +I2C Master synchronous driver +============================= + +I2C (Inter-Integrated Circuit) is a two wire serial interface usually used +for on-board low-speed bi-directional communication between controllers and +peripherals. The master device is responsible for initiating and controlling +all transfers on the I2C bus. Only one master device can be active on the I2C +bus at the time, but the master role can be transferred between devices on the +same I2C bus. I2C uses only two bidirectional open-drain lines, usually +designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up +resistors. + +The stop condition is automatically controlled by the driver if the I/O write and +read functions are used, but can be manually controlled by using the +i2c_m_sync_transfer function. + +Often a master accesses different information in the slave by accessing +different registers in the slave. This is done by first sending a message to +the target slave containing the register address, followed by a repeated start +condition (no stop condition between) ending with transferring register data. +This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read +function, but limited to 8-bit register addresses. + +I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in +Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to +stick within the SCL clock frequency range supported by the selected mode. +The requested SCL clock frequency is not validated by the +i2c_m_sync_set_baudrate function against the selected I2C mode. + +Features +-------- + + * I2C Master support + * Initialization and de-initialization + * Enabling and disabling + * Run-time bus speed configuration + * Write and read I2C messages + * Slave register access functions (limited to 8-bit address) + * Manual or automatic stop condition generation + * 10- and 7- bit addressing + * I2C Modes supported + +----------------------+-------------------+ + |* Standard/Fast mode | (SCL: 1 - 400kHz) | + +----------------------+-------------------+ + |* Fastmode+ | (SCL: 1 - 1000kHz)| + +----------------------+-------------------+ + |* Highspeed mode | (SCL: 1 - 3400kHz)| + +----------------------+-------------------+ + +Applications +------------ + +* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals +* Data communication between micro controllers +* Controlling displays + +Dependencies +------------ + +* I2C Master capable hardware + +Concurrency +----------- + +N/A + +Limitations +----------- + +General +^^^^^^^ + + * System Managmenet Bus (SMBus) not supported. + * Power Management Bus (PMBus) not supported. + +Clock considerations +^^^^^^^^^^^^^^^^^^^^ + +The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected. + +Known issues and workarounds +---------------------------- + +N/A + + diff --git a/watch-library/hardware/hal/documentation/rand_sync.rst b/watch-library/hardware/hal/documentation/rand_sync.rst new file mode 100755 index 00000000..19ec1d36 --- /dev/null +++ b/watch-library/hardware/hal/documentation/rand_sync.rst @@ -0,0 +1,43 @@ +========================================== +Random Number Generator Synchronous driver +========================================== + +Random Number Generator (RAND) generates a sequence of numbers that can not +be reasonably predicted better than by a random chance. + +In some implementation cases, seed is required for the Random Number Generator +to generate random numbers. rand_sync_set_seed is used to update the seed. +If it's actually not required by the generator implementation, the function just +returns ERR_UNSUPPORTED_OP. + +Features +-------- + +* Initialization and de-initialization +* Enabling and Disabling +* Setting seed +* 8-bit and 32-bit random data/data array generation + +Applications +------------ + +* Generate random keys for data encryption + +Dependencies +------------ + +* Random number generation hardware/software + +Concurrency +----------- +N/A + +Limitations +----------- + +N/A + +Known issues and workarounds +---------------------------- +N/A + diff --git a/watch-library/hardware/hal/documentation/slcd_sync.rst b/watch-library/hardware/hal/documentation/slcd_sync.rst new file mode 100644 index 00000000..e18aa9dd --- /dev/null +++ b/watch-library/hardware/hal/documentation/slcd_sync.rst @@ -0,0 +1,82 @@ + +SLCD Synchronous driver +======================= + +An LCD display is made of several segments (pixels or complete symbols) which +can be block light or let light through. In each segment is one electrode +connected to the common terminal (COM pin) and one is connected to the segment +terminal (SEG pin). When a voltage above a certain threshold level is applied +across the liquid crystal, it will change orientation and either let light +through or block it. + +The driver supports segment on/off/blink, animation and character display. + +Each segment has a unique int32 segment id which is used by the driver. The id is +combined by common number(COM) and segment number(SEG), the COM and SEG start from 0. +The unique segment id is calculated by this formula: (COM << 16) | SEG +For example a 8(coms)*8(segments)SLCD, the unique segment id for segment should be + + +-----+-----+---------+ + | COM | SEG | ID | + +-----+-----+---------+ + | 0 | 0 | 0x00000 | + +-----+-----+---------+ + | 1 | 0 | 0x10000 | + +-----+-----+---------+ + | 7 | 7 | 0x70007 | + +-----+-----+---------+ + +Segment ID can be calculated using the pre-defined macro SLCD_SEGID(com, seg). + +For character display, the "segment character mapping table" and "character mapping table" +should be setup in configuration. The driver have no API to setup/change those +mapping setting. +There are two pre-defined "segment character mapping table" in this driver, 7 segments +and 14 segments. The 7 segment character mapping can display 0-9 and a-f, the 14 +segments character mapping can display 0-9, A-Z and some special ASCII, for more +details please refer to hpl_slcd_cm_7_seg_mapping.h and hpl_slcd_cm_14_seg_mapping.h. +Application can also adjust this mapping table in the configuration header file, +to add more character mapping or remove some unused character. + +The "character mapping" is used to setup each character in SLCD display screen. +The driver supports multiple character mapping, the max number varies on different +MCU/MPU. For example if an LCD display screen has five "7-segments character" and +eight "14-segments character", and the MCU support max 44 characters setting, then +the 13 character should be setup in configuration. Application can select any +position from those 44 characters setting to save those 13 character. +The index of character setting will be used in the driver API. For example: +five "7-segments character" setting to 0 to 4 and eight "14-segments character" setting +to 10 to 17. Then the application can use index from 0 to 4 to display the +"7-segments character" and use index from 10 to 14 to display "14-segments character". + +Features +-------- + +* Initialization and de-initialization +* Enabling and Disabling +* Switching segment on/off +* Set segment blink +* Autonomous animation +* Character display + +Applications +------------ +* SLCD display control, segment on/off/blink +* Play battery animation, running wheel, wifi signal, etc. +* Display Time Clock by 7 segments character mapping +* Display ASCII character by 14 segments character mapping + +Dependencies +------------ +* SLCD capable hardware + +Concurrency +----------- +N/A + +Limitations +----------- + +Known issues and workarounds +---------------------------- +N/A diff --git a/watch-library/hardware/hal/documentation/spi_master_sync.rst b/watch-library/hardware/hal/documentation/spi_master_sync.rst new file mode 100755 index 00000000..4fbe45e2 --- /dev/null +++ b/watch-library/hardware/hal/documentation/spi_master_sync.rst @@ -0,0 +1,51 @@ +The SPI Master Synchronous Driver +================================= + +The serial peripheral interface (SPI) is a synchronous serial communication +interface. + +SPI devices communicate in full duplex mode using a master-slave +architecture with a single master. The master device originates the frame for +reading and writing. Multiple slave devices are supported through selection +with individual slave select (SS) lines. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * SPI mode + * Character size + * Data order +* Data transfer: transmission, reception and full-duplex + +Applications +------------ + +Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card, +LCD controller, etc. + +Dependencies +------------ + +SPI master capable hardware + +Concurrency +----------- + +N/A + +Limitations +----------- + +The slave select (SS) is not automatically inserted during read/write/transfer, +user must use I/O to control the devices' SS. + +Known issues and workarounds +---------------------------- + +N/A + diff --git a/watch-library/hardware/hal/documentation/usart_sync.rst b/watch-library/hardware/hal/documentation/usart_sync.rst new file mode 100755 index 00000000..15e4b138 --- /dev/null +++ b/watch-library/hardware/hal/documentation/usart_sync.rst @@ -0,0 +1,58 @@ +The USART Synchronous Driver +============================ + +The universal synchronous and asynchronous receiver and transmitter +(USART) is usually used to transfer data from one device to the other. + +User can set action for flow control pins by function usart_set_flow_control, +if the flow control is enabled. All the available states are defined in union +usart_flow_control_state. + +Note that user can set state of flow control pins only if automatic support of +the flow control is not supported by the hardware. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * UART or USRT communication mode + * Character size + * Data order + * Flow control +* Data transfer: transmission, reception + +Applications +------------ + +They are commonly used in a terminal application or low-speed communication +between devices. + +Dependencies +------------ + +USART capable hardware. + +Concurrency +----------- + +Write buffer should not be changed while data is being sent. + + +Limitations +----------- + +* The driver does not support 9-bit character size. +* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. + And the SCK pin can't be set directly. Application can use a GCLK output PIN + to generate SCK. For example to communicate with a SMARTCARD with ISO7816 + (F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be + config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/watch-library/hardware/hal/include/hal_atomic.h b/watch-library/hardware/hal/include/hal_atomic.h new file mode 100644 index 00000000..82151fc5 --- /dev/null +++ b/watch-library/hardware/hal/include/hal_atomic.h @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hal_calendar.h b/watch-library/hardware/hal/include/hal_calendar.h new file mode 100644 index 00000000..e69de29b diff --git a/watch-library/hardware/hal/include/hal_delay.h b/watch-library/hardware/hal/include/hal_delay.h new file mode 100644 index 00000000..9d4aa5c1 --- /dev/null +++ b/watch-library/hardware/hal/include/hal_delay.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hal_ext_irq.h b/watch-library/hardware/hal/include/hal_ext_irq.h new file mode 100644 index 00000000..a7c26005 --- /dev/null +++ b/watch-library/hardware/hal/include/hal_ext_irq.h @@ -0,0 +1,118 @@ +/** + * \file + * + * \brief External interrupt functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_EXT_IRQ_H_INCLUDED +#define _HAL_EXT_IRQ_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_ext_irq + * + * @{ + */ + +/** + * \brief External IRQ callback type + */ +typedef void (*ext_irq_cb_t)(void); + +/** + * \brief Initialize external IRQ component, if any + * + * \return Initialization status. + * \retval -1 External IRQ module is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t ext_irq_init(void); + +/** + * \brief Deinitialize external IRQ, if any + * + * \return De-initialization status. + * \retval -1 External IRQ module is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t ext_irq_deinit(void); + +/** + * \brief Register callback for the given external interrupt + * + * \param[in] pin Pin to enable external IRQ on + * \param[in] cb Callback function + * + * \return Registration status. + * \retval -1 Passed parameters were invalid + * \retval 0 The callback registration is completed successfully + */ +int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb); + +/** + * \brief Enable external IRQ + * + * \param[in] pin Pin to enable external IRQ on + * + * \return Enabling status. + * \retval -1 Passed parameters were invalid + * \retval 0 The enabling is completed successfully + */ +int32_t ext_irq_enable(const uint32_t pin); + +/** + * \brief Disable external IRQ + * + * \param[in] pin Pin to enable external IRQ on + * + * \return Disabling status. + * \retval -1 Passed parameters were invalid + * \retval 0 The disabling is completed successfully + */ +int32_t ext_irq_disable(const uint32_t pin); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t ext_irq_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_EXT_IRQ_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hal_flash.h b/watch-library/hardware/hal/include/hal_flash.h new file mode 100755 index 00000000..8216afde --- /dev/null +++ b/watch-library/hardware/hal/include/hal_flash.h @@ -0,0 +1,209 @@ +/** + * \file + * + * \brief Flash related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_FLASH_H_INCLUDED +#define _HAL_FLASH_H_INCLUDED + +#include + +/** + * \addtogroup doc_driver_hal_flash + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Forward declaration of flash_descriptor. */ +struct flash_descriptor; + +/** The callback types */ +enum flash_cb_type { + /** Callback type for ready to accept a new command */ + FLASH_CB_READY, + /** Callback type for error */ + FLASH_CB_ERROR, + FLASH_CB_N +}; + +/** \brief Prototype of callback on FLASH + * + */ +typedef void (*flash_cb_t)(struct flash_descriptor *const descr); + +/** \brief FLASH HAL callbacks + * + */ +struct flash_callbacks { + /** Callback invoked when ready to accept a new command */ + flash_cb_t cb_ready; + /** Callback invoked when error occurs */ + flash_cb_t cb_error; +}; + +/** \brief FLASH HAL driver struct for asynchronous access + */ +struct flash_descriptor { + /** Pointer to FLASH device instance */ + struct _flash_device dev; + /** Callbacks for asynchronous transfer */ + struct flash_callbacks callbacks; +}; + +/** \brief Initialize the FLASH HAL instance and hardware for callback mode + * + * Initialize FLASH HAL with interrupt mode (uses callbacks). + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] hw Pointer to the hardware base. + * \return Initialize status. + */ +int32_t flash_init(struct flash_descriptor *flash, void *const hw); + +/** \brief Deinitialize the FLASH HAL instance + * + * Abort transfer, disable and reset FLASH, and deinitialize software. + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \return Deinitialze status. + */ +int32_t flash_deinit(struct flash_descriptor *flash); + +/** \brief Writes a number of bytes to a page in the internal Flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to a buffer where the content + * will be written to the flash + * \param[in] length Number of bytes to write + * \return Write status. + */ +int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Appends a number of bytes to a page in the internal Flash + * + * This functions never erases the flash before writing. + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address to write to flash + * \param[in] buffer Pointer to a buffer with data to write to flash + * \param[in] length Number of bytes to append + * \return Append status. + */ +int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Reads a number of bytes to a page in the internal Flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] src_addr Source bytes address to read from flash + * \param[out] buffer Pointer to a buffer where the content + * of the read pages will be stored + * \param[in] length Number of bytes to read + * \return Read status. + */ +int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length); + +/** \brief Register a function as FLASH transfer completion callback + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] type Callback type (\ref flash_cb_type). + * \param[in] func Pointer to callback function. + * \retval 0 Success + * \retval -1 Error + */ +int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func); + +/** \brief Execute lock in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be locked + * \param[in] page_nums Number of pages to be locked + * + * \return Real locked numbers of pages. + */ +int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** \brief Execute unlock in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be unlocked + * \param[in] page_nums Number of pages to be unlocked + * + * \return Real unlocked numbers of pages. + */ +int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** \brief Execute erase in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be erased + * \param[in] page_nums Number of pages to be erased + * \retval 0 Success + * \retval -1 Error + */ +int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** + * \brief Get the flash page size + * + * \param[in, out] flash Pointer to the HAL FLASH instance + * + * \return The flash page size + */ +uint32_t flash_get_page_size(struct flash_descriptor *flash); + +/** + * \brief Get the number of flash page + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * + * \return The flash total page numbers + */ +uint32_t flash_get_total_pages(struct flash_descriptor *flash); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t flash_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* ifndef _HAL_FLASH_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hal_gpio.h b/watch-library/hardware/hal/include/hal_gpio.h new file mode 100644 index 00000000..fbfa2d4a --- /dev/null +++ b/watch-library/hardware/hal/include/hal_gpio.h @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor + * GPIO_PULL_UP = Pull pin high with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/watch-library/hardware/hal/include/hal_i2c_m_sync.h b/watch-library/hardware/hal/include/hal_i2c_m_sync.h new file mode 100644 index 00000000..f7772483 --- /dev/null +++ b/watch-library/hardware/hal/include/hal_i2c_m_sync.h @@ -0,0 +1,244 @@ +/** + * \file + * + * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_I2C_M_SYNC_H_INCLUDED +#define _HAL_I2C_M_SYNC_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_i2c_controller_sync + * + * @{ + */ + +#define I2C_M_MAX_RETRY 1 + +/** + * \brief I2C descriptor structure, embed i2c_device & i2c_interface + */ +struct i2c_m_sync_desc { + struct _i2c_m_sync_device device; + struct io_descriptor io; + uint16_t periph_addr; +}; + +/** + * \brief Initialize synchronous I2C interface + * + * This function initializes the given I/O descriptor to be used as a + * synchronous I2C interface descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + * \retval -1 The passed parameters were invalid or the interface is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw); + +/** + * \brief Deinitialize I2C interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Uninitialization status. + * \retval -1 The passed parameters were invalid or the interface is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c); + +/** + * \brief Set the peripheral device address + * + * This function sets the next transfer target peripheral I2C device address. + * It takes no effect to any already started access. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] addr The peripheral address to access + * \param[in] addr_len The peripheral address length, can be I2C_M_TEN or I2C_M_SEVEN + * + * \return Masked peripheral address. The mask is a maximum 10-bit address, and 10th + * bit is set if a 10-bit address is used + */ +int32_t i2c_m_sync_set_periphaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len); + +/** + * \brief Set baudrate + * + * This function sets the I2C device to the specified baudrate. + * It only takes effect when the hardware is disabled. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] clkrate Unused parameter. Should always be 0 + * \param[in] baudrate The baudrate value set to controller + * + * \return Whether successfully set the baudrate + * \retval -1 The passed parameters were invalid or the device is already enabled + * \retval 0 The baudrate set is completed successfully + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Sync version of enable hardware + * + * This function enables the I2C device, and then waits for this enabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully enable the device + * \retval -1 The passed parameters were invalid or the device enable failed + * \retval 0 The hardware enabling is completed successfully + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of disable hardware + * + * This function disables the I2C device and then waits for this disabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully disable the device + * \retval -1 The passed parameters were invalid or the device disable failed + * \retval 0 The hardware disabling is completed successfully + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of write command to I2C peripheral + * + * This function will write the value to a specified register in the I2C peripheral device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C peripheral device + * \param[in] buffer The buffer holding data to write to the I2C peripheral device + * \param[in] length The length (in bytes) to write to the I2C peripheral device + * + * \return Whether successfully write to the device + * \retval <0 The passed parameters were invalid or write fail + * \retval 0 Writing to register is completed successfully + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of read register value from I2C peripheral + * + * This function will read a byte value from a specified register in the I2C peripheral device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C peripheral device + * \param[in] buffer The buffer to hold the read data from the I2C peripheral device + * \param[in] length The length (in bytes) to read from the I2C peripheral device + * + * \return Whether successfully read from the device + * \retval <0 The passed parameters were invalid or read fail + * \retval 0 Reading from register is completed successfully + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of transfer message to/from the I2C peripheral + * + * This function will transfer a message between the I2C peripheral and the controller. + * This function will wait for the operation to be done. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] msg An i2c_m_msg struct + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg); + +/** + * \brief Sync version of send stop condition on the i2c bus + * + * This function will create a stop condition on the i2c bus to release the bus + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c); + +/** + * \brief Return I/O descriptor for this I2C instance + * + * This function will return a I/O instance for this I2C driver instance + * + * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C + * \param[in] io_descriptor A pointer to an I/O descriptor pointer type + * + * \return Error code + * \retval 0 No error detected + * \retval <0 Error code + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t i2c_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/watch-library/hardware/hal/include/hal_init.h b/watch-library/hardware/hal/include/hal_init.h new file mode 100644 index 00000000..d7bc6fe2 --- /dev/null +++ b/watch-library/hardware/hal/include/hal_init.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hal_io.h b/watch-library/hardware/hal/include/hal_io.h new file mode 100644 index 00000000..f50401d7 --- /dev/null +++ b/watch-library/hardware/hal/include/hal_io.h @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hal_rand_sync.h b/watch-library/hardware/hal/include/hal_rand_sync.h new file mode 100755 index 00000000..9f8cc31e --- /dev/null +++ b/watch-library/hardware/hal/include/hal_rand_sync.h @@ -0,0 +1,134 @@ +/** + * \file + * + * \brief Generic Random Number Generator (RAND) functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_RAND_SYNC_H_INCLUDED +#define _HAL_RAND_SYNC_H_INCLUDED + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_rand_sync + * + *@{ + */ + +/** Random Number Generator polling device. */ +struct rand_sync_desc { + struct _rand_sync_dev dev; +}; + +/** + * \brief Initialize the Random Number Generator Driver + * \param[out] desc Pointer to the device descriptor instance struct + * \param[in, out] hw Pointer to the hardware for device instance + * \return Initialization operation result status, ERR_NONE (0) for OK. + */ +int32_t rand_sync_init(struct rand_sync_desc *const desc, void *const hw); + +/** + * \brief Deinitialize the Random Number Generator Driver + * \param[out] desc Pointer to the device descriptor instance struct + */ +void rand_sync_deinit(struct rand_sync_desc *const desc); + +/** + * \brief Enable the Random Number Generator Driver + * \param[out] desc Pointer to the device descriptor instance struct + * \return Enable operation result status, ERR_NONE (0) for OK. + */ +int32_t rand_sync_enable(struct rand_sync_desc *const desc); + +/** + * \brief Disable the Random Number Generator Driver + * \param[out] desc Pointer to the device descriptor instance struct + */ +void rand_sync_disable(struct rand_sync_desc *const desc); + +/** + * \brief Set seed for the Random Number Generator Driver + * \param[out] desc Pointer to the device descriptor instance struct + */ +int32_t rand_sync_set_seed(struct rand_sync_desc *const desc, const uint32_t seed); + +/** + * \brief Read the 8-bit Random Number + * \param[in] desc Pointer to the device descriptor instance struct + * \return The random number generated + */ +uint8_t rand_sync_read8(const struct rand_sync_desc *const desc); + +/** + * \brief Read the 32-bit Random Number + * \param[in] desc Pointer to the device descriptor instance struct + * \return The random number generated + */ +uint32_t rand_sync_read32(const struct rand_sync_desc *const desc); + +/** + * \brief Read the 8-bit Random Number Sequence into a buffer + * \param[in] desc Pointer to the device descriptor instance struct + * \param[out] buf Pointer to the buffer to fill an array of generated numbers + * \param[in] len Number of random numbers to read + */ +void rand_sync_read_buf8(const struct rand_sync_desc *const desc, uint8_t *buf, uint32_t len); + +/** + * \brief Read the 32-bit Random Number Sequence into a buffer + * \param[in] desc Pointer to the device descriptor instance struct + * \param[out] buf Pointer to the buffer to fill an array of generated numbers + * \param[in] len Number of random numbers to read + */ +void rand_sync_read_buf32(const struct rand_sync_desc *const desc, uint32_t *buf, uint32_t len); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t rand_sync_get_version(void); + +/* I/O read will be used to get random data. */ + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_RAND_SYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hal_slcd_sync.h b/watch-library/hardware/hal/include/hal_slcd_sync.h new file mode 100644 index 00000000..84c4e1f9 --- /dev/null +++ b/watch-library/hardware/hal/include/hal_slcd_sync.h @@ -0,0 +1,168 @@ +/** + * \file + * + * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality + * declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HAL_SLCD_SYNC_H_INCLUDED +#define HAL_SLCD_SYNC_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_slcd_sync + * + *@{ + */ + +struct slcd_sync_descriptor { + struct _slcd_sync_device dev; /*!< SLCD HPL device descriptor */ +}; + +/** + * \brief Initialize SLCD Descriptor + * + * \param[in] descr SLCD descriptor to be initialized + * \param[in] hw The pointer to hardware instance + */ +int32_t slcd_sync_init(struct slcd_sync_descriptor *const descr, void *const hw); + +/** + * \brief Deinitialize SLCD Descriptor + * + * \param[in] descr SLCD descriptor to be deinitialized + */ +int32_t slcd_sync_deinit(struct slcd_sync_descriptor *const descr); + +/** + * \brief Enable SLCD driver + * + * \param[in] descr SLCD descriptor to be initialized + */ +int32_t slcd_sync_enable(struct slcd_sync_descriptor *const descr); + +/** + * \brief Disable SLCD driver + * + * \param[in] descr SLCD descriptor to be disabled + */ +int32_t slcd_sync_disable(struct slcd_sync_descriptor *const descr); + +/** + * \brief Turn on a Segment + * + * \param[in] descr SLCD descriptor to be enabled + * \param[in] seg Segment index. The segment index is by the combination + * of common and segment terminal index. The + * SLCD_SEGID(com, seg) macro can generate the index. + */ +int32_t slcd_sync_seg_on(struct slcd_sync_descriptor *const descr, uint32_t seg); + +/** + * \brief Turn off a Segment + * + * \param[in] descr SLCD descriptor + * \param[in] seg Segment index + * value is "(common terminals << 16 | segment terminal)" + */ +int32_t slcd_sync_seg_off(struct slcd_sync_descriptor *const descr, uint32_t seg); + +/** + * \brief Blink a Segment + * + * \param[in] descr SLCD descriptor + * \param[in] seg Segment index + * value is "(common terminals << 16 | segment terminal)" + * \param[in] period Blink period, unit is millisecond + */ +int32_t slcd_sync_seg_blink(struct slcd_sync_descriptor *const descr, uint32_t seg, const uint32_t period); + +/** + * \brief Displays a character + * + * \param[in] descr SLCD descriptor + * \param[in] character Character to be displayed + * \param[in] index Index of the character Mapping Group + */ +int32_t slcd_sync_write_char(struct slcd_sync_descriptor *const descr, const uint8_t character, uint32_t index); + +/** + * \brief Displays character string string + * + * \param[in] descr SLCD descriptor + * \param[in] str String to be displayed, 0 will turn off the + * corresponding char to display + * \param[in] len Length of the string array + * \param[in] index Index of the character Mapping Group + */ +int32_t slcd_sync_write_string(struct slcd_sync_descriptor *const descr, uint8_t *const str, uint32_t len, + uint32_t index); + +/** + * \brief Start animation play by a segment array + * + * \param[in] descr SLCD descriptor + * \param[in] segs Segment array + * \param[in] len Length of the segment array + * \param[in] period Period (milliseconds) of each segment to animation + */ +int32_t slcd_sync_start_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len, + const uint32_t period); + +/** + * \brief Stop animation play by a segment array + * + * \param[in] descr SLCD descriptor + * \param[in] segs Segment array + * \param[in] len Length of the segment array + */ +int32_t slcd_sync_stop_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len); + +/** + * \brief Set animation Frequency + * + * \param[in] descr SLCD descriptor + * \param[in] period Period (million second) of each segment to animation + */ +int32_t slcd_sync_set_animation_period(struct slcd_sync_descriptor *const descr, const uint32_t period); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/watch-library/hardware/hal/include/hal_sleep.h b/watch-library/hardware/hal/include/hal_sleep.h new file mode 100644 index 00000000..b90ef6a5 --- /dev/null +++ b/watch-library/hardware/hal/include/hal_sleep.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hal_spi_m_sync.h b/watch-library/hardware/hal/include/hal_spi_m_sync.h new file mode 100755 index 00000000..5d040558 --- /dev/null +++ b/watch-library/hardware/hal/include/hal_spi_m_sync.h @@ -0,0 +1,221 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SPI_M_SYNC_H_INCLUDED +#define _HAL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup doc_driver_hal_spi_master_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief SPI HAL driver struct for polling mode + * + */ +struct spi_m_sync_descriptor { + struct _spi_m_sync_hpl_interface *func; + /** SPI device instance */ + struct _spi_sync_dev dev; + /** I/O read/write */ + struct io_descriptor io; + /** Flags for HAL driver */ + uint16_t flags; +}; + +/** \brief Set the SPI HAL instance function pointer for HPL APIs. + * + * Set SPI HAL instance function pointer for HPL APIs. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] func Pointer to the HPL api structure. + * + */ +void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func); + +/** \brief Initialize SPI HAL instance and hardware for polling mode + * + * Initialize SPI HAL with polling mode. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] hw Pointer to the hardware base. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_INVALID_DATA Error, initialized. + */ +int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw); + +/** \brief Deinitialize the SPI HAL instance and hardware + * + * Abort transfer, disable and reset SPI, deinit software. + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi); + +/** \brief Enable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_enable(struct spi_m_sync_descriptor *spi); + +/** \brief Disable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_disable(struct spi_m_sync_descriptor *spi); + +/** \brief Set SPI baudrate + * + * Works if SPI is initialized as master, it sets the baudrate. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] baud_val The target baudrate value + * (see "baudrate calculation" for calculating the value). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The baudrate is not supported. + */ +int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val); + +/** \brief Set SPI mode + * + * Set the SPI transfer mode (\ref spi_transfer_mode), + * which controls the clock polarity and clock phase: + * - Mode 0: leading edge is rising edge, data sample on leading edge. + * - Mode 1: leading edge is rising edge, data sample on trailing edge. + * - Mode 2: leading edge is falling edge, data sample on leading edge. + * - Mode 3: leading edge is falling edge, data sample on trailing edge. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] mode The mode (0~3). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The mode is not supported. + */ +int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode); + +/** \brief Set SPI transfer character size in number of bits + * + * The character size (\ref spi_char_size) influence the way the data is + * sent/received. + * For char size <= 8-bit, data is stored byte by byte. + * For char size between 9-bit ~ 16-bit, data is stored in 2-byte length. + * Note that the default and recommended char size is 8-bit since it's + * supported by all system. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] char_size The char size (~16, recommended 8). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The char size is not supported. + */ +int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size); + +/** \brief Set SPI transfer data order + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] dord The data order: send LSB/MSB first. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The data order is not supported. + */ +int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord); + +/** \brief Perform the SPI data transfer (TX and RX) in polling way + * + * Activate CS, do TX and RX and deactivate CS. It blocks. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[in] xfer Pointer to the transfer information (\ref spi_xfer). + * + * \retval size Success. + * \retval >=0 Timeout, with number of characters transferred. + * \retval ERR_BUSY SPI is busy + */ +int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer); + +/** + * \brief Return the I/O descriptor for this SPI instance + * + * This function will return an I/O instance for this SPI driver instance. + * + * \param[in] spi An SPI master descriptor, which is used to communicate through + * SPI + * \param[in, out] io A pointer to an I/O descriptor pointer type + * + * \retval ERR_NONE + */ +int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t spi_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hal_usart_sync.h b/watch-library/hardware/hal/include/hal_usart_sync.h new file mode 100755 index 00000000..1ef22fc6 --- /dev/null +++ b/watch-library/hardware/hal/include/hal_usart_sync.h @@ -0,0 +1,247 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SYNC_USART_H_INCLUDED +#define _HAL_SYNC_USART_H_INCLUDED + +#include "hal_io.h" +#include + +/** + * \addtogroup doc_driver_hal_usart_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Synchronous USART descriptor + */ +struct usart_sync_descriptor { + struct io_descriptor io; + struct _usart_sync_device device; +}; + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used + * as USART interface descriptor. + * It checks if the given hardware is not initialized and + * if the given hardware is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via USART + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to as set of functions pointers + * + * \return Initialization status. + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and + * if the given hardware is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of the I/O descriptor retrieving. + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Specify action for flow control pins + * + * This function sets the action (or state) for the flow control pins + * if the flow control is enabled. + * It sets the state of flow control pins only if the automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins + * if the flow control is enabled. + * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_sync_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_calendar.h b/watch-library/hardware/hal/include/hpl_calendar.h new file mode 100644 index 00000000..0dce40fd --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_calendar.h @@ -0,0 +1,75 @@ +/** + * \file + * + * \brief Generic CALENDAR functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_CALENDER_H_INCLUDED +#define _HPL_CALENDER_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Time struct for calendar + */ +struct calendar_time { + /*range from 0 to 59*/ + uint8_t sec; + /*range from 0 to 59*/ + uint8_t min; + /*range from 0 to 23*/ + uint8_t hour; +}; + +/** + * \brief Time struct for calendar + */ +struct calendar_date { + /*range from 1 to 28/29/30/31*/ + uint8_t day; + /*range from 1 to 12*/ + uint8_t month; + /*absolute year>= 1970(such as 2000)*/ + uint16_t year; +}; + +/** \brief Date&Time struct for calendar + */ +struct calendar_date_time { + struct calendar_time time; + struct calendar_date date; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_RTC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_core.h b/watch-library/hardware/hal/include/hpl_core.h new file mode 100644 index 00000000..9324c43e --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_core.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_delay.h b/watch-library/hardware/hal/include/hpl_delay.h new file mode 100644 index 00000000..a0f1ac81 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_delay.h @@ -0,0 +1,97 @@ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_dma.h b/watch-library/hardware/hal/include/hpl_dma.h new file mode 100644 index 00000000..1e08434a --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_dma.h @@ -0,0 +1,176 @@ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Set next descriptor address + * + * \param[in] current_channel Current DMA channel to set next descriptor address + * \param[in] next_channel Next DMA channel used as next descriptor + * + * \return setting status + */ +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Enable/disable Destination address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set destination address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_ext_irq.h b/watch-library/hardware/hal/include/hpl_ext_irq.h new file mode 100644 index 00000000..3a169b69 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_ext_irq.h @@ -0,0 +1,95 @@ +/** + * \file + * + * \brief External IRQ related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_EXT_IRQ_H_INCLUDED +#define _HPL_EXT_IRQ_H_INCLUDED + +/** + * \addtogroup HPL EXT IRQ + * + * \section hpl_ext_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize external interrupt module + * + * This function does low level external interrupt configuration. + * + * \param[in] cb The pointer to callback function from external interrupt + * + * \return Initialization status. + * \retval -1 External irq module is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t _ext_irq_init(void (*cb)(const uint32_t pin)); + +/** + * \brief Deinitialize external interrupt module + * + * \return Initialization status. + * \retval -1 External irq module is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t _ext_irq_deinit(void); + +/** + * \brief Enable / disable external irq + * + * \param[in] pin Pin to enable external irq on + * \param[in] enable True to enable, false to disable + * + * \return Status of external irq enabling / disabling + * \retval -1 External irq module can't be enabled / disabled + * \retval 0 External irq module is enabled / disabled successfully + */ +int32_t _ext_irq_enable(const uint32_t pin, const bool enable); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_EXT_IRQ_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_flash.h b/watch-library/hardware/hal/include/hpl_flash.h new file mode 100755 index 00000000..3a42c448 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_flash.h @@ -0,0 +1,265 @@ +/** + * \file + * + * \brief FLASH related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_FLASH_H_INCLUDED +#define _HPL_FLASH_H_INCLUDED + +/** + * \addtogroup hpl__flash__group FLASH HPL APIs + * + */ + +/**@{*/ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief FLASH device structure + * + * The FLASH device structure forward declaration. + */ +struct _flash_device; + +/** The callback types */ +enum _flash_cb_type { FLASH_DEVICE_CB_READY, FLASH_DEVICE_CB_ERROR, FLASH_DEVICE_CB_N }; + +/** + * \brief FLASH interrupt handlers structure + */ +struct _flash_callback { + /** Ready to accept new command handler */ + void (*ready_cb)(struct _flash_device *device); + /** Error handler */ + void (*error_cb)(struct _flash_device *device); +}; + +/** + * \brief FLASH descriptor device structure. + */ +struct _flash_device { + struct _flash_callback flash_cb; /*!< Interrupt handers */ + struct _irq_descriptor irq; /*!< Interrupt descriptor */ + void * hw; /*!< Hardware module instance handler */ +}; + +/** + * \brief Initialize FLASH. + * + * This function does low level FLASH configuration. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialize status. + */ +int32_t _flash_init(struct _flash_device *const device, void *const hw); + +/** + * \brief Deinitialize FLASH. + * + * \param[in] device The pointer to FLASH device instance + */ +void _flash_deinit(struct _flash_device *const device); + +/** + * \brief Reads a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] src_addr Source bytes address to read from flash + * \param[out] buffer Pointer to a buffer where the content + * of the read page will be stored + * \param[in] length Number of bytes to read + */ +void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length); + +/** + * \brief Writes a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to buffer where the data to + * write is stored + * \param[in] length Number of bytes to write + */ +void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** + * \brief Appends a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to buffer with data to write to flash + * \param[in] length Number of bytes to write + */ +void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Execute lock in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be locked + * \param[in] page_nums Number of pages to be locked + * + * \return Real locked numbers of pages. + */ +int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** \brief Execute unlock in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be unlocked + * \param[in] page_nums Number of pages to be unlocked + * + * \return Real unlocked numbers of pages. + */ +int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** \brief check whether the region which is pointed by address + * is locked + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to check + * + * \return The lock status of assigned address. + */ +bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr); + +/** \brief Execute erase in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be erased + * \param[in] page_nums Number of pages to be erased + */ +void _flash_erase(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** + * \brief Get the flash page size. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash page size + */ +uint32_t _flash_get_page_size(struct _flash_device *const device); + +/** + * \brief Get the numbers of flash page. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash total page numbers + */ +uint32_t _flash_get_total_pages(struct _flash_device *const device); + +/** + * \brief Get the number of wait states for read and write operations. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The number of wait states for read and write operations + */ +uint8_t _flash_get_wait_state(struct _flash_device *const device); + +/** + * \brief Set the number of wait states for read and write operations. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] state The number of wait states + * + */ +void _flash_set_wait_state(struct _flash_device *const device, uint8_t state); + +/** + * \brief Enable/disable Flash interrupt + * + * param[in] device The pointer to Flash device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state); + +/* + * Below RWW flash APIs are only available for device which has RWWEE + * flash array, such as SAM C20/C21/D21/L21/L22/R30/DA1/HA1 etc. + */ +/** + * \brief Get the RWWEE flash page size. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash page size + */ +uint32_t _rww_flash_get_page_size(struct _flash_device *const device); + +/** + * \brief Get the total page numbers of RWWEE flash. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash total page numbers + */ +uint32_t _rww_flash_get_total_pages(struct _flash_device *const device); + +/** + * \brief Reads a number of bytes in the internal RWWEE Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] src_addr Source bytes address to read from flash + * \param[out] buffer Pointer to a buffer where the content + * of the read page will be stored + * \param[in] length Number of bytes to read + * + * \return Read status, ERR_NONE for successful read. + */ +int32_t _rww_flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length); + +/** + * \brief Writes a number of bytes in the internal RWWEE Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to buffer where the data to + * write is stored + * \param[in] length Number of bytes to write + * + * \return Write status, ERR_NONE for successful write. + */ +int32_t _rww_flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* _HPL_FLASH_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_gpio.h b/watch-library/hardware/hal/include/hpl_gpio.h new file mode 100644 index 00000000..5cdd387b --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_gpio.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_i2c_m_async.h b/watch-library/hardware/hal/include/hpl_i2c_m_async.h new file mode 100644 index 00000000..8a9491de --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_i2c_m_async.h @@ -0,0 +1,205 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED +#define _HPL_I2C_M_ASYNC_H_INCLUDED + +#include "hpl_i2c_m_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c master callback names + */ +enum _i2c_m_async_callback_type { + I2C_M_ASYNC_DEVICE_ERROR, + I2C_M_ASYNC_DEVICE_TX_COMPLETE, + I2C_M_ASYNC_DEVICE_RX_COMPLETE +}; + +struct _i2c_m_async_device; + +typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); +typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); + +/** + * \brief i2c callback pointers structure + */ +struct _i2c_m_async_callback { + _i2c_error_cb_t error; + _i2c_complete_cb_t tx_complete; + _i2c_complete_cb_t rx_complete; +}; + +/** + * \brief i2c device structure + */ +struct _i2c_m_async_device { + struct _i2c_m_service service; + void * hw; + struct _i2c_m_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C in interrupt mode + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c interrupt device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C in interrupt mode + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Register callback to I2C + * + * This function does low level I2C callback register. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] cb_type The callback type request + * \param[in] func The callback function pointer + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, + FUNC_PTR func); + +/** + * \brief Generate stop condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Operation status + * \retval 0 Operation executed successfully + * \retval <0 Operation failed + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Returns the number of bytes left or not used in the I2C message buffer + * + * This function will return the number of bytes left (not written to the bus) or still free + * (not received from the bus) in the message buffer, depending on direction of transmission. + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Number of bytes or error code + * \retval >0 Positive number indicating bytes left + * \retval 0 Buffer is full/empty depending on direction + * \retval <0 Error code + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable/disable I2C master interrupt + * + * param[in] device The pointer to I2C master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/watch-library/hardware/hal/include/hpl_i2c_m_sync.h b/watch-library/hardware/hal/include/hpl_i2c_m_sync.h new file mode 100644 index 00000000..ce173ae2 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_i2c_m_sync.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_SYNC_H_INCLUDED +#define _HPL_I2C_M_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c flags + */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_BUSY 0x0100 +#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ +#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ +#define I2C_M_FAIL 0x1000 +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * \brief i2c Return codes + */ +#define I2C_OK 0 /* Operation successful */ +#define I2C_ACK -1 /* Received ACK from device on I2C bus */ +#define I2C_NACK -2 /* Received NACK from device on I2C bus */ +#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ +#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ +#define I2C_ERR_BUS -5 /* Bus error */ +#define I2C_ERR_BUSY -6 /* Device busy */ +#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ + +/** + * \brief i2c I2C Modes + */ +#define I2C_STANDARD_MODE 0x00 +#define I2C_FASTMODE 0x01 +#define I2C_HIGHSPEED_MODE 0x02 + +/** + * \brief i2c master message structure + */ +struct _i2c_m_msg { + uint16_t addr; + volatile uint16_t flags; + int32_t len; + uint8_t * buffer; +}; + +/** + * \brief i2c master service + */ +struct _i2c_m_service { + struct _i2c_m_msg msg; + uint16_t mode; + uint16_t trise; +}; + +/** + * \brief i2c sync master device structure + */ +struct _i2c_m_sync_device { + struct _i2c_m_service service; + void * hw; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Send send condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_dev The pointer to i2c device struct + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/watch-library/hardware/hal/include/hpl_i2c_s_async.h b/watch-library/hardware/hal/include/hpl_i2c_s_async.h new file mode 100644 index 00000000..92a5765d --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_i2c_s_async.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED +#define _HPL_I2C_S_ASYNC_H_INCLUDED + +#include "hpl_i2c_s_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c callback types + */ +enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; + +/** + * \brief Forward declaration of I2C Slave device + */ +struct _i2c_s_async_device; + +/** + * \brief i2c slave callback function type + */ +typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); + +/** + * \brief i2c slave callback pointers structure + */ +struct _i2c_s_async_callback { + void (*error)(struct _i2c_s_async_device *const device); + void (*tx)(struct _i2c_s_async_device *const device); + void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); +}; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_async_device { + void * hw; + struct _i2c_s_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize asynchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c interrupt device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); + +/** + * \brief Deinitialize asynchronous I2C in interrupt mode + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); + +/** + * \brief Abort data transmission + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); + +/** + * \brief Enable/disable I2C slave interrupt + * + * param[in] device The pointer to I2C slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool disable); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_i2c_s_sync.h b/watch-library/hardware/hal/include/hpl_i2c_s_sync.h new file mode 100644 index 00000000..93b59345 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_i2c_s_sync.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_SYNC_H_INCLUDED +#define _HPL_I2C_S_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I2C Slave status type + */ +typedef uint32_t i2c_s_status_t; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_sync_device { + void *hw; +}; + +#include + +/** + * \name HPL functions + */ + +/** + * \brief Initialize synchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize synchronous I2C slave + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); + +/** + * \brief Clear the Data Ready interrupt flag + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); + +/** + * \brief Read a byte from the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Data received via I2C interface. + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if I2C is ready to send next byte + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the ready check. + * \retval true if the I2C is ready to send next byte + * \retval false if the I2C is not ready to send next byte + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if there is data received by I2C + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the data received check. + * \retval true if the I2C has received a byte + * \retval false if the I2C has not received a byte + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_init.h b/watch-library/hardware/hal/include/hpl_init.h new file mode 100644 index 00000000..71bf49c9 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_init.h @@ -0,0 +1,124 @@ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_irq.h b/watch-library/hardware/hal/include/hpl_irq.h new file mode 100644 index 00000000..2894944a --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_irq.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_missing_features.h b/watch-library/hardware/hal/include/hpl_missing_features.h new file mode 100644 index 00000000..7071db29 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_missing_features.h @@ -0,0 +1,37 @@ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/watch-library/hardware/hal/include/hpl_rand_sync.h b/watch-library/hardware/hal/include/hpl_rand_sync.h new file mode 100755 index 00000000..5fdf1340 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_rand_sync.h @@ -0,0 +1,99 @@ +/** + * \file + * + * \brief Random Number Generator (RAND) related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RAND_SYNC_H_INCLUDED +#define _HPL_RAND_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Random Number Generator polling device. */ +struct _rand_sync_dev { + /** Pointer to private data or hardware base */ + void *prvt; + /** Number of bits generated for each read operation */ + uint8_t n_bits; +}; + +/** + * \brief Initialize the Random Number Generator Driver + * \param[out] dev Pointer to the device instance struct + * \param[in, out] hw Pointer to the hardware for device instance + * \return Initialization operation result status, 0 for OK. + */ +int32_t _rand_sync_init(struct _rand_sync_dev *const dev, void *const hw); + +/** + * \brief Deinitialize the Random Number Generator Driver + * \param[in, out] dev Pointer to the device instance struct + */ +void _rand_sync_deinit(struct _rand_sync_dev *const dev); + +/** + * \brief Enable the Random Number Generator Driver + * \param[out] dev Pointer to the device instance struct + * \return Enable operation result status, 0 for OK. + */ +int32_t _rand_sync_enable(struct _rand_sync_dev *const dev); + +/** + * \brief Disable the Random Number Generator Driver + * \param[out] dev Pointer to the device instance struct + */ +void _rand_sync_disable(struct _rand_sync_dev *const dev); + +/** + * \brief Set seed for the Random Number Generator Driver + * \param[out] dev Pointer to the device instance struct + * \param[in] seed The seed to set + * \return Operation result + * \retval ERR_NONE Operation complete success + * \retval ERR_UNSUPPORTED_OP Seed not supported + */ +int32_t _rand_sync_set_seed(struct _rand_sync_dev *const dev, const uint32_t seed); + +/** + * \brief Polling random number until it's read back + * \param[in] dev Pointer to the device instance struct + * \return The random number value + */ +uint32_t _rand_sync_read_one(const struct _rand_sync_dev *const dev); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RAND_SYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_reset.h b/watch-library/hardware/hal/include/hpl_reset.h new file mode 100644 index 00000000..75738b6f --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_reset.h @@ -0,0 +1,92 @@ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + RESET_REASON_POR = 1, + RESET_REASON_BOD12 = 2, + RESET_REASON_BOD33 = 4, + RESET_REASON_EXT = 16, + RESET_REASON_WDT = 32, + RESET_REASON_SYST = 64, + RESET_REASON_BACKUP = 128 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_slcd.h b/watch-library/hardware/hal/include/hpl_slcd.h new file mode 100644 index 00000000..f3ccbbcd --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_slcd.h @@ -0,0 +1,49 @@ +/** + * \file + * + * \brief SLCD common declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_SLCD_H_INCLUDED +#define HPL_SLCD_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#define SLCD_SEGID(com, seg) (((com) << 16) | (seg)) +#define SLCD_COMNUM(segid) (((segid) >> 16) & 0xFF) +#define SLCD_SEGNUM(segid) ((segid)&0xFF) + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_SLCD_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_slcd_sync.h b/watch-library/hardware/hal/include/hpl_slcd_sync.h new file mode 100644 index 00000000..2f5a05d7 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_slcd_sync.h @@ -0,0 +1,154 @@ +/** + * \file + * + * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality + * declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_SLCD_SYNC_H_INCLUDED +#define HPL_SLCD_SYNC_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SLCD sync device structure + * + * The SLCD device structure forward declaration. + */ +struct _slcd_sync_device; + +struct _slcd_sync_device { + void *hw; /*!< Hardware module instance handler */ +}; + +/** + * \brief Initialize SLCD Device Descriptor + * + * \param[in] desc SLCD descriptor to be initialized + * \param[in] hw The pointer to hardware instance + */ +int32_t _slcd_sync_init(struct _slcd_sync_device *const dev, void *const hw); + +/** + * \brief Deinitialize SLCD Device Descriptor + * + * \param[in] desc SLCD device descriptor to be deinitialized + */ +int32_t _slcd_sync_deinit(struct _slcd_sync_device *const dev); + +/** + * \brief Enable SLCD driver + * + * \param[in] dev SLCD device descriptor to be enabled + */ +int32_t _slcd_sync_enable(struct _slcd_sync_device *const dev); + +/** + * \brief Disable SLCD driver + * + * \param[in] dev SLCD Device descriptor to be disabled + */ +int32_t _slcd_sync_disable(struct _slcd_sync_device *const dev); + +/** + * \brief Turn on a Segment + * + * \param[in] dev SLCD Device descriptor + * \param[in] seg Segment id + * value is (common terminals << 16 | segment terminal) + */ +int32_t _slcd_sync_seg_on(struct _slcd_sync_device *const dev, uint32_t seg); + +/** + * \brief Turn off a Segment + * + * \param[in] dev SLCD Device descriptor + * \param[in] seg Segment id + * value is (common terminals << 16 | segment terminal) + */ +int32_t _slcd_sync_seg_off(struct _slcd_sync_device *const dev, uint32_t seg); + +/** + * \brief Blink a Segment + * + * \param[in] dev SLCD Device descriptor + * \param[in] seg Segment index + * value is (common terminals << 16 | segment terminal) + * \param[in] period Blink period, unit is million second + */ +int32_t _slcd_sync_seg_blink(struct _slcd_sync_device *const dev, uint32_t seg, const uint32_t period); + +/** + * \brief Displays a character + * + * \param[in] dev SLCD Device descriptor + * \param[in] character Character to be displayed + * \param[in] index Index of Character Mapping Group + */ +int32_t _slcd_sync_write_char(struct _slcd_sync_device *const dev, const uint8_t character, uint32_t index); + +/** + * \brief Start animation play by a segment array + * + * \param[in] dev SLCD Device descriptor + * \param[in] segs Segment array + * \param[in] len Length of the segment array + * \param[in] period Period(milliseconds) of the each segment to animation + */ +int32_t _slcd_sync_start_animation(struct _slcd_sync_device *const dev, const uint32_t segs[], uint32_t len, + const uint32_t period); + +/** + * \brief Stop animation play by a segment array + * + * \param[in] dev SLCD device descriptor + * \param[in] segs Segment array + * \param[in] len Length of the segment array + */ +int32_t _slcd_sync_stop_animation(struct _slcd_sync_device *const dev, const uint32_t segs[], uint32_t len); + +/** + * \brief Set animation Frequency + * + * \param[in] dev SLCD Device descriptor + * \param[in] period Period(million second) of the each segment to animation + */ +int32_t _slcd_sync_set_animation_period(struct _slcd_sync_device *const dev, const uint32_t period); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/watch-library/hardware/hal/include/hpl_sleep.h b/watch-library/hardware/hal/include/hpl_sleep.h new file mode 100644 index 00000000..6731ec30 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_sleep.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_spi.h b/watch-library/hardware/hal/include/hpl_spi.h new file mode 100644 index 00000000..a5652e50 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_spi.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_H_INCLUDED +#define _HPL_SPI_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SPI Dummy char is used when reading data from the SPI slave + */ +#define SPI_DUMMY_CHAR 0x1ff + +/** + * \brief SPI message to let driver to process + */ +//@{ +struct spi_msg { + /** Pointer to the output data buffer */ + uint8_t *txbuf; + /** Pointer to the input data buffer */ + uint8_t *rxbuf; + /** Size of the message data in SPI characters */ + uint32_t size; +}; +//@} + +/** + * \brief SPI transfer modes + * SPI transfer mode controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + */ +enum spi_transfer_mode { + /** Leading edge is rising edge, data sample on leading edge. */ + SPI_MODE_0, + /** Leading edge is rising edge, data sample on trailing edge. */ + SPI_MODE_1, + /** Leading edge is falling edge, data sample on leading edge. */ + SPI_MODE_2, + /** Leading edge is falling edge, data sample on trailing edge. */ + SPI_MODE_3 +}; + +/** + * \brief SPI character sizes + * The character size influence the way the data is sent/received. + * For char size <= 8 data is stored byte by byte. + * For char size between 9 ~ 16 data is stored in 2-byte length. + * Note that the default and recommended char size is 8 bit since it's + * supported by all system. + */ +enum spi_char_size { + /** Character size is 8 bit. */ + SPI_CHAR_SIZE_8 = 0, + /** Character size is 9 bit. */ + SPI_CHAR_SIZE_9 = 1, + /** Character size is 10 bit. */ + SPI_CHAR_SIZE_10 = 2, + /** Character size is 11 bit. */ + SPI_CHAR_SIZE_11 = 3, + /** Character size is 12 bit. */ + SPI_CHAR_SIZE_12 = 4, + /** Character size is 13 bit. */ + SPI_CHAR_SIZE_13 = 5, + /** Character size is 14 bit. */ + SPI_CHAR_SIZE_14 = 6, + /** Character size is 15 bit. */ + SPI_CHAR_SIZE_15 = 7, + /** Character size is 16 bit. */ + SPI_CHAR_SIZE_16 = 8 +}; + +/** + * \brief SPI data order + */ +enum spi_data_order { + /** MSB goes first. */ + SPI_DATA_ORDER_MSB_1ST = 0, + /** LSB goes first. */ + SPI_DATA_ORDER_LSB_1ST = 1 +}; + +/** \brief Transfer descriptor for SPI + * Transfer descriptor holds TX and RX buffers + */ +struct spi_xfer { + /** Pointer to data buffer to TX */ + uint8_t *txbuf; + /** Pointer to data buffer to RX */ + uint8_t *rxbuf; + /** Size of data characters to TX & RX */ + uint32_t size; +}; + +/** SPI generic driver. */ +struct spi_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Reference start of sync/async variables */ + uint32_t sync_async_misc[1]; +}; + +/** + * \brief Calculate the baudrate value for hardware to use to set baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] clk Clock frequency (Hz) for baudrate generation. + * \param[in] baud Target baudrate (bps). + * \return Error or baudrate value. + * \retval >0 Baudrate value. + * \retval ERR_INVALID_ARG Calculation fail. + */ +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_spi_async.h b/watch-library/hardware/hal/include/hpl_spi_async.h new file mode 100644 index 00000000..8e5a8485 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_spi_async.h @@ -0,0 +1,131 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_ASYNC_H_INCLUDED +#define _HPL_SPI_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Callbacks the SPI driver must offer in async mode + */ +//@{ +/** The callback types */ +enum _spi_async_dev_cb_type { + /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_TX, + /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_RX, + /** Callback type for \ref _spi_async_dev_cb_complete_t. */ + SPI_DEV_CB_COMPLETE, + /** Callback type for error */ + SPI_DEV_CB_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_N +}; + +struct _spi_async_dev; + +/** \brief The prototype for callback on SPI transfer error. + * If status code is zero, it indicates the normal completion, that is, + * SS deactivation. + * If status code belows zero, it indicates complete. + */ +typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); + +/** \brief The prototype for callback on SPI transmit/receive event + * For TX, the callback is invoked when transmit is done or ready to start + * transmit. + * For RX, the callback is invoked when receive is done or ready to read data, + * see \ref _spi_async_dev_read_one_t on data reading. + * Without DMA enabled, the callback is invoked on each character event. + * With DMA enabled, the callback is invoked on DMA buffer done. + */ +typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_async_dev_callbacks { + /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t tx; + /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t rx; + /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ + _spi_async_dev_cb_xfer_t complete; + /** Error callback, see \ref */ + _spi_async_dev_cb_error_t err; +}; +//@} + +/** + * \brief SPI async driver + */ +//@{ + +/** SPI driver to support async HAL */ +struct _spi_async_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; + + /** \brief Pointer to callback functions, ignored for polling mode + * Pointer to the callback functions so that initialize the driver to + * handle interrupts. + */ + struct _spi_async_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; +}; +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_spi_dma.h b/watch-library/hardware/hal/include/hpl_spi_dma.h new file mode 100755 index 00000000..04a30158 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_spi_dma.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Common SPI DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_DMA_H_INCLUDED +#define _HPL_SPI_DMA_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** The callback types */ +enum _spi_dma_dev_cb_type { + /** Callback type for DMA transmit. */ + SPI_DEV_CB_DMA_TX, + /** Callback type for DMA receive. */ + SPI_DEV_CB_DMA_RX, + /** Callback type for DMA error. */ + SPI_DEV_CB_DMA_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_DMA_N +}; + +struct _spi_dma_dev; + +/** + * \brief The prototype for callback on SPI DMA. + */ +typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_dma_dev_callbacks { + _spi_dma_cb_t tx; + _spi_dma_cb_t rx; + _spi_dma_cb_t error; +}; + +/** SPI driver to support DMA HAL */ +struct _spi_dma_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Pointer to callback functions */ + struct _spi_dma_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; + /** DMA resource */ + struct _dma_resource *resource; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_spi_m_async.h b/watch-library/hardware/hal/include/hpl_spi_m_async.h new file mode 100644 index 00000000..8d3555ed --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_spi_m_async.h @@ -0,0 +1,243 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED +#define _HPL_SPI_M_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_async_dev _spi_async_dev + +#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on after data transmission complate + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_spi_m_dma.h b/watch-library/hardware/hal/include/hpl_spi_m_dma.h new file mode 100644 index 00000000..2b48300e --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_spi_m_dma.h @@ -0,0 +1,182 @@ +/** + * \file + * + * \brief SPI Master DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_DMA_H_INCLUDED +#define _HPL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI dma device driver. */ +#define _spi_m_dma_dev _spi_dma_dev + +#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); + +/** + * \brief Register the SPI device callback + * \param[in] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); + +/** \brief Do SPI data transfer (TX & RX) with DMA + * Log the TX & RX buffers and transfer them in background. It never blocks. + * + * \param[in] dev Pointer to the SPI device instance. + * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). + * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). + * \param[in] length spi transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_spi_m_sync.h b/watch-library/hardware/hal/include/hpl_spi_m_sync.h new file mode 100644 index 00000000..38df15b4 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_spi_m_sync.h @@ -0,0 +1,166 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_SYNC_H_INCLUDED +#define _HPL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_m_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); + +/** + * \brief Deinitialize SPI + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI char size + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Transfer the whole message without interrupt + * Transfer the message, it will keep waiting until the message finish or + * error. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] msg Pointer to the message instance to process. + * \return Error or number of characters transferred. + * \retval ERR_BUSY SPI hardware is not ready to start transfer (not + * enabled, busy applying settings, ...). + * \retval SPI_ERR_OVERFLOW Overflow error. + * \retval >=0 Number of characters transferred. + */ +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_spi_s_async.h b/watch-library/hardware/hal/include/hpl_spi_s_async.h new file mode 100644 index 00000000..56472439 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_spi_s_async.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED +#define _HPL_SPI_S_ASYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_async_dev _spi_async_dev + +#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_spi_s_sync.h b/watch-library/hardware/hal/include/hpl_spi_s_sync.h new file mode 100644 index 00000000..ff4c811a --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_spi_s_sync.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_SYNC_H_INCLUDED +#define _HPL_SPI_S_SYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_s_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retval 0 OK Status + */ +int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); + +/** + * \brief Check if TX ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return TX ready state + * \retval true TX ready + * \retval false TX not ready + */ +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if RX character ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return RX character ready state + * \retval true RX character ready + * \retval false RX character not ready + */ +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if SS deactiviation detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return SS deactiviation state + * \retval true SS deactiviation detected + * \retval false SS deactiviation not detected + */ +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if error is detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return Error detection state + * \retval true Error detected + * \retval false Error not detected + */ +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_spi_sync.h b/watch-library/hardware/hal/include/hpl_spi_sync.h new file mode 100644 index 00000000..dc88648f --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_spi_sync.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_SYNC_H_INCLUDED +#define _HPL_SPI_SYNC_H_INCLUDED + +#include +#include + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * \section hpl_spi_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI driver to support sync HAL */ +struct _spi_sync_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; +}; + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_time_measure.h b/watch-library/hardware/hal/include/hpl_time_measure.h new file mode 100644 index 00000000..5d688df5 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_time_measure.h @@ -0,0 +1,94 @@ +/** + * \file + * + * \brief Time measure related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIME_MEASURE_H_INCLUDED +#define _HPL_TIME_MEASURE_H_INCLUDED + +/** + * \addtogroup HPL Time measure + * + * \section hpl_time_measure_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief System time type + */ +typedef uint32_t system_time_t; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize system time module + * + * \param[in] hw The pointer to hardware instance to initialize + */ +void _system_time_init(void *const hw); + +/** + * \brief Deinitialize system time module + * + * \param[in] hw The pointer to hardware instance to initialize + */ +void _system_time_deinit(void *const hw); + +/** + * \brief Get system time + * + * \param[in] hw The pointer to hardware instance to initialize + */ +system_time_t _system_time_get(const void *const hw); + +/** + * \brief Get maximum possible system time + * + * \param[in] hw The pointer to hardware instance to initialize + */ +system_time_t _system_time_get_max_time_value(const void *const hw); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIME_MEASURE_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_timer.h b/watch-library/hardware/hal/include/hpl_timer.h new file mode 100644 index 00000000..9bdfbb77 --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_timer.h @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief Timer related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIMER_H_INCLUDED +#define _HPL_TIMER_H_INCLUDED + +/** + * \addtogroup HPL Timer + * + * \section hpl_timer_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Timer device structure + * + * The Timer device structure forward declaration. + */ +struct _timer_device; + +/** + * \brief Timer interrupt callbacks + */ +struct _timer_callbacks { + void (*period_expired)(struct _timer_device *device); +}; + +/** + * \brief Timer device structure + */ +struct _timer_device { + struct _timer_callbacks timer_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief Timer functions, pointers to low-level functions + */ +struct _timer_hpl_interface { + int32_t (*init)(struct _timer_device *const device, void *const hw); + void (*deinit)(struct _timer_device *const device); + void (*start_timer)(struct _timer_device *const device); + void (*stop_timer)(struct _timer_device *const device); + void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); + uint32_t (*get_period)(const struct _timer_device *const device); + bool (*is_timer_started)(const struct _timer_device *const device); + void (*set_timer_irq)(struct _timer_device *const device); +}; +/** + * \brief Initialize TCC + * + * This function does low level TCC configuration. + * + * \param[in] device The pointer to timer device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw); + +/** + * \brief Deinitialize TCC + * + * \param[in] device The pointer to timer device instance + */ +void _timer_deinit(struct _timer_device *const device); + +/** + * \brief Start hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_start(struct _timer_device *const device); + +/** + * \brief Stop hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_stop(struct _timer_device *const device); + +/** + * \brief Set timer period + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); + +/** + * \brief Retrieve timer period + * + * \param[in] device The pointer to timer device instance + * + * \return Timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device); + +/** + * \brief Check if timer is running + * + * \param[in] device The pointer to timer device instance + * + * \return Check status. + * \retval true The given timer is running + * \retval false The given timer is not running + */ +bool _timer_is_started(const struct _timer_device *const device); + +/** + * \brief Set timer IRQ + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_irq(struct _timer_device *const device); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_usart.h b/watch-library/hardware/hal/include/hpl_usart.h new file mode 100644 index 00000000..0e09501d --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_usart.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_usart_async.h b/watch-library/hardware/hal/include/hpl_usart_async.h new file mode 100644 index 00000000..3f833d1a --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_usart_async.h @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_usart_sync.h b/watch-library/hardware/hal/include/hpl_usart_sync.h new file mode 100644 index 00000000..abc7264f --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_usart_sync.h @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART transmitter has sent the byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART transmitter has sent the byte + * \retval false if the USART transmitter has not send the byte + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/watch-library/hardware/hal/include/hpl_user_area.h b/watch-library/hardware/hal/include/hpl_user_area.h new file mode 100755 index 00000000..1f14098d --- /dev/null +++ b/watch-library/hardware/hal/include/hpl_user_area.h @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief Special user data area access + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USER_DATA_H_INCLUDED +#define _HPL_USER_DATA_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Read data from user data area + * + * The user data area could be the area that stores user data that is not erased + * with the flash contents, e.g., + * - NVM Software Calibration Area of SAM D/L/C family + * - User Signature of SAM E/S/V 70 + * + * \param[in] base The base address of the user area + * \param[in] offset The byte offset of the data to be read inside the area + * \param[out] buf Pointer to buffer to place the read data + * \param[in] size Size of data in number of bytes + * + * \return Operation status or bytes read. + * \retval ERR_NONE Data read successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, const uint32_t size); + +/** + * \brief Read no more than 32 bits data from user data area + * + * When reading bits, the bitfield can cross 32-bis boundaries. + * + * \param[in] base The base address of the user area + * \param[in] bit_offset Offset in number of bits + * \param[in] n_bits Number of bits to read + * \return data read, assert if anything wrong (address not in user area + * offset, size error, etc.). + */ +uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits); + +/** + * \brief Write data to user data area + * + * The user data area could be the area that stores user data that is not erased + * with the flash contents, e.g., + * - NVM Software Calibration Area of SAM D/L/C family + * - User Signature of SAM E/S/V 70 + * + * When assigned offset and size exceeds the data area, error is reported. + * + * \param[out] base The base address of the user area + * \param[in] offset The offset of the data to be written inside the area + * \param[in] buf Pointer to buffer to place the written data + * \param[in] size Size of data in number of bytes + * + * \return Operation status or bytes writting. + * \retval ERR_NONE Data written successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_DENIED Security bit is set + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size); + +/** + * \brief Write no more than 32 bits data to user data area + * + * When writting bits, the bitfield can cross 32-bis boundaries. + * + * \param[out] base The base address of the user area + * \param[in] bit_offset Offset in number of bits + * \param[in] bits The data content + * \param[in] n_bits Number of bits to write + * \return Operation result + * \retval ERR_NONE Data written successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_DENIED Security bit is set + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_USER_DATA_H_INCLUDED */ diff --git a/watch-library/hardware/hal/src/hal_atomic.c b/watch-library/hardware/hal/src/hal_atomic.c new file mode 100644 index 00000000..f56418ee --- /dev/null +++ b/watch-library/hardware/hal/src/hal_atomic.c @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/watch-library/hardware/hal/src/hal_calendar.c b/watch-library/hardware/hal/src/hal_calendar.c new file mode 100644 index 00000000..e69de29b diff --git a/watch-library/hardware/hal/src/hal_delay.c b/watch-library/hardware/hal/src/hal_delay.c new file mode 100644 index 00000000..6f77cc70 --- /dev/null +++ b/watch-library/hardware/hal/src/hal_delay.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/watch-library/hardware/hal/src/hal_ext_irq.c b/watch-library/hardware/hal/src/hal_ext_irq.c new file mode 100644 index 00000000..2c383b4b --- /dev/null +++ b/watch-library/hardware/hal/src/hal_ext_irq.c @@ -0,0 +1,188 @@ +/** + * \file + * + * \brief External interrupt functionality imkplementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_ext_irq.h" + +#define EXT_IRQ_AMOUNT 6 + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief External IRQ struct + */ +struct ext_irq { + ext_irq_cb_t cb; + uint32_t pin; +}; + +/* Remove KEIL compiling error in case no IRQ line selected */ +#if EXT_IRQ_AMOUNT == 0 +#undef EXT_IRQ_AMOUNT +#define EXT_IRQ_AMOUNT 1 +#endif + +/** + * \brief Array of external IRQs callbacks + */ +static struct ext_irq ext_irqs[EXT_IRQ_AMOUNT]; + +static void process_ext_irq(const uint32_t pin); + +/** + * \brief Initialize external irq component if any + */ +int32_t ext_irq_init(void) +{ + uint16_t i; + + for (i = 0; i < EXT_IRQ_AMOUNT; i++) { + ext_irqs[i].pin = 0xFFFFFFFF; + ext_irqs[i].cb = NULL; + } + + return _ext_irq_init(process_ext_irq); +} + +/** + * \brief Deinitialize external irq if any + */ +int32_t ext_irq_deinit(void) +{ + return _ext_irq_deinit(); +} + +/** + * \brief Register callback for the given external interrupt + */ +int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb) +{ + uint8_t i = 0, j = 0; + bool found = false; + + for (; i < EXT_IRQ_AMOUNT; i++) { + if (ext_irqs[i].pin == pin) { + ext_irqs[i].cb = cb; + found = true; + break; + } + } + + if (NULL == cb) { + if (!found) { + return ERR_INVALID_ARG; + } + return _ext_irq_enable(pin, false); + } + + if (!found) { + for (i = 0; i < EXT_IRQ_AMOUNT; i++) { + if (NULL == ext_irqs[i].cb) { + ext_irqs[i].cb = cb; + ext_irqs[i].pin = pin; + found = true; + break; + } + } + for (; (j < EXT_IRQ_AMOUNT) && (i < EXT_IRQ_AMOUNT); j++) { + if ((ext_irqs[i].pin < ext_irqs[j].pin) && (ext_irqs[j].pin != 0xFFFFFFFF)) { + struct ext_irq tmp = ext_irqs[j]; + + ext_irqs[j] = ext_irqs[i]; + ext_irqs[i] = tmp; + } + } + } + + if (!found) { + return ERR_INVALID_ARG; + } + + return _ext_irq_enable(pin, true); +} + +/** + * \brief Enable external irq + */ +int32_t ext_irq_enable(const uint32_t pin) +{ + return _ext_irq_enable(pin, true); +} + +/** + * \brief Disable external irq + */ +int32_t ext_irq_disable(const uint32_t pin) +{ + return _ext_irq_enable(pin, false); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t ext_irq_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief Interrupt processing routine + * + * \param[in] pin The pin which triggered the interrupt + */ +static void process_ext_irq(const uint32_t pin) +{ + uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; + + while (upper >= lower) { + middle = (upper + lower) >> 1; + if (middle >= EXT_IRQ_AMOUNT) { + return; + } + + if (ext_irqs[middle].pin == pin) { + if (ext_irqs[middle].cb) { + ext_irqs[middle].cb(); + } + return; + } + + if (ext_irqs[middle].pin < pin) { + lower = middle + 1; + } else { + upper = middle - 1; + } + } +} diff --git a/watch-library/hardware/hal/src/hal_flash.c b/watch-library/hardware/hal/src/hal_flash.c new file mode 100755 index 00000000..b1a58b71 --- /dev/null +++ b/watch-library/hardware/hal/src/hal_flash.c @@ -0,0 +1,314 @@ +/** + * \file + * + * \brief Flash functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_flash.h" +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static void flash_ready(struct _flash_device *device); +static void flash_error(struct _flash_device *device); + +static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr); + +/** + * \brief Initialize the FLASH HAL instance and hardware for callback mode. + */ +int32_t flash_init(struct flash_descriptor *flash, void *const hw) +{ + int32_t rc; + + ASSERT(flash && hw); + + rc = _flash_init(&flash->dev, hw); + if (rc) { + return rc; + } + + flash->dev.flash_cb.ready_cb = flash_ready; + flash->dev.flash_cb.error_cb = flash_error; + + return ERR_NONE; +} + +/** + * \brief Deinitialize the FLASH HAL instance. + */ +int32_t flash_deinit(struct flash_descriptor *flash) +{ + ASSERT(flash); + + _flash_deinit(&flash->dev); + + return ERR_NONE; +} + +/** + * \brief Reads a number of bytes to a page in the internal Flash + */ +int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((src_addr > page_size * total_pages) || (src_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + _flash_read(&flash->dev, src_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Updates several bytes to the internal Flash + */ +int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + if (_flash_is_locked(&flash->dev, dst_addr)) { + return ERR_DENIED; + } + + _flash_write(&flash->dev, dst_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Appends a number of bytes to a page in the internal Flash + */ +int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + if (_flash_is_locked(&flash->dev, dst_addr)) { + return ERR_DENIED; + } + + _flash_append(&flash->dev, dst_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Execute erase in the internal flash + */ +int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + _flash_erase(&flash->dev, dst_addr, page_nums); + + return ERR_NONE; +} + +/** + * \brief Register a function as FLASH transfer completion callback + */ +int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func) +{ + ASSERT(flash); + + switch (type) { + case FLASH_CB_READY: + flash->callbacks.cb_ready = func; + break; + + case FLASH_CB_ERROR: + flash->callbacks.cb_error = func; + break; + + default: + return ERR_INVALID_ARG; + } + + _flash_set_irq_state(&flash->dev, (enum _flash_cb_type)type, NULL != func); + + return ERR_NONE; +} + +/** + * \brief Execute lock in the internal flash + */ +int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + return _flash_lock(&flash->dev, dst_addr, page_nums); +} + +/** + * \brief Execute unlock in the internal flash + */ +int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + return _flash_unlock(&flash->dev, dst_addr, page_nums); +} + +/** + * \brief Get the flash page size. + */ +uint32_t flash_get_page_size(struct flash_descriptor *flash) +{ + ASSERT(flash); + return _flash_get_page_size(&flash->dev); +} + +/** + * \brief Get the numbers of flash page. + */ +uint32_t flash_get_total_pages(struct flash_descriptor *flash) +{ + ASSERT(flash); + return _flash_get_total_pages(&flash->dev); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t flash_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal check the address whether it is aligned + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] flash_addr address to be check in flash + * + * \return whether it is valid + * \retval 0 Valid. + * \retval -1 Error, invalid. + */ +static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr) +{ + ASSERT(flash); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + + /* Check if the read address not aligned to the start of a page */ + if (flash_addr & (page_size - 1)) { + return ERR_BAD_ADDRESS; + } + return ERR_NONE; +} + +/** + * \internal Ready for a new flash command + * + * \param[in] device The pointer to flash device structure + */ +static void flash_ready(struct _flash_device *device) +{ + struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); + if (descr->callbacks.cb_ready) { + descr->callbacks.cb_ready(descr); + } +} + +/** + * \internal Error occurs in flash command + * + * \param[in] device The pointer to flash device structure + */ +static void flash_error(struct _flash_device *device) +{ + struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); + if (descr->callbacks.cb_error) { + descr->callbacks.cb_error(descr); + } +} diff --git a/watch-library/hardware/hal/src/hal_gpio.c b/watch-library/hardware/hal/src/hal_gpio.c new file mode 100644 index 00000000..00dfea6f --- /dev/null +++ b/watch-library/hardware/hal/src/hal_gpio.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/watch-library/hardware/hal/src/hal_i2c_m_sync.c b/watch-library/hardware/hal/src/hal_i2c_m_sync.c new file mode 100644 index 00000000..9be16be4 --- /dev/null +++ b/watch-library/hardware/hal/src/hal_i2c_m_sync.c @@ -0,0 +1,258 @@ +/** + * \file + * + * \brief I/O I2C related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Sync version of I2C I/O read + */ +static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->periph_addr; + msg.len = n; + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret) { + return ret; + } + + return n; +} + +/** + * \brief Sync version of I2C I/O write + */ +static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->periph_addr; + msg.len = n; + msg.flags = I2C_M_STOP; + msg.buffer = (uint8_t *)buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret) { + return ret; + } + + return n; +} + +/** + * \brief Sync version of i2c initialize + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) +{ + int32_t init_status; + ASSERT(i2c); + + init_status = _i2c_m_sync_init(&i2c->device, hw); + if (init_status) { + return init_status; + } + + /* Init I/O */ + i2c->io.read = i2c_m_sync_read; + i2c->io.write = i2c_m_sync_write; + + return ERR_NONE; +} + +/** + * \brief deinitialize + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c) +{ + int32_t status; + ASSERT(i2c); + + status = _i2c_m_sync_deinit(&i2c->device); + if (status) { + return status; + } + + i2c->io.read = NULL; + i2c->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c enable + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_enable(&i2c->device); +} + +/** + * \brief Sync version of i2c disable + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_disable(&i2c->device); +} + +/** + * \brief Sync version of i2c set peripheral address + */ +int32_t i2c_m_sync_set_periphaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len) +{ + return i2c->periph_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN); +} + +/** + * \brief Sync version of i2c set baudrate + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate) +{ + return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate); +} + +/** + * \brief Sync version of i2c write command + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->periph_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c read command + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->periph_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c transfer command + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg) +{ + return _i2c_m_sync_transfer(&i2c->device, msg); +} + +/** + * \brief Sync version of i2c send stop condition command + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c) +{ + return _i2c_m_sync_send_stop(&i2c->device); +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io) +{ + *io = &i2c->io; + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t i2c_m_sync_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/watch-library/hardware/hal/src/hal_init.c b/watch-library/hardware/hal/src/hal_init.c new file mode 100644 index 00000000..fb65341f --- /dev/null +++ b/watch-library/hardware/hal/src/hal_init.c @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/watch-library/hardware/hal/src/hal_io.c b/watch-library/hardware/hal/src/hal_io.c new file mode 100644 index 00000000..ae787d42 --- /dev/null +++ b/watch-library/hardware/hal/src/hal_io.c @@ -0,0 +1,58 @@ +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/watch-library/hardware/hal/src/hal_rand_sync.c b/watch-library/hardware/hal/src/hal_rand_sync.c new file mode 100755 index 00000000..8b29ed1b --- /dev/null +++ b/watch-library/hardware/hal/src/hal_rand_sync.c @@ -0,0 +1,122 @@ +/** + * \file + * + * \brief Generic Random Number Generator (RNG) functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include "hal_rand_sync.h" + +#define HAL_RNG_SYNC_VERSION 0x00000001u + +int32_t rand_sync_init(struct rand_sync_desc *const desc, void *const hw) +{ + ASSERT(desc); + + return _rand_sync_init(&desc->dev, hw); +} + +void rand_sync_deinit(struct rand_sync_desc *const desc) +{ + ASSERT(desc); + _rand_sync_deinit(&desc->dev); +} + +int32_t rand_sync_enable(struct rand_sync_desc *const desc) +{ + ASSERT(desc); + return _rand_sync_enable(&desc->dev); +} + +void rand_sync_disable(struct rand_sync_desc *const desc) +{ + ASSERT(desc); + _rand_sync_disable(&desc->dev); +} + +int32_t rand_sync_set_seed(struct rand_sync_desc *const desc, const uint32_t seed) +{ + ASSERT(desc); + return _rand_sync_set_seed(&desc->dev, seed); +} + +/** + * \brief Read data bits + */ +static uint32_t _rand_sync_read_data(const struct _rand_sync_dev *dev, const uint8_t n_bits) +{ + uint8_t r_bits = (dev->n_bits < 1) ? 32 : dev->n_bits; + if (r_bits < n_bits) { + uint8_t i; + uint32_t d = 0; + /* Join read bits */ + for (i = 0; i < n_bits; i += r_bits) { + d |= (uint32_t)(_rand_sync_read_one(dev) << i); + } + return d; + } else { + return _rand_sync_read_one(dev); + } +} + +uint8_t rand_sync_read8(const struct rand_sync_desc *const desc) +{ + ASSERT(desc); + return (uint8_t)_rand_sync_read_data(&desc->dev, 8); +} + +uint32_t rand_sync_read32(const struct rand_sync_desc *const desc) +{ + ASSERT(desc); + return (uint32_t)_rand_sync_read_data(&desc->dev, 32); +} + +void rand_sync_read_buf8(const struct rand_sync_desc *const desc, uint8_t *buf, uint32_t len) +{ + uint32_t i; + ASSERT(desc && (buf && len)); + for (i = 0; i < len; i++) { + buf[i] = (uint8_t)_rand_sync_read_data(&desc->dev, 8); + } +} + +void rand_sync_read_buf32(const struct rand_sync_desc *const desc, uint32_t *buf, uint32_t len) +{ + uint32_t i; + ASSERT(desc && (buf && len)); + for (i = 0; i < len; i++) { + buf[i] = (uint32_t)_rand_sync_read_data(&desc->dev, 32); + } +} + +uint32_t rand_sync_get_version(void) +{ + return HAL_RNG_SYNC_VERSION; +} diff --git a/watch-library/hardware/hal/src/hal_slcd_sync.c b/watch-library/hardware/hal/src/hal_slcd_sync.c new file mode 100644 index 00000000..573eb0e2 --- /dev/null +++ b/watch-library/hardware/hal/src/hal_slcd_sync.c @@ -0,0 +1,150 @@ +/** + * \file + * + * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality + * declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize SLCD Descriptor + */ +int32_t slcd_sync_init(struct slcd_sync_descriptor *const descr, void *const hw) +{ + ASSERT(descr && hw); + return _slcd_sync_init(&descr->dev, hw); +} + +/** + * \brief Deinitialize SLCD Descriptor + */ +int32_t slcd_sync_deinit(struct slcd_sync_descriptor *const descr) +{ + ASSERT(descr); + return _slcd_sync_deinit(&descr->dev); +} + +/** + * \brief Enable SLCD driver + * + */ +int32_t slcd_sync_enable(struct slcd_sync_descriptor *const descr) +{ + ASSERT(descr); + return _slcd_sync_enable(&descr->dev); +} +/** + * \brief Disable SLCD driver + * + */ +int32_t slcd_sync_disable(struct slcd_sync_descriptor *const descr) +{ + ASSERT(descr); + return _slcd_sync_disable(&descr->dev); +} +/** + * \brief Turn on a Segment + */ +int32_t slcd_sync_seg_on(struct slcd_sync_descriptor *const descr, uint32_t seg) +{ + ASSERT(descr); + return _slcd_sync_seg_on(&descr->dev, seg); +} +/** + * \brief Turn off a Segment + */ +int32_t slcd_sync_seg_off(struct slcd_sync_descriptor *const descr, uint32_t seg) +{ + ASSERT(descr); + return _slcd_sync_seg_off(&descr->dev, seg); +} +/** + * \brief Blink a Segment + */ +int32_t slcd_sync_seg_blink(struct slcd_sync_descriptor *const descr, uint32_t seg, const uint32_t period) +{ + ASSERT(descr && period); + return _slcd_sync_seg_blink(&descr->dev, seg, period); +} + +/** + * \brief Displays a character + */ +int32_t slcd_sync_write_char(struct slcd_sync_descriptor *const descr, const uint8_t character, uint32_t index) +{ + ASSERT(descr); + return _slcd_sync_write_char(&descr->dev, character, index); +} + +/** + * \brief Displays character string string + */ +int32_t slcd_sync_write_string(struct slcd_sync_descriptor *const descr, uint8_t *const str, uint32_t len, + uint32_t index) +{ + uint32_t i; + ASSERT(descr && len); + + for (i = 0; i < len; i++) { + if (_slcd_sync_write_char(&descr->dev, *(str + i), index + i) != ERR_NONE) { + return ERR_INVALID_ARG; + } + } + return ERR_NONE; +} +/** + * \brief Start animation play by a segment array + */ +int32_t slcd_sync_start_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len, + const uint32_t period) +{ + ASSERT(descr && segs && len && period); + return _slcd_sync_start_animation(&descr->dev, segs, len, period); +} + +/** + * \brief Stop animation play by a segment array + */ +int32_t slcd_sync_stop_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len) +{ + ASSERT(descr && segs && len); + return _slcd_sync_stop_animation(&descr->dev, segs, len); +} + +/** + * \brief Set animation Frequency + */ +int32_t slcd_sync_set_animation_period(struct slcd_sync_descriptor *const descr, const uint32_t period) +{ + ASSERT(descr && period); + return _slcd_sync_set_animation_period(&descr->dev, period); +} diff --git a/watch-library/hardware/hal/src/hal_sleep.c b/watch-library/hardware/hal/src/hal_sleep.c new file mode 100644 index 00000000..89472f15 --- /dev/null +++ b/watch-library/hardware/hal/src/hal_sleep.c @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/watch-library/hardware/hal/src/hal_spi_m_sync.c b/watch-library/hardware/hal/src/hal_spi_m_sync.c new file mode 100755 index 00000000..1a64296a --- /dev/null +++ b/watch-library/hardware/hal/src/hal_spi_m_sync.c @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief I/O SPI related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_spi_m_sync.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Driver version + */ +#define SPI_M_SYNC_DRIVER_VERSION 0x00000001u + +#define SPI_DEACTIVATE_NEXT 0x8000 + +static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length); +static int32_t _spi_m_sync_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize the SPI HAL instance function pointer for HPL APIs. + */ +void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func) +{ + ASSERT(spi); + spi->func = (struct _spi_m_sync_hpl_interface *)func; +} + +int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw) +{ + int32_t rc = 0; + ASSERT(spi && hw); + spi->dev.prvt = (void *)hw; + rc = _spi_m_sync_init(&spi->dev, hw); + + if (rc < 0) { + return rc; + } + + spi->flags = SPI_DEACTIVATE_NEXT; + spi->io.read = _spi_m_sync_io_read; + spi->io.write = _spi_m_sync_io_write; + + return ERR_NONE; +} + +void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_m_sync_deinit(&spi->dev); +} + +void spi_m_sync_enable(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_m_sync_enable(&spi->dev); +} + +void spi_m_sync_disable(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_m_sync_disable(&spi->dev); +} + +int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val) +{ + ASSERT(spi); + return _spi_m_sync_set_baudrate(&spi->dev, baud_val); +} + +int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode) +{ + ASSERT(spi); + return _spi_m_sync_set_mode(&spi->dev, mode); +} + +int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size) +{ + ASSERT(spi); + return _spi_m_sync_set_char_size(&spi->dev, char_size); +} + +int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord) +{ + ASSERT(spi); + return _spi_m_sync_set_data_order(&spi->dev, dord); +} + +/** \brief Do SPI read in polling way + * For SPI master, activate CS, do send 0xFFs and read data, deactivate CS. + * + * It blocks until all data read or error. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[out] buf Pointer to the buffer to store read data. + * \param[in] size Size of the data in number of characters. + * \return Operation status. + * \retval size Success. + * \retval >=0 Time out, with number of characters read. + */ +static int32_t _spi_m_sync_io_read(struct io_descriptor *io, uint8_t *buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); + struct spi_xfer xfer; + + xfer.rxbuf = buf; + xfer.txbuf = 0; + xfer.size = length; + + return spi_m_sync_transfer(spi, &xfer); +} + +/** \brief Do SPI data write in polling way + * For SPI master, activate CS, do buffer send and deactivate CS. The data back + * is discarded. + * + * The data read back is discarded. + * + * It blocks until all data sent or error. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[in] p_xfer Pointer to the transfer information (\ref spi_transfer). + * \return Operation status. + * \retval size Success. + * \retval >=0 Timeout, with number of characters transferred. + */ +static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); + struct spi_xfer xfer; + + xfer.rxbuf = 0; + xfer.txbuf = (uint8_t *)buf; + xfer.size = length; + + return spi_m_sync_transfer(spi, &xfer); +} + +int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer) +{ + struct spi_msg msg; + + ASSERT(spi && p_xfer); + + msg.txbuf = p_xfer->txbuf; + msg.rxbuf = p_xfer->rxbuf; + msg.size = p_xfer->size; + return _spi_m_sync_trans(&spi->dev, &msg); +} + +int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io) +{ + ASSERT(spi && io); + *io = &spi->io; + return 0; +} + +uint32_t spi_m_sync_get_version(void) +{ + return SPI_M_SYNC_DRIVER_VERSION; +} + +#ifdef __cplusplus +} +#endif diff --git a/watch-library/hardware/hal/src/hal_usart_sync.c b/watch-library/hardware/hal/src/hal_usart_sync.c new file mode 100755 index 00000000..ab99c1d1 --- /dev/null +++ b/watch-library/hardware/hal/src/hal_usart_sync.c @@ -0,0 +1,276 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_sync.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize usart interface + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw); + init_status = _usart_sync_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_sync_read; + descr->io.write = usart_sync_write; + + return ERR_NONE; +} + +/** + * \brief Uninitialize usart interface + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_deinit(&descr->device); + + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_sync_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_sync_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_sync_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_sync_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_sync_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_sync_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_sync_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_sync_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_ready_to_send(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_received(&descr->device); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + do { + _usart_sync_write_byte(&descr->device, buf[offset]); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + } while (++offset < length); + while (!_usart_sync_is_transmit_done(&descr->device)) + ; + return (int32_t)offset; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + do { + while (!_usart_sync_is_byte_received(&descr->device)) + ; + buf[offset] = _usart_sync_read_byte(&descr->device); + } while (++offset < length); + + return (int32_t)offset; +} diff --git a/watch-library/hardware/hal/utils/include/compiler.h b/watch-library/hardware/hal/utils/include/compiler.h new file mode 100644 index 00000000..010b2637 --- /dev/null +++ b/watch-library/hardware/hal/utils/include/compiler.h @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Header + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin + ******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef __EMSCRIPTEN__ +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/watch-library/hardware/hal/utils/include/err_codes.h b/watch-library/hardware/hal/utils/include/err_codes.h new file mode 100644 index 00000000..a7aff018 --- /dev/null +++ b/watch-library/hardware/hal/utils/include/err_codes.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/watch-library/hardware/hal/utils/include/events.h b/watch-library/hardware/hal/utils/include/events.h new file mode 100644 index 00000000..3ee891a7 --- /dev/null +++ b/watch-library/hardware/hal/utils/include/events.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/watch-library/hardware/hal/utils/include/parts.h b/watch-library/hardware/hal/utils/include/parts.h new file mode 100644 index 00000000..df30040f --- /dev/null +++ b/watch-library/hardware/hal/utils/include/parts.h @@ -0,0 +1,41 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "saml22.h" + +#include "hri_l22.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/watch-library/hardware/hal/utils/include/utils.h b/watch-library/hardware/hal/utils/include/utils.h new file mode 100644 index 00000000..1cf26996 --- /dev/null +++ b/watch-library/hardware/hal/utils/include/utils.h @@ -0,0 +1,368 @@ +/** + * \file + * + * \brief Different macros. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + ( \ + ((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) \ + ? 0 \ + : ((u) & (1ul << 30)) \ + ? 1 \ + : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) \ + ? 6 \ + : ((u) & (1ul << 24)) \ + ? 7 \ + : ((u) & (1ul << 23)) \ + ? 8 \ + : ((u) & (1ul << 22)) \ + ? 9 \ + : ((u) & (1ul << 21)) \ + ? 10 \ + : ((u) & (1ul << 20)) \ + ? 11 \ + : ((u) & (1ul << 19)) \ + ? 12 \ + : ((u) & (1ul << 18)) \ + ? 13 \ + : ((u) & (1ul << 17)) ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) & (1ul << 15)) ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 \ + : ((u) & (1ul << 12)) ? 19 \ + : ((u) \ + & (1ul \ + << 11)) \ + ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) \ + & (1ul \ + << 9)) \ + ? 22 \ + : ((u) \ + & (1ul \ + << 8)) \ + ? 23 \ + : ((u) & (1ul << 7)) ? 24 \ + : ((u) & (1ul << 6)) ? 25 \ + : ((u) \ + & (1ul \ + << 5)) \ + ? 26 \ + : ((u) & (1ul << 4)) ? 27 \ + : ((u) & (1ul << 3)) ? 28 \ + : ((u) & (1ul << 2)) ? 29 \ + : ( \ + (u) & (1ul << 1)) \ + ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) \ + ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul << 14) \ + ? 14 \ + : (u) & (1ul << 15) \ + ? 15 \ + : (u) & (1ul << 16) \ + ? 16 \ + : (u) & (1ul << 17) \ + ? 17 \ + : (u) & (1ul << 18) \ + ? 18 \ + : (u) & (1ul << 19) ? 19 \ + : (u) & (1ul << 20) ? 20 \ + : (u) & (1ul << 21) ? 21 \ + : (u) & (1ul << 22) ? 22 \ + : (u) & (1ul << 23) ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 \ + : (u) & (1ul << 27) ? 27 \ + : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/watch-library/hardware/hal/utils/include/utils_assert.h b/watch-library/hardware/hal/utils/include/utils_assert.h new file mode 100644 index 00000000..c2328d6c --- /dev/null +++ b/watch-library/hardware/hal/utils/include/utils_assert.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/watch-library/hardware/hal/utils/include/utils_decrement_macro.h b/watch-library/hardware/hal/utils/include/utils_decrement_macro.h new file mode 100644 index 00000000..2b524699 --- /dev/null +++ b/watch-library/hardware/hal/utils/include/utils_decrement_macro.h @@ -0,0 +1,309 @@ +/** + * \file + * + * \brief Decrement macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_DECREMENT_MACRO_H +#define _UTILS_DECREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time decrement, result value is entire integer literal + * + * \param[in] val - value to be decremented + */ +#define DEC_VALUE(val) DEC_##val + +// Preprocessor increment implementation +#define DEC_256 255 +#define DEC_255 254 +#define DEC_254 253 +#define DEC_253 252 +#define DEC_252 251 +#define DEC_251 250 +#define DEC_250 249 +#define DEC_249 248 +#define DEC_248 247 +#define DEC_247 246 +#define DEC_246 245 +#define DEC_245 244 +#define DEC_244 243 +#define DEC_243 242 +#define DEC_242 241 +#define DEC_241 240 +#define DEC_240 239 +#define DEC_239 238 +#define DEC_238 237 +#define DEC_237 236 +#define DEC_236 235 +#define DEC_235 234 +#define DEC_234 233 +#define DEC_233 232 +#define DEC_232 231 +#define DEC_231 230 +#define DEC_230 229 +#define DEC_229 228 +#define DEC_228 227 +#define DEC_227 226 +#define DEC_226 225 +#define DEC_225 224 +#define DEC_224 223 +#define DEC_223 222 +#define DEC_222 221 +#define DEC_221 220 +#define DEC_220 219 +#define DEC_219 218 +#define DEC_218 217 +#define DEC_217 216 +#define DEC_216 215 +#define DEC_215 214 +#define DEC_214 213 +#define DEC_213 212 +#define DEC_212 211 +#define DEC_211 210 +#define DEC_210 209 +#define DEC_209 208 +#define DEC_208 207 +#define DEC_207 206 +#define DEC_206 205 +#define DEC_205 204 +#define DEC_204 203 +#define DEC_203 202 +#define DEC_202 201 +#define DEC_201 200 +#define DEC_200 199 +#define DEC_199 198 +#define DEC_198 197 +#define DEC_197 196 +#define DEC_196 195 +#define DEC_195 194 +#define DEC_194 193 +#define DEC_193 192 +#define DEC_192 191 +#define DEC_191 190 +#define DEC_190 189 +#define DEC_189 188 +#define DEC_188 187 +#define DEC_187 186 +#define DEC_186 185 +#define DEC_185 184 +#define DEC_184 183 +#define DEC_183 182 +#define DEC_182 181 +#define DEC_181 180 +#define DEC_180 179 +#define DEC_179 178 +#define DEC_178 177 +#define DEC_177 176 +#define DEC_176 175 +#define DEC_175 174 +#define DEC_174 173 +#define DEC_173 172 +#define DEC_172 171 +#define DEC_171 170 +#define DEC_170 169 +#define DEC_169 168 +#define DEC_168 167 +#define DEC_167 166 +#define DEC_166 165 +#define DEC_165 164 +#define DEC_164 163 +#define DEC_163 162 +#define DEC_162 161 +#define DEC_161 160 +#define DEC_160 159 +#define DEC_159 158 +#define DEC_158 157 +#define DEC_157 156 +#define DEC_156 155 +#define DEC_155 154 +#define DEC_154 153 +#define DEC_153 152 +#define DEC_152 151 +#define DEC_151 150 +#define DEC_150 149 +#define DEC_149 148 +#define DEC_148 147 +#define DEC_147 146 +#define DEC_146 145 +#define DEC_145 144 +#define DEC_144 143 +#define DEC_143 142 +#define DEC_142 141 +#define DEC_141 140 +#define DEC_140 139 +#define DEC_139 138 +#define DEC_138 137 +#define DEC_137 136 +#define DEC_136 135 +#define DEC_135 134 +#define DEC_134 133 +#define DEC_133 132 +#define DEC_132 131 +#define DEC_131 130 +#define DEC_130 129 +#define DEC_129 128 +#define DEC_128 127 +#define DEC_127 126 +#define DEC_126 125 +#define DEC_125 124 +#define DEC_124 123 +#define DEC_123 122 +#define DEC_122 121 +#define DEC_121 120 +#define DEC_120 119 +#define DEC_119 118 +#define DEC_118 117 +#define DEC_117 116 +#define DEC_116 115 +#define DEC_115 114 +#define DEC_114 113 +#define DEC_113 112 +#define DEC_112 111 +#define DEC_111 110 +#define DEC_110 109 +#define DEC_109 108 +#define DEC_108 107 +#define DEC_107 106 +#define DEC_106 105 +#define DEC_105 104 +#define DEC_104 103 +#define DEC_103 102 +#define DEC_102 101 +#define DEC_101 100 +#define DEC_100 99 +#define DEC_99 98 +#define DEC_98 97 +#define DEC_97 96 +#define DEC_96 95 +#define DEC_95 94 +#define DEC_94 93 +#define DEC_93 92 +#define DEC_92 91 +#define DEC_91 90 +#define DEC_90 89 +#define DEC_89 88 +#define DEC_88 87 +#define DEC_87 86 +#define DEC_86 85 +#define DEC_85 84 +#define DEC_84 83 +#define DEC_83 82 +#define DEC_82 81 +#define DEC_81 80 +#define DEC_80 79 +#define DEC_79 78 +#define DEC_78 77 +#define DEC_77 76 +#define DEC_76 75 +#define DEC_75 74 +#define DEC_74 73 +#define DEC_73 72 +#define DEC_72 71 +#define DEC_71 70 +#define DEC_70 69 +#define DEC_69 68 +#define DEC_68 67 +#define DEC_67 66 +#define DEC_66 65 +#define DEC_65 64 +#define DEC_64 63 +#define DEC_63 62 +#define DEC_62 61 +#define DEC_61 60 +#define DEC_60 59 +#define DEC_59 58 +#define DEC_58 57 +#define DEC_57 56 +#define DEC_56 55 +#define DEC_55 54 +#define DEC_54 53 +#define DEC_53 52 +#define DEC_52 51 +#define DEC_51 50 +#define DEC_50 49 +#define DEC_49 48 +#define DEC_48 47 +#define DEC_47 46 +#define DEC_46 45 +#define DEC_45 44 +#define DEC_44 43 +#define DEC_43 42 +#define DEC_42 41 +#define DEC_41 40 +#define DEC_40 39 +#define DEC_39 38 +#define DEC_38 37 +#define DEC_37 36 +#define DEC_36 35 +#define DEC_35 34 +#define DEC_34 33 +#define DEC_33 32 +#define DEC_32 31 +#define DEC_31 30 +#define DEC_30 29 +#define DEC_29 28 +#define DEC_28 27 +#define DEC_27 26 +#define DEC_26 25 +#define DEC_25 24 +#define DEC_24 23 +#define DEC_23 22 +#define DEC_22 21 +#define DEC_21 20 +#define DEC_20 19 +#define DEC_19 18 +#define DEC_18 17 +#define DEC_17 16 +#define DEC_16 15 +#define DEC_15 14 +#define DEC_14 13 +#define DEC_13 12 +#define DEC_12 11 +#define DEC_11 10 +#define DEC_10 9 +#define DEC_9 8 +#define DEC_8 7 +#define DEC_7 6 +#define DEC_6 5 +#define DEC_5 4 +#define DEC_4 3 +#define DEC_3 2 +#define DEC_2 1 +#define DEC_1 0 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_DECREMENT_MACRO_H */ diff --git a/watch-library/hardware/hal/utils/include/utils_event.h b/watch-library/hardware/hal/utils/include/utils_event.h new file mode 100644 index 00000000..13067c4f --- /dev/null +++ b/watch-library/hardware/hal/utils/include/utils_event.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/watch-library/hardware/hal/utils/include/utils_increment_macro.h b/watch-library/hardware/hal/utils/include/utils_increment_macro.h new file mode 100644 index 00000000..464c6cbb --- /dev/null +++ b/watch-library/hardware/hal/utils/include/utils_increment_macro.h @@ -0,0 +1,308 @@ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/watch-library/hardware/hal/utils/include/utils_list.h b/watch-library/hardware/hal/utils/include/utils_list.h new file mode 100644 index 00000000..977e8cca --- /dev/null +++ b/watch-library/hardware/hal/utils/include/utils_list.h @@ -0,0 +1,164 @@ +/** + * \file + * + * \brief List declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/watch-library/hardware/hal/utils/include/utils_recursion_macro.h b/watch-library/hardware/hal/utils/include/utils_recursion_macro.h new file mode 100644 index 00000000..294314c4 --- /dev/null +++ b/watch-library/hardware/hal/utils/include/utils_recursion_macro.h @@ -0,0 +1,69 @@ +/** + * \file + * + * \brief Recursion macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_RECURSION_MACRO_H +#define _UTILS_RECURSION_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Macro recursion + * + * \param[in] macro Macro to be repeated recursively + * \param[in] arg A recursive threshold, building on this to decline by times + * defined with parameter n + * \param[in] n The number of repetitious calls to macro + */ +#define RECURSION_MACRO(macro, arg, n) RECURSION_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define RECURSION_MACRO_I(macro, arg, n) RECURSION##n(macro, arg) + +#define RECURSION0(macro, arg) +#define RECURSION1(macro, arg) RECURSION0(macro, DEC_VALUE(arg)) macro(arg, 0) +#define RECURSION2(macro, arg) RECURSION1(macro, DEC_VALUE(arg)) macro(arg, 1) +#define RECURSION3(macro, arg) RECURSION2(macro, DEC_VALUE(arg)) macro(arg, 2) +#define RECURSION4(macro, arg) RECURSION3(macro, DEC_VALUE(arg)) macro(arg, 3) +#define RECURSION5(macro, arg) RECURSION4(macro, DEC_VALUE(arg)) macro(arg, 4) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_RECURSION_MACRO_H */ diff --git a/watch-library/hardware/hal/utils/include/utils_repeat_macro.h b/watch-library/hardware/hal/utils/include/utils_repeat_macro.h new file mode 100644 index 00000000..89e6f52d --- /dev/null +++ b/watch-library/hardware/hal/utils/include/utils_repeat_macro.h @@ -0,0 +1,322 @@ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/watch-library/hardware/hal/utils/src/utils_assert.c b/watch-library/hardware/hal/utils/src/utils_assert.c new file mode 100644 index 00000000..b376c970 --- /dev/null +++ b/watch-library/hardware/hal/utils/src/utils_assert.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/watch-library/hardware/hal/utils/src/utils_event.c b/watch-library/hardware/hal/utils/src/utils_event.c new file mode 100644 index 00000000..d1af9d0c --- /dev/null +++ b/watch-library/hardware/hal/utils/src/utils_event.c @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Events implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/watch-library/hardware/hal/utils/src/utils_list.c b/watch-library/hardware/hal/utils/src/utils_list.c new file mode 100644 index 00000000..4006a019 --- /dev/null +++ b/watch-library/hardware/hal/utils/src/utils_list.c @@ -0,0 +1,136 @@ +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/watch-library/hardware/hal/utils/src/utils_syscalls.c b/watch-library/hardware/hal/utils/src/utils_syscalls.c new file mode 100644 index 00000000..79e2f1fe --- /dev/null +++ b/watch-library/hardware/hal/utils/src/utils_syscalls.c @@ -0,0 +1,152 @@ +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} + +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} + +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/watch-library/hardware/hpl/core/hpl_core_m0plus_base.c b/watch-library/hardware/hpl/core/hpl_core_m0plus_base.c new file mode 100644 index 00000000..cad2a662 --- /dev/null +++ b/watch-library/hardware/hpl/core/hpl_core_m0plus_base.c @@ -0,0 +1,202 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +#if CONF_CPU_FREQUENCY < 1000 +#define CPU_FREQ_POWER 3 +#elif CONF_CPU_FREQUENCY < 10000 +#define CPU_FREQ_POWER 4 +#elif CONF_CPU_FREQUENCY < 100000 +#define CPU_FREQ_POWER 5 +#elif CONF_CPU_FREQUENCY < 1000000 +#define CPU_FREQ_POWER 6 +#elif CONF_CPU_FREQUENCY < 10000000 +#define CPU_FREQ_POWER 7 +#elif CONF_CPU_FREQUENCY < 100000000 +#define CPU_FREQ_POWER 8 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (us * (freq / 100000) - 1) / 10 + 1; + case 7: + return (us * (freq / 10000) - 1) / 100 + 1; + case 6: + return (us * (freq / 1000) - 1) / 1000 + 1; + case 5: + return (us * (freq / 100) - 1) / 10000 + 1; + case 4: + return (us * (freq / 10) - 1) / 100000 + 1; + default: + return (us * freq - 1) / 1000000 + 1; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + int32_t freq = hri_usbdevice_get_CTRLA_ENABLE_bit(USB) ? 8000000 : 4000000; + return _get_cycles_for_us_internal(us, freq, CPU_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (ms * (freq / 100000)) * 100; + case 7: + return (ms * (freq / 10000)) * 10; + case 6: + return (ms * (freq / 1000)); + case 5: + return (ms * (freq / 100) - 1) / 10 + 1; + case 4: + return (ms * (freq / 10) - 1) / 100 + 1; + default: + return (ms * freq - 1) / 1000 + 1; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + int32_t freq = hri_usbdevice_get_CTRLA_ENABLE_bit(USB) ? 8000000 : 4000000; + return _get_cycles_for_ms_internal(ms, freq, CPU_FREQ_POWER); +} diff --git a/watch-library/hardware/hpl/core/hpl_core_port.h b/watch-library/hardware/hpl/core/hpl_core_port.h new file mode 100644 index 00000000..33c18dd0 --- /dev/null +++ b/watch-library/hardware/hpl/core/hpl_core_port.h @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +void Default_Handler(void); + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/watch-library/hardware/hpl/core/hpl_init.c b/watch-library/hardware/hpl/core/hpl_init.c new file mode 100644 index 00000000..900cf420 --- /dev/null +++ b/watch-library/hardware/hpl/core/hpl_init.c @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#include +#include + +/* Referenced GCLKs (out of 0~4), should be initialized firstly + */ +#define _GCLK_INIT_1ST 0x00000000 +/* Not referenced GCLKs, initialized last */ +#define _GCLK_INIT_LAST 0x0000001F + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _set_performance_level(2); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); +#if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); +#endif + _oscctrl_init_referenced_generators(); + _gclk_init_generators_by_fref(_GCLK_INIT_LAST); + +#if CONF_DMAC_ENABLE + hri_mclk_set_AHBMASK_DMAC_bit(MCLK); + _dma_init(); +#endif + +#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) + _port_event_init(); +#endif +} diff --git a/watch-library/hardware/hpl/dmac/hpl_dmac.c b/watch-library/hardware/hpl/dmac/hpl_dmac.c new file mode 100644 index 00000000..c12e0254 --- /dev/null +++ b/watch-library/hardware/hpl/dmac/hpl_dmac.c @@ -0,0 +1,244 @@ + +/** + * \file + * + * \brief Generic DMAC related functionality. + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include + +#if CONF_DMAC_ENABLE + +/* Section containing first descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _descriptor_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Section containing current descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _write_back_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | (CONF_DMAC_ENABLE_##n << DMAC_CHCTRLA_ENABLE_Pos), \ + DMAC_CHCTRLB_TRIGACT(CONF_DMAC_TRIGACT_##n) | DMAC_CHCTRLB_TRIGSRC(CONF_DMAC_TRIGSRC_##n) \ + | DMAC_CHCTRLB_LVL(CONF_DMAC_LVL_##n) | (CONF_DMAC_EVOE_##n << DMAC_CHCTRLB_EVOE_Pos) \ + | (CONF_DMAC_EVIE_##n << DMAC_CHCTRLB_EVIE_Pos) | DMAC_CHCTRLB_EVACT(CONF_DMAC_EVACT_##n), \ + DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ + | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ + | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ + | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint8_t ctrla; + uint32_t ctrlb; + uint16_t btctrl; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +/** + * \brief Initialize DMAC + */ +int32_t _dma_init(void) +{ + uint8_t i = 0; + + hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); + hri_dmac_clear_CTRL_CRCENABLE_bit(DMAC); + hri_dmac_set_CHCTRLA_SWRST_bit(DMAC); + + hri_dmac_write_CTRL_reg(DMAC, + (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) + | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) + | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); + hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); + + hri_dmac_write_QOSCTRL_reg(DMAC, + DMAC_QOSCTRL_WRBQOS(CONF_DMAC_WRBQOS) | DMAC_QOSCTRL_FQOS(CONF_DMAC_FQOS) + | DMAC_QOSCTRL_DQOS(CONF_DMAC_DQOS)); + + hri_dmac_write_PRICTRL0_reg( + DMAC, + DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) + | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) + | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) + | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); + hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); + hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); + + for (; i < DMAC_CH_NUM; i++) { + hri_dmac_write_CHID_reg(DMAC, i); + + hri_dmac_write_CHCTRLA_RUNSTDBY_bit(DMAC, _cfgs[i].ctrla & DMAC_CHCTRLA_RUNSTDBY); + + hri_dmac_write_CHCTRLB_reg(DMAC, _cfgs[i].ctrlb); + hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); + } + + NVIC_DisableIRQ(DMAC_IRQn); + NVIC_ClearPendingIRQ(DMAC_IRQn); + NVIC_EnableIRQ(DMAC_IRQn); + + hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); + + return ERR_NONE; +} + +/** + * \brief Enable/disable DMA interrupt + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + + if (DMA_TRANSFER_COMPLETE_CB == type) { + hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, state); + } else if (DMA_TRANSFER_ERROR_CB == type) { + hri_dmac_write_CHINTEN_TERR_bit(DMAC, state); + } +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) +{ + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], + (uint32_t)&_descriptor_section[next_channel]); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); + uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); + hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC); + if (software_trigger) { + hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +/** + * \internal DMAC interrupt handler + */ +static inline void _dmac_handler(void) +{ + uint8_t channel = hri_dmac_read_INTPEND_ID_bf(DMAC); + uint8_t current_channel = hri_dmac_read_CHID_reg(DMAC); + uint8_t flag_status; + struct _dma_resource *tmp_resource = &_resources[channel]; + + hri_dmac_write_CHID_reg(DMAC, channel); + flag_status = hri_dmac_get_CHINTFLAG_reg(DMAC, DMAC_CHINTFLAG_MASK); + + if (flag_status & DMAC_CHINTFLAG_TERR) { + hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC); + tmp_resource->dma_cb.error(tmp_resource); + } else if (flag_status & DMAC_CHINTFLAG_TCMPL) { + hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC); + tmp_resource->dma_cb.transfer_done(tmp_resource); + } + hri_dmac_write_CHID_reg(DMAC, current_channel); +} + +/** + * \brief DMAC interrupt handler + */ +void DMAC_Handler(void) +{ + _dmac_handler(); +} + +#endif /* CONF_DMAC_ENABLE */ diff --git a/watch-library/hardware/hpl/eic/hpl_eic.c b/watch-library/hardware/hpl/eic/hpl_eic.c new file mode 100644 index 00000000..2bd31615 --- /dev/null +++ b/watch-library/hardware/hpl/eic/hpl_eic.c @@ -0,0 +1,255 @@ + +/** + * \file + * + * \brief EIC related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include + +#ifdef __MINGW32__ +#define ffs __builtin_ffs +#endif +#if defined(__CC_ARM) || defined(__ICCARM__) +/* Find the first bit set */ +static int ffs(int v) +{ + int i, bit = 1; + for (i = 0; i < sizeof(int) * 8; i++) { + if (v & bit) { + return i + 1; + } + bit <<= 1; + } + return 0; +} +#endif + +/** + * \brief Invalid external interrupt and pin numbers + */ +#define INVALID_EXTINT_NUMBER 0xFF +#define INVALID_PIN_NUMBER 0xFFFFFFFF + +#ifndef CONFIG_EIC_EXTINT_MAP +/** Dummy mapping to pass compiling. */ +#define CONFIG_EIC_EXTINT_MAP \ + { \ + INVALID_EXTINT_NUMBER, INVALID_PIN_NUMBER \ + } +#endif + +#define EXT_IRQ_AMOUNT 6 + +/** + * \brief EXTINTx and pin number map + */ +struct _eic_map { + uint8_t extint; + uint32_t pin; +}; + +/** + * \brief PIN and EXTINT map for enabled external interrupts + */ +static const struct _eic_map _map[] = {CONFIG_EIC_EXTINT_MAP}; + +/** + * \brief The callback to upper layer's interrupt processing routine + */ +static void (*callback)(const uint32_t pin); + +static void _ext_irq_handler(void); + +/** + * \brief Initialize external interrupt module + */ +int32_t _ext_irq_init(void (*cb)(const uint32_t pin)) +{ + if (!hri_eic_is_syncing(EIC, EIC_SYNCBUSY_SWRST)) { + if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) { + hri_eic_clear_CTRLA_ENABLE_bit(EIC); + hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE); + } + hri_eic_write_CTRLA_reg(EIC, EIC_CTRLA_SWRST); + } + hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST); + + hri_eic_write_CTRLA_CKSEL_bit(EIC, CONF_EIC_CKSEL); + + hri_eic_write_NMICTRL_reg(EIC, + (CONF_EIC_NMIFILTEN << EIC_NMICTRL_NMIFILTEN_Pos) + | EIC_NMICTRL_NMISENSE(CONF_EIC_NMISENSE) | EIC_ASYNCH_ASYNCH(CONF_EIC_NMIASYNCH) + | 0); + + hri_eic_write_EVCTRL_reg(EIC, + (CONF_EIC_EXTINTEO0 << 0) | (CONF_EIC_EXTINTEO1 << 1) | (CONF_EIC_EXTINTEO2 << 2) + | (CONF_EIC_EXTINTEO3 << 3) | (CONF_EIC_EXTINTEO4 << 4) | (CONF_EIC_EXTINTEO5 << 5) + | (CONF_EIC_EXTINTEO6 << 6) | (CONF_EIC_EXTINTEO7 << 7) | (CONF_EIC_EXTINTEO8 << 8) + | (CONF_EIC_EXTINTEO9 << 9) | (CONF_EIC_EXTINTEO10 << 10) | (CONF_EIC_EXTINTEO11 << 11) + | (CONF_EIC_EXTINTEO12 << 12) | (CONF_EIC_EXTINTEO13 << 13) + | (CONF_EIC_EXTINTEO14 << 14) | (CONF_EIC_EXTINTEO15 << 15) | 0); + hri_eic_write_ASYNCH_reg(EIC, + (CONF_EIC_ASYNCH0 << 0) | (CONF_EIC_ASYNCH1 << 1) | (CONF_EIC_ASYNCH2 << 2) + | (CONF_EIC_ASYNCH3 << 3) | (CONF_EIC_ASYNCH4 << 4) | (CONF_EIC_ASYNCH5 << 5) + | (CONF_EIC_ASYNCH6 << 6) | (CONF_EIC_ASYNCH7 << 7) | (CONF_EIC_ASYNCH8 << 8) + | (CONF_EIC_ASYNCH9 << 9) | (CONF_EIC_ASYNCH10 << 10) | (CONF_EIC_ASYNCH11 << 11) + | (CONF_EIC_ASYNCH12 << 12) | (CONF_EIC_ASYNCH13 << 13) | (CONF_EIC_ASYNCH14 << 14) + | (CONF_EIC_ASYNCH15 << 15) | 0); + + hri_eic_write_CONFIG_reg(EIC, + 0, + (CONF_EIC_FILTEN0 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE0) + | (CONF_EIC_FILTEN1 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE1) + | (CONF_EIC_FILTEN2 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE2) + | (CONF_EIC_FILTEN3 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE3) + | (CONF_EIC_FILTEN4 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE4) + | (CONF_EIC_FILTEN5 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE5) + | (CONF_EIC_FILTEN6 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE6) + | (CONF_EIC_FILTEN7 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE7) + | 0); + + hri_eic_write_CONFIG_reg(EIC, + 1, + (CONF_EIC_FILTEN8 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE8) + | (CONF_EIC_FILTEN9 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE9) + | (CONF_EIC_FILTEN10 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE10) + | (CONF_EIC_FILTEN11 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE11) + | (CONF_EIC_FILTEN12 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE12) + | (CONF_EIC_FILTEN13 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE13) + | (CONF_EIC_FILTEN14 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE14) + | (CONF_EIC_FILTEN15 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE15) + | 0); + + hri_eic_set_CTRLA_ENABLE_bit(EIC); + NVIC_DisableIRQ(EIC_IRQn); + NVIC_ClearPendingIRQ(EIC_IRQn); + NVIC_EnableIRQ(EIC_IRQn); + + callback = cb; + + return ERR_NONE; +} + +/** + * \brief De-initialize external interrupt module + */ +int32_t _ext_irq_deinit(void) +{ + NVIC_DisableIRQ(EIC_IRQn); + callback = NULL; + + hri_eic_clear_CTRLA_ENABLE_bit(EIC); + hri_eic_set_CTRLA_SWRST_bit(EIC); + + return ERR_NONE; +} + +/** + * \brief Enable / disable external irq + */ +int32_t _ext_irq_enable(const uint32_t pin, const bool enable) +{ + uint8_t extint = INVALID_EXTINT_NUMBER; + uint8_t i = 0; + + for (; i < ARRAY_SIZE(_map); i++) { + if (_map[i].pin == pin) { + extint = _map[i].extint; + break; + } + } + if (INVALID_EXTINT_NUMBER == extint) { + return -1; + } + + if (enable) { + hri_eic_set_INTEN_reg(EIC, 1ul << extint); + } else { + hri_eic_clear_INTEN_reg(EIC, 1ul << extint); + hri_eic_clear_INTFLAG_reg(EIC, 1ul << extint); + } + + return ERR_NONE; +} + +/** + * \brief Inter EIC interrupt handler + */ +static void _ext_irq_handler(void) +{ + volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC); + int8_t pos; + uint32_t pin = INVALID_PIN_NUMBER; + + hri_eic_clear_INTFLAG_reg(EIC, flags); + + ASSERT(callback); + + while (flags) { + pos = ffs(flags) - 1; + while (-1 != pos) { + uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; + + while (upper >= lower) { + middle = (upper + lower) >> 1; + if (_map[middle].extint == pos) { + pin = _map[middle].pin; + break; + } + if (_map[middle].extint < pos) { + lower = middle + 1; + } else { + upper = middle - 1; + } + } + + if (INVALID_PIN_NUMBER != pin) { + callback(pin); + } + flags &= ~(1ul << pos); + pos = ffs(flags) - 1; + } + flags = hri_eic_read_INTFLAG_reg(EIC); + hri_eic_clear_INTFLAG_reg(EIC, flags); + } +} + +/** + * \brief EIC interrupt handler + */ +void EIC_Handler(void) +{ + _ext_irq_handler(); +} diff --git a/watch-library/hardware/hpl/gclk/hpl_gclk.c b/watch-library/hardware/hpl/gclk/hpl_gclk.c new file mode 100644 index 00000000..be66ef77 --- /dev/null +++ b/watch-library/hardware/hpl/gclk/hpl_gclk.c @@ -0,0 +1,164 @@ + +/** + * \file + * + * \brief Generic Clock Controller related functionality. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +/* Compatible naming definition */ +#ifndef GCLK_GENCTRL_SRC_DPLL +#define GCLK_GENCTRL_SRC_DPLL GCLK_GENCTRL_SRC_FDPLL +#endif + +/** + * \brief Initializes generators + */ +void _gclk_init_generators(void) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); +#endif +} + +void _gclk_init_generators_by_fref(uint32_t bm) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + if (bm & (1ul << 0)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + if (bm & (1ul << 1)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + if (bm & (1ul << 2)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + if (bm & (1ul << 3)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + if (bm & (1ul << 4)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); + } +#endif +} diff --git a/watch-library/hardware/hpl/gclk/hpl_gclk_base.h b/watch-library/hardware/hpl/gclk/hpl_gclk_base.h new file mode 100644 index 00000000..3e7d2825 --- /dev/null +++ b/watch-library/hardware/hpl/gclk/hpl_gclk_base.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief Generic Clock Controller. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GCLK_H_INCLUDED +#define _HPL_GCLK_H_INCLUDED + +#include +#ifdef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup gclk_group GCLK Hardware Proxy Layer + * + * \section gclk_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Enable clock on the given channel with the given clock source + * + * This function maps the given clock source to the given clock channel + * and enables channel. + * + * \param[in] channel The channel to enable clock for + * \param[in] source The clock source for the given channel + */ +static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); +} + +/** + * \brief Initialize GCLK generators by function references + * \param[in] bm Bit mapping for referenced generators, + * a bit 1 in position triggers generator initialization. + */ +void _gclk_init_generators_by_fref(uint32_t bm); + +//@} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/watch-library/hardware/hpl/mclk/hpl_mclk.c b/watch-library/hardware/hpl/mclk/hpl_mclk.c new file mode 100644 index 00000000..46e7c853 --- /dev/null +++ b/watch-library/hardware/hpl/mclk/hpl_mclk.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief SAM Main Clock. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void) +{ + void *hw = (void *)MCLK; + hri_mclk_write_BUPDIV_reg(hw, MCLK_BUPDIV_BUPDIV(CONF_MCLK_BUPDIV)); + hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_CPUDIV(CONF_MCLK_CPUDIV)); +} diff --git a/watch-library/hardware/hpl/nvmctrl/hpl_nvmctrl.c b/watch-library/hardware/hpl/nvmctrl/hpl_nvmctrl.c new file mode 100755 index 00000000..c1d42c5e --- /dev/null +++ b/watch-library/hardware/hpl/nvmctrl/hpl_nvmctrl.c @@ -0,0 +1,782 @@ + +/** + * \file + * + * \brief Non-Volatile Memory Controller + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#define NVM_MEMORY ((volatile uint16_t *)FLASH_ADDR) + +/** + * \brief NVM configuration type + */ +struct nvm_configuration { + hri_nvmctrl_ctrlb_reg_t ctrlb; /*!< Control B Register */ +}; + +/** + * \brief Array of NVM configurations + */ +static struct nvm_configuration _nvm + = {(CONF_NVM_CACHE << NVMCTRL_CTRLB_CACHEDIS_Pos) | (CONF_NVM_READ_MODE << NVMCTRL_CTRLB_READMODE_Pos) + | (CONF_NVM_SLEEPPRM << NVMCTRL_CTRLB_SLEEPPRM_Pos)}; + +/*!< Pointer to hpl device */ +static struct _flash_device *_nvm_dev = NULL; + +static void _flash_erase_row(void *const hw, const uint32_t dst_addr, uint32_t nvmctrl_cmd); +static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size, + uint32_t nvmctrl_cmd); + +/** + * \brief Initialize NVM + */ +int32_t _flash_init(struct _flash_device *const device, void *const hw) +{ + ASSERT(device && (hw == NVMCTRL)); + uint32_t ctrlb; + + device->hw = hw; + ctrlb = _nvm.ctrlb & ~(NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW); + ctrlb |= hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW); + hri_nvmctrl_write_CTRLB_reg(device->hw, ctrlb); + + _nvm_dev = device; + NVIC_DisableIRQ(NVMCTRL_IRQn); + NVIC_ClearPendingIRQ(NVMCTRL_IRQn); + NVIC_EnableIRQ(NVMCTRL_IRQn); + return ERR_NONE; +} + +/** + * \brief De-initialize NVM + */ +void _flash_deinit(struct _flash_device *const device) +{ + device->hw = NULL; + NVIC_DisableIRQ(NVMCTRL_IRQn); +} + +/** + * \brief Get the flash page size. + */ +uint32_t _flash_get_page_size(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)NVMCTRL_PAGE_SIZE; +} + +/** + * \brief Get the numbers of flash page. + */ +uint32_t _flash_get_total_pages(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)FLASH_NB_OF_PAGES; +} + +/** + * \brief Get the number of wait states for read and write operations. + */ +uint8_t _flash_get_wait_state(struct _flash_device *const device) +{ + return hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk); +} + +/** + * \brief Set the number of wait states for read and write operations. + */ +void _flash_set_wait_state(struct _flash_device *const device, uint8_t state) +{ + hri_nvmctrl_write_CTRLB_RWS_bf(device->hw, state); +} + +/** + * \brief Reads a number of bytes to a page in the internal Flash. + */ +void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length) +{ + uint32_t nvm_address = src_addr / 2; + uint32_t i; + uint16_t data; + + /* Check if the module is busy */ + while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); + + /* Check whether byte address is word-aligned*/ + if (src_addr % 2) { + data = NVM_MEMORY[nvm_address++]; + buffer[0] = data >> 8; + i = 1; + } else { + i = 0; + } + + /* NVM _must_ be accessed as a series of 16-bit words, perform manual copy + * to ensure alignment */ + while (i < length) { + data = NVM_MEMORY[nvm_address++]; + buffer[i] = (data & 0xFF); + if (i < (length - 1)) { + buffer[i + 1] = (data >> 8); + } + i += 2; + } +} + +/** + * \brief Writes a number of bytes to a page in the internal Flash. + */ +void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE]; + uint32_t row_start_addr, row_end_addr; + uint32_t i, j, k; + uint32_t wr_start_addr = dst_addr; + + do { + row_start_addr = wr_start_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + row_end_addr = row_start_addr + NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE - 1; + + /* store the erase data into temp buffer before write */ + for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { + _flash_read(device, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); + } + + /* temp buffer update */ + j = (wr_start_addr - row_start_addr) / NVMCTRL_PAGE_SIZE; + k = wr_start_addr - row_start_addr - j * NVMCTRL_PAGE_SIZE; + while ((wr_start_addr <= row_end_addr) && (length > 0)) { + tmp_buffer[j][k] = *buffer; + k = (k + 1) % NVMCTRL_PAGE_SIZE; + if (0 == k) { + j++; + } + wr_start_addr++; + buffer++; + length--; + } + + /* erase row before write */ + _flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_ER); + + /* write buffer to flash */ + for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { + _flash_program(device->hw, + row_start_addr + i * NVMCTRL_PAGE_SIZE, + tmp_buffer[i], + NVMCTRL_PAGE_SIZE, + NVMCTRL_CTRLA_CMD_WP); + } + + } while (row_end_addr < (wr_start_addr + length - 1)); +} + +/** + * \brief Appends a number of bytes in the internal Flash. + */ +void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1); + uint32_t size; + uint32_t offset = 0; + + if (dst_addr != page_start_addr) { + /* Need to write some data to the end of a page */ + size = min(length, NVMCTRL_PAGE_SIZE - (dst_addr - page_start_addr)); + _flash_program(device->hw, dst_addr, buffer, size, NVMCTRL_CTRLA_CMD_WP); + page_start_addr += NVMCTRL_PAGE_SIZE; + offset += size; + } + + while (offset < length) { + size = min(length - offset, NVMCTRL_PAGE_SIZE); + _flash_program(device->hw, page_start_addr, buffer + offset, size, NVMCTRL_CTRLA_CMD_WP); + page_start_addr += NVMCTRL_PAGE_SIZE; + offset += size; + } +} + +/** + * \brief Execute erase in the internal flash + */ +void _flash_erase(struct _flash_device *const device, uint32_t dst_addr, uint32_t page_nums) +{ + uint8_t tmp_buffer[NVMCTRL_PAGE_SIZE]; + uint32_t row_start_addr; + uint32_t i; + + row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + + memset(tmp_buffer, 0xFF, NVMCTRL_PAGE_SIZE); + + /* when address is not aligned with row start address */ + if (dst_addr != row_start_addr) { + row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE; + for (i = 0; i < NVMCTRL_ROW_PAGES - 1; i++) { + _flash_write(device, dst_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); + if (--page_nums == 0) { + return; + } + dst_addr += NVMCTRL_PAGE_SIZE; + if (dst_addr == row_start_addr) { + break; + } + } + } + + while (page_nums >= NVMCTRL_ROW_PAGES) { + _flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_ER); + row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE; + page_nums -= NVMCTRL_ROW_PAGES; + } + + if (page_nums != 0) { + for (i = 0; i < page_nums; i++) { + _flash_write(device, row_start_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); + row_start_addr += NVMCTRL_PAGE_SIZE; + } + } +} + +/** + * \brief Execute lock in the internal flash + */ +int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) +{ + uint32_t region_pages; + uint32_t row_start_addr; + + region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); + row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + + if ((page_nums != region_pages) || (dst_addr != row_start_addr)) { + return ERR_INVALID_ARG; + } + + while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); + + hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_LR | NVMCTRL_CTRLA_CMDEX_KEY); + + return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); +} + +/** + * \brief Execute unlock in the internal flash + */ +int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) +{ + uint32_t region_pages; + uint32_t row_start_addr; + + region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); + row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + + if ((page_nums != region_pages) || (dst_addr != row_start_addr)) { + return ERR_INVALID_ARG; + } + + while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); + + hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_UR | NVMCTRL_CTRLA_CMDEX_KEY); + + return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); +} + +/** + * \brief check whether the region which is pointed by address + */ +bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr) +{ + uint16_t region_id; + + /* Get region for given page */ + region_id = dst_addr / (NVMCTRL_FLASH_SIZE / 16); + + return !(hri_nvmctrl_get_LOCK_reg(device->hw, 1 << region_id)); +} + +/** + * \brief Enable/disable Flash interrupt + */ +void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state) +{ + ASSERT(device); + + if (FLASH_DEVICE_CB_READY == type) { + hri_nvmctrl_write_INTEN_READY_bit(device->hw, state); + } else if (FLASH_DEVICE_CB_ERROR == type) { + hri_nvmctrl_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal erase a row in flash + * \param[in] hw The pointer to hardware instance + * \param[in] dst_addr Destination page address to erase + */ +static void _flash_erase_row(void *const hw, const uint32_t dst_addr, uint32_t nvmctrl_cmd) +{ + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); + + /* Set address and command */ + hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(hw, nvmctrl_cmd | NVMCTRL_CTRLA_CMDEX_KEY); +} + +/** + * \internal write a page in flash + * \param[in] hw The pointer to hardware instance + * \param[in] dst_addr Destination page address to write + * \param[in] buffer Pointer to buffer where the data to + * write is stored + * \param[in] size The size of data to write to a page + */ +static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size, + uint32_t nvmctrl_cmd) +{ + ASSERT(!(dst_addr % 2)); + + uint32_t nvm_address = dst_addr / 2; + uint16_t i, data; + + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY); + + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); + + for (i = 0; i < size; i += 2) { + data = buffer[i]; + if (i < NVMCTRL_PAGE_SIZE - 1) { + data |= (buffer[i + 1] << 8); + } + NVM_MEMORY[nvm_address++] = data; + } + + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(hw, nvmctrl_cmd | NVMCTRL_CTRLA_CMDEX_KEY); +} + +/** + * \internal NVM interrupt handler + */ +void NVMCTRL_Handler(void) +{ + void *const hw = _nvm_dev->hw; + + if (hri_nvmctrl_get_interrupt_READY_bit(hw)) { + if (NULL != _nvm_dev->flash_cb.ready_cb) { + _nvm_dev->flash_cb.ready_cb(_nvm_dev); + } + } else if (hri_nvmctrl_get_interrupt_ERROR_bit(hw)) { + hri_nvmctrl_clear_interrupt_ERROR_bit(hw); + if (NULL != _nvm_dev->flash_cb.error_cb) { + _nvm_dev->flash_cb.error_cb(_nvm_dev); + } + } +} + +/* +The NVM User Row contains calibration data that are automatically read at device +power on. +The NVM User Row can be read at address 0x804000. +*/ +#ifndef _NVM_USER_ROW_BASE +#define _NVM_USER_ROW_BASE 0x804000 +#endif +#define _NVM_USER_ROW_N_BITS 64 +#define _NVM_USER_ROW_N_BYTES (_NVM_USER_ROW_N_BITS / 8) +#define _NVM_USER_ROW_END (((uint8_t *)_NVM_USER_ROW_BASE) + _NVM_USER_ROW_N_BYTES - 1) +#define _IS_NVM_USER_ROW(b) \ + (((uint8_t *)(b) >= (uint8_t *)(_NVM_USER_ROW_BASE)) && ((uint8_t *)(b) <= (uint8_t *)(_NVM_USER_ROW_END))) +#define _IN_NVM_USER_ROW(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_USER_ROW_END)) + +/* +The NVM Software Calibration Area can be read at address 0x806020. +The NVM Software Calibration Area can not be written. +*/ +#ifndef _NVM_SW_CALIB_AREA_BASE +#define _NVM_SW_CALIB_AREA_BASE 0x806020 +#endif +#define _NVM_SW_CALIB_AREA_N_BITS 128 +#define _NVM_SW_CALIB_AREA_N_BYTES (_NVM_SW_CALIB_AREA_N_BITS / 8) +#define _NVM_SW_CALIB_AREA_END (((uint8_t *)_NVM_SW_CALIB_AREA_BASE) + _NVM_SW_CALIB_AREA_N_BYTES - 1) +#define _IS_NVM_SW_CALIB_AREA(b) \ + (((uint8_t *)(b) >= (uint8_t *)_NVM_SW_CALIB_AREA_BASE) && ((uint8_t *)(b) <= (uint8_t *)_NVM_SW_CALIB_AREA_END)) +#define _IN_NVM_SW_CALIB_AREA(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_SW_CALIB_AREA_END)) + +/** + * \internal Read left aligned data bits + * \param[in] base Base address for the data + * \param[in] bit_offset Offset for the bitfield start + * \param[in] n_bits Number of bits in the bitfield + */ +static inline uint32_t _user_area_read_l32_bits(const volatile uint32_t *base, const uint32_t bit_offset, + const uint8_t n_bits) +{ + return base[bit_offset >> 5] & ((1 << n_bits) - 1); +} + +/** + * \internal Read right aligned data bits + * \param[in] base Base address for the data + * \param[in] bit_offset Offset for the bitfield start + * \param[in] n_bits Number of bits in the bitfield + */ +static inline uint32_t _user_area_read_r32_bits(const volatile uint32_t *base, const uint32_t bit_offset, + const uint8_t n_bits) +{ + return (base[bit_offset >> 5] >> (bit_offset & 0x1F)) & ((1 << n_bits) - 1); +} + +int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, uint32_t size) +{ + ASSERT(buf); + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, offset)) { + return ERR_BAD_ADDRESS; + } + /* Cut off if request too many bytes */ + if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + if (!_IN_NVM_SW_CALIB_AREA(base, offset)) { + return ERR_BAD_ADDRESS; + } + /* Cut off if request too many bytes */ + if (!_IN_NVM_SW_CALIB_AREA(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else { + return ERR_UNSUPPORTED_OP; + } + + /* Copy data */ + memcpy(buf, ((uint8_t *)base) + offset, size); + return ERR_NONE; +} + +uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits) +{ + volatile uint32_t *mem_base = (volatile uint32_t *)base; + uint32_t l_off, l_bits; + uint32_t r_off, r_bits; + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + ASSERT(_IN_NVM_USER_ROW(base, bit_offset >> 3) && _IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)); + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + ASSERT(_IN_NVM_SW_CALIB_AREA(base, bit_offset >> 3) + && _IN_NVM_SW_CALIB_AREA(base, (bit_offset + n_bits - 1) >> 3)); + } else { + ASSERT(false); + } + + /* Since the bitfield can cross 32-bits boundaries, + * left and right bits are read from 32-bit aligned address + * and then combined together. */ + l_off = bit_offset & (~(32 - 1)); + r_off = l_off + 32; + l_bits = 32 - (bit_offset & (32 - 1)); + if (n_bits > l_bits) { + r_bits = n_bits - l_bits; + } else { + l_bits = n_bits; + r_bits = 0; + } + return _user_area_read_r32_bits(mem_base, bit_offset, l_bits) + + (_user_area_read_l32_bits(mem_base, r_off, r_bits) << l_bits); +} + +/** \internal Write 64-bit user row + * \param[in] _row Pointer to 64-bit user row data. + */ +static int32_t _user_row_write_exec(const uint32_t *_row) +{ + Nvmctrl *hw = NVMCTRL; + uint32_t ctrlb = hri_nvmctrl_read_CTRLB_reg(NVMCTRL); + + /* Denie if Security Bit is set */ + if (hri_nvmctrl_get_STATUS_reg(hw, NVMCTRL_STATUS_SB)) { + return ERR_DENIED; + } + + /* Do Save */ + + /* - Prepare. */ + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); + hri_nvmctrl_set_CTRLB_MANW_bit(hw); + + /* - Erase AUX row. */ + hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)(_NVM_USER_ROW_BASE / 2)); + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_EAR | NVMCTRL_CTRLA_CMDEX_KEY); + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + + /* - Page buffer clear & write. */ + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY); + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + *((uint32_t *)NVMCTRL_AUX0_ADDRESS) = _row[0]; + *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1) = _row[1]; + + /* - Write AUX row. */ + hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)(_NVM_USER_ROW_BASE / 2)); + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_WAP | NVMCTRL_CTRLA_CMDEX_KEY); + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + + /* Restore CTRLB */ + hri_nvmctrl_write_CTRLB_reg(NVMCTRL, ctrlb); + + return ERR_NONE; +} + +int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size) +{ + uint32_t _row[2]; /* Copy of user row. */ + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, offset)) { + return ERR_BAD_ADDRESS; + } else if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + return ERR_DENIED; + } else { + return ERR_UNSUPPORTED_OP; + } + + memcpy(_row, base, 8); /* Store previous data. */ + memcpy((uint8_t *)_row + offset, buf, size); /* Modify with buf data. */ + + return _user_row_write_exec(_row); +} + +int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits) +{ + uint32_t _row[2]; /* Copy of user row. */ + uint32_t l_off, l_bits; + uint32_t r_off, r_bits; + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, bit_offset >> 3)) { + return ERR_BAD_ADDRESS; + } else if (!_IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + return ERR_DENIED; + } else { + return ERR_UNSUPPORTED_OP; + } + + /* Since the bitfield can cross 32-bits boundaries, + * left and right bits are splitted for 32-bit aligned address + * and then saved. */ + l_off = bit_offset & (~(32 - 1)); + r_off = l_off + 32; + l_bits = 32 - (bit_offset & (32 - 1)); + if (n_bits > l_bits) { + r_bits = n_bits - l_bits; + } else { + l_bits = n_bits; + r_bits = 0; + } + + memcpy(_row, base, 8); /* Store previous data. */ + if (l_bits) { + uint32_t l_mask = ((1 << l_bits) - 1) << (bit_offset & (32 - 1)); + _row[bit_offset >> 5] &= ~l_mask; + _row[bit_offset >> 5] |= (bits << (bit_offset & (32 - 1))) & l_mask; + } + if (r_bits) { + uint32_t r_mask = (1 << r_bits) - 1; + _row[r_off >> 5] &= ~r_mask; + _row[r_off >> 5] |= bits >> l_bits; + } + return _user_row_write_exec(_row); +} + +/** + * \brief Return if given address is in Flash RWWEE array range. + */ +static bool _is_valid_rww_flash_address(uint32_t addr) +{ +#define RWWEE_ADDR_START NVMCTRL_RWW_EEPROM_ADDR +#define RWWEE_ADDR_END (NVMCTRL_RWW_EEPROM_ADDR + NVMCTRL_PAGE_SIZE * NVMCTRL_RWWEE_PAGES) + + if ((addr < NVMCTRL_RWW_EEPROM_ADDR) + || (addr > (NVMCTRL_RWW_EEPROM_ADDR + NVMCTRL_PAGE_SIZE * NVMCTRL_RWWEE_PAGES))) { + return false; + } + return true; +} + +/** + * \brief Get the RWWEE flash page size. + */ +uint32_t _rww_flash_get_page_size(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)NVMCTRL_PAGE_SIZE; +} + +/** + * \brief Get the total page numbers of RWWEE flash. + */ +uint32_t _rww_flash_get_total_pages(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)NVMCTRL_RWWEE_PAGES; +} + +/** + * \brief Reads a number of bytes in the internal RWWEE Flash. + */ +int32_t _rww_flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length) +{ + /* Check if the address is valid */ + if (!_is_valid_rww_flash_address(src_addr) || !_is_valid_rww_flash_address(src_addr + length)) { + return ERR_BAD_ADDRESS; + } + + _flash_read(device, src_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Writes a number of bytes in the internal RWWEE Flash. + */ +int32_t _rww_flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE]; + uint32_t row_start_addr, row_end_addr; + uint32_t i, j, k; + uint32_t wr_start_addr = dst_addr; + + /* Check if the address is valid */ + if (!_is_valid_rww_flash_address(dst_addr) || !_is_valid_rww_flash_address(dst_addr + length)) { + return ERR_BAD_ADDRESS; + } + + do { + row_start_addr = wr_start_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + row_end_addr = row_start_addr + NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE - 1; + + /* store the erase data into temp buffer before write */ + for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { + _rww_flash_read(device, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); + } + + /* temp buffer update */ + j = (wr_start_addr - row_start_addr) / NVMCTRL_PAGE_SIZE; + k = wr_start_addr - row_start_addr - j * NVMCTRL_PAGE_SIZE; + while ((wr_start_addr <= row_end_addr) && (length > 0)) { + tmp_buffer[j][k] = *buffer; + k = (k + 1) % NVMCTRL_PAGE_SIZE; + if (0 == k) { + j++; + } + wr_start_addr++; + buffer++; + length--; + } + + /* erase row before write */ + _flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_RWWEEER); + + /* write buffer to flash */ + for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { + _flash_program(device->hw, + row_start_addr + i * NVMCTRL_PAGE_SIZE, + tmp_buffer[i], + NVMCTRL_PAGE_SIZE, + NVMCTRL_CTRLA_CMD_RWWEEWP); + } + + } while (row_end_addr < (wr_start_addr + length - 1)); + + return ERR_NONE; +} diff --git a/watch-library/hardware/hpl/osc32kctrl/hpl_osc32kctrl.c b/watch-library/hardware/hpl/osc32kctrl/hpl_osc32kctrl.c new file mode 100644 index 00000000..b6c624cc --- /dev/null +++ b/watch-library/hardware/hpl/osc32kctrl/hpl_osc32kctrl.c @@ -0,0 +1,86 @@ +/** + * \file + * + * \brief SAM 32k Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void) +{ + void * hw = (void *)OSC32KCTRL; + uint16_t calib = 0; + +#if CONF_XOSC32K_CONFIG == 1 + hri_osc32kctrl_write_XOSC32K_reg( + hw, + OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) + | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) + | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) + | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) + | (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); + + hri_osc32kctrl_write_CFDCTRL_reg(hw, + (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos) + | (CONF_XOSC32K_SWBEN << OSC32KCTRL_CFDCTRL_SWBACK_Pos)); + + hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); +#endif + +#if CONF_OSCULP32K_CONFIG == 1 + calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); + hri_osc32kctrl_write_OSCULP32K_reg(hw, +#if CONF_OSC32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB) +#else + OSC32KCTRL_OSCULP32K_CALIB(calib) +#endif + ); +#endif + +#if CONF_XOSC32K_CONFIG +#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) + ; +#endif +#if CONF_OSCULP32K_ULP32KSW == 1 + hri_osc32kctrl_set_OSCULP32K_reg(hw, OSC32KCTRL_OSCULP32K_ULP32KSW); + while (!hri_osc32kctrl_get_STATUS_ULP32KSW_bit(hw)) + ; +#endif +#endif + + hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); + (void)calib; +} diff --git a/watch-library/hardware/hpl/oscctrl/hpl_oscctrl.c b/watch-library/hardware/hpl/oscctrl/hpl_oscctrl.c new file mode 100644 index 00000000..e11d70d8 --- /dev/null +++ b/watch-library/hardware/hpl/oscctrl/hpl_oscctrl.c @@ -0,0 +1,179 @@ + +/** + * \file + * + * \brief SAM Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_XOSC_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg( + hw, + OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC_STARTUP) | (0 << OSCCTRL_XOSCCTRL_AMPGC_Pos) + | OSCCTRL_XOSCCTRL_GAIN(CONF_XOSC_GAIN) | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) + | (CONF_XOSC_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) | (CONF_XOSC_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) + | (CONF_XOSC_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) | (CONF_XOSC_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) + | (CONF_XOSC_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); + + hri_oscctrl_write_EVCTRL_reg(hw, (CONF_XOSC_CFDEO << OSCCTRL_EVCTRL_CFDEO_Pos)); +#endif + +#if CONF_OSC16M_CONFIG == 1 + hri_oscctrl_write_OSC16MCTRL_reg(hw, + (CONF_OSC16M_ONDEMAND << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos) + | (CONF_OSC16M_RUNSTDBY << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos) + | (CONF_OSC16M_ENABLE << OSCCTRL_OSC16MCTRL_ENABLE_Pos) + | OSCCTRL_OSC16MCTRL_FSEL(CONF_OSC16M_FSEL)); +#endif + +#if CONF_XOSC_CONFIG == 1 +#if CONF_XOSC_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY_bit(hw)) + ; +#endif +#if CONF_XOSC_AMPGC == 1 + hri_oscctrl_set_XOSCCTRL_AMPGC_bit(hw); +#endif +#if CONF_XOSC_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_OSC16M_CONFIG == 1 +#if CONF_OSC16M_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_OSC16MRDY_bit(hw)) + ; +#endif +#if CONF_OSC16M_ONDEMAND == 1 + hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(hw); +#endif +#endif + (void)hw; +} + +void _oscctrl_init_referenced_generators(void) +{ + void * hw = (void *)OSCCTRL; + hri_oscctrl_dfllctrl_reg_t tmp = 0; + +#if CONF_DFLL_CONFIG == 1 +#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 +#define NVM_DFLL_COARSE_POS 26 +#define NVM_DFLL_COARSE_SIZE 6 + uint32_t coarse; + coarse = *((uint32_t *)(NVMCTRL_OTP5)) >> NVM_DFLL_COARSE_POS; +#endif +#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 + hri_gclk_write_PCHCTRL_reg(GCLK, 0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); +#endif + hri_oscctrl_write_DFLLCTRL_reg(hw, OSCCTRL_DFLLCTRL_ENABLE); + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + hri_oscctrl_write_DFLLMUL_reg(hw, + OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) + | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + +#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 + /* FINE is set to fixed value, which defined by DFLL48M Characteristics */ + hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(coarse) | OSCCTRL_DFLLVAL_FINE(512)); +#else + hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); +#endif + + tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRL_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRL_BPLCKC_Pos) + | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRL_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRL_CCDIS_Pos) + | (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos) | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRL_USBCRM_Pos) + | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRL_LLAW_Pos) | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRL_STABLE_Pos) + | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRL_MODE_Pos) | (CONF_DFLL_ENABLE << OSCCTRL_DFLLCTRL_ENABLE_Pos); + hri_oscctrl_write_DFLLCTRL_reg(hw, tmp); + +#endif + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_REFCLK == 2 + hri_gclk_write_PCHCTRL_reg(GCLK, 1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DPLL_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_DPLL_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_DPLL_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + OSCCTRL_DPLLCTRLB_DIV(CONF_DPLL_DIV) | (CONF_DPLL_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) + | OSCCTRL_DPLLCTRLB_LTIME(CONF_DPLL_LTIME) | OSCCTRL_DPLLCTRLB_REFCLK(CONF_DPLL_REFCLK) + | (CONF_DPLL_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) | (CONF_DPLL_LPEN << OSCCTRL_DPLLCTRLB_LPEN_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_DPLL_FILTER)); + hri_oscctrl_write_DPLLPRESC_reg(hw, OSCCTRL_DPLLPRESC_PRESC(CONF_DPLL_PRESC)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + (0 << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) + | (CONF_DPLL_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_DPLL_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_DFLL_CONFIG == 1 + if (hri_oscctrl_get_DFLLCTRL_MODE_bit(hw)) { + hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; + + while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) + ; + } else { + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + } +#if CONF_DFLL_ONDEMAND == 1 + hri_oscctrl_set_DFLLCTRL_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw))) + ; +#endif +#if CONF_DPLL_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_DFLL_CONFIG == 1 + while (hri_gclk_read_SYNCBUSY_reg(GCLK)) + ; +#endif + (void)hw, (void)tmp; +} diff --git a/watch-library/hardware/hpl/pm/hpl_pm.c b/watch-library/hardware/hpl/pm/hpl_pm.c new file mode 100644 index 00000000..d6439f1d --- /dev/null +++ b/watch-library/hardware/hpl/pm/hpl_pm.c @@ -0,0 +1,77 @@ + +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Retrieve the reset reason + */ +enum reset_reason _get_reset_reason(void) +{ + return (enum reset_reason)hri_rstc_read_RCAUSE_reg(RSTC); +} + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + switch (mode) { + case 2: /* IDLE */ + case 4: /* STANDBY */ + case 5: /* BACKUP */ + case 6: /* OFF */ + hri_pm_write_SLEEPCFG_SLEEPMODE_bf(PM, mode); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Set performance level + */ +void _set_performance_level(const uint8_t level) +{ + if (hri_pm_get_PLCFG_PLSEL_bf(PM, PM_PLCFG_PLSEL_Msk) != level) { + hri_pm_clear_INTFLAG_reg(PM, 0xFF); + hri_pm_write_PLCFG_PLSEL_bf(PM, level); + while (!hri_pm_read_INTFLAG_reg(PM)) + ; + } +} diff --git a/watch-library/hardware/hpl/pm/hpl_pm_base.h b/watch-library/hardware/hpl/pm/hpl_pm_base.h new file mode 100644 index 00000000..5a50a914 --- /dev/null +++ b/watch-library/hardware/hpl/pm/hpl_pm_base.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_PM_BASE_H_INCLUDED +#define _HPL_PM_BASE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/watch-library/hardware/hpl/port/hpl_gpio_base.h b/watch-library/hardware/hpl/port/hpl_gpio_base.h new file mode 100644 index 00000000..3cc1981f --- /dev/null +++ b/watch-library/hardware/hpl/port/hpl_gpio_base.h @@ -0,0 +1,170 @@ + +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + case GPIO_DIRECTION_OFF: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_IN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg(PORT, + port, + PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + if (level) { + hri_port_set_OUT_reg(PORT_IOBUS, port, mask); + } else { + hri_port_clear_OUT_reg(PORT_IOBUS, port, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + hri_port_toggle_OUT_reg(PORT_IOBUS, port, mask); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + + CRITICAL_SECTION_ENTER(); + + uint32_t dir_tmp = hri_port_read_DIR_reg(PORT_IOBUS, port); + + tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; + tmp |= hri_port_read_OUT_reg(PORT_IOBUS, port) & dir_tmp; + + CRITICAL_SECTION_LEAVE(); + + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); + break; + + case GPIO_PULL_UP: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_set_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_clear_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); + + } else { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); + + if (pin & 1) { + // Odd numbered pin + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} + +static inline void _port_event_init() +{ + hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); +} diff --git a/watch-library/hardware/hpl/sercom/hpl_sercom.c b/watch-library/hardware/hpl/sercom/hpl_sercom.c new file mode 100644 index 00000000..f01476dc --- /dev/null +++ b/watch-library/hardware/hpl/sercom/hpl_sercom.c @@ -0,0 +1,2932 @@ + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_USART_ENABLE +#define CONF_SERCOM_5_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_USART_ENABLE +#define CONF_SERCOM_6_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as USART. */ +#define SERCOM_USART_AMOUNT \ + (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ + + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ + + CONF_SERCOM_7_USART_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define SERCOM_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ + | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ + | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ + | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ + | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ + | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ + | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ + | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ + SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ + | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ + | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ + | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ + | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ + | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ + (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ + CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ + } + +/** + * \brief SERCOM USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_sercomusart_ctrla_reg_t ctrl_a; + hri_sercomusart_ctrlb_reg_t ctrl_b; + hri_sercomusart_baud_reg_t baud; + uint8_t fractional; + hri_sercomusart_rxpl_reg_t rxpl; + hri_sercomusart_dbgctrl_reg_t debug_ctrl; +}; + +#if SERCOM_USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of SERCOM USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_SERCOM_0_USART_ENABLE == 1 + SERCOM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_USART_ENABLE == 1 + SERCOM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_USART_ENABLE == 1 + SERCOM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_USART_ENABLE == 1 + SERCOM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_USART_ENABLE == 1 + SERCOM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_USART_ENABLE == 1 + SERCOM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_USART_ENABLE == 1 + SERCOM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_USART_ENABLE == 1 + SERCOM_CONFIGURATION(7), +#endif +}; +#endif + +static uint8_t _get_sercom_index(const void *const hw); +static uint8_t _sercom_get_irq_num(const void *const hw); +static void _sercom_init_irq_param(const void *const hw, void *dev); +static uint8_t _sercom_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Initialize synchronous SERCOM USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous SERCOM USART + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_async_deinit(struct _usart_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_async_enable(struct _usart_async_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_async_disable(struct _usart_async_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given SERCOM USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_DATA_reg(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if USART transmission complete + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_TXC_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_RXC_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_DRE_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_TXC_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given sercom hardware instance + */ +static uint8_t _sercom_get_hardware_index(const void *const hw) +{ +#ifdef _UNIT_TEST_ + return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom); +#endif + + return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10; +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); + hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); + } else if (USART_ASYNC_RX_DONE == type) { + hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); + } else if (USART_ASYNC_ERROR == type) { + hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static uint8_t _get_sercom_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Init irq param with the given sercom hardware instance + */ +static void _sercom_init_irq_param(const void *const hw, void *dev) +{ + (void)hw; + (void)dev; +} + +/** + * \internal Initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + uint8_t i = _get_sercom_index(hw); + + if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { + uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; + if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + } + hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); + } + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; + } else { + hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); + } + + hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); + hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate SERCOM clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud / 2 - 1; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_BAUD_reg(hw, baud_rate); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_DORD_bit(hw, order); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + + if (USART_PARITY_NONE != parity) { + hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); + } else { + hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); + } + + hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomusart_set_CTRLA_ENABLE_bit(hw); + } +} + + /* Sercom I2C implementation */ + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CM_ENABLE +#define CONF_SERCOM_4_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CM_ENABLE +#define CONF_SERCOM_5_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CM_ENABLE +#define CONF_SERCOM_6_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CM_ENABLE +#define CONF_SERCOM_7_I2CM_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Master. */ +#define SERCOM_I2CM_AMOUNT \ + (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ + + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) + +/** + * \brief Macro is used to fill i2cm configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CM_CONFIGURATION(n) \ + { \ + (n), \ + (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ + | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ + SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ + CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ + } + +#define ERROR_FLAG (1 << 7) +#define SB_FLAG (1 << 1) +#define MB_FLAG (1 << 0) + +#define CMD_STOP 0x3 +#define I2C_IDLE 0x1 +#define I2C_SM 0x0 +#define I2C_FM 0x1 +#define I2C_HS 0x2 +#define TEN_ADDR_FRAME 0x78 +#define TEN_ADDR_MASK 0x3ff +#define SEVEN_ADDR_MASK 0x7f + +/** + * \brief SERCOM I2CM configuration type + */ +struct i2cm_configuration { + uint8_t number; + hri_sercomi2cm_ctrla_reg_t ctrl_a; + hri_sercomi2cm_ctrlb_reg_t ctrl_b; + hri_sercomi2cm_baud_reg_t baud; + hri_sercomi2cm_dbgctrl_reg_t dbgctrl; + uint16_t trise; + uint32_t clk; /* SERCOM peripheral clock frequency */ +}; + +static inline int32_t _i2c_m_enable_implementation(void *hw); +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); + +#if SERCOM_I2CM_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct i2cm_configuration _i2cms[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2CM configurations + */ +static struct i2cm_configuration _i2cms[] = { +#if CONF_SERCOM_0_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2cm_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { + if (_i2cms[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +static inline void _sercom_i2c_send_stop(void *const hw) +{ + hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); +} + +/** + * \brief SERCOM I2CM analyze hardware status and transfer next byte + */ +static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) +{ + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); + + if (flags & MB_FLAG) { + /* tx error */ + if (status & SERCOM_I2CM_STATUS_ARBLOST) { + hri_sercomi2cm_clear_interrupt_MB_bit(hw); + msg->flags |= I2C_M_FAIL; + msg->flags &= ~I2C_M_BUSY; + + if (status & SERCOM_I2CM_STATUS_BUSERR) { + return I2C_ERR_BUS; + } + + return I2C_ERR_BAD_ADDRESS; + } else { + if (status & SERCOM_I2CM_STATUS_RXNACK) { + + /* Slave rejects to receive more data */ + if (msg->len > 0) { + msg->flags |= I2C_M_FAIL; + } + + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + + return I2C_NACK; + } + + if (msg->flags & I2C_M_TEN) { + hri_sercomi2cm_write_ADDR_reg(hw, + ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + msg->flags &= ~I2C_M_TEN; + + return I2C_OK; + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } else { + hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); + msg->buffer++; + msg->len--; + } + + return I2C_OK; + } + } else if (flags & SB_FLAG) { + if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { + msg->len--; + + /* last byte, send nack */ + if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } + + /* Accessing DATA.DATA auto-triggers I2C bus operations. + * The operation performed depends on the state of + * CTRLB.ACKACT, CTRLB.SMEN + **/ + *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); + } else { + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + return I2C_NACK; + } + + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + } + + return I2C_OK; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _sercom_get_irq_num(const void *const hw) +{ + return SERCOM0_IRQn + _sercom_get_hardware_index(hw); +} + +/** + * \brief Initialize sercom i2c module to use in async mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) +{ + int32_t init_status; + + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); + if (init_status) { + return init_status; + } + + _sercom_init_irq_param(hw, (void *)i2c_dev); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Transfer the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + return ERR_NONE; +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail, return the error code + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) +{ + int ret; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (msg->len == 0) { + return ERR_NONE; + } + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); + + ret = _sercom_i2c_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Set callback to be called in interrupt handler + * + * \param[in] i2c_dev The pointer to master i2c device + * \param[in] type The callback type + * \param[in] func The callback function pointer + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, + FUNC_PTR func) +{ + switch (type) { + case I2C_M_ASYNC_DEVICE_ERROR: + i2c_dev->cb.error = (_i2c_error_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_TX_COMPLETE: + i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_RX_COMPLETE: + i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; + break; + default: + /* error */ + break; + } + + return ERR_NONE; +} + +/** + * \brief Set stop condition on I2C + * + * \param i2c_dev Pointer to master i2c device + * + * \return Operation status + * \retval I2C_OK Operation was successfull + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +/** + * \brief Get number of bytes left in transfer buffer + * + * \param i2c_dev Pointer to i2c master device + * + * \return Bytes left in buffer + * \retval =>0 Bytes left in buffer + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) +{ + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return i2c_dev->service.msg.len; + } + + return 0; +} + +/** + * \brief Initialize sercom i2c module to use in sync mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) +{ + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + return _i2c_m_sync_init_impl(&i2c_dev->service, hw); +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C master interrupt + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state) +{ + if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); + hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); + } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { + hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \brief Wait for bus response + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] flags Store the hardware response + * + * \return Bus response status. + * \retval 0 Bus response status OK + * \retval <0 Bus response fail + */ +inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) +{ + uint32_t timeout = 65535; + void * hw = i2c_dev->hw; + + do { + *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); + + if (timeout-- == 0) { + return I2C_ERR_BUS; + } + } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); + + return I2C_OK; +} + +/** + * \brief Send the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint32_t flags; + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + return _sercom_i2c_sync_analyse_flags(hw, flags, msg); +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail or partial fail, return the error code + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) +{ + uint32_t flags; + int ret; + void * hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return I2C_ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); + + ret = _sercom_i2c_sync_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + while (i2c_dev->service.msg.flags & I2C_M_BUSY) { + ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + + if (ret) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); + } + + return ret; +} + +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +static inline int32_t _i2c_m_enable_implementation(void *const hw) +{ + int timeout = 65535; + int timeout_attempt = 4; + + ASSERT(hw); + + /* Enable interrupts */ + hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); + + while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { + timeout--; + + if (timeout <= 0) { + if (--timeout_attempt) + timeout = 65535; + else + return I2C_ERR_BUSY; + hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); + } + } + return ERR_NONE; +} + +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) +{ + uint8_t i = _get_i2cm_index(hw); + + if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { + uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; + if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); + } + hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); + } + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + + hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); + hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); + hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); + + service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); + + service->trise = _i2cms[i].trise; + + return ERR_NONE; +} + + /* SERCOM I2C slave */ + +#ifndef CONF_SERCOM_0_I2CS_ENABLE +#define CONF_SERCOM_0_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CS_ENABLE +#define CONF_SERCOM_1_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CS_ENABLE +#define CONF_SERCOM_2_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CS_ENABLE +#define CONF_SERCOM_3_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CS_ENABLE +#define CONF_SERCOM_4_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CS_ENABLE +#define CONF_SERCOM_5_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CS_ENABLE +#define CONF_SERCOM_6_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CS_ENABLE +#define CONF_SERCOM_7_I2CS_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Slave. */ +#define SERCOM_I2CS_AMOUNT \ + (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ + + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) + +/** + * \brief Macro is used to fill I2C slave configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CS_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ + | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ + | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ + SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ + (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ + | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ + } + +/** + * \brief Macro to check 10-bit addressing + */ +#define I2CS_7BIT_ADDRESSING_MASK 0x7F + +static int32_t _i2c_s_init(void *const hw); +static int8_t _get_i2c_s_index(const void *const hw); +static inline void _i2c_s_deinit(void *const hw); +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); + +/** + * \brief SERCOM I2C slave configuration type + */ +struct i2cs_configuration { + uint8_t number; + hri_sercomi2cs_ctrla_reg_t ctrl_a; + hri_sercomi2cs_ctrlb_reg_t ctrl_b; + hri_sercomi2cs_addr_reg_t address; +}; + +#if SERCOM_I2CS_AMOUNT < 1 +/** Dummy array for compiling. */ +static struct i2cs_configuration _i2css[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2C slave configurations + */ +static struct i2cs_configuration _i2css[] = { +#if CONF_SERCOM_0_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \brief Initialize synchronous I2C slave + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) +{ + int32_t status; + + ASSERT(device); + + status = _i2c_s_init(hw); + if (status) { + return status; + } + device->hw = hw; + + return ERR_NONE; +} + +/** + * \brief Initialize asynchronous I2C slave + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _i2c_s_init(hw); + if (init_status) { + return init_status; + } + + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + // Enable Address Match and PREC interrupt by default. + hri_sercomi2cs_set_INTEN_AMATCH_bit(hw); + hri_sercomi2cs_set_INTEN_PREC_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize synchronous I2C + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) +{ + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize asynchronous I2C + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given I2C instance + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_DATA_reg(device->hw); +} + +/** + * \brief Check if I2C is ready to send next byt + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by I2C + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Clear the Data Ready interrupt flag + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Abort data transmission + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C slave interrupt + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); + } else if (I2C_S_DEVICE_ERROR == type) { + hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); + } + + return ERR_NONE; +} + +/** + * \internal Initalize i2c slave hardware + * + * \param[in] p The pointer to hardware instance + * + *\ return status of initialization + */ +static int32_t _i2c_s_init(void *const hw) +{ + int8_t i = _get_i2c_s_index(hw); + if (i == -1) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { + uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; + if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); + } + hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); + } + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + + hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); + hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); + hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); + + return ERR_NONE; +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + * + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2c_s_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2css); i++) { + if (_i2css[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _i2c_s_deinit(void *const hw) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + * \param[in] address Address to set + */ +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) +{ + bool enabled; + + enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); + } + + return ERR_NONE; +} + + /* Sercom SPI implementation */ + +#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) +#endif + +#define SPI_DEV_IRQ_MODE 0x8000 + +#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) +#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) + +COMPILER_PACK_SET(1) +/** Initialization configuration of registers. */ +struct sercomspi_regs_cfg { + uint32_t ctrla; + uint32_t ctrlb; + uint32_t addr; + uint8_t baud; + uint8_t dbgctrl; + uint16_t dummy_byte; + uint8_t n; +}; +COMPILER_PACK_RESET() + +/** Build configuration from header macros. */ +#define SERCOMSPI_REGS(n) \ + { \ + (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ + | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ + | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ + | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ + ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ + | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ + | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ + | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ + (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ + | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ + ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ + (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ + CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ + n /* sercom number */ \ + } + +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_SPI_ENABLE +#define CONF_SERCOM_1_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_SPI_ENABLE +#define CONF_SERCOM_2_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_SPI_ENABLE +#define CONF_SERCOM_7_SPI_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as SPI */ +#define SERCOM_SPI_AMOUNT \ + (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ + + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) + +#if SERCOM_SPI_AMOUNT < 1 +/** Dummy array for compiling. */ +static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; +#else +/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ +static const struct sercomspi_regs_cfg sercomspi_regs[] = { +#if CONF_SERCOM_0_SPI_ENABLE + SERCOMSPI_REGS(0), +#endif +#if CONF_SERCOM_1_SPI_ENABLE + SERCOMSPI_REGS(1), +#endif +#if CONF_SERCOM_2_SPI_ENABLE + SERCOMSPI_REGS(2), +#endif +#if CONF_SERCOM_3_SPI_ENABLE + SERCOMSPI_REGS(3), +#endif +#if CONF_SERCOM_4_SPI_ENABLE + SERCOMSPI_REGS(4), +#endif +#if CONF_SERCOM_5_SPI_ENABLE + SERCOMSPI_REGS(5), +#endif +#if CONF_SERCOM_6_SPI_ENABLE + SERCOMSPI_REGS(6), +#endif +#if CONF_SERCOM_7_SPI_ENABLE + SERCOMSPI_REGS(7), +#endif +}; +#endif + +/** \internal De-initialize SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return De-initialization status + */ +static int32_t _spi_deinit(void *const hw) +{ + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_async_enable(void *const hw) +{ + _spi_sync_enable(hw); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_async_disable(void *const hw) +{ + _spi_sync_disable(hw); + hri_sercomspi_clear_INTEN_reg( + hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI mode + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] mode The mode to set + * + * \return Setting mode status + */ +static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); + ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI baudrate + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting baudrate status + */ +static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_write_BAUD_reg(hw, baud_val); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI char size + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * \param[out] size Stored char size + * + * \return Setting char size status + */ +static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) +{ + /* Only 8-bit or 9-bit accepted */ + if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { + return ERR_INVALID_ARG; + } + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); + *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI data order + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting data order status + */ +static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + + if (dord == SPI_DATA_ORDER_LSB_1ST) { + ctrla |= SERCOM_SPI_CTRLA_DORD; + } else { + ctrla &= ~SERCOM_SPI_CTRLA_DORD; + } + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \brief Load SERCOM registers to init for SPI master mode + * The settings will be applied with default master mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg( + hw, + (regs->ctrlb + & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) + | (SERCOM_SPI_CTRLB_RXEN)); + hri_sercomspi_write_BAUD_reg(hw, regs->baud); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); +} + +/** \brief Load SERCOM registers to init for SPI slave mode + * The settings will be applied with default slave mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg(hw, + (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) + | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); + hri_sercomspi_write_ADDR_reg(hw, regs->addr); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); + while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) + ; +} + +/** \brief Return the pointer to register settings of specific SERCOM + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific SERCOM. + */ +static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { + if (sercomspi_regs[i].n == n) { + return &sercomspi_regs[i]; + } + } + + return NULL; +} + +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; + if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); + } + hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); + } + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + + dev->prvt = hw; + + if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { + _spi_load_regs_slave(hw, regs); + } else { + _spi_load_regs_master(hw, regs); + } + + /* Load character size from default hardware configuration */ + dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; + + dev->dummy_byte = regs->dummy_byte; + + return ERR_NONE; +} + +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) +{ + return _spi_m_sync_init(dev, hw); +} + +int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) +{ + struct _spi_async_dev *spid = dev; + /* Do hardware initialize. */ + int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); + + if (rc < 0) { + return rc; + } + + _sercom_init_irq_param(hw, (void *)dev); + /* Initialize callbacks: must use them */ + spid->callbacks.complete = NULL; + spid->callbacks.rx = NULL; + spid->callbacks.tx = NULL; + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) +{ + return _spi_m_async_init(dev, hw); +} + +int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_async_enable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_async_disable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) +{ + int32_t rc; + ASSERT(dev); + (void)dev; + + /* Not accept 0es */ + if (clk == 0 || baud == 0) { + return ERR_INVALID_ARG; + } + + /* Check baudrate range of current assigned clock */ + if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { + return ERR_INVALID_ARG; + } + + rc = ((clk >> 1) / baud) - 1; + return rc; +} + +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +/** Wait until SPI bus idle. */ +static inline void _spi_wait_bus_idle(void *const hw) +{ + while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { + ; + } + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); +} + +/** Holds run time information for message sync transaction. */ +struct _spi_trans_ctrl { + /** Pointer to transmitting data buffer. */ + uint8_t *txbuf; + /** Pointer to receiving data buffer. */ + uint8_t *rxbuf; + /** Count number of data transmitted. */ + uint32_t txcnt; + /** Count number of data received. */ + uint32_t rxcnt; + /** Data character size. */ + uint8_t char_size; +}; + +/** Check interrupt flag of RXC and update transaction runtime information. */ +static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) +{ + uint32_t data; + + if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { + return false; + } + + data = hri_sercomspi_read_DATA_reg(hw); + + if (ctrl->rxbuf) { + *ctrl->rxbuf++ = (uint8_t)data; + + if (ctrl->char_size > 1) { + *ctrl->rxbuf++ = (uint8_t)(data >> 8); + } + } + + ctrl->rxcnt++; + + return true; +} + +/** Check interrupt flag of DRE and update transaction runtime information. */ +static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, + uint16_t dummy) +{ + uint32_t data; + + if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { + return; + } + + if (ctrl->txbuf) { + data = *ctrl->txbuf++; + + if (ctrl->char_size > 1) { + data |= (*ctrl->txbuf) << 8; + ctrl->txbuf++; + } + } else { + data = dummy; + } + + ctrl->txcnt++; + hri_sercomspi_write_DATA_reg(hw, data); +} + +/** Check interrupt flag of ERROR and update transaction runtime information. */ +static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) +{ + if (SERCOM_SPI_INTFLAG_ERROR & iflag) { + hri_sercomspi_clear_STATUS_reg(hw, ~0); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return ERR_OVERFLOW; + } + + return ERR_NONE; +} + +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) +{ + void * hw = dev->prvt; + int32_t rc = 0; + struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; + + ASSERT(dev && hw); + + /* If settings are not applied (pending), we can not go on */ + if (hri_sercomspi_is_syncing( + hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { + return ERR_BUSY; + } + + /* SPI must be enabled to start synchronous transfer */ + if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_NOT_INITIALIZED; + } + + for (;;) { + uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); + + if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { + /* In master mode, do not start next byte before previous byte received + * to make better output waveform */ + if (ctrl.rxcnt >= ctrl.txcnt) { + _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); + } + } + + rc = _spi_err_check(iflag, hw); + + if (rc < 0) { + break; + } + if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { + rc = ctrl.txcnt; + break; + } + } + /* Wait until SPI bus idle */ + _spi_wait_bus_idle(hw); + + return rc; +} + +int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (state) { + hri_sercomspi_set_INTEN_DRE_bit(hw); + } else { + hri_sercomspi_clear_INTEN_DRE_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx(dev, state); +} + +int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev); + ASSERT(hw); + + if (state) { + hri_sercomspi_set_INTEN_RXC_bit(hw); + } else { + hri_sercomspi_clear_INTEN_RXC_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_rx(dev, state); +} + +int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) +{ + ASSERT(dev && dev->prvt); + + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); + } else { + hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx_complete(dev, state); +} + +int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + typedef void (*func_t)(void); + struct _spi_async_dev *spid = dev; + + ASSERT(dev && (cb_type < SPI_DEV_CB_N)); + + func_t *p_ls = (func_t *)&spid->callbacks; + p_ls[cb_type] = (func_t)func; + + return ERR_NONE; +} + +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + return _spi_m_async_register_callback(dev, cb_type, func); +} + +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); +} + +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); +} + +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); + return true; + } + return false; +} + +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { + hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return true; + } + return false; +} + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + ASSERT(device); + + if (SPI_DEV_CB_ERROR == type) { + hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); + } +} + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + _spi_m_async_set_irq_state(device, type, state); +} diff --git a/watch-library/hardware/hpl/slcd/hpl_slcd.c b/watch-library/hardware/hpl/slcd/hpl_slcd.c new file mode 100644 index 00000000..0f58b1f5 --- /dev/null +++ b/watch-library/hardware/hpl/slcd/hpl_slcd.c @@ -0,0 +1,289 @@ +/** + * \file + * + * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality + * Implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +static int32_t _slcd_sync_set_segment(struct _slcd_sync_device *dev, const uint32_t com, const uint32_t seg, + const bool on); + +/** + * \brief SLCD configuration type + */ +struct slcd_configuration { + hri_slcd_ctrla_reg_t ctrla; /*!< Control A Register */ + hri_slcd_ctrlb_reg_t ctrlb; /*!< Control B Register */ + hri_slcd_ctrlc_reg_t ctrlc; /*!< Control C Register */ + hri_slcd_ctrld_reg_t ctrld; /*!< Control D Register */ +}; + +/** + * \brief Array of AC configurations + */ +static struct slcd_configuration _slcd + = {SLCD_CTRLA_DUTY(CONF_SLCD_COM_NUM) | CONF_SLCD_WMOD << SLCD_CTRLA_WMOD_Pos + | CONF_SLCD_RUNSTDBY << SLCD_CTRLA_RUNSTDBY_Pos | SLCD_CTRLA_PRESC(CONF_SLCD_PRESC) + | SLCD_CTRLA_CKDIV(CONF_SLCD_CKDIV) | SLCD_CTRLA_BIAS(CONF_SLCD_BIAS) + | CONF_SLCD_XVLCD << SLCD_CTRLA_XVLCD_Pos | SLCD_CTRLA_PRF(CONF_SLCD_PRF) | SLCD_CTRLA_RRF(CONF_SLCD_RRF), + CONF_SLCD_BBEN << SLCD_CTRLB_BBEN_Pos | SLCD_CTRLB_BBD(CONF_SLCD_BBD - 1), + SLCD_CTRLC_CTST(CONF_SLCD_CONTRAST_ADJUST), + SLCD_CTRLD_DISPEN}; +/** + * \brief Initialize SLCD Device Descriptor + */ +int32_t _slcd_sync_init(struct _slcd_sync_device *dev, void *const hw) +{ + if (!hri_slcd_is_syncing(hw, SLCD_SYNCBUSY_SWRST)) { + if (hri_slcd_get_CTRLA_ENABLE_bit(hw)) { + hri_slcd_clear_CTRLA_ENABLE_bit(hw); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_ENABLE); + } + hri_slcd_write_CTRLA_reg(hw, SLCD_CTRLA_SWRST); + } + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST); + + dev->hw = hw; + hri_slcd_write_CTRLA_reg(hw, _slcd.ctrla); + hri_slcd_write_CTRLB_reg(hw, _slcd.ctrlb); + hri_slcd_write_CTRLC_reg(hw, _slcd.ctrlc); + hri_slcd_write_CTRLD_reg(hw, _slcd.ctrld); + hri_slcd_write_LPENL_reg(hw, CONF_SLCD_LPENL); + hri_slcd_write_LPENH_reg(hw, CONF_SLCD_LPENH); + hri_slcd_write_SDATAL0_reg(hw, 0); + hri_slcd_write_SDATAH0_reg(hw, 0); + hri_slcd_write_SDATAL1_reg(hw, 0); + hri_slcd_write_SDATAH1_reg(hw, 0); + hri_slcd_write_SDATAL2_reg(hw, 0); + hri_slcd_write_SDATAH2_reg(hw, 0); + hri_slcd_write_SDATAL3_reg(hw, 0); + hri_slcd_write_SDATAH3_reg(hw, 0); + hri_slcd_write_SDATAL4_reg(hw, 0); + hri_slcd_write_SDATAH4_reg(hw, 0); + hri_slcd_write_SDATAL5_reg(hw, 0); + hri_slcd_write_SDATAH5_reg(hw, 0); + hri_slcd_write_SDATAL6_reg(hw, 0); + hri_slcd_write_SDATAH6_reg(hw, 0); + hri_slcd_write_SDATAL7_reg(hw, 0); + hri_slcd_write_SDATAH7_reg(hw, 0); + hri_slcd_set_BCFG_MODE_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief DeInitialize SLCD Device Descriptor + */ +int32_t _slcd_sync_deinit(struct _slcd_sync_device *dev) +{ + hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw); + hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE); + hri_slcd_set_CTRLA_SWRST_bit(dev->hw); + dev->hw = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable SLCD driver + * + * \param[in] dev SLCD device descriptor to be enabled + */ +int32_t _slcd_sync_enable(struct _slcd_sync_device *dev) +{ + hri_slcd_set_CTRLA_ENABLE_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief Disable SLCD driver + */ +int32_t _slcd_sync_disable(struct _slcd_sync_device *dev) +{ + hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief Turn on a Segment + */ +int32_t _slcd_sync_seg_on(struct _slcd_sync_device *dev, uint32_t seg) +{ + return _slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), true); +} + +/** + * \brief Turn off a Segment + */ +int32_t _slcd_sync_seg_off(struct _slcd_sync_device *dev, uint32_t seg) +{ + return _slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), false); +} + +/** + * \brief Blink a Segment + */ +int32_t _slcd_sync_seg_blink(struct _slcd_sync_device *dev, uint32_t seg, const uint32_t period) +{ + if ((SLCD_COMNUM(seg) >= CONF_SLCD_COM_NUM) || (SLCD_SEGNUM(seg) >= CONF_SLCD_SEG_NUM)) { + return ERR_INVALID_ARG; + } + /* COM[0..7], Seg[0,1] support blink */ + if (SLCD_SEGNUM(seg) >= 2) { + return ERR_INVALID_ARG; + } + /* Verify period */ + if (period > SLCD_FC_MAX_MS || period < SLCD_FC_MIN_MS) { + return ERR_INVALID_ARG; + } + /* Set Period, use Frame Counter 0 for blink */ + hri_slcd_clear_CTRLD_FC0EN_bit(dev->hw); + hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD); + if (period <= SLCD_FC_BYPASS_MAX_MS) { + hri_slcd_set_FC0_reg(dev->hw, SLCD_FC0_PB | ((period / (1000 / SLCD_FRAME_FREQUENCY)) - 1)); + } else { + hri_slcd_set_FC0_reg(dev->hw, (((period / (1000 / SLCD_FRAME_FREQUENCY)) / 8 - 1))); + } + hri_slcd_set_CTRLD_FC0EN_bit(dev->hw); + + /* Set Blink Segments */ + _slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), true); + hri_slcd_clear_CTRLD_BLINK_bit(dev->hw); + + hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw); + hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE); + + /* Update BCFG */ + if (SLCD_SEGNUM(seg) == 0) { + hri_slcd_set_BCFG_BSS0_bf(dev->hw, 1 << SLCD_COMNUM(seg)); + } else { + hri_slcd_set_BCFG_BSS1_bf(dev->hw, 1 << SLCD_COMNUM(seg)); + } + hri_slcd_set_CTRLA_ENABLE_bit(dev->hw); + hri_slcd_set_CTRLD_BLINK_bit(dev->hw); + + return ERR_NONE; +} + +/** + * \brief Start animation play by a segment array + */ +int32_t _slcd_sync_start_animation(struct _slcd_sync_device *dev, const uint32_t segs[], uint32_t len, + const uint32_t period) +{ + uint32_t i; + uint32_t csrlen = 0; + if (len > 16) { + return ERR_INVALID_ARG; + } + /* COM[0..7], Seg[2,3] support animation */ + for (i = 0; i < len; i++) { + if ((SLCD_SEGNUM(segs[i]) != 2 && SLCD_SEGNUM(segs[i]) != 3)) { + return ERR_INVALID_ARG; + } + } + /* Verify period */ + if (period > SLCD_FC_MAX_MS || period < SLCD_FC_MIN_MS) { + return ERR_INVALID_ARG; + } + /* Set Period */ + _slcd_sync_set_animation_period(dev, period); + + /* Set animation segments */ + hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw); + hri_slcd_clear_CTRLD_CSREN_bit(dev->hw); + + hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE | SLCD_SYNCBUSY_CTRLD); + hri_slcd_set_CSRCFG_FCS_bf(dev->hw, 1); + hri_slcd_write_CSRCFG_DATA_bf(dev->hw, 0); + for (i = 0; i < len; i++) { + hri_slcd_set_CSRCFG_DATA_bf(dev->hw, (1 << ((SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2)))); + if (((SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2)) > csrlen) { + csrlen = (SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2); + } + } + hri_slcd_set_CSRCFG_SIZE_bf(dev->hw, csrlen + 1); + hri_slcd_set_BCFG_MODE_bit(dev->hw); + hri_slcd_set_CTRLD_CSREN_bit(dev->hw); + hri_slcd_set_CTRLA_ENABLE_bit(dev->hw); + + return ERR_NONE; +} + +/** + * \brief Stop animation play by a segment array + */ +int32_t _slcd_sync_stop_animation(struct _slcd_sync_device *dev, const uint32_t segs[], uint32_t len) +{ + /* Not used because of the current version is not supported, Reserved */ + (void)segs; + (void)len; + hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD); + hri_slcd_clear_CTRLD_CSREN_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief Set animation Frequency + */ +int32_t _slcd_sync_set_animation_period(struct _slcd_sync_device *dev, const uint32_t period) +{ + hri_slcd_clear_CTRLD_FC1EN_bit(dev->hw); + hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD); + /* Use Frame Counter 1 for blink */ + if (period <= SLCD_FC_BYPASS_MAX_MS) { + hri_slcd_set_FC1_reg(dev->hw, SLCD_FC1_PB | ((period / (1000 / SLCD_FRAME_FREQUENCY)) - 1)); + } else { + hri_slcd_set_FC1_reg(dev->hw, (((period / (1000 / SLCD_FRAME_FREQUENCY)) / 8 - 1))); + } + hri_slcd_set_CTRLD_FC1EN_bit(dev->hw); + return ERR_NONE; +} + +static int32_t _slcd_sync_set_segment(struct _slcd_sync_device *dev, const uint32_t com, const uint32_t seg, + const bool on) +{ + if ((SLCD_COMNUM(seg) >= CONF_SLCD_COM_NUM) || (SLCD_SEGNUM(seg) >= CONF_SLCD_SEG_NUM)) { + return ERR_INVALID_ARG; + } + /* Use register instead hri interface to optimization code */ + if (on) { + ((uint32_t *)&(((Slcd *)dev->hw)->SDATAL0))[(com * 2) + (seg >> 5)] + |= (seg < 32) ? (1 << seg) : (1 << (seg >> 5)); + } else { + ((uint32_t *)&(((Slcd *)dev->hw)->SDATAL0))[(com * 2) + (seg >> 5)] + &= ~((seg < 32) ? (1 << seg) : (1 << (seg >> 5))); + } + + return ERR_NONE; +} diff --git a/watch-library/hardware/hpl/slcd/hpl_slcd_cm.h b/watch-library/hardware/hpl/slcd/hpl_slcd_cm.h new file mode 100644 index 00000000..66dbde93 --- /dev/null +++ b/watch-library/hardware/hpl/slcd/hpl_slcd_cm.h @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief SLCD Character Mapping declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_SLCD_CM_H_INCLUDED +#define HPL_SLCD_CM_H_INCLUDED + +#include + +/* Character Mapping Struct */ +struct slcd_char_mapping { + uint32_t character : 8; /*!< ASCII character */ + uint32_t mapping : 24; /*!< Mapping value */ +}; + +/* SLCD Character settting Struct */ +struct slcd_char_setting { + uint8_t com_index; /*!< Common terminal index, start from 0 */ + uint8_t seg_index; /*!< Segment terminal index, start from 0 */ + uint8_t nseg; /*!< Number of Segment, this field is used to + indentify which segments line will be + used. For example, if char mapping from + COM1/SEG2 and nseg=2,size=7, then + COM1/SEG2, COM1/SEG3, COM2/SEG2, + COM2/SEG3, COM3/SEG2, COM3/SEG3, + COM4/SEG2 will be used for mapping + */ + uint8_t size; /*!< char size, typical is 7/14/16 */ +}; +#endif /* HPL_SLCD_CM_H_INCLUDED */ diff --git a/watch-library/hardware/hpl/systick/hpl_systick.c b/watch-library/hardware/hpl/systick/hpl_systick.c new file mode 100644 index 00000000..c2f3b29e --- /dev/null +++ b/watch-library/hardware/hpl/systick/hpl_systick.c @@ -0,0 +1,104 @@ + +/** + * \file + * + * \brief SysTick related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initialize system time module + */ +void _system_time_init(void *const hw) +{ + (void)hw; + SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos); + SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos) + | (1 << SysTick_CTRL_CLKSOURCE_Pos); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + _system_time_init(hw); +} + +/** + * \brief De-initialize system time module + */ +void _system_time_deinit(void *const hw) +{ + (void)hw; + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; +} + +/** + * \brief Get system time + */ +system_time_t _system_time_get(const void *const hw) +{ + (void)hw; + return (system_time_t)SysTick->VAL; +} + +/** + * \brief Get maximum possible system time + */ +system_time_t _system_time_get_max_time_value(const void *const hw) +{ + (void)hw; + return 0xFFFFFF; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ + (void)hw; + uint8_t n = cycles >> 24; + uint32_t buf = cycles; + + while (n--) { + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0xFFFFFF; + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) + ; + buf -= 0xFFFFFF; + } + + SysTick->LOAD = buf; + SysTick->VAL = buf; + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) + ; +} diff --git a/watch-library/hardware/hpl/trng/hpl_trng.c b/watch-library/hardware/hpl/trng/hpl_trng.c new file mode 100755 index 00000000..43ede044 --- /dev/null +++ b/watch-library/hardware/hpl/trng/hpl_trng.c @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief True Random Number Generator + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +static inline int32_t _trng_init(void *hw) +{ + if (hri_trng_get_CTRLA_reg(hw, TRNG_CTRLA_ENABLE)) { + return ERR_DENIED; + } + if (CONF_TRNG_RUNSTDBY) { + hri_trng_set_CTRLA_RUNSTDBY_bit(hw); + } else { + hri_trng_clear_CTRLA_RUNSTDBY_bit(hw); + } + if (CONF_TRNG_DATARDYEO) { + hri_trng_set_EVCTRL_DATARDYEO_bit(hw); + } else { + hri_trng_clear_EVCTRL_DATARDYEO_bit(hw); + } + return ERR_NONE; +} + +int32_t _rand_sync_init(struct _rand_sync_dev *const dev, void *const hw) +{ + int32_t rc; + + ASSERT(dev && hw); + + rc = _trng_init(hw); + if (rc == ERR_NONE) { + dev->prvt = hw; + dev->n_bits = 32; + } + return rc; +} + +void _rand_sync_deinit(struct _rand_sync_dev *const dev) +{ + _rand_sync_disable(dev); +} + +int32_t _rand_sync_enable(struct _rand_sync_dev *const dev) +{ + ASSERT(dev); + ASSERT(dev->prvt); + + hri_trng_set_CTRLA_ENABLE_bit(dev->prvt); + return ERR_NONE; +} + +void _rand_sync_disable(struct _rand_sync_dev *const dev) +{ + ASSERT(dev); + ASSERT(dev->prvt); + + hri_trng_clear_CTRLA_ENABLE_bit(dev->prvt); +} + +int32_t _rand_sync_set_seed(struct _rand_sync_dev *const dev, const uint32_t seed) +{ + (void)dev; + (void)seed; + return ERR_UNSUPPORTED_OP; +} + +uint32_t _rand_sync_read_one(const struct _rand_sync_dev *const dev) +{ + ASSERT(dev); + ASSERT(dev->prvt); + ASSERT(hri_trng_get_CTRLA_reg(dev->prvt, TRNG_CTRLA_ENABLE)); + + while (!hri_trng_get_INTFLAG_reg(dev->prvt, TRNG_INTFLAG_DATARDY)) { + /* Wait until data ready. */ + } + return hri_trng_read_DATA_reg(dev->prvt); +} diff --git a/watch-library/hardware/hri/hri_ac_l22.h b/watch-library/hardware/hri/hri_ac_l22.h new file mode 100644 index 00000000..f1e17cef --- /dev/null +++ b/watch-library/hardware/hri/hri_ac_l22.h @@ -0,0 +1,1746 @@ +/** + * \file + * + * \brief SAM AC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_AC_COMPONENT_ +#ifndef _HRI_AC_L22_H_INCLUDED_ +#define _HRI_AC_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AC_CRITICAL_SECTIONS) +#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AC_CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_ac_evctrl_reg_t; +typedef uint32_t hri_ac_compctrl_reg_t; +typedef uint32_t hri_ac_syncbusy_reg_t; +typedef uint8_t hri_ac_ctrla_reg_t; +typedef uint8_t hri_ac_ctrlb_reg_t; +typedef uint8_t hri_ac_dbgctrl_reg_t; +typedef uint8_t hri_ac_intenset_reg_t; +typedef uint8_t hri_ac_intflag_reg_t; +typedef uint8_t hri_ac_scaler_reg_t; +typedef uint8_t hri_ac_statusa_reg_t; +typedef uint8_t hri_ac_statusb_reg_t; +typedef uint8_t hri_ac_winctrl_reg_t; + +static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + while (((Ac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + return ((Ac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) +{ + return ((Ac *)hw)->INTFLAG.reg; +} + +static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + ((Ac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; +} + +static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; +} + +static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; + } +} + +static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; +} + +static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; +} + +static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; +} + +static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; + } +} + +static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; +} + +static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; +} + +static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; +} + +static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; + } +} + +static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; +} + +static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENSET.reg = mask; +} + +static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) +{ + return ((Ac *)hw)->INTENSET.reg; +} + +static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) +{ + ((Ac *)hw)->INTENSET.reg = data; + ((Ac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSA.reg; +} + +static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; +} + +static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSB.reg; +} + +static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Ac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_ENABLE; + tmp |= value << AC_CTRLA_ENABLE_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->CTRLA.reg; +} + +static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO0; + tmp |= value << AC_EVCTRL_COMPEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO1; + tmp |= value << AC_EVCTRL_COMPEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO0; + tmp |= value << AC_EVCTRL_WINEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI0; + tmp |= value << AC_EVCTRL_COMPEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI1; + tmp |= value << AC_EVCTRL_COMPEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI0; + tmp |= value << AC_EVCTRL_INVEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI1; + tmp |= value << AC_EVCTRL_INVEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->EVCTRL.reg; +} + +static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= ~AC_DBGCTRL_DBGRUN; + tmp |= value << AC_DBGCTRL_DBGRUN_Pos; + ((Ac *)hw)->DBGCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->DBGCTRL.reg; +} + +static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN0; + tmp |= value << AC_WINCTRL_WEN0_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL0_Msk; + tmp |= AC_WINCTRL_WINTSEL0(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + return ((Ac *)hw)->WINCTRL.reg; +} + +static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, + hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= ~AC_SCALER_VALUE_Msk; + tmp |= AC_SCALER_VALUE(data); + ((Ac *)hw)->SCALER[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->SCALER[index].reg; +} + +static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_ENABLE; + tmp |= value << AC_COMPCTRL_ENABLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SINGLE; + tmp |= value << AC_COMPCTRL_SINGLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_RUNSTDBY; + tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SWAP; + tmp |= value << AC_COMPCTRL_SWAP_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYSTEN; + tmp |= value << AC_COMPCTRL_HYSTEN_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_INTSEL_Msk; + tmp |= AC_COMPCTRL_INTSEL(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXNEG_Msk; + tmp |= AC_COMPCTRL_MUXNEG(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXPOS_Msk; + tmp |= AC_COMPCTRL_MUXPOS(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SPEED_Msk; + tmp |= AC_COMPCTRL_SPEED(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYST_Msk; + tmp |= AC_COMPCTRL_HYST(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_FLEN_Msk; + tmp |= AC_COMPCTRL_FLEN(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_OUT_Msk; + tmp |= AC_COMPCTRL_OUT(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->COMPCTRL[index].reg; +} + +static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AC_L22_H_INCLUDED */ +#endif /* _SAML22_AC_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_adc_l22.h b/watch-library/hardware/hri/hri_adc_l22.h new file mode 100644 index 00000000..53ba6af8 --- /dev/null +++ b/watch-library/hardware/hri/hri_adc_l22.h @@ -0,0 +1,2803 @@ +/** + * \file + * + * \brief SAM ADC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_ADC_COMPONENT_ +#ifndef _HRI_ADC_L22_H_INCLUDED_ +#define _HRI_ADC_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ADC_CRITICAL_SECTIONS) +#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ADC_CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_adc_calib_reg_t; +typedef uint16_t hri_adc_ctrlc_reg_t; +typedef uint16_t hri_adc_gaincorr_reg_t; +typedef uint16_t hri_adc_inputctrl_reg_t; +typedef uint16_t hri_adc_offsetcorr_reg_t; +typedef uint16_t hri_adc_result_reg_t; +typedef uint16_t hri_adc_syncbusy_reg_t; +typedef uint16_t hri_adc_winlt_reg_t; +typedef uint16_t hri_adc_winut_reg_t; +typedef uint32_t hri_adc_seqctrl_reg_t; +typedef uint8_t hri_adc_avgctrl_reg_t; +typedef uint8_t hri_adc_ctrla_reg_t; +typedef uint8_t hri_adc_ctrlb_reg_t; +typedef uint8_t hri_adc_dbgctrl_reg_t; +typedef uint8_t hri_adc_evctrl_reg_t; +typedef uint8_t hri_adc_intenset_reg_t; +typedef uint8_t hri_adc_intflag_reg_t; +typedef uint8_t hri_adc_refctrl_reg_t; +typedef uint8_t hri_adc_sampctrl_reg_t; +typedef uint8_t hri_adc_seqstatus_reg_t; +typedef uint8_t hri_adc_swtrig_reg_t; + +static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + while (((Adc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + return ((Adc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) +{ + return ((Adc *)hw)->INTFLAG.reg; +} + +static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + ((Adc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; +} + +static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; + } +} + +static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; +} + +static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; +} + +static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; + } +} + +static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; +} + +static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; +} + +static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; +} + +static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; + } +} + +static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; +} + +static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENSET.reg = mask; +} + +static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) +{ + return ((Adc *)hw)->INTENSET.reg; +} + +static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) +{ + ((Adc *)hw)->INTENSET.reg = data; + ((Adc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_adc_get_SEQSTATUS_SEQBUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY) >> ADC_SEQSTATUS_SEQBUSY_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_SEQSTATE_bf(const void *const hw, + hri_adc_seqstatus_reg_t mask) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE(mask)) >> ADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_SEQSTATE_bf(const void *const hw) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE_Msk) >> ADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_reg(const void *const hw, hri_adc_seqstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SEQSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_reg(const void *const hw) +{ + return ((Adc *)hw)->SEQSTATUS.reg; +} + +static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_CTRLC_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLC) >> ADC_SYNCBUSY_CTRLC_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Adc *)hw)->SYNCBUSY.reg; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) +{ + return ((Adc *)hw)->RESULT.reg; +} + +static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ENABLE; + tmp |= value << ADC_CTRLA_ENABLE_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_RUNSTDBY; + tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ONDEMAND; + tmp |= value << ADC_CTRLA_ONDEMAND_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + return ((Adc *)hw)->CTRLA.reg; +} + +static inline void hri_adc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER(mask)) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_PRESCALER_Msk; + tmp |= ADC_CTRLB_PRESCALER(data); + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_PRESCALER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER_Msk) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) +{ + return ((Adc *)hw)->CTRLB.reg; +} + +static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFCOMP; + tmp |= value << ADC_REFCTRL_REFCOMP_Pos; + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFSEL_Msk; + tmp |= ADC_REFCTRL_REFSEL(data); + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->REFCTRL.reg; +} + +static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHEI; + tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTEI; + tmp |= value << ADC_EVCTRL_STARTEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHINV; + tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTINV; + tmp |= value << ADC_EVCTRL_STARTINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_RESRDYEO; + tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_WINMONEO; + tmp |= value << ADC_EVCTRL_WINMONEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->EVCTRL.reg; +} + +static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; + tmp |= ADC_INPUTCTRL_MUXPOS(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; + tmp |= ADC_INPUTCTRL_MUXNEG(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_adc_set_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_DIFFMODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_DIFFMODE) >> ADC_CTRLC_DIFFMODE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_DIFFMODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_DIFFMODE; + tmp |= value << ADC_CTRLC_DIFFMODE_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_LEFTADJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_LEFTADJ) >> ADC_CTRLC_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_LEFTADJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_LEFTADJ; + tmp |= value << ADC_CTRLC_LEFTADJ_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_FREERUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_FREERUN) >> ADC_CTRLC_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_FREERUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_FREERUN; + tmp |= value << ADC_CTRLC_FREERUN_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_CORREN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_CORREN) >> ADC_CTRLC_CORREN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_CORREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_CORREN; + tmp |= value << ADC_CTRLC_CORREN_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_R2R_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_R2R) >> ADC_CTRLC_R2R_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_R2R_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_R2R; + tmp |= value << ADC_CTRLC_R2R_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_RESSEL(mask)) >> ADC_CTRLC_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_RESSEL_Msk; + tmp |= ADC_CTRLC_RESSEL(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_RESSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_RESSEL_Msk) >> ADC_CTRLC_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_WINMODE(mask)) >> ADC_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_WINMODE_Msk; + tmp |= ADC_CTRLC_WINMODE(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_WINMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_WINMODE_Msk) >> ADC_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_DUALSEL(mask)) >> ADC_CTRLC_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_DUALSEL_Msk; + tmp |= ADC_CTRLC_DUALSEL(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_DUALSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_DUALSEL_Msk) >> ADC_CTRLC_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->CTRLC.reg; +} + +static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; + tmp |= ADC_AVGCTRL_SAMPLENUM(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_ADJRES_Msk; + tmp |= ADC_AVGCTRL_ADJRES(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->AVGCTRL.reg; +} + +static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_OFFCOMP; + tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; + tmp |= ADC_SAMPCTRL_SAMPLEN(data); + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SAMPCTRL.reg; +} + +static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= ~ADC_WINLT_WINLT_Msk; + tmp |= ADC_WINLT_WINLT(data); + ((Adc *)hw)->WINLT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + return ((Adc *)hw)->WINLT.reg; +} + +static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= ~ADC_WINUT_WINUT_Msk; + tmp |= ADC_WINUT_WINUT(data); + ((Adc *)hw)->WINUT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + return ((Adc *)hw)->WINUT.reg; +} + +static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= ~ADC_GAINCORR_GAINCORR_Msk; + tmp |= ADC_GAINCORR_GAINCORR(data); + ((Adc *)hw)->GAINCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + return ((Adc *)hw)->GAINCORR.reg; +} + +static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= ADC_OFFSETCORR_OFFSETCORR(data); + ((Adc *)hw)->OFFSETCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_FLUSH; + tmp |= value << ADC_SWTRIG_FLUSH_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_START; + tmp |= value << ADC_SWTRIG_START_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SWTRIG.reg; +} + +static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= ~ADC_DBGCTRL_DBGRUN; + tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; + ((Adc *)hw)->DBGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DBGCTRL.reg; +} + +static inline void hri_adc_set_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg |= ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp = (tmp & ADC_SEQCTRL_SEQEN(mask)) >> ADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t data) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp &= ~ADC_SEQCTRL_SEQEN_Msk; + tmp |= ADC_SEQCTRL_SEQEN(data); + ((Adc *)hw)->SEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg &= ~ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg ^= ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_SEQEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp = (tmp & ADC_SEQCTRL_SEQEN_Msk) >> ADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->SEQCTRL.reg; +} + +static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASCOMP_Msk; + tmp |= ADC_CALIB_BIASCOMP(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASREFBUF_Msk; + tmp |= ADC_CALIB_BIASREFBUF(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) +{ + return ((Adc *)hw)->CALIB.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ADC_L22_H_INCLUDED */ +#endif /* _SAML22_ADC_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_aes_l22.h b/watch-library/hardware/hri/hri_aes_l22.h new file mode 100644 index 00000000..f88f081e --- /dev/null +++ b/watch-library/hardware/hri/hri_aes_l22.h @@ -0,0 +1,1213 @@ +/** + * \file + * + * \brief SAM AES + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_AES_COMPONENT_ +#ifndef _HRI_AES_L22_H_INCLUDED_ +#define _HRI_AES_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AES_CRITICAL_SECTIONS) +#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AES_CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_aes_ciplen_reg_t; +typedef uint32_t hri_aes_ctrla_reg_t; +typedef uint32_t hri_aes_ghash_reg_t; +typedef uint32_t hri_aes_hashkey_reg_t; +typedef uint32_t hri_aes_indata_reg_t; +typedef uint32_t hri_aes_intvectv_reg_t; +typedef uint32_t hri_aes_keyword_reg_t; +typedef uint32_t hri_aes_randseed_reg_t; +typedef uint8_t hri_aes_ctrlb_reg_t; +typedef uint8_t hri_aes_databufptr_reg_t; +typedef uint8_t hri_aes_dbgctrl_reg_t; +typedef uint8_t hri_aes_intenset_reg_t; +typedef uint8_t hri_aes_intflag_reg_t; + +static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) +{ + return ((Aes *)hw)->INTFLAG.reg; +} + +static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + ((Aes *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; +} + +static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; +} + +static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; + } +} + +static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; +} + +static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; +} + +static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; +} + +static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; + } +} + +static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; +} + +static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENSET.reg = mask; +} + +static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) +{ + return ((Aes *)hw)->INTENSET.reg; +} + +static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) +{ + ((Aes *)hw)->INTENSET.reg = data; + ((Aes *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_ENABLE; + tmp |= value << AES_CTRLA_ENABLE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CIPHER; + tmp |= value << AES_CTRLA_CIPHER_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_STARTMODE; + tmp |= value << AES_CTRLA_STARTMODE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_LOD; + tmp |= value << AES_CTRLA_LOD_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYGEN; + tmp |= value << AES_CTRLA_KEYGEN_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_XORKEY; + tmp |= value << AES_CTRLA_XORKEY_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_AESMODE_Msk; + tmp |= AES_CTRLA_AESMODE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CFBS_Msk; + tmp |= AES_CTRLA_CFBS(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYSIZE_Msk; + tmp |= AES_CTRLA_KEYSIZE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CTYPE_Msk; + tmp |= AES_CTRLA_CTYPE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLA.reg; +} + +static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_START; + tmp |= value << AES_CTRLB_START_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_NEWMSG; + tmp |= value << AES_CTRLB_NEWMSG_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_EOM; + tmp |= value << AES_CTRLB_EOM_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_GFMUL; + tmp |= value << AES_CTRLB_GFMUL_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLB.reg; +} + +static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, + hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; + tmp |= AES_DATABUFPTR_INDATAPTR(data); + ((Aes *)hw)->DATABUFPTR.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) +{ + return ((Aes *)hw)->DATABUFPTR.reg; +} + +static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->INDATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) +{ + return ((Aes *)hw)->INDATA.reg; +} + +static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, + hri_aes_hashkey_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->HASHKEY[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->HASHKEY[index].reg; +} + +static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->GHASH[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->GHASH[index].reg; +} + +static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CIPLEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) +{ + return ((Aes *)hw)->CIPLEN.reg; +} + +static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->RANDSEED.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) +{ + return ((Aes *)hw)->RANDSEED.reg; +} + +static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->KEYWORD[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INTVECTV[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AES_L22_H_INCLUDED */ +#endif /* _SAML22_AES_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_ccl_l22.h b/watch-library/hardware/hri/hri_ccl_l22.h new file mode 100644 index 00000000..b510c86a --- /dev/null +++ b/watch-library/hardware/hri/hri_ccl_l22.h @@ -0,0 +1,776 @@ +/** + * \file + * + * \brief SAM CCL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_CCL_COMPONENT_ +#ifndef _HRI_CCL_L22_H_INCLUDED_ +#define _HRI_CCL_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CCL_CRITICAL_SECTIONS) +#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CCL_CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ccl_lutctrl_reg_t; +typedef uint8_t hri_ccl_ctrl_reg_t; +typedef uint8_t hri_ccl_seqctrl_reg_t; + +static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_ENABLE; + tmp |= value << CCL_CTRL_ENABLE_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_RUNSTDBY; + tmp |= value << CCL_CTRL_RUNSTDBY_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) +{ + return ((Ccl *)hw)->CTRL.reg; +} + +static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; + tmp |= CCL_SEQCTRL_SEQSEL(data); + ((Ccl *)hw)->SEQCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->SEQCTRL[index].reg; +} + +static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_ENABLE; + tmp |= value << CCL_LUTCTRL_ENABLE_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_EDGESEL; + tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INVEI; + tmp |= value << CCL_LUTCTRL_INVEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEI; + tmp |= value << CCL_LUTCTRL_LUTEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEO; + tmp |= value << CCL_LUTCTRL_LUTEO_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; + tmp |= CCL_LUTCTRL_FILTSEL(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL0_Msk; + tmp |= CCL_LUTCTRL_INSEL0(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL1_Msk; + tmp |= CCL_LUTCTRL_INSEL1(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL2_Msk; + tmp |= CCL_LUTCTRL_INSEL2(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_TRUTH_Msk; + tmp |= CCL_LUTCTRL_TRUTH(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->LUTCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CCL_L22_H_INCLUDED */ +#endif /* _SAML22_CCL_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_dmac_l22.h b/watch-library/hardware/hri/hri_dmac_l22.h new file mode 100644 index 00000000..a20e28ee --- /dev/null +++ b/watch-library/hardware/hri/hri_dmac_l22.h @@ -0,0 +1,4559 @@ +/** + * \file + * + * \brief SAM DMAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_DMAC_COMPONENT_ +#ifndef _HRI_DMAC_L22_H_INCLUDED_ +#define _HRI_DMAC_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) +#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DMAC_CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dmac_crcctrl_reg_t; +typedef uint16_t hri_dmac_ctrl_reg_t; +typedef uint16_t hri_dmac_intpend_reg_t; +typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; +typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; +typedef uint32_t hri_dmac_active_reg_t; +typedef uint32_t hri_dmac_baseaddr_reg_t; +typedef uint32_t hri_dmac_busych_reg_t; +typedef uint32_t hri_dmac_chctrlb_reg_t; +typedef uint32_t hri_dmac_crcchksum_reg_t; +typedef uint32_t hri_dmac_crcdatain_reg_t; +typedef uint32_t hri_dmac_intstatus_reg_t; +typedef uint32_t hri_dmac_pendch_reg_t; +typedef uint32_t hri_dmac_prictrl0_reg_t; +typedef uint32_t hri_dmac_swtrigctrl_reg_t; +typedef uint32_t hri_dmac_wrbaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; +typedef uint8_t hri_dmac_chctrla_reg_t; +typedef uint8_t hri_dmac_chid_reg_t; +typedef uint8_t hri_dmac_chintenset_reg_t; +typedef uint8_t hri_dmac_chintflag_reg_t; +typedef uint8_t hri_dmac_chstatus_reg_t; +typedef uint8_t hri_dmac_crcstatus_reg_t; +typedef uint8_t hri_dmac_dbgctrl_reg_t; +typedef uint8_t hri_dmac_qosctrl_reg_t; + +static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTFLAG.reg; +} + +static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + ((Dmac *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTENSET.reg; +} + +static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) +{ + ((Dmac *)hw)->CHINTENSET.reg = data; + ((Dmac *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTSTATUS.reg; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; +} + +static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->BUSYCH.reg; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PENDCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->PENDCH.reg; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->ACTIVE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) +{ + return ((Dmac *)hw)->ACTIVE.reg; +} + +static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHSTATUS.reg; +} + +static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_DMAENABLE; + tmp |= value << DMAC_CTRL_DMAENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_CRCENABLE; + tmp |= value << DMAC_CTRL_CRCENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN0; + tmp |= value << DMAC_CTRL_LVLEN0_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN1; + tmp |= value << DMAC_CTRL_LVLEN1_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN2; + tmp |= value << DMAC_CTRL_LVLEN2_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN3; + tmp |= value << DMAC_CTRL_LVLEN3_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CTRL.reg; +} + +static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, + hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; + tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; + tmp |= DMAC_CRCCTRL_CRCPOLY(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; + tmp |= DMAC_CRCCTRL_CRCSRC(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCTRL.reg; +} + +static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, + hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; + tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); + ((Dmac *)hw)->CRCDATAIN.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCDATAIN.reg; +} + +static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, + hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; + tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); + ((Dmac *)hw)->CRCCHKSUM.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCHKSUM.reg; +} + +static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= ~DMAC_DBGCTRL_DBGRUN; + tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; + ((Dmac *)hw)->DBGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk; + tmp |= DMAC_QOSCTRL_WRBQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_FQOS_Msk; + tmp |= DMAC_QOSCTRL_FQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_DQOS_Msk; + tmp |= DMAC_QOSCTRL_DQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->QOSCTRL.reg; +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, + hri_dmac_swtrigctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->SWTRIGCTRL.reg; +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN0; + tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN1; + tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN2; + tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN3; + tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) +{ + return ((Dmac *)hw)->PRICTRL0.reg; +} + +static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TERR; + tmp |= value << DMAC_INTPEND_TERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TCMPL; + tmp |= value << DMAC_INTPEND_TCMPL_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_SUSP; + tmp |= value << DMAC_INTPEND_SUSP_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_FERR; + tmp |= value << DMAC_INTPEND_FERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_BUSY; + tmp |= value << DMAC_INTPEND_BUSY_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_PEND; + tmp |= value << DMAC_INTPEND_PEND_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_ID_Msk; + tmp |= DMAC_INTPEND_ID(data); + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTPEND.reg; +} + +static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, + hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; + tmp |= DMAC_BASEADDR_BASEADDR(data); + ((Dmac *)hw)->BASEADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->BASEADDR.reg; +} + +static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; + tmp |= DMAC_WRBADDR_WRBADDR(data); + ((Dmac *)hw)->WRBADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->WRBADDR.reg; +} + +static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= ~DMAC_CHID_ID_Msk; + tmp |= DMAC_CHID_ID(data); + ((Dmac *)hw)->CHID.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHID.reg; +} + +static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((Dmac *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((Dmac *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLA.reg; +} + +static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVIE; + tmp |= value << DMAC_CHCTRLB_EVIE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVOE; + tmp |= value << DMAC_CHCTRLB_EVOE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVACT_Msk; + tmp |= DMAC_CHCTRLB_EVACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_LVL_Msk; + tmp |= DMAC_CHCTRLB_LVL(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLB_TRIGSRC(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk; + tmp |= DMAC_CHCTRLB_TRIGACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLB.reg; +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CRCSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCSTATUS.reg; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_VALID; + tmp |= value << DMAC_BTCTRL_VALID_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_SRCINC; + tmp |= value << DMAC_BTCTRL_SRCINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_DSTINC; + tmp |= value << DMAC_BTCTRL_DSTINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSEL; + tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; + tmp |= DMAC_BTCTRL_EVOSEL(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; + tmp |= DMAC_BTCTRL_BLOCKACT(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; + tmp |= DMAC_BTCTRL_BEATSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; + tmp |= DMAC_BTCTRL_STEPSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCTRL.reg; +} + +static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= ~DMAC_BTCNT_BTCNT_Msk; + tmp |= DMAC_BTCNT_BTCNT(data); + ((DmacDescriptor *)hw)->BTCNT.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCNT.reg; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t +hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; + tmp |= DMAC_SRCADDR_SRCADDR(data); + ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->SRCADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; + tmp |= DMAC_DSTADDR_DSTADDR(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; + tmp |= DMAC_DESCADDR_DESCADDR(data); + ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DESCADDR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DMAC_L22_H_INCLUDED */ +#endif /* _SAML22_DMAC_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_dsu_l22.h b/watch-library/hardware/hri/hri_dsu_l22.h new file mode 100644 index 00000000..2e8bbe8b --- /dev/null +++ b/watch-library/hardware/hri/hri_dsu_l22.h @@ -0,0 +1,1163 @@ +/** + * \file + * + * \brief SAM DSU + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_DSU_COMPONENT_ +#ifndef _HRI_DSU_L22_H_INCLUDED_ +#define _HRI_DSU_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DSU_CRITICAL_SECTIONS) +#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DSU_CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dsu_addr_reg_t; +typedef uint32_t hri_dsu_cid0_reg_t; +typedef uint32_t hri_dsu_cid1_reg_t; +typedef uint32_t hri_dsu_cid2_reg_t; +typedef uint32_t hri_dsu_cid3_reg_t; +typedef uint32_t hri_dsu_data_reg_t; +typedef uint32_t hri_dsu_dcc_reg_t; +typedef uint32_t hri_dsu_dcfg_reg_t; +typedef uint32_t hri_dsu_did_reg_t; +typedef uint32_t hri_dsu_end_reg_t; +typedef uint32_t hri_dsu_entry0_reg_t; +typedef uint32_t hri_dsu_entry1_reg_t; +typedef uint32_t hri_dsu_length_reg_t; +typedef uint32_t hri_dsu_memtype_reg_t; +typedef uint32_t hri_dsu_pid0_reg_t; +typedef uint32_t hri_dsu_pid1_reg_t; +typedef uint32_t hri_dsu_pid2_reg_t; +typedef uint32_t hri_dsu_pid3_reg_t; +typedef uint32_t hri_dsu_pid4_reg_t; +typedef uint32_t hri_dsu_pid5_reg_t; +typedef uint32_t hri_dsu_pid6_reg_t; +typedef uint32_t hri_dsu_pid7_reg_t; +typedef uint8_t hri_dsu_ctrl_reg_t; +typedef uint8_t hri_dsu_statusa_reg_t; +typedef uint8_t hri_dsu_statusb_reg_t; + +static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; +} + +static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSB.reg; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) +{ + return ((Dsu *)hw)->DID.reg; +} + +static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; +} + +static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY0.reg; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY1.reg; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->END.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) +{ + return ((Dsu *)hw)->END.reg; +} + +static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) +{ + return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MEMTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) +{ + return ((Dsu *)hw)->MEMTYPE.reg; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID4.reg; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID5.reg; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID6.reg; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID7.reg; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID0.reg; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID1.reg; +} + +static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID2.reg; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID3.reg; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID0.reg; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID1.reg; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID2.reg; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID3.reg; +} + +static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_AMOD_Msk; + tmp |= DSU_ADDR_AMOD(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_ADDR_Msk; + tmp |= DSU_ADDR_ADDR(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) +{ + return ((Dsu *)hw)->ADDR.reg; +} + +static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= ~DSU_LENGTH_LENGTH_Msk; + tmp |= DSU_LENGTH_LENGTH(data); + ((Dsu *)hw)->LENGTH.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) +{ + return ((Dsu *)hw)->LENGTH.reg; +} + +static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= ~DSU_DATA_DATA_Msk; + tmp |= DSU_DATA_DATA(data); + ((Dsu *)hw)->DATA.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) +{ + return ((Dsu *)hw)->DATA.reg; +} + +static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= ~DSU_DCC_DATA_Msk; + tmp |= DSU_DCC_DATA(data); + ((Dsu *)hw)->DCC[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCC[index].reg; +} + +static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= ~DSU_DCFG_DCFG_Msk; + tmp |= DSU_DCFG_DCFG(data); + ((Dsu *)hw)->DCFG[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCFG[index].reg; +} + +static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; +} + +static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; +} + +static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; +} + +static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSA.reg; +} + +static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DSU_L22_H_INCLUDED */ +#endif /* _SAML22_DSU_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_eic_l22.h b/watch-library/hardware/hri/hri_eic_l22.h new file mode 100644 index 00000000..058012bf --- /dev/null +++ b/watch-library/hardware/hri/hri_eic_l22.h @@ -0,0 +1,1463 @@ +/** + * \file + * + * \brief SAM EIC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_EIC_COMPONENT_ +#ifndef _HRI_EIC_L22_H_INCLUDED_ +#define _HRI_EIC_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EIC_CRITICAL_SECTIONS) +#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EIC_CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_eic_nmiflag_reg_t; +typedef uint32_t hri_eic_asynch_reg_t; +typedef uint32_t hri_eic_config_reg_t; +typedef uint32_t hri_eic_evctrl_reg_t; +typedef uint32_t hri_eic_intenset_reg_t; +typedef uint32_t hri_eic_intflag_reg_t; +typedef uint32_t hri_eic_syncbusy_reg_t; +typedef uint8_t hri_eic_ctrla_reg_t; +typedef uint8_t hri_eic_nmictrl_reg_t; + +static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + while (((Eic *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + return ((Eic *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) +{ + return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; +} + +static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) +{ + ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Eic *)hw)->NMIFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->NMIFLAG.reg; +} + +static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + ((Eic *)hw)->NMIFLAG.reg = mask; +} + +static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->INTFLAG.reg; +} + +static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + ((Eic *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); + ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); +} + +static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = mask; +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) +{ + return ((Eic *)hw)->INTENSET.reg; +} + +static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = data; + ((Eic *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Eic *)hw)->SYNCBUSY.reg; +} + +static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_ENABLE; + tmp |= value << EIC_CTRLA_ENABLE_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_CKSEL; + tmp |= value << EIC_CTRLA_CKSEL_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg = data; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) +{ + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + return ((Eic *)hw)->CTRLA.reg; +} + +static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIFILTEN; + tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIASYNCH; + tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMISENSE_Msk; + tmp |= EIC_NMICTRL_NMISENSE(data); + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->NMICTRL.reg; +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; + tmp |= EIC_EVCTRL_EXTINTEO(data); + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->EVCTRL.reg; +} + +static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= ~EIC_ASYNCH_ASYNCH_Msk; + tmp |= EIC_ASYNCH_ASYNCH(data); + ((Eic *)hw)->ASYNCH.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) +{ + return ((Eic *)hw)->ASYNCH.reg; +} + +static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN0; + tmp |= value << EIC_CONFIG_FILTEN0_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN1; + tmp |= value << EIC_CONFIG_FILTEN1_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN2; + tmp |= value << EIC_CONFIG_FILTEN2_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN3; + tmp |= value << EIC_CONFIG_FILTEN3_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN4; + tmp |= value << EIC_CONFIG_FILTEN4_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN5; + tmp |= value << EIC_CONFIG_FILTEN5_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN6; + tmp |= value << EIC_CONFIG_FILTEN6_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN7; + tmp |= value << EIC_CONFIG_FILTEN7_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE0_Msk; + tmp |= EIC_CONFIG_SENSE0(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE1_Msk; + tmp |= EIC_CONFIG_SENSE1(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE2_Msk; + tmp |= EIC_CONFIG_SENSE2(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE3_Msk; + tmp |= EIC_CONFIG_SENSE3(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE4_Msk; + tmp |= EIC_CONFIG_SENSE4(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE5_Msk; + tmp |= EIC_CONFIG_SENSE5(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE6_Msk; + tmp |= EIC_CONFIG_SENSE6(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE7_Msk; + tmp |= EIC_CONFIG_SENSE7(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) +{ + return ((Eic *)hw)->CONFIG[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EIC_L22_H_INCLUDED */ +#endif /* _SAML22_EIC_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_evsys_l22.h b/watch-library/hardware/hri/hri_evsys_l22.h new file mode 100644 index 00000000..a2964f94 --- /dev/null +++ b/watch-library/hardware/hri/hri_evsys_l22.h @@ -0,0 +1,1333 @@ +/** + * \file + * + * \brief SAM EVSYS + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_EVSYS_COMPONENT_ +#ifndef _HRI_EVSYS_L22_H_INCLUDED_ +#define _HRI_EVSYS_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) +#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EVSYS_CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_evsys_channel_reg_t; +typedef uint32_t hri_evsys_chstatus_reg_t; +typedef uint32_t hri_evsys_intenset_reg_t; +typedef uint32_t hri_evsys_intflag_reg_t; +typedef uint32_t hri_evsys_swevt_reg_t; +typedef uint32_t hri_evsys_user_reg_t; +typedef uint8_t hri_evsys_ctrla_reg_t; + +static inline bool hri_evsys_get_INTFLAG_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_INTFLAG_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_INTFLAG_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_INTFLAG_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_INTFLAG_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_INTFLAG_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_INTFLAG_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_INTFLAG_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_INTFLAG_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_INTFLAG_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_INTFLAG_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_INTFLAG_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_INTFLAG_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_INTFLAG_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_INTFLAG_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_INTFLAG_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline bool hri_evsys_get_interrupt_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_interrupt_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_interrupt_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_interrupt_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_interrupt_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_interrupt_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_interrupt_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_interrupt_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_interrupt_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_interrupt_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_interrupt_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_interrupt_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_interrupt_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_interrupt_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_interrupt_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_interrupt_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_get_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_read_INTFLAG_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTFLAG.reg; +} + +static inline void hri_evsys_clear_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + ((Evsys *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; +} + +static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; + } +} + +static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; +} + +static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; +} + +static inline bool hri_evsys_get_INTEN_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; + } +} + +static inline void hri_evsys_clear_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; +} + +static inline void hri_evsys_set_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; +} + +static inline bool hri_evsys_get_INTEN_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; + } +} + +static inline void hri_evsys_clear_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; +} + +static inline void hri_evsys_set_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; +} + +static inline bool hri_evsys_get_INTEN_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR3) >> EVSYS_INTENSET_OVR3_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; + } +} + +static inline void hri_evsys_clear_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; +} + +static inline void hri_evsys_set_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; +} + +static inline bool hri_evsys_get_INTEN_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR4) >> EVSYS_INTENSET_OVR4_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; + } +} + +static inline void hri_evsys_clear_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; +} + +static inline void hri_evsys_set_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; +} + +static inline bool hri_evsys_get_INTEN_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR5) >> EVSYS_INTENSET_OVR5_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; + } +} + +static inline void hri_evsys_clear_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; +} + +static inline void hri_evsys_set_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; +} + +static inline bool hri_evsys_get_INTEN_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR6) >> EVSYS_INTENSET_OVR6_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; + } +} + +static inline void hri_evsys_clear_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; +} + +static inline void hri_evsys_set_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; +} + +static inline bool hri_evsys_get_INTEN_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR7) >> EVSYS_INTENSET_OVR7_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; + } +} + +static inline void hri_evsys_clear_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; +} + +static inline void hri_evsys_set_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; +} + +static inline bool hri_evsys_get_INTEN_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD0) >> EVSYS_INTENSET_EVD0_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; + } +} + +static inline void hri_evsys_clear_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; +} + +static inline void hri_evsys_set_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; +} + +static inline bool hri_evsys_get_INTEN_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD1) >> EVSYS_INTENSET_EVD1_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; + } +} + +static inline void hri_evsys_clear_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; +} + +static inline void hri_evsys_set_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; +} + +static inline bool hri_evsys_get_INTEN_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD2) >> EVSYS_INTENSET_EVD2_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; + } +} + +static inline void hri_evsys_clear_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; +} + +static inline void hri_evsys_set_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; +} + +static inline bool hri_evsys_get_INTEN_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD3) >> EVSYS_INTENSET_EVD3_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; + } +} + +static inline void hri_evsys_clear_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; +} + +static inline void hri_evsys_set_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; +} + +static inline bool hri_evsys_get_INTEN_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD4) >> EVSYS_INTENSET_EVD4_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; + } +} + +static inline void hri_evsys_clear_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; +} + +static inline void hri_evsys_set_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; +} + +static inline bool hri_evsys_get_INTEN_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD5) >> EVSYS_INTENSET_EVD5_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; + } +} + +static inline void hri_evsys_clear_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; +} + +static inline void hri_evsys_set_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; +} + +static inline bool hri_evsys_get_INTEN_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD6) >> EVSYS_INTENSET_EVD6_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; + } +} + +static inline void hri_evsys_clear_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; +} + +static inline void hri_evsys_set_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; +} + +static inline bool hri_evsys_get_INTEN_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD7) >> EVSYS_INTENSET_EVD7_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; + } +} + +static inline void hri_evsys_clear_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; +} + +static inline void hri_evsys_set_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENSET.reg = mask; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_get_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_read_INTEN_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTENSET.reg; +} + +static inline void hri_evsys_write_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t data) +{ + ((Evsys *)hw)->INTENSET.reg = data; + ((Evsys *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_evsys_clear_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY0) >> EVSYS_CHSTATUS_USRRDY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY1) >> EVSYS_CHSTATUS_USRRDY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY2) >> EVSYS_CHSTATUS_USRRDY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY3) >> EVSYS_CHSTATUS_USRRDY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY4) >> EVSYS_CHSTATUS_USRRDY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY5) >> EVSYS_CHSTATUS_USRRDY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY6) >> EVSYS_CHSTATUS_USRRDY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY7) >> EVSYS_CHSTATUS_USRRDY7_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY0) >> EVSYS_CHSTATUS_CHBUSY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY1) >> EVSYS_CHSTATUS_CHBUSY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY2) >> EVSYS_CHSTATUS_CHBUSY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY3) >> EVSYS_CHSTATUS_CHBUSY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY4) >> EVSYS_CHSTATUS_CHBUSY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY5) >> EVSYS_CHSTATUS_CHBUSY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY6) >> EVSYS_CHSTATUS_CHBUSY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY7) >> EVSYS_CHSTATUS_CHBUSY7_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, hri_evsys_chstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw) +{ + return ((Evsys *)hw)->CHSTATUS.reg; +} + +static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) +{ + return ((Evsys *)hw)->CTRLA.reg; +} + +static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->CHANNEL[index].reg; +} + +static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= ~EVSYS_USER_CHANNEL_Msk; + tmp |= EVSYS_USER_CHANNEL(data); + ((Evsys *)hw)->USER[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->USER[index].reg; +} + +static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->SWEVT.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EVSYS_L22_H_INCLUDED */ +#endif /* _SAML22_EVSYS_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_freqm_l22.h b/watch-library/hardware/hri/hri_freqm_l22.h new file mode 100644 index 00000000..e221bbfd --- /dev/null +++ b/watch-library/hardware/hri/hri_freqm_l22.h @@ -0,0 +1,464 @@ +/** + * \file + * + * \brief SAM FREQM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_FREQM_COMPONENT_ +#ifndef _HRI_FREQM_L22_H_INCLUDED_ +#define _HRI_FREQM_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) +#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define FREQM_CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_freqm_cfga_reg_t; +typedef uint32_t hri_freqm_syncbusy_reg_t; +typedef uint32_t hri_freqm_value_reg_t; +typedef uint8_t hri_freqm_ctrla_reg_t; +typedef uint8_t hri_freqm_ctrlb_reg_t; +typedef uint8_t hri_freqm_intenset_reg_t; +typedef uint8_t hri_freqm_intflag_reg_t; +typedef uint8_t hri_freqm_status_reg_t; + +static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + while (((Freqm *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + return ((Freqm *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTFLAG.reg; +} + +static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + ((Freqm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; +} + +static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; +} + +static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; + } else { + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; + } +} + +static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; +} + +static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENSET.reg = mask; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTENSET.reg; +} + +static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) +{ + ((Freqm *)hw)->INTENSET.reg = data; + ((Freqm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Freqm *)hw)->SYNCBUSY.reg; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->VALUE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) +{ + return ((Freqm *)hw)->VALUE.reg; +} + +static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= ~FREQM_CTRLA_ENABLE; + tmp |= value << FREQM_CTRLA_ENABLE_Pos; + ((Freqm *)hw)->CTRLA.reg = tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg = data; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) +{ + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + return ((Freqm *)hw)->CTRLA.reg; +} + +static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) +{ + uint16_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= ~FREQM_CFGA_REFNUM_Msk; + tmp |= FREQM_CFGA_REFNUM(data); + ((Freqm *)hw)->CFGA.reg = tmp; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) +{ + return ((Freqm *)hw)->CFGA.reg; +} + +static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; +} + +static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; +} + +static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) +{ + return ((Freqm *)hw)->STATUS.reg; +} + +static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLB.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_FREQM_L22_H_INCLUDED */ +#endif /* _SAML22_FREQM_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_gclk_l22.h b/watch-library/hardware/hri/hri_gclk_l22.h new file mode 100644 index 00000000..2ae6d491 --- /dev/null +++ b/watch-library/hardware/hri/hri_gclk_l22.h @@ -0,0 +1,770 @@ +/** + * \file + * + * \brief SAM GCLK + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_GCLK_COMPONENT_ +#ifndef _HRI_GCLK_L22_H_INCLUDED_ +#define _HRI_GCLK_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) +#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GCLK_CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gclk_genctrl_reg_t; +typedef uint32_t hri_gclk_pchctrl_reg_t; +typedef uint32_t hri_gclk_syncbusy_reg_t; +typedef uint8_t hri_gclk_ctrla_reg_t; + +static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + while (((Gclk *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + return ((Gclk *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Gclk *)hw)->SYNCBUSY.reg; +} + +static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + return ((Gclk *)hw)->CTRLA.reg; +} + +static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_GENEN; + tmp |= value << GCLK_GENCTRL_GENEN_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_IDC; + tmp |= value << GCLK_GENCTRL_IDC_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OOV; + tmp |= value << GCLK_GENCTRL_OOV_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OE; + tmp |= value << GCLK_GENCTRL_OE_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIVSEL; + tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_RUNSTDBY; + tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_SRC_Msk; + tmp |= GCLK_GENCTRL_SRC(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIV_Msk; + tmp |= GCLK_GENCTRL_DIV(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + return ((Gclk *)hw)->GENCTRL[index].reg; +} + +static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_CHEN; + tmp |= value << GCLK_PCHCTRL_CHEN_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_WRTLOCK; + tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_GEN_Msk; + tmp |= GCLK_PCHCTRL_GEN(data); + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Gclk *)hw)->PCHCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GCLK_L22_H_INCLUDED */ +#endif /* _SAML22_GCLK_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_l22.h b/watch-library/hardware/hri/hri_l22.h new file mode 100644 index 00000000..d99268c1 --- /dev/null +++ b/watch-library/hardware/hri/hri_l22.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief SAM L22 HRI top-level header file + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HRI_L22_H_INCLUDED_ +#define _HRI_L22_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_L22_H_INCLUDED_ */ diff --git a/watch-library/hardware/hri/hri_mclk_l22.h b/watch-library/hardware/hri/hri_mclk_l22.h new file mode 100644 index 00000000..b03c0064 --- /dev/null +++ b/watch-library/hardware/hri/hri_mclk_l22.h @@ -0,0 +1,2300 @@ +/** + * \file + * + * \brief SAM MCLK + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_MCLK_COMPONENT_ +#ifndef _HRI_MCLK_L22_H_INCLUDED_ +#define _HRI_MCLK_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) +#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MCLK_CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mclk_ahbmask_reg_t; +typedef uint32_t hri_mclk_apbamask_reg_t; +typedef uint32_t hri_mclk_apbbmask_reg_t; +typedef uint32_t hri_mclk_apbcmask_reg_t; +typedef uint8_t hri_mclk_bupdiv_reg_t; +typedef uint8_t hri_mclk_cpudiv_reg_t; +typedef uint8_t hri_mclk_intenset_reg_t; +typedef uint8_t hri_mclk_intflag_reg_t; + +static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTFLAG.reg; +} + +static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + ((Mclk *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; +} + +static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; +} + +static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; + } else { + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; + } +} + +static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; +} + +static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENSET.reg = mask; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTENSET.reg; +} + +static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) +{ + ((Mclk *)hw)->INTENSET.reg = data; + ((Mclk *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_mclk_set_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_CPUDIV(mask)) >> MCLK_CPUDIV_CPUDIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= ~MCLK_CPUDIV_CPUDIV_Msk; + tmp |= MCLK_CPUDIV_CPUDIV(data); + ((Mclk *)hw)->CPUDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_CPUDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_CPUDIV_Msk) >> MCLK_CPUDIV_CPUDIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->CPUDIV.reg; +} + +static inline void hri_mclk_set_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg |= MCLK_BUPDIV_BUPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp = (tmp & MCLK_BUPDIV_BUPDIV(mask)) >> MCLK_BUPDIV_BUPDIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp &= ~MCLK_BUPDIV_BUPDIV_Msk; + tmp |= MCLK_BUPDIV_BUPDIV(data); + ((Mclk *)hw)->BUPDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg &= ~MCLK_BUPDIV_BUPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg ^= MCLK_BUPDIV_BUPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_BUPDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp = (tmp & MCLK_BUPDIV_BUPDIV_Msk) >> MCLK_BUPDIV_BUPDIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->BUPDIV.reg; +} + +static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB0; + tmp |= value << MCLK_AHBMASK_HPB0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB1; + tmp |= value << MCLK_AHBMASK_HPB1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB2; + tmp |= value << MCLK_AHBMASK_HPB2_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DMAC; + tmp |= value << MCLK_AHBMASK_DMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_USB; + tmp |= value << MCLK_AHBMASK_USB_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DSU; + tmp |= value << MCLK_AHBMASK_DSU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PAC; + tmp |= value << MCLK_AHBMASK_PAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL; + tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM; + tmp |= value << MCLK_AHBMASK_HSRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_PICACHU) >> MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; + tmp |= value << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->AHBMASK.reg; +} + +static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PAC; + tmp |= value << MCLK_APBAMASK_PAC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PM; + tmp |= value << MCLK_APBAMASK_PM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_MCLK; + tmp |= value << MCLK_APBAMASK_MCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RSTC; + tmp |= value << MCLK_APBAMASK_RSTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSCCTRL; + tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSC32KCTRL; + tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SUPC; + tmp |= value << MCLK_APBAMASK_SUPC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_GCLK; + tmp |= value << MCLK_APBAMASK_GCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_WDT; + tmp |= value << MCLK_APBAMASK_WDT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RTC; + tmp |= value << MCLK_APBAMASK_RTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_EIC; + tmp |= value << MCLK_APBAMASK_EIC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_FREQM; + tmp |= value << MCLK_APBAMASK_FREQM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBAMASK.reg; +} + +static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_USB; + tmp |= value << MCLK_APBBMASK_USB_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_DSU; + tmp |= value << MCLK_APBBMASK_DSU_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_NVMCTRL; + tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_PORT; + tmp |= value << MCLK_APBBMASK_PORT_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBBMASK.reg; +} + +static inline void hri_mclk_set_APBCMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_EVSYS) >> MCLK_APBCMASK_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_EVSYS; + tmp |= value << MCLK_APBCMASK_EVSYS_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM0) >> MCLK_APBCMASK_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM0; + tmp |= value << MCLK_APBCMASK_SERCOM0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM1) >> MCLK_APBCMASK_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM1; + tmp |= value << MCLK_APBCMASK_SERCOM1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM2) >> MCLK_APBCMASK_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM2; + tmp |= value << MCLK_APBCMASK_SERCOM2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM3) >> MCLK_APBCMASK_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM3; + tmp |= value << MCLK_APBCMASK_SERCOM3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM4) >> MCLK_APBCMASK_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM4; + tmp |= value << MCLK_APBCMASK_SERCOM4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM5) >> MCLK_APBCMASK_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM5; + tmp |= value << MCLK_APBCMASK_SERCOM5_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC0) >> MCLK_APBCMASK_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC0; + tmp |= value << MCLK_APBCMASK_TCC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC0) >> MCLK_APBCMASK_TC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC0; + tmp |= value << MCLK_APBCMASK_TC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC1) >> MCLK_APBCMASK_TC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC1; + tmp |= value << MCLK_APBCMASK_TC1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC2) >> MCLK_APBCMASK_TC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC2; + tmp |= value << MCLK_APBCMASK_TC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC3) >> MCLK_APBCMASK_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC3; + tmp |= value << MCLK_APBCMASK_TC3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_ADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_ADC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_ADC) >> MCLK_APBCMASK_ADC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_ADC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_ADC; + tmp |= value << MCLK_APBCMASK_ADC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_ADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_ADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AC; + tmp |= value << MCLK_APBCMASK_AC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_PTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_PTC) >> MCLK_APBCMASK_PTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_PTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_PTC; + tmp |= value << MCLK_APBCMASK_PTC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SLCD_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SLCD; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SLCD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SLCD) >> MCLK_APBCMASK_SLCD_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SLCD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SLCD; + tmp |= value << MCLK_APBCMASK_SLCD_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SLCD_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SLCD; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SLCD_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SLCD; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AES; + tmp |= value << MCLK_APBCMASK_AES_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TRNG; + tmp |= value << MCLK_APBCMASK_TRNG_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_CCL; + tmp |= value << MCLK_APBCMASK_CCL_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBCMASK.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MCLK_L22_H_INCLUDED */ +#endif /* _SAML22_MCLK_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_mtb_l22.h b/watch-library/hardware/hri/hri_mtb_l22.h new file mode 100644 index 00000000..f8cb66d5 --- /dev/null +++ b/watch-library/hardware/hri/hri_mtb_l22.h @@ -0,0 +1,551 @@ +/** + * \file + * + * \brief SAM MTB + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_MTB_COMPONENT_ +#ifndef _HRI_MTB_L22_H_INCLUDED_ +#define _HRI_MTB_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MTB_CRITICAL_SECTIONS) +#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MTB_CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mtb_authstatus_reg_t; +typedef uint32_t hri_mtb_base_reg_t; +typedef uint32_t hri_mtb_cid0_reg_t; +typedef uint32_t hri_mtb_cid1_reg_t; +typedef uint32_t hri_mtb_cid2_reg_t; +typedef uint32_t hri_mtb_cid3_reg_t; +typedef uint32_t hri_mtb_claimset_reg_t; +typedef uint32_t hri_mtb_devarch_reg_t; +typedef uint32_t hri_mtb_devid_reg_t; +typedef uint32_t hri_mtb_devtype_reg_t; +typedef uint32_t hri_mtb_flow_reg_t; +typedef uint32_t hri_mtb_itctrl_reg_t; +typedef uint32_t hri_mtb_lockaccess_reg_t; +typedef uint32_t hri_mtb_lockstatus_reg_t; +typedef uint32_t hri_mtb_master_reg_t; +typedef uint32_t hri_mtb_pid0_reg_t; +typedef uint32_t hri_mtb_pid1_reg_t; +typedef uint32_t hri_mtb_pid2_reg_t; +typedef uint32_t hri_mtb_pid3_reg_t; +typedef uint32_t hri_mtb_pid4_reg_t; +typedef uint32_t hri_mtb_pid5_reg_t; +typedef uint32_t hri_mtb_pid6_reg_t; +typedef uint32_t hri_mtb_pid7_reg_t; +typedef uint32_t hri_mtb_position_reg_t; + +static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMSET.reg = mask; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CLAIMSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw) +{ + return ((Mtb *)hw)->CLAIMSET.reg; +} + +static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data) +{ + ((Mtb *)hw)->CLAIMSET.reg = data; + ((Mtb *)hw)->CLAIMCLR.reg = ~data; +} + +static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMCLR.reg = mask; +} + +static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->BASE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw) +{ + return ((Mtb *)hw)->BASE.reg; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKSTATUS.reg; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->AUTHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->AUTHSTATUS.reg; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVARCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVARCH.reg; +} + +static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVID.reg; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVTYPE.reg; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID4.reg; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID5.reg; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID6.reg; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID7.reg; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID0.reg; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID1.reg; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID2.reg; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID3.reg; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID0.reg; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID1.reg; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID2.reg; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID3.reg; +} + +static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->POSITION.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw) +{ + return ((Mtb *)hw)->POSITION.reg; +} + +static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->MASTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw) +{ + return ((Mtb *)hw)->MASTER.reg; +} + +static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->FLOW.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw) +{ + return ((Mtb *)hw)->FLOW.reg; +} + +static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->ITCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw) +{ + return ((Mtb *)hw)->ITCTRL.reg; +} + +static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKACCESS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKACCESS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MTB_L22_H_INCLUDED */ +#endif /* _SAML22_MTB_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_nvic_l22.h b/watch-library/hardware/hri/hri_nvic_l22.h new file mode 100644 index 00000000..5596c99a --- /dev/null +++ b/watch-library/hardware/hri/hri_nvic_l22.h @@ -0,0 +1,269 @@ +/** + * \file + * + * \brief SAM NVIC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_NVIC_COMPONENT_ +#ifndef _HRI_NVIC_L22_H_INCLUDED_ +#define _HRI_NVIC_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVIC_CRITICAL_SECTIONS) +#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVIC_CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_nvic_icer_reg_t; +typedef uint32_t hri_nvic_icpr_reg_t; +typedef uint32_t hri_nvic_ipr_reg_t; +typedef uint32_t hri_nvic_iser_reg_t; +typedef uint32_t hri_nvic_ispr_reg_t; + +static inline void hri_nvic_set_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ISER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ISER_reg(const void *const hw, hri_nvic_iser_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw) +{ + return ((Nvic *)hw)->ISER.reg; +} + +static inline void hri_nvic_set_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ICER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ICER_reg(const void *const hw, hri_nvic_icer_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw) +{ + return ((Nvic *)hw)->ICER.reg; +} + +static inline void hri_nvic_set_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ISPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->ISPR.reg; +} + +static inline void hri_nvic_set_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ICPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->ICPR.reg; +} + +static inline void hri_nvic_set_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ipr_reg_t hri_nvic_get_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->IPR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ipr_reg_t hri_nvic_read_IPR_reg(const void *const hw, uint8_t index) +{ + return ((Nvic *)hw)->IPR[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVIC_L22_H_INCLUDED */ +#endif /* _SAML22_NVIC_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_nvmctrl_l22.h b/watch-library/hardware/hri/hri_nvmctrl_l22.h new file mode 100644 index 00000000..07629fba --- /dev/null +++ b/watch-library/hardware/hri/hri_nvmctrl_l22.h @@ -0,0 +1,1104 @@ +/** + * \file + * + * \brief SAM NVMCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_NVMCTRL_COMPONENT_ +#ifndef _HRI_NVMCTRL_L22_H_INCLUDED_ +#define _HRI_NVMCTRL_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) +#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVMCTRL_CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_nvmctrl_ctrla_reg_t; +typedef uint16_t hri_nvmctrl_lock_reg_t; +typedef uint16_t hri_nvmctrl_status_reg_t; +typedef uint32_t hri_nvmctrl_addr_reg_t; +typedef uint32_t hri_nvmctrl_ctrlb_reg_t; +typedef uint32_t hri_nvmctrl_param_reg_t; +typedef uint8_t hri_nvmctrl_intenset_reg_t; +typedef uint8_t hri_nvmctrl_intflag_reg_t; + +static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, + hri_nvmctrl_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; +} + +static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; + } +} + +static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; +} + +static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, + hri_nvmctrl_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTENSET.reg; +} + +static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) +{ + ((Nvmctrl *)hw)->INTENSET.reg = data; + ((Nvmctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMD_Msk; + tmp |= NVMCTRL_CTRLA_CMD(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk; + tmp |= NVMCTRL_CTRLA_CMDEX(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLA.reg; +} + +static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_MANW; + tmp |= value << NVMCTRL_CTRLB_MANW_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_FWUP_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_FWUP; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_FWUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_FWUP) >> NVMCTRL_CTRLB_FWUP_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_FWUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_FWUP; + tmp |= value << NVMCTRL_CTRLB_FWUP_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_FWUP_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_FWUP; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_FWUP_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_FWUP; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_CACHEDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS) >> NVMCTRL_CTRLB_CACHEDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_CACHEDIS; + tmp |= value << NVMCTRL_CTRLB_CACHEDIS_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_RWS_Msk; + tmp |= NVMCTRL_CTRLB_RWS(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk; + tmp |= NVMCTRL_CTRLB_SLEEPPRM(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_READMODE_Msk; + tmp |= NVMCTRL_CTRLB_READMODE(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLB.reg; +} + +static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_NVMP_Msk; + tmp |= NVMCTRL_PARAM_NVMP(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_PSZ_Msk; + tmp |= NVMCTRL_PARAM_PSZ(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_RWWEEP_bf(const void *const hw, + hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_RWWEEP(mask)) >> NVMCTRL_PARAM_RWWEEP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_RWWEEP_Msk; + tmp |= NVMCTRL_PARAM_RWWEEP(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_RWWEEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PARAM.reg; +} + +static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= ~NVMCTRL_ADDR_ADDR_Msk; + tmp |= NVMCTRL_ADDR_ADDR(data); + ((Nvmctrl *)hw)->ADDR.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ADDR.reg; +} + +static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= ~NVMCTRL_LOCK_LOCK_Msk; + tmp |= NVMCTRL_LOCK_LOCK(data); + ((Nvmctrl *)hw)->LOCK.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->LOCK.reg; +} + +static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVMCTRL_L22_H_INCLUDED */ +#endif /* _SAML22_NVMCTRL_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_osc32kctrl_l22.h b/watch-library/hardware/hri/hri_osc32kctrl_l22.h new file mode 100644 index 00000000..44bb32ba --- /dev/null +++ b/watch-library/hardware/hri/hri_osc32kctrl_l22.h @@ -0,0 +1,1233 @@ +/** + * \file + * + * \brief SAM OSC32KCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_OSC32KCTRL_COMPONENT_ +#ifndef _HRI_OSC32KCTRL_L22_H_INCLUDED_ +#define _HRI_OSC32KCTRL_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; +typedef uint32_t hri_osc32kctrl_intenset_reg_t; +typedef uint32_t hri_osc32kctrl_intflag_reg_t; +typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; +typedef uint32_t hri_osc32kctrl_status_reg_t; +typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; +typedef uint8_t hri_osc32kctrl_evctrl_reg_t; +typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t; +typedef uint8_t hri_osc32kctrl_slcdctrl_reg_t; + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, + hri_osc32kctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL; +} + +static inline bool hri_osc32kctrl_get_INTEN_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_CLKFAIL) >> OSC32KCTRL_INTENSET_CLKFAIL_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_CLKFAIL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL; +} + +static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, + hri_osc32kctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTENSET.reg; +} + +static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = data; + ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKFAIL) >> OSC32KCTRL_STATUS_CLKFAIL_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_CLKSW_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKSW) >> OSC32KCTRL_STATUS_CLKSW_Pos; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, + hri_osc32kctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->STATUS.reg; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; + tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); + ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->RTCCTRL.reg; +} + +static inline void hri_osc32kctrl_set_SLCDCTRL_SLCDSEL_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->SLCDCTRL.reg |= OSC32KCTRL_SLCDCTRL_SLCDSEL; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_SLCDCTRL_SLCDSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg; + tmp = (tmp & OSC32KCTRL_SLCDCTRL_SLCDSEL) >> OSC32KCTRL_SLCDCTRL_SLCDSEL_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_SLCDCTRL_SLCDSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg; + tmp &= ~OSC32KCTRL_SLCDCTRL_SLCDSEL; + tmp |= value << OSC32KCTRL_SLCDCTRL_SLCDSEL_Pos; + ((Osc32kctrl *)hw)->SLCDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_SLCDCTRL_SLCDSEL_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->SLCDCTRL.reg &= ~OSC32KCTRL_SLCDCTRL_SLCDSEL; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_SLCDCTRL_SLCDSEL_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->SLCDCTRL.reg ^= OSC32KCTRL_SLCDCTRL_SLCDSEL; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->SLCDCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_slcdctrl_reg_t hri_osc32kctrl_get_SLCDCTRL_reg(const void *const hw, + hri_osc32kctrl_slcdctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->SLCDCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->SLCDCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->SLCDCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_slcdctrl_reg_t hri_osc32kctrl_read_SLCDCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->SLCDCTRL.reg; +} + +static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; + tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; + tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN32K; + tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN1K; + tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->XOSC32K.reg; +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; + tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, + hri_osc32kctrl_cfdctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->CFDCTRL.reg; +} + +static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; + tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; + ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, + hri_osc32kctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN32K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN1K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSCULP32K.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSC32KCTRL_L22_H_INCLUDED */ +#endif /* _SAML22_OSC32KCTRL_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_oscctrl_l22.h b/watch-library/hardware/hri/hri_oscctrl_l22.h new file mode 100644 index 00000000..d1bc4b60 --- /dev/null +++ b/watch-library/hardware/hri/hri_oscctrl_l22.h @@ -0,0 +1,3451 @@ +/** + * \file + * + * \brief SAM OSCCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_OSCCTRL_COMPONENT_ +#ifndef _HRI_OSCCTRL_L22_H_INCLUDED_ +#define _HRI_OSCCTRL_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) +#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSCCTRL_CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_oscctrl_dfllctrl_reg_t; +typedef uint16_t hri_oscctrl_xoscctrl_reg_t; +typedef uint32_t hri_oscctrl_dfllmul_reg_t; +typedef uint32_t hri_oscctrl_dfllval_reg_t; +typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrl_dpllratio_reg_t; +typedef uint32_t hri_oscctrl_intenset_reg_t; +typedef uint32_t hri_oscctrl_intflag_reg_t; +typedef uint32_t hri_oscctrl_status_reg_t; +typedef uint8_t hri_oscctrl_cfdpresc_reg_t; +typedef uint8_t hri_oscctrl_dfllsync_reg_t; +typedef uint8_t hri_oscctrl_dpllctrla_reg_t; +typedef uint8_t hri_oscctrl_dpllpresc_reg_t; +typedef uint8_t hri_oscctrl_dpllstatus_reg_t; +typedef uint8_t hri_oscctrl_dpllsyncbusy_reg_t; +typedef uint8_t hri_oscctrl_evctrl_reg_t; +typedef uint8_t hri_oscctrl_osc16mctrl_reg_t; + +static inline void hri_oscctrl_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrl_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL; +} + +static inline bool hri_oscctrl_get_INTFLAG_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL; +} + +static inline bool hri_oscctrl_get_interrupt_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, + hri_oscctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) +{ + ((Oscctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY) >> OSCCTRL_INTENSET_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL) >> OSCCTRL_INTENSET_XOSCFAIL_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL; +} + +static inline void hri_oscctrl_set_INTEN_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; +} + +static inline bool hri_oscctrl_get_INTEN_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_OSC16MRDY) >> OSCCTRL_INTENSET_OSC16MRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_OSC16MRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKR) >> OSCCTRL_INTENSET_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKF) >> OSCCTRL_INTENSET_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLTO) >> OSCCTRL_INTENSET_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLDRTO) >> OSCCTRL_INTENSET_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; +} + +static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, + hri_oscctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTENSET.reg; +} + +static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) +{ + ((Oscctrl *)hw)->INTENSET.reg = data; + ((Oscctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY) >> OSCCTRL_STATUS_XOSCRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL) >> OSCCTRL_STATUS_XOSCFAIL_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW) >> OSCCTRL_STATUS_XOSCCKSW_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_OSC16MRDY) >> OSCCTRL_STATUS_OSC16MRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKR) >> OSCCTRL_STATUS_DPLLLCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKF) >> OSCCTRL_STATUS_DPLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLTO) >> OSCCTRL_STATUS_DPLLTO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLDRTO) >> OSCCTRL_STATUS_DPLLLDRTO_Pos; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->STATUS.reg; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLPRESC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) >> OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, + hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLSTATUS.reg; +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; + tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_XTALEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; + tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_XTALEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_XTALEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_CFDEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; + tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_CFDEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_CFDEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_SWBEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; + tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_SWBEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_SWBEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_AMPGC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_AMPGC) >> OSCCTRL_XOSCCTRL_AMPGC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_AMPGC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_AMPGC; + tmp |= value << OSCCTRL_XOSCCTRL_AMPGC_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_AMPGC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_AMPGC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_GAIN(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_GAIN_bf(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN(mask)) >> OSCCTRL_XOSCCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_GAIN_Msk; + tmp |= OSCCTRL_XOSCCTRL_GAIN(data); + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_GAIN(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_GAIN(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_GAIN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN_Msk) >> OSCCTRL_XOSCCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; + tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->XOSCCTRL.reg; +} + +static inline void hri_oscctrl_set_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg |= OSCCTRL_CFDPRESC_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_CFDPRESC_bf(const void *const hw, + hri_oscctrl_cfdpresc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC(mask)) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp &= ~OSCCTRL_CFDPRESC_CFDPRESC_Msk; + tmp |= OSCCTRL_CFDPRESC_CFDPRESC(data); + ((Oscctrl *)hw)->CFDPRESC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg &= ~OSCCTRL_CFDPRESC_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg ^= OSCCTRL_CFDPRESC_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_CFDPRESC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC_Msk) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_reg(const void *const hw, + hri_oscctrl_cfdpresc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->CFDPRESC.reg; +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO) >> OSCCTRL_EVCTRL_CFDEO_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO; + tmp |= value << OSCCTRL_EVCTRL_CFDEO_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_oscctrl_set_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_ENABLE) >> OSCCTRL_OSC16MCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_ENABLE; + tmp |= value << OSCCTRL_OSC16MCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_RUNSTDBY) >> OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_ONDEMAND) >> OSCCTRL_OSC16MCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_ONDEMAND; + tmp |= value << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_FSEL(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_FSEL_bf(const void *const hw, + hri_oscctrl_osc16mctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL(mask)) >> OSCCTRL_OSC16MCTRL_FSEL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_FSEL_Msk; + tmp |= OSCCTRL_OSC16MCTRL_FSEL(data); + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_FSEL(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_FSEL(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_FSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL_Msk) >> OSCCTRL_OSC16MCTRL_FSEL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_reg(const void *const hw, + hri_oscctrl_osc16mctrl_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->OSC16MCTRL.reg; +} + +static inline void hri_oscctrl_set_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_ENABLE) >> OSCCTRL_DFLLCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_ENABLE; + tmp |= value << OSCCTRL_DFLLCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_MODE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_MODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_MODE) >> OSCCTRL_DFLLCTRL_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_MODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_MODE; + tmp |= value << OSCCTRL_DFLLCTRL_MODE_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_MODE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_MODE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_STABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_STABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_STABLE) >> OSCCTRL_DFLLCTRL_STABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_STABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_STABLE; + tmp |= value << OSCCTRL_DFLLCTRL_STABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_STABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_STABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_LLAW; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_LLAW_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_LLAW) >> OSCCTRL_DFLLCTRL_LLAW_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_LLAW_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_LLAW; + tmp |= value << OSCCTRL_DFLLCTRL_LLAW_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_LLAW; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_LLAW; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_USBCRM; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_USBCRM) >> OSCCTRL_DFLLCTRL_USBCRM_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_USBCRM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_USBCRM; + tmp |= value << OSCCTRL_DFLLCTRL_USBCRM_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_USBCRM; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_USBCRM; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_RUNSTDBY) >> OSCCTRL_DFLLCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_ONDEMAND) >> OSCCTRL_DFLLCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_ONDEMAND; + tmp |= value << OSCCTRL_DFLLCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_CCDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_CCDIS) >> OSCCTRL_DFLLCTRL_CCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_CCDIS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_CCDIS; + tmp |= value << OSCCTRL_DFLLCTRL_CCDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_CCDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_CCDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_QLDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_QLDIS) >> OSCCTRL_DFLLCTRL_QLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_QLDIS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_QLDIS; + tmp |= value << OSCCTRL_DFLLCTRL_QLDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_QLDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_QLDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_BPLCKC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_BPLCKC) >> OSCCTRL_DFLLCTRL_BPLCKC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_BPLCKC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_BPLCKC; + tmp |= value << OSCCTRL_DFLLCTRL_BPLCKC_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_BPLCKC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_BPLCKC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_WAITLOCK; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_WAITLOCK) >> OSCCTRL_DFLLCTRL_WAITLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_WAITLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_WAITLOCK; + tmp |= value << OSCCTRL_DFLLCTRL_WAITLOCK_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_WAITLOCK; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_WAITLOCK; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_get_DFLLCTRL_reg(const void *const hw, + hri_oscctrl_dfllctrl_reg_t mask) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_read_DFLLCTRL_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->DFLLCTRL.reg; +} + +static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; + tmp |= OSCCTRL_DFLLVAL_FINE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; + tmp |= OSCCTRL_DFLLVAL_COARSE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; + tmp |= OSCCTRL_DFLLVAL_DIFF(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLVAL.reg; +} + +static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; + tmp |= OSCCTRL_DFLLMUL_MUL(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_FSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_CSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLMUL.reg; +} + +static inline void hri_oscctrl_set_DFLLSYNC_READREQ_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_READREQ; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_READREQ_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_READREQ) >> OSCCTRL_DFLLSYNC_READREQ_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_READREQ_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_READREQ; + tmp |= value << OSCCTRL_DFLLSYNC_READREQ_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_READREQ_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_READREQ; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_READREQ_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_READREQ; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, + hri_oscctrl_dfllsync_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLSYNC.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->DPLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->DPLLRATIO.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LPEN) >> OSCCTRL_DPLLCTRLB_LPEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LPEN; + tmp |= value << OSCCTRL_DPLLCTRLB_LPEN_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLCTRLB.reg; +} + +static inline void hri_oscctrl_set_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg |= OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_PRESC_bf(const void *const hw, + hri_oscctrl_dpllpresc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC(mask)) >> OSCCTRL_DPLLPRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp &= ~OSCCTRL_DPLLPRESC_PRESC_Msk; + tmp |= OSCCTRL_DPLLPRESC_PRESC(data); + ((Oscctrl *)hw)->DPLLPRESC.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg &= ~OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg ^= OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_PRESC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC_Msk) >> OSCCTRL_DPLLPRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_reg(const void *const hw, + hri_oscctrl_dpllpresc_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->DPLLPRESC.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSCCTRL_L22_H_INCLUDED */ +#endif /* _SAML22_OSCCTRL_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_pac_l22.h b/watch-library/hardware/hri/hri_pac_l22.h new file mode 100644 index 00000000..488c7079 --- /dev/null +++ b/watch-library/hardware/hri/hri_pac_l22.h @@ -0,0 +1,1076 @@ +/** + * \file + * + * \brief SAM PAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_PAC_COMPONENT_ +#ifndef _HRI_PAC_L22_H_INCLUDED_ +#define _HRI_PAC_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PAC_CRITICAL_SECTIONS) +#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PAC_CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pac_intflaga_reg_t; +typedef uint32_t hri_pac_intflagahb_reg_t; +typedef uint32_t hri_pac_intflagb_reg_t; +typedef uint32_t hri_pac_intflagc_reg_t; +typedef uint32_t hri_pac_statusa_reg_t; +typedef uint32_t hri_pac_statusb_reg_t; +typedef uint32_t hri_pac_statusc_reg_t; +typedef uint32_t hri_pac_wrctrl_reg_t; +typedef uint8_t hri_pac_evctrl_reg_t; +typedef uint8_t hri_pac_intenset_reg_t; + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMCM0P) >> PAC_INTFLAGAHB_HSRAMCM0P_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMCM0P; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDSU) >> PAC_INTFLAGAHB_HSRAMDSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDSU; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMDMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDMAC) >> PAC_INTFLAGAHB_HSRAMDMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMDMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDMAC; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGAHB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGAHB.reg; +} + +static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGAHB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; +} + +static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; +} + +static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; +} + +static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; +} + +static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; +} + +static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; +} + +static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; +} + +static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; +} + +static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; +} + +static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; +} + +static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGA.reg; +} + +static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + ((Pac *)hw)->INTFLAGA.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; +} + +static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; +} + +static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; +} + +static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; +} + +static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; +} + +static inline bool hri_pac_get_INTFLAGB_MTB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_MTB) >> PAC_INTFLAGB_MTB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_MTB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_MTB; +} + +static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGB.reg; +} + +static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGC_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_EVSYS) >> PAC_INTFLAGC_EVSYS_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_EVSYS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_EVSYS; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM0) >> PAC_INTFLAGC_SERCOM0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM0; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM1) >> PAC_INTFLAGC_SERCOM1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM1; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM2) >> PAC_INTFLAGC_SERCOM2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM2; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM3) >> PAC_INTFLAGC_SERCOM3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM3; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM4) >> PAC_INTFLAGC_SERCOM4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM4; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM5) >> PAC_INTFLAGC_SERCOM5_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM5; +} + +static inline bool hri_pac_get_INTFLAGC_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC0) >> PAC_INTFLAGC_TCC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC0; +} + +static inline bool hri_pac_get_INTFLAGC_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC0) >> PAC_INTFLAGC_TC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC0; +} + +static inline bool hri_pac_get_INTFLAGC_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC1) >> PAC_INTFLAGC_TC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC1; +} + +static inline bool hri_pac_get_INTFLAGC_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC2) >> PAC_INTFLAGC_TC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC2; +} + +static inline bool hri_pac_get_INTFLAGC_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC3) >> PAC_INTFLAGC_TC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC3; +} + +static inline bool hri_pac_get_INTFLAGC_ADC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ADC) >> PAC_INTFLAGC_ADC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_ADC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ADC; +} + +static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; +} + +static inline bool hri_pac_get_INTFLAGC_PTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PTC) >> PAC_INTFLAGC_PTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PTC; +} + +static inline bool hri_pac_get_INTFLAGC_SLCD_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SLCD) >> PAC_INTFLAGC_SLCD_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SLCD_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SLCD; +} + +static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; +} + +static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; +} + +static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; +} + +static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGC.reg; +} + +static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + ((Pac *)hw)->INTFLAGC.reg = mask; +} + +static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; +} + +static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; +} + +static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; + } else { + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; + } +} + +static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; +} + +static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENSET.reg = mask; +} + +static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) +{ + return ((Pac *)hw)->INTENSET.reg; +} + +static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) +{ + ((Pac *)hw)->INTENSET.reg = data; + ((Pac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; +} + +static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; +} + +static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; +} + +static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; +} + +static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; +} + +static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; +} + +static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSA.reg; +} + +static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; +} + +static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; +} + +static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; +} + +static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; +} + +static inline bool hri_pac_get_STATUSB_MTB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_MTB) >> PAC_STATUSB_MTB_Pos; +} + +static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSB.reg; +} + +static inline bool hri_pac_get_STATUSC_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_EVSYS) >> PAC_STATUSC_EVSYS_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM0) >> PAC_STATUSC_SERCOM0_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM1) >> PAC_STATUSC_SERCOM1_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM2) >> PAC_STATUSC_SERCOM2_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM3) >> PAC_STATUSC_SERCOM3_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM4) >> PAC_STATUSC_SERCOM4_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM5) >> PAC_STATUSC_SERCOM5_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC0) >> PAC_STATUSC_TCC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC0) >> PAC_STATUSC_TC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC1) >> PAC_STATUSC_TC1_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC2) >> PAC_STATUSC_TC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC3) >> PAC_STATUSC_TC3_Pos; +} + +static inline bool hri_pac_get_STATUSC_ADC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ADC) >> PAC_STATUSC_ADC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; +} + +static inline bool hri_pac_get_STATUSC_PTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PTC) >> PAC_STATUSC_PTC_Pos; +} + +static inline bool hri_pac_get_STATUSC_SLCD_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SLCD) >> PAC_STATUSC_SLCD_Pos; +} + +static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; +} + +static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; +} + +static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; +} + +static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSC.reg; +} + +static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_PERID_Msk; + tmp |= PAC_WRCTRL_PERID(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_KEY_Msk; + tmp |= PAC_WRCTRL_KEY(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->WRCTRL.reg; +} + +static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= ~PAC_EVCTRL_ERREO; + tmp |= value << PAC_EVCTRL_ERREO_Pos; + ((Pac *)hw)->EVCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PAC_L22_H_INCLUDED */ +#endif /* _SAML22_PAC_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_pm_l22.h b/watch-library/hardware/hri/hri_pm_l22.h new file mode 100644 index 00000000..d56d3cf7 --- /dev/null +++ b/watch-library/hardware/hri/hri_pm_l22.h @@ -0,0 +1,592 @@ +/** + * \file + * + * \brief SAM PM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_PM_COMPONENT_ +#ifndef _HRI_PM_L22_H_INCLUDED_ +#define _HRI_PM_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PM_CRITICAL_SECTIONS) +#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PM_CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_pm_stdbycfg_reg_t; +typedef uint8_t hri_pm_ctrla_reg_t; +typedef uint8_t hri_pm_intenset_reg_t; +typedef uint8_t hri_pm_intflag_reg_t; +typedef uint8_t hri_pm_plcfg_reg_t; +typedef uint8_t hri_pm_sleepcfg_reg_t; + +static inline bool hri_pm_get_INTFLAG_PLRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos; +} + +static inline void hri_pm_clear_INTFLAG_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY; +} + +static inline bool hri_pm_get_interrupt_PLRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos; +} + +static inline void hri_pm_clear_interrupt_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY; +} + +static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) +{ + return ((Pm *)hw)->INTFLAG.reg; +} + +static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + ((Pm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pm_set_INTEN_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; +} + +static inline bool hri_pm_get_INTEN_PLRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_PLRDY) >> PM_INTENSET_PLRDY_Pos; +} + +static inline void hri_pm_write_INTEN_PLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; + } else { + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; + } +} + +static inline void hri_pm_clear_INTEN_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; +} + +static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENSET.reg = mask; +} + +static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) +{ + return ((Pm *)hw)->INTENSET.reg; +} + +static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) +{ + ((Pm *)hw)->INTENSET.reg = data; + ((Pm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= ~PM_CTRLA_IORET; + tmp |= value << PM_CTRLA_IORET_Pos; + ((Pm *)hw)->CTRLA.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) +{ + return ((Pm *)hw)->CTRLA.reg; +} + +static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; + tmp |= PM_SLEEPCFG_SLEEPMODE(data); + ((Pm *)hw)->SLEEPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->SLEEPCFG.reg; +} + +static inline void hri_pm_set_PLCFG_PLDIS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLDIS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_PLCFG_PLDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp = (tmp & PM_PLCFG_PLDIS) >> PM_PLCFG_PLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_PLCFG_PLDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PLCFG.reg; + tmp &= ~PM_PLCFG_PLDIS; + tmp |= value << PM_PLCFG_PLDIS_Pos; + ((Pm *)hw)->PLCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PLCFG_PLDIS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLDIS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PLCFG_PLDIS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLDIS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLSEL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp = (tmp & PM_PLCFG_PLSEL(mask)) >> PM_PLCFG_PLSEL_Pos; + return tmp; +} + +static inline void hri_pm_write_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PLCFG.reg; + tmp &= ~PM_PLCFG_PLSEL_Msk; + tmp |= PM_PLCFG_PLSEL(data); + ((Pm *)hw)->PLCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLSEL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLSEL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_PLSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp = (tmp & PM_PLCFG_PLSEL_Msk) >> PM_PLCFG_PLSEL_Pos; + return tmp; +} + +static inline void hri_pm_set_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->PLCFG.reg; +} + +static inline void hri_pm_set_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_VREGSMOD(mask)) >> PM_STDBYCFG_VREGSMOD_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_VREGSMOD_Msk; + tmp |= PM_STDBYCFG_VREGSMOD(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_VREGSMOD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_VREGSMOD_Msk) >> PM_STDBYCFG_VREGSMOD_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASHS(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASHS(mask)) >> PM_STDBYCFG_BBIASHS_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_BBIASHS_Msk; + tmp |= PM_STDBYCFG_BBIASHS(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASHS(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASHS(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASHS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASHS_Msk) >> PM_STDBYCFG_BBIASHS_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->STDBYCFG.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PM_L22_H_INCLUDED */ +#endif /* _SAML22_PM_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_port_l22.h b/watch-library/hardware/hri/hri_port_l22.h new file mode 100644 index 00000000..ee99c2e8 --- /dev/null +++ b/watch-library/hardware/hri/hri_port_l22.h @@ -0,0 +1,2357 @@ +/** + * \file + * + * \brief SAM PORT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_PORT_COMPONENT_ +#ifndef _HRI_PORT_L22_H_INCLUDED_ +#define _HRI_PORT_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PORT_CRITICAL_SECTIONS) +#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PORT_CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_port_ctrl_reg_t; +typedef uint32_t hri_port_dir_reg_t; +typedef uint32_t hri_port_evctrl_reg_t; +typedef uint32_t hri_port_in_reg_t; +typedef uint32_t hri_port_out_reg_t; +typedef uint32_t hri_port_wrconfig_reg_t; +typedef uint32_t hri_portgroup_ctrl_reg_t; +typedef uint32_t hri_portgroup_dir_reg_t; +typedef uint32_t hri_portgroup_evctrl_reg_t; +typedef uint32_t hri_portgroup_in_reg_t; +typedef uint32_t hri_portgroup_out_reg_t; +typedef uint32_t hri_portgroup_wrconfig_reg_t; +typedef uint8_t hri_port_pincfg_reg_t; +typedef uint8_t hri_port_pmux_reg_t; +typedef uint8_t hri_portgroup_pincfg_reg_t; +typedef uint8_t hri_portgroup_pmux_reg_t; + +static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) +{ + return ((PortGroup *)hw)->DIR.reg; +} + +static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = data; + ((PortGroup *)hw)->DIRCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = mask; +} + +static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) +{ + return ((PortGroup *)hw)->OUT.reg; +} + +static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = data; + ((PortGroup *)hw)->OUTCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) +{ + return ((PortGroup *)hw)->IN.reg; +} + +static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((PortGroup *)hw)->CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->CTRL.reg; +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->EVCTRL.reg; +} + +static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PMUX[index].reg; +} + +static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PINCFG[index].reg; +} + +static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].DIR.reg; +} + +static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; +} + +static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; +} + +static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].OUT.reg; +} + +static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; +} + +static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; +} + +static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].IN.reg; +} + +static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].CTRL.reg; +} + +static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; +} + +static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; +} + +static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; +} + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PORT_L22_H_INCLUDED */ +#endif /* _SAML22_PORT_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_rstc_l22.h b/watch-library/hardware/hri/hri_rstc_l22.h new file mode 100644 index 00000000..853744e2 --- /dev/null +++ b/watch-library/hardware/hri/hri_rstc_l22.h @@ -0,0 +1,132 @@ +/** + * \file + * + * \brief SAM RSTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_RSTC_COMPONENT_ +#ifndef _HRI_RSTC_L22_H_INCLUDED_ +#define _HRI_RSTC_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) +#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSTC_CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_rstc_bkupexit_reg_t; +typedef uint8_t hri_rstc_rcause_reg_t; + +static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->RCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->RCAUSE.reg; +} + +static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->BKUPEXIT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) +{ + return ((Rstc *)hw)->BKUPEXIT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSTC_L22_H_INCLUDED */ +#endif /* _SAML22_RSTC_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_rtc_l22.h b/watch-library/hardware/hri/hri_rtc_l22.h new file mode 100644 index 00000000..0b46f010 --- /dev/null +++ b/watch-library/hardware/hri/hri_rtc_l22.h @@ -0,0 +1,9084 @@ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_RTC_COMPONENT_ +#ifndef _HRI_RTC_L22_H_INCLUDED_ +#define _HRI_RTC_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rtcmode0_ctrla_reg_t; +typedef uint16_t hri_rtcmode0_ctrlb_reg_t; +typedef uint16_t hri_rtcmode0_intenset_reg_t; +typedef uint16_t hri_rtcmode0_intflag_reg_t; +typedef uint16_t hri_rtcmode1_comp_reg_t; +typedef uint16_t hri_rtcmode1_count_reg_t; +typedef uint16_t hri_rtcmode1_ctrla_reg_t; +typedef uint16_t hri_rtcmode1_ctrlb_reg_t; +typedef uint16_t hri_rtcmode1_intenset_reg_t; +typedef uint16_t hri_rtcmode1_intflag_reg_t; +typedef uint16_t hri_rtcmode1_per_reg_t; +typedef uint16_t hri_rtcmode2_ctrla_reg_t; +typedef uint16_t hri_rtcmode2_ctrlb_reg_t; +typedef uint16_t hri_rtcmode2_intenset_reg_t; +typedef uint16_t hri_rtcmode2_intflag_reg_t; +typedef uint32_t hri_rtc_bkup_reg_t; +typedef uint32_t hri_rtc_gp_reg_t; +typedef uint32_t hri_rtc_tampctrl_reg_t; +typedef uint32_t hri_rtc_tampid_reg_t; +typedef uint32_t hri_rtcalarm_alarm_reg_t; +typedef uint32_t hri_rtcmode0_comp_reg_t; +typedef uint32_t hri_rtcmode0_count_reg_t; +typedef uint32_t hri_rtcmode0_evctrl_reg_t; +typedef uint32_t hri_rtcmode0_syncbusy_reg_t; +typedef uint32_t hri_rtcmode0_timestamp_reg_t; +typedef uint32_t hri_rtcmode1_evctrl_reg_t; +typedef uint32_t hri_rtcmode1_syncbusy_reg_t; +typedef uint32_t hri_rtcmode1_timestamp_reg_t; +typedef uint32_t hri_rtcmode2_alarm_reg_t; +typedef uint32_t hri_rtcmode2_clock_reg_t; +typedef uint32_t hri_rtcmode2_evctrl_reg_t; +typedef uint32_t hri_rtcmode2_syncbusy_reg_t; +typedef uint32_t hri_rtcmode2_timestamp_reg_t; +typedef uint8_t hri_rtc_dbgctrl_reg_t; +typedef uint8_t hri_rtc_freqcorr_reg_t; +typedef uint8_t hri_rtcalarm_mask_reg_t; +typedef uint8_t hri_rtcmode2_mask_reg_t; + +static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, + hri_rtcmode0_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTFLAG.reg; +} + +static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, + hri_rtcmode1_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTFLAG.reg; +} + +static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, + hri_rtcmode2_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTFLAG.reg; +} + +static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; + } +} + +static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = mask; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, + hri_rtcmode0_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTENSET.reg; +} + +static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = data; + ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; + } +} + +static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = mask; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, + hri_rtcmode1_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTENSET.reg; +} + +static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = data; + ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; + } +} + +static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = mask; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, + hri_rtcmode2_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTENSET.reg; +} + +static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = data; + ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode0_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode1_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode2_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.TIMESTAMP.reg; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.TIMESTAMP.reg; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.TIMESTAMP.reg; +} + +static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_ENABLE; + tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_BKTRST; + tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_GPTRST; + tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; + tmp |= RTC_MODE0_CTRLA_MODE(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE0_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE0.CTRLA.reg; +} + +static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_ENABLE; + tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_BKTRST; + tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_GPTRST; + tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; + tmp |= RTC_MODE1_CTRLA_MODE(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE1_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE1.CTRLA.reg; +} + +static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_ENABLE; + tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLKREP; + tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_BKTRST; + tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_GPTRST; + tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; + tmp |= RTC_MODE2_CTRLA_MODE(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE2_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + return ((Rtc *)hw)->MODE2.CTRLA.reg; +} + +static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_GP0EN; + tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_RTCOUT; + tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DMAEN; + tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk; + tmp |= RTC_MODE0_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk; + tmp |= RTC_MODE0_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.CTRLB.reg; +} + +static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_GP0EN; + tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_RTCOUT; + tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DMAEN; + tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk; + tmp |= RTC_MODE1_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk; + tmp |= RTC_MODE1_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.CTRLB.reg; +} + +static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_GP0EN; + tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_RTCOUT; + tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DMAEN; + tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk; + tmp |= RTC_MODE2_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk; + tmp |= RTC_MODE2_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.CTRLB.reg; +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO0; + tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO1; + tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO2; + tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO3; + tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO4; + tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO5; + tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO6; + tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO7; + tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_OVFEO; + tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, + hri_rtcmode0_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.EVCTRL.reg; +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO0; + tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO1; + tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO2; + tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO3; + tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO4; + tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO5; + tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO6; + tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO7; + tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_OVFEO; + tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, + hri_rtcmode1_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.EVCTRL.reg; +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO0; + tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO1; + tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO2; + tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO3; + tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO4; + tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO5; + tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO6; + tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO7; + tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_OVFEO; + tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, + hri_rtcmode2_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.EVCTRL.reg; +} + +static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.DBGCTRL.reg; +} + +static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + return ((Rtc *)hw)->MODE0.FREQCORR.reg; +} + +static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; + tmp |= RTC_MODE0_COUNT_COUNT(data); + ((Rtc *)hw)->MODE0.COUNT.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.COUNT.reg; +} + +static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; + tmp |= RTC_MODE1_COUNT_COUNT(data); + ((Rtc *)hw)->MODE1.COUNT.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.COUNT.reg; +} + +static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; + tmp |= RTC_MODE2_CLOCK_SECOND(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; + tmp |= RTC_MODE2_CLOCK_MINUTE(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; + tmp |= RTC_MODE2_CLOCK_HOUR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; + tmp |= RTC_MODE2_CLOCK_DAY(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; + tmp |= RTC_MODE2_CLOCK_MONTH(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; + tmp |= RTC_MODE2_CLOCK_YEAR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.CLOCK.reg; +} + +static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= ~RTC_MODE1_PER_PER_Msk; + tmp |= RTC_MODE1_PER_PER(data); + ((Rtc *)hw)->MODE1.PER.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + return ((Rtc *)hw)->MODE1.PER.reg; +} + +static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= ~RTC_MODE0_COMP_COMP_Msk; + tmp |= RTC_MODE0_COMP_COMP(data); + ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + return ((Rtc *)hw)->MODE0.COMP[index].reg; +} + +static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= ~RTC_MODE1_COMP_COMP_Msk; + tmp |= RTC_MODE1_COMP_COMP(data); + ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + return ((Rtc *)hw)->MODE1.COMP[index].reg; +} + +static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= ~RTC_GP_GP_Msk; + tmp |= RTC_GP_GP(data); + ((Rtc *)hw)->MODE0.GP[index].reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); + return ((Rtc *)hw)->MODE0.GP[index].reg; +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL0; + tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL1; + tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL2; + tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL3; + tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL4; + tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC0; + tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC1; + tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC2; + tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC3; + tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC4; + tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; + tmp |= RTC_TAMPCTRL_IN0ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; + tmp |= RTC_TAMPCTRL_IN1ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; + tmp |= RTC_TAMPCTRL_IN2ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; + tmp |= RTC_TAMPCTRL_IN3ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; + tmp |= RTC_TAMPCTRL_IN4ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPCTRL.reg; +} + +static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID0; + tmp |= value << RTC_TAMPID_TAMPID0_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID1; + tmp |= value << RTC_TAMPID_TAMPID1_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID2; + tmp |= value << RTC_TAMPID_TAMPID2_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID3; + tmp |= value << RTC_TAMPID_TAMPID3_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID4; + tmp |= value << RTC_TAMPID_TAMPID4_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPEVT; + tmp |= value << RTC_TAMPID_TAMPEVT_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPID.reg; +} + +static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= ~RTC_BKUP_BKUP_Msk; + tmp |= RTC_BKUP_BKUP(data); + ((Rtc *)hw)->MODE0.BKUP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE0.BKUP[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_L22_H_INCLUDED */ +#endif /* _SAML22_RTC_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_sercom_l22.h b/watch-library/hardware/hri/hri_sercom_l22.h new file mode 100644 index 00000000..6d97ca8a --- /dev/null +++ b/watch-library/hardware/hri/hri_sercom_l22.h @@ -0,0 +1,7827 @@ +/** + * \file + * + * \brief SAM SERCOM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_SERCOM_COMPONENT_ +#ifndef _HRI_SERCOM_L22_H_INCLUDED_ +#define _HRI_SERCOM_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) +#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SERCOM_CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sercomi2cm_status_reg_t; +typedef uint16_t hri_sercomi2cs_status_reg_t; +typedef uint16_t hri_sercomspi_status_reg_t; +typedef uint16_t hri_sercomusart_baud_reg_t; +typedef uint16_t hri_sercomusart_data_reg_t; +typedef uint16_t hri_sercomusart_status_reg_t; +typedef uint32_t hri_sercomi2cm_addr_reg_t; +typedef uint32_t hri_sercomi2cm_baud_reg_t; +typedef uint32_t hri_sercomi2cm_ctrla_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; +typedef uint32_t hri_sercomi2cs_addr_reg_t; +typedef uint32_t hri_sercomi2cs_ctrla_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; +typedef uint32_t hri_sercomspi_addr_reg_t; +typedef uint32_t hri_sercomspi_ctrla_reg_t; +typedef uint32_t hri_sercomspi_ctrlb_reg_t; +typedef uint32_t hri_sercomspi_data_reg_t; +typedef uint32_t hri_sercomspi_syncbusy_reg_t; +typedef uint32_t hri_sercomusart_ctrla_reg_t; +typedef uint32_t hri_sercomusart_ctrlb_reg_t; +typedef uint32_t hri_sercomusart_ctrlc_reg_t; +typedef uint32_t hri_sercomusart_syncbusy_reg_t; +typedef uint8_t hri_sercomi2cm_data_reg_t; +typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; +typedef uint8_t hri_sercomi2cm_intenset_reg_t; +typedef uint8_t hri_sercomi2cm_intflag_reg_t; +typedef uint8_t hri_sercomi2cs_data_reg_t; +typedef uint8_t hri_sercomi2cs_intenset_reg_t; +typedef uint8_t hri_sercomi2cs_intflag_reg_t; +typedef uint8_t hri_sercomspi_baud_reg_t; +typedef uint8_t hri_sercomspi_dbgctrl_reg_t; +typedef uint8_t hri_sercomspi_intenset_reg_t; +typedef uint8_t hri_sercomspi_intflag_reg_t; +typedef uint8_t hri_sercomusart_dbgctrl_reg_t; +typedef uint8_t hri_sercomusart_intenset_reg_t; +typedef uint8_t hri_sercomusart_intflag_reg_t; +typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; +typedef uint8_t hri_sercomusart_rxpl_reg_t; + +static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTFLAG.reg; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cs_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTFLAG.reg; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; +} + +static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, + hri_sercomspi_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTFLAG.reg; +} + +static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = mask; +} + +static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, + hri_sercomusart_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTFLAG.reg; +} + +static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = mask; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, + hri_sercomi2cm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTENSET.reg; +} + +static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = data; + ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; +} + +static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = mask; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, + hri_sercomi2cs_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTENSET.reg; +} + +static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = data; + ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; +} + +static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; +} + +static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; + } +} + +static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; +} + +static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; + } +} + +static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; + } +} + +static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = mask; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, + hri_sercomspi_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTENSET.reg; +} + +static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = data; + ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; +} + +static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = mask; +} + +static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; +} + +static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + } +} + +static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; + } +} + +static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; + } +} + +static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENSET.reg = mask; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, + hri_sercomusart_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTENSET.reg; +} + +static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) +{ + ((Sercom *)hw)->USART.INTENSET.reg = data; + ((Sercom *)hw)->USART.INTENCLR.reg = ~data; +} + +static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cs_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, + hri_sercomspi_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, + hri_sercomusart_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const hw, + hri_sercomusart_rxerrcnt_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXERRCNT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXERRCNT.reg; +} + +static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CM_CTRLA_MODE(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CM_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; + tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CM.CTRLA.reg; +} + +static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CS_CTRLA_MODE(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CS_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + return ((Sercom *)hw)->I2CS.CTRLA.reg; +} + +static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_ENABLE; + tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_IBON; + tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPHA; + tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPOL; + tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DORD; + tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; + tmp |= SERCOM_SPI_CTRLA_MODE(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DOPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DIPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; + tmp |= SERCOM_SPI_CTRLA_FORM(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->SPI.CTRLA.reg; +} + +static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_ENABLE; + tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_IBON; + tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXINV; + tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXINV; + tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CMODE; + tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CPOL; + tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_DORD; + tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; + tmp |= SERCOM_USART_CTRLA_MODE(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPR(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; + tmp |= SERCOM_USART_CTRLA_TXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; + tmp |= SERCOM_USART_CTRLA_RXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPA(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; + tmp |= SERCOM_USART_CTRLA_FORM(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->USART.CTRLA.reg; +} + +static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_SMEN; + tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_QCEN; + tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CM_CTRLB_CMD(data); + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.CTRLB.reg; +} + +static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_SMEN; + tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_GCMD; + tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; + tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; + tmp |= SERCOM_I2CS_CTRLB_AMODE(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CS_CTRLB_CMD(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLB.reg; +} + +static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; + tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_SSDE; + tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_MSSEN; + tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_RXEN; + tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; + tmp |= SERCOM_SPI_CTRLB_AMODE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SBMODE; + tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_COLDEN; + tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SFDE; + tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_ENC; + tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_PMODE; + tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_TXEN; + tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_RXEN; + tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_USART_CTRLB_CHSIZE(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_INACK; + tmp |= value << SERCOM_USART_CTRLC_INACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_DSNACK; + tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; + tmp |= SERCOM_USART_CTRLC_GTIME(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk; + tmp |= SERCOM_USART_CTRLC_MAXITER(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLC.reg; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.BAUD.reg; +} + +static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; + tmp |= SERCOM_SPI_BAUD_BAUD(data); + ((Sercom *)hw)->SPI.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; + tmp |= SERCOM_USART_RXPL_RXPL(data); + ((Sercom *)hw)->USART.RXPL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXPL.reg; +} + +static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LENEN; + tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_HS; + tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CM_ADDR_ADDR(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; + tmp |= SERCOM_I2CM_ADDR_LEN(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.ADDR.reg; +} + +static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_GENCEN; + tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDR(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.ADDR.reg; +} + +static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; + tmp |= SERCOM_SPI_ADDR_ADDR(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.ADDR.reg; +} + +static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; + tmp |= SERCOM_I2CM_DATA_DATA(data); + ((Sercom *)hw)->I2CM.DATA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint8_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.DATA.reg; +} + +static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; + tmp |= SERCOM_I2CS_DATA_DATA(data); + ((Sercom *)hw)->I2CS.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.DATA.reg; +} + +static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, + hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= ~SERCOM_SPI_DATA_DATA_Msk; + tmp |= SERCOM_SPI_DATA_DATA(data); + ((Sercom *)hw)->SPI.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DATA.reg; +} + +static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= ~SERCOM_USART_DATA_DATA_Msk; + tmp |= SERCOM_USART_DATA_DATA(data); + ((Sercom *)hw)->USART.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DATA.reg; +} + +static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, + hri_sercomi2cm_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DBGCTRL.reg; +} + +static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, + hri_sercomspi_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DBGCTRL.reg; +} + +static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, + hri_sercomusart_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DBGCTRL.reg; +} + +static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, + hri_sercomi2cs_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.STATUS.reg; +} + +static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, + hri_sercomspi_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.STATUS.reg; +} + +static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, + hri_sercomusart_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSERR; + tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; + tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_RXNACK; + tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; + tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; + tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LENERR; + tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; + tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg |= mask; +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.STATUS.reg; +} + +static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + ((Sercom *)hw)->I2CM.STATUS.reg = data; +} + +static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; +} + +static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SERCOM_L22_H_INCLUDED */ +#endif /* _SAML22_SERCOM_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_slcd_l22.h b/watch-library/hardware/hri/hri_slcd_l22.h new file mode 100644 index 00000000..89fde269 --- /dev/null +++ b/watch-library/hardware/hri/hri_slcd_l22.h @@ -0,0 +1,5440 @@ +/** + * \file + * + * \brief SAM SLCD + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_SLCD_COMPONENT_ +#ifndef _HRI_SLCD_L22_H_INCLUDED_ +#define _HRI_SLCD_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SLCD_CRITICAL_SECTIONS) +#define SLCD_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SLCD_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SLCD_CRITICAL_SECTION_ENTER() +#define SLCD_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_slcd_cmindex_reg_t; +typedef uint16_t hri_slcd_ctrlb_reg_t; +typedef uint16_t hri_slcd_ctrlc_reg_t; +typedef uint32_t hri_slcd_acmcfg_reg_t; +typedef uint32_t hri_slcd_bcfg_reg_t; +typedef uint32_t hri_slcd_cmdata_reg_t; +typedef uint32_t hri_slcd_cmdmask_reg_t; +typedef uint32_t hri_slcd_csrcfg_reg_t; +typedef uint32_t hri_slcd_ctrla_reg_t; +typedef uint32_t hri_slcd_isdata_reg_t; +typedef uint32_t hri_slcd_lpenh_reg_t; +typedef uint32_t hri_slcd_lpenl_reg_t; +typedef uint32_t hri_slcd_sdatah0_reg_t; +typedef uint32_t hri_slcd_sdatah1_reg_t; +typedef uint32_t hri_slcd_sdatah2_reg_t; +typedef uint32_t hri_slcd_sdatah3_reg_t; +typedef uint32_t hri_slcd_sdatah4_reg_t; +typedef uint32_t hri_slcd_sdatah5_reg_t; +typedef uint32_t hri_slcd_sdatah6_reg_t; +typedef uint32_t hri_slcd_sdatah7_reg_t; +typedef uint32_t hri_slcd_sdatal0_reg_t; +typedef uint32_t hri_slcd_sdatal1_reg_t; +typedef uint32_t hri_slcd_sdatal2_reg_t; +typedef uint32_t hri_slcd_sdatal3_reg_t; +typedef uint32_t hri_slcd_sdatal4_reg_t; +typedef uint32_t hri_slcd_sdatal5_reg_t; +typedef uint32_t hri_slcd_sdatal6_reg_t; +typedef uint32_t hri_slcd_sdatal7_reg_t; +typedef uint32_t hri_slcd_syncbusy_reg_t; +typedef uint8_t hri_slcd_abmcfg_reg_t; +typedef uint8_t hri_slcd_cmcfg_reg_t; +typedef uint8_t hri_slcd_ctrld_reg_t; +typedef uint8_t hri_slcd_evctrl_reg_t; +typedef uint8_t hri_slcd_fc0_reg_t; +typedef uint8_t hri_slcd_fc1_reg_t; +typedef uint8_t hri_slcd_fc2_reg_t; +typedef uint8_t hri_slcd_intenset_reg_t; +typedef uint8_t hri_slcd_intflag_reg_t; +typedef uint8_t hri_slcd_status_reg_t; + +static inline void hri_slcd_wait_for_sync(const void *const hw, hri_slcd_syncbusy_reg_t reg) +{ + while (((Slcd *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_slcd_is_syncing(const void *const hw, hri_slcd_syncbusy_reg_t reg) +{ + return ((Slcd *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_slcd_get_INTFLAG_FC0O_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC0O) >> SLCD_INTFLAG_FC0O_Pos; +} + +static inline void hri_slcd_clear_INTFLAG_FC0O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC0O; +} + +static inline bool hri_slcd_get_INTFLAG_FC1O_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC1O) >> SLCD_INTFLAG_FC1O_Pos; +} + +static inline void hri_slcd_clear_INTFLAG_FC1O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC1O; +} + +static inline bool hri_slcd_get_INTFLAG_FC2O_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC2O) >> SLCD_INTFLAG_FC2O_Pos; +} + +static inline void hri_slcd_clear_INTFLAG_FC2O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC2O; +} + +static inline bool hri_slcd_get_INTFLAG_VLCDRT_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDRT) >> SLCD_INTFLAG_VLCDRT_Pos; +} + +static inline void hri_slcd_clear_INTFLAG_VLCDRT_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDRT; +} + +static inline bool hri_slcd_get_INTFLAG_VLCDST_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDST) >> SLCD_INTFLAG_VLCDST_Pos; +} + +static inline void hri_slcd_clear_INTFLAG_VLCDST_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDST; +} + +static inline bool hri_slcd_get_INTFLAG_PRST_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_PRST) >> SLCD_INTFLAG_PRST_Pos; +} + +static inline void hri_slcd_clear_INTFLAG_PRST_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_PRST; +} + +static inline bool hri_slcd_get_interrupt_FC0O_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC0O) >> SLCD_INTFLAG_FC0O_Pos; +} + +static inline void hri_slcd_clear_interrupt_FC0O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC0O; +} + +static inline bool hri_slcd_get_interrupt_FC1O_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC1O) >> SLCD_INTFLAG_FC1O_Pos; +} + +static inline void hri_slcd_clear_interrupt_FC1O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC1O; +} + +static inline bool hri_slcd_get_interrupt_FC2O_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC2O) >> SLCD_INTFLAG_FC2O_Pos; +} + +static inline void hri_slcd_clear_interrupt_FC2O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC2O; +} + +static inline bool hri_slcd_get_interrupt_VLCDRT_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDRT) >> SLCD_INTFLAG_VLCDRT_Pos; +} + +static inline void hri_slcd_clear_interrupt_VLCDRT_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDRT; +} + +static inline bool hri_slcd_get_interrupt_VLCDST_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDST) >> SLCD_INTFLAG_VLCDST_Pos; +} + +static inline void hri_slcd_clear_interrupt_VLCDST_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDST; +} + +static inline bool hri_slcd_get_interrupt_PRST_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_PRST) >> SLCD_INTFLAG_PRST_Pos; +} + +static inline void hri_slcd_clear_interrupt_PRST_bit(const void *const hw) +{ + ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_PRST; +} + +static inline hri_slcd_intflag_reg_t hri_slcd_get_INTFLAG_reg(const void *const hw, hri_slcd_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_slcd_intflag_reg_t hri_slcd_read_INTFLAG_reg(const void *const hw) +{ + return ((Slcd *)hw)->INTFLAG.reg; +} + +static inline void hri_slcd_clear_INTFLAG_reg(const void *const hw, hri_slcd_intflag_reg_t mask) +{ + ((Slcd *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_slcd_set_INTEN_FC0O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC0O; +} + +static inline bool hri_slcd_get_INTEN_FC0O_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC0O) >> SLCD_INTENSET_FC0O_Pos; +} + +static inline void hri_slcd_write_INTEN_FC0O_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC0O; + } else { + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC0O; + } +} + +static inline void hri_slcd_clear_INTEN_FC0O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC0O; +} + +static inline void hri_slcd_set_INTEN_FC1O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC1O; +} + +static inline bool hri_slcd_get_INTEN_FC1O_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC1O) >> SLCD_INTENSET_FC1O_Pos; +} + +static inline void hri_slcd_write_INTEN_FC1O_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC1O; + } else { + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC1O; + } +} + +static inline void hri_slcd_clear_INTEN_FC1O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC1O; +} + +static inline void hri_slcd_set_INTEN_FC2O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC2O; +} + +static inline bool hri_slcd_get_INTEN_FC2O_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC2O) >> SLCD_INTENSET_FC2O_Pos; +} + +static inline void hri_slcd_write_INTEN_FC2O_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC2O; + } else { + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC2O; + } +} + +static inline void hri_slcd_clear_INTEN_FC2O_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC2O; +} + +static inline void hri_slcd_set_INTEN_VLCDRT_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDRT; +} + +static inline bool hri_slcd_get_INTEN_VLCDRT_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_VLCDRT) >> SLCD_INTENSET_VLCDRT_Pos; +} + +static inline void hri_slcd_write_INTEN_VLCDRT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDRT; + } else { + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDRT; + } +} + +static inline void hri_slcd_clear_INTEN_VLCDRT_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDRT; +} + +static inline void hri_slcd_set_INTEN_VLCDST_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDST; +} + +static inline bool hri_slcd_get_INTEN_VLCDST_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_VLCDST) >> SLCD_INTENSET_VLCDST_Pos; +} + +static inline void hri_slcd_write_INTEN_VLCDST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDST; + } else { + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDST; + } +} + +static inline void hri_slcd_clear_INTEN_VLCDST_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDST; +} + +static inline void hri_slcd_set_INTEN_PRST_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_PRST; +} + +static inline bool hri_slcd_get_INTEN_PRST_bit(const void *const hw) +{ + return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_PRST) >> SLCD_INTENSET_PRST_Pos; +} + +static inline void hri_slcd_write_INTEN_PRST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_PRST; + } else { + ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_PRST; + } +} + +static inline void hri_slcd_clear_INTEN_PRST_bit(const void *const hw) +{ + ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_PRST; +} + +static inline void hri_slcd_set_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask) +{ + ((Slcd *)hw)->INTENSET.reg = mask; +} + +static inline hri_slcd_intenset_reg_t hri_slcd_get_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_slcd_intenset_reg_t hri_slcd_read_INTEN_reg(const void *const hw) +{ + return ((Slcd *)hw)->INTENSET.reg; +} + +static inline void hri_slcd_write_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t data) +{ + ((Slcd *)hw)->INTENSET.reg = data; + ((Slcd *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_slcd_clear_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask) +{ + ((Slcd *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_slcd_get_STATUS_VLCDR_bit(const void *const hw) +{ + return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_VLCDR) >> SLCD_STATUS_VLCDR_Pos; +} + +static inline bool hri_slcd_get_STATUS_PRUN_bit(const void *const hw) +{ + return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_PRUN) >> SLCD_STATUS_PRUN_Pos; +} + +static inline bool hri_slcd_get_STATUS_VLCDS_bit(const void *const hw) +{ + return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_VLCDS) >> SLCD_STATUS_VLCDS_Pos; +} + +static inline bool hri_slcd_get_STATUS_CMWRBUSY_bit(const void *const hw) +{ + return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_CMWRBUSY) >> SLCD_STATUS_CMWRBUSY_Pos; +} + +static inline bool hri_slcd_get_STATUS_ACMBUSY_bit(const void *const hw) +{ + return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_ACMBUSY) >> SLCD_STATUS_ACMBUSY_Pos; +} + +static inline bool hri_slcd_get_STATUS_ABMBUSY_bit(const void *const hw) +{ + return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_ABMBUSY) >> SLCD_STATUS_ABMBUSY_Pos; +} + +static inline hri_slcd_status_reg_t hri_slcd_get_STATUS_reg(const void *const hw, hri_slcd_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_slcd_status_reg_t hri_slcd_read_STATUS_reg(const void *const hw) +{ + return ((Slcd *)hw)->STATUS.reg; +} + +static inline bool hri_slcd_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_SWRST) >> SLCD_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_slcd_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_ENABLE) >> SLCD_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_slcd_get_SYNCBUSY_CTRLD_bit(const void *const hw) +{ + return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_CTRLD) >> SLCD_SYNCBUSY_CTRLD_Pos; +} + +static inline hri_slcd_syncbusy_reg_t hri_slcd_get_SYNCBUSY_reg(const void *const hw, hri_slcd_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_slcd_syncbusy_reg_t hri_slcd_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Slcd *)hw)->SYNCBUSY.reg; +} + +static inline void hri_slcd_set_CTRLA_SWRST_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_SWRST; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_SWRST) >> SLCD_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_ENABLE; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_ENABLE) >> SLCD_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= ~SLCD_CTRLA_ENABLE; + tmp |= value << SLCD_CTRLA_ENABLE_Pos; + ((Slcd *)hw)->CTRLA.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_ENABLE; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_ENABLE; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLA_WMOD_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_WMOD; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLA_WMOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_WMOD) >> SLCD_CTRLA_WMOD_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLA_WMOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= ~SLCD_CTRLA_WMOD; + tmp |= value << SLCD_CTRLA_WMOD_Pos; + ((Slcd *)hw)->CTRLA.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_WMOD_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_WMOD; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_WMOD_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_WMOD; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_RUNSTDBY; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_RUNSTDBY) >> SLCD_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= ~SLCD_CTRLA_RUNSTDBY; + tmp |= value << SLCD_CTRLA_RUNSTDBY_Pos; + ((Slcd *)hw)->CTRLA.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_RUNSTDBY; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_RUNSTDBY; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLA_XVLCD_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_XVLCD; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLA_XVLCD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_XVLCD) >> SLCD_CTRLA_XVLCD_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLA_XVLCD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= ~SLCD_CTRLA_XVLCD; + tmp |= value << SLCD_CTRLA_XVLCD_Pos; + ((Slcd *)hw)->CTRLA.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_XVLCD_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_XVLCD; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_XVLCD_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_XVLCD; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_DUTY(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_DUTY(mask)) >> SLCD_CTRLA_DUTY_Pos; + return tmp; +} + +static inline void hri_slcd_write_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= ~SLCD_CTRLA_DUTY_Msk; + tmp |= SLCD_CTRLA_DUTY(data); + ((Slcd *)hw)->CTRLA.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_DUTY(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_DUTY(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_DUTY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_DUTY_Msk) >> SLCD_CTRLA_DUTY_Pos; + return tmp; +} + +static inline void hri_slcd_set_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_PRESC(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_PRESC(mask)) >> SLCD_CTRLA_PRESC_Pos; + return tmp; +} + +static inline void hri_slcd_write_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= ~SLCD_CTRLA_PRESC_Msk; + tmp |= SLCD_CTRLA_PRESC(data); + ((Slcd *)hw)->CTRLA.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_PRESC(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_PRESC(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_PRESC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_PRESC_Msk) >> SLCD_CTRLA_PRESC_Pos; + return tmp; +} + +static inline void hri_slcd_set_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_CKDIV(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_CKDIV(mask)) >> SLCD_CTRLA_CKDIV_Pos; + return tmp; +} + +static inline void hri_slcd_write_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= ~SLCD_CTRLA_CKDIV_Msk; + tmp |= SLCD_CTRLA_CKDIV(data); + ((Slcd *)hw)->CTRLA.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_CKDIV(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_CKDIV(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_CKDIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_CKDIV_Msk) >> SLCD_CTRLA_CKDIV_Pos; + return tmp; +} + +static inline void hri_slcd_set_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_BIAS(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_BIAS(mask)) >> SLCD_CTRLA_BIAS_Pos; + return tmp; +} + +static inline void hri_slcd_write_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= ~SLCD_CTRLA_BIAS_Msk; + tmp |= SLCD_CTRLA_BIAS(data); + ((Slcd *)hw)->CTRLA.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_BIAS(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_BIAS(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_BIAS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_BIAS_Msk) >> SLCD_CTRLA_BIAS_Pos; + return tmp; +} + +static inline void hri_slcd_set_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_PRF(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_PRF(mask)) >> SLCD_CTRLA_PRF_Pos; + return tmp; +} + +static inline void hri_slcd_write_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= ~SLCD_CTRLA_PRF_Msk; + tmp |= SLCD_CTRLA_PRF(data); + ((Slcd *)hw)->CTRLA.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_PRF(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_PRF(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_PRF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_PRF_Msk) >> SLCD_CTRLA_PRF_Pos; + return tmp; +} + +static inline void hri_slcd_set_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_DMFCS(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_DMFCS(mask)) >> SLCD_CTRLA_DMFCS_Pos; + return tmp; +} + +static inline void hri_slcd_write_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= ~SLCD_CTRLA_DMFCS_Msk; + tmp |= SLCD_CTRLA_DMFCS(data); + ((Slcd *)hw)->CTRLA.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_DMFCS(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_DMFCS(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_DMFCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_DMFCS_Msk) >> SLCD_CTRLA_DMFCS_Pos; + return tmp; +} + +static inline void hri_slcd_set_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_RRF(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_RRF(mask)) >> SLCD_CTRLA_RRF_Pos; + return tmp; +} + +static inline void hri_slcd_write_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= ~SLCD_CTRLA_RRF_Msk; + tmp |= SLCD_CTRLA_RRF(data); + ((Slcd *)hw)->CTRLA.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_RRF(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_RRF(mask); + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_RRF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp = (tmp & SLCD_CTRLA_RRF_Msk) >> SLCD_CTRLA_RRF_Pos; + return tmp; +} + +static inline void hri_slcd_set_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg |= mask; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); + tmp = ((Slcd *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg = data; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg &= ~mask; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLA.reg ^= mask; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_reg(const void *const hw) +{ + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); + return ((Slcd *)hw)->CTRLA.reg; +} + +static inline void hri_slcd_set_CTRLB_BBEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_BBEN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLB_BBEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLB.reg; + tmp = (tmp & SLCD_CTRLB_BBEN) >> SLCD_CTRLB_BBEN_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLB_BBEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLB.reg; + tmp &= ~SLCD_CTRLB_BBEN; + tmp |= value << SLCD_CTRLB_BBEN_Pos; + ((Slcd *)hw)->CTRLB.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLB_BBEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_BBEN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLB_BBEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_BBEN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLB_LREN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_LREN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLB_LREN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLB.reg; + tmp = (tmp & SLCD_CTRLB_LREN) >> SLCD_CTRLB_LREN_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLB_LREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLB.reg; + tmp &= ~SLCD_CTRLB_LREN; + tmp |= value << SLCD_CTRLB_LREN_Pos; + ((Slcd *)hw)->CTRLB.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLB_LREN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_LREN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLB_LREN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_LREN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_BBD(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLB.reg; + tmp = (tmp & SLCD_CTRLB_BBD(mask)) >> SLCD_CTRLB_BBD_Pos; + return tmp; +} + +static inline void hri_slcd_write_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t data) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLB.reg; + tmp &= ~SLCD_CTRLB_BBD_Msk; + tmp |= SLCD_CTRLB_BBD(data); + ((Slcd *)hw)->CTRLB.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_BBD(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_BBD(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_BBD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLB.reg; + tmp = (tmp & SLCD_CTRLB_BBD_Msk) >> SLCD_CTRLB_BBD_Pos; + return tmp; +} + +static inline void hri_slcd_set_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_LRD(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLB.reg; + tmp = (tmp & SLCD_CTRLB_LRD(mask)) >> SLCD_CTRLB_LRD_Pos; + return tmp; +} + +static inline void hri_slcd_write_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t data) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLB.reg; + tmp &= ~SLCD_CTRLB_LRD_Msk; + tmp |= SLCD_CTRLB_LRD(data); + ((Slcd *)hw)->CTRLB.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_LRD(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_LRD(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_LRD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLB.reg; + tmp = (tmp & SLCD_CTRLB_LRD_Msk) >> SLCD_CTRLB_LRD_Pos; + return tmp; +} + +static inline void hri_slcd_set_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLB.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_reg(const void *const hw) +{ + return ((Slcd *)hw)->CTRLB.reg; +} + +static inline void hri_slcd_set_CTRLC_CLEAR_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_CLEAR; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLC_CLEAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp = (tmp & SLCD_CTRLC_CLEAR) >> SLCD_CTRLC_CLEAR_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLC_CLEAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp &= ~SLCD_CTRLC_CLEAR; + tmp |= value << SLCD_CTRLC_CLEAR_Pos; + ((Slcd *)hw)->CTRLC.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLC_CLEAR_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_CLEAR; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLC_CLEAR_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_CLEAR; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLC_LOCK_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_LOCK; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLC_LOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp = (tmp & SLCD_CTRLC_LOCK) >> SLCD_CTRLC_LOCK_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLC_LOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp &= ~SLCD_CTRLC_LOCK; + tmp |= value << SLCD_CTRLC_LOCK_Pos; + ((Slcd *)hw)->CTRLC.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLC_LOCK_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_LOCK; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLC_LOCK_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_LOCK; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLC_ABMEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_ABMEN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLC_ABMEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp = (tmp & SLCD_CTRLC_ABMEN) >> SLCD_CTRLC_ABMEN_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLC_ABMEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp &= ~SLCD_CTRLC_ABMEN; + tmp |= value << SLCD_CTRLC_ABMEN_Pos; + ((Slcd *)hw)->CTRLC.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLC_ABMEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_ABMEN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLC_ABMEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_ABMEN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLC_ACMEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_ACMEN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLC_ACMEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp = (tmp & SLCD_CTRLC_ACMEN) >> SLCD_CTRLC_ACMEN_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLC_ACMEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp &= ~SLCD_CTRLC_ACMEN; + tmp |= value << SLCD_CTRLC_ACMEN_Pos; + ((Slcd *)hw)->CTRLC.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLC_ACMEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_ACMEN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLC_ACMEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_ACMEN; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_CTST(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp = (tmp & SLCD_CTRLC_CTST(mask)) >> SLCD_CTRLC_CTST_Pos; + return tmp; +} + +static inline void hri_slcd_write_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t data) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp &= ~SLCD_CTRLC_CTST_Msk; + tmp |= SLCD_CTRLC_CTST(data); + ((Slcd *)hw)->CTRLC.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_CTST(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_CTST(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_CTST_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp = (tmp & SLCD_CTRLC_CTST_Msk) >> SLCD_CTRLC_CTST_Pos; + return tmp; +} + +static inline void hri_slcd_set_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_LPPM(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp = (tmp & SLCD_CTRLC_LPPM(mask)) >> SLCD_CTRLC_LPPM_Pos; + return tmp; +} + +static inline void hri_slcd_write_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t data) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp &= ~SLCD_CTRLC_LPPM_Msk; + tmp |= SLCD_CTRLC_LPPM(data); + ((Slcd *)hw)->CTRLC.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_LPPM(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_LPPM(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_LPPM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp = (tmp & SLCD_CTRLC_LPPM_Msk) >> SLCD_CTRLC_LPPM_Pos; + return tmp; +} + +static inline void hri_slcd_set_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLC.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_reg(const void *const hw) +{ + return ((Slcd *)hw)->CTRLC.reg; +} + +static inline void hri_slcd_set_CTRLD_BLANK_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_BLANK; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLD_BLANK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp = (tmp & SLCD_CTRLD_BLANK) >> SLCD_CTRLD_BLANK_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLD_BLANK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp &= ~SLCD_CTRLD_BLANK; + tmp |= value << SLCD_CTRLD_BLANK_Pos; + ((Slcd *)hw)->CTRLD.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLD_BLANK_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_BLANK; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLD_BLANK_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_BLANK; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLD_BLINK_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_BLINK; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLD_BLINK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp = (tmp & SLCD_CTRLD_BLINK) >> SLCD_CTRLD_BLINK_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLD_BLINK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp &= ~SLCD_CTRLD_BLINK; + tmp |= value << SLCD_CTRLD_BLINK_Pos; + ((Slcd *)hw)->CTRLD.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLD_BLINK_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_BLINK; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLD_BLINK_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_BLINK; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLD_CSREN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_CSREN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLD_CSREN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp = (tmp & SLCD_CTRLD_CSREN) >> SLCD_CTRLD_CSREN_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLD_CSREN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp &= ~SLCD_CTRLD_CSREN; + tmp |= value << SLCD_CTRLD_CSREN_Pos; + ((Slcd *)hw)->CTRLD.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLD_CSREN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_CSREN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLD_CSREN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_CSREN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLD_FC0EN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC0EN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLD_FC0EN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp = (tmp & SLCD_CTRLD_FC0EN) >> SLCD_CTRLD_FC0EN_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLD_FC0EN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp &= ~SLCD_CTRLD_FC0EN; + tmp |= value << SLCD_CTRLD_FC0EN_Pos; + ((Slcd *)hw)->CTRLD.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLD_FC0EN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC0EN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLD_FC0EN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC0EN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLD_FC1EN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC1EN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLD_FC1EN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp = (tmp & SLCD_CTRLD_FC1EN) >> SLCD_CTRLD_FC1EN_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLD_FC1EN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp &= ~SLCD_CTRLD_FC1EN; + tmp |= value << SLCD_CTRLD_FC1EN_Pos; + ((Slcd *)hw)->CTRLD.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLD_FC1EN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC1EN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLD_FC1EN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC1EN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLD_FC2EN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC2EN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLD_FC2EN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp = (tmp & SLCD_CTRLD_FC2EN) >> SLCD_CTRLD_FC2EN_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLD_FC2EN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp &= ~SLCD_CTRLD_FC2EN; + tmp |= value << SLCD_CTRLD_FC2EN_Pos; + ((Slcd *)hw)->CTRLD.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLD_FC2EN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC2EN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLD_FC2EN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC2EN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLD_DISPEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_DISPEN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CTRLD_DISPEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp = (tmp & SLCD_CTRLD_DISPEN) >> SLCD_CTRLD_DISPEN_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CTRLD_DISPEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp &= ~SLCD_CTRLD_DISPEN; + tmp |= value << SLCD_CTRLD_DISPEN_Pos; + ((Slcd *)hw)->CTRLD.reg = tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLD_DISPEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_DISPEN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLD_DISPEN_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_DISPEN; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg |= mask; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrld_reg_t hri_slcd_get_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask) +{ + uint8_t tmp; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + tmp = ((Slcd *)hw)->CTRLD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg = data; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg &= ~mask; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CTRLD.reg ^= mask; + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_ctrld_reg_t hri_slcd_read_CTRLD_reg(const void *const hw) +{ + hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); + return ((Slcd *)hw)->CTRLD.reg; +} + +static inline void hri_slcd_set_EVCTRL_FC0OEO_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC0OEO; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_EVCTRL_FC0OEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->EVCTRL.reg; + tmp = (tmp & SLCD_EVCTRL_FC0OEO) >> SLCD_EVCTRL_FC0OEO_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_EVCTRL_FC0OEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->EVCTRL.reg; + tmp &= ~SLCD_EVCTRL_FC0OEO; + tmp |= value << SLCD_EVCTRL_FC0OEO_Pos; + ((Slcd *)hw)->EVCTRL.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_EVCTRL_FC0OEO_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC0OEO; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_EVCTRL_FC0OEO_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC0OEO; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_EVCTRL_FC1OEO_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC1OEO; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_EVCTRL_FC1OEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->EVCTRL.reg; + tmp = (tmp & SLCD_EVCTRL_FC1OEO) >> SLCD_EVCTRL_FC1OEO_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_EVCTRL_FC1OEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->EVCTRL.reg; + tmp &= ~SLCD_EVCTRL_FC1OEO; + tmp |= value << SLCD_EVCTRL_FC1OEO_Pos; + ((Slcd *)hw)->EVCTRL.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_EVCTRL_FC1OEO_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC1OEO; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_EVCTRL_FC1OEO_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC1OEO; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_EVCTRL_FC2OEO_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC2OEO; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_EVCTRL_FC2OEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->EVCTRL.reg; + tmp = (tmp & SLCD_EVCTRL_FC2OEO) >> SLCD_EVCTRL_FC2OEO_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_EVCTRL_FC2OEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->EVCTRL.reg; + tmp &= ~SLCD_EVCTRL_FC2OEO; + tmp |= value << SLCD_EVCTRL_FC2OEO_Pos; + ((Slcd *)hw)->EVCTRL.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_EVCTRL_FC2OEO_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC2OEO; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_EVCTRL_FC2OEO_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC2OEO; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_evctrl_reg_t hri_slcd_get_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->EVCTRL.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_evctrl_reg_t hri_slcd_read_EVCTRL_reg(const void *const hw) +{ + return ((Slcd *)hw)->EVCTRL.reg; +} + +static inline void hri_slcd_set_FC0_PB_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC0.reg |= SLCD_FC0_PB; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_FC0_PB_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC0.reg; + tmp = (tmp & SLCD_FC0_PB) >> SLCD_FC0_PB_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_FC0_PB_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->FC0.reg; + tmp &= ~SLCD_FC0_PB; + tmp |= value << SLCD_FC0_PB_Pos; + ((Slcd *)hw)->FC0.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_FC0_PB_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC0.reg &= ~SLCD_FC0_PB; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_FC0_PB_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC0.reg ^= SLCD_FC0_PB; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC0.reg |= SLCD_FC0_OVF(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc0_reg_t hri_slcd_get_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC0.reg; + tmp = (tmp & SLCD_FC0_OVF(mask)) >> SLCD_FC0_OVF_Pos; + return tmp; +} + +static inline void hri_slcd_write_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t data) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->FC0.reg; + tmp &= ~SLCD_FC0_OVF_Msk; + tmp |= SLCD_FC0_OVF(data); + ((Slcd *)hw)->FC0.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC0.reg &= ~SLCD_FC0_OVF(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC0.reg ^= SLCD_FC0_OVF(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc0_reg_t hri_slcd_read_FC0_OVF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC0.reg; + tmp = (tmp & SLCD_FC0_OVF_Msk) >> SLCD_FC0_OVF_Pos; + return tmp; +} + +static inline void hri_slcd_set_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC0.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc0_reg_t hri_slcd_get_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC0.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC0.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC0.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc0_reg_t hri_slcd_read_FC0_reg(const void *const hw) +{ + return ((Slcd *)hw)->FC0.reg; +} + +static inline void hri_slcd_set_FC1_PB_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC1.reg |= SLCD_FC1_PB; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_FC1_PB_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC1.reg; + tmp = (tmp & SLCD_FC1_PB) >> SLCD_FC1_PB_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_FC1_PB_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->FC1.reg; + tmp &= ~SLCD_FC1_PB; + tmp |= value << SLCD_FC1_PB_Pos; + ((Slcd *)hw)->FC1.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_FC1_PB_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC1.reg &= ~SLCD_FC1_PB; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_FC1_PB_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC1.reg ^= SLCD_FC1_PB; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC1.reg |= SLCD_FC1_OVF(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc1_reg_t hri_slcd_get_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC1.reg; + tmp = (tmp & SLCD_FC1_OVF(mask)) >> SLCD_FC1_OVF_Pos; + return tmp; +} + +static inline void hri_slcd_write_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t data) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->FC1.reg; + tmp &= ~SLCD_FC1_OVF_Msk; + tmp |= SLCD_FC1_OVF(data); + ((Slcd *)hw)->FC1.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC1.reg &= ~SLCD_FC1_OVF(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC1.reg ^= SLCD_FC1_OVF(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc1_reg_t hri_slcd_read_FC1_OVF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC1.reg; + tmp = (tmp & SLCD_FC1_OVF_Msk) >> SLCD_FC1_OVF_Pos; + return tmp; +} + +static inline void hri_slcd_set_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC1.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc1_reg_t hri_slcd_get_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC1.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC1.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC1.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc1_reg_t hri_slcd_read_FC1_reg(const void *const hw) +{ + return ((Slcd *)hw)->FC1.reg; +} + +static inline void hri_slcd_set_FC2_PB_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC2.reg |= SLCD_FC2_PB; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_FC2_PB_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC2.reg; + tmp = (tmp & SLCD_FC2_PB) >> SLCD_FC2_PB_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_FC2_PB_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->FC2.reg; + tmp &= ~SLCD_FC2_PB; + tmp |= value << SLCD_FC2_PB_Pos; + ((Slcd *)hw)->FC2.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_FC2_PB_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC2.reg &= ~SLCD_FC2_PB; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_FC2_PB_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC2.reg ^= SLCD_FC2_PB; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC2.reg |= SLCD_FC2_OVF(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc2_reg_t hri_slcd_get_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC2.reg; + tmp = (tmp & SLCD_FC2_OVF(mask)) >> SLCD_FC2_OVF_Pos; + return tmp; +} + +static inline void hri_slcd_write_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t data) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->FC2.reg; + tmp &= ~SLCD_FC2_OVF_Msk; + tmp |= SLCD_FC2_OVF(data); + ((Slcd *)hw)->FC2.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC2.reg &= ~SLCD_FC2_OVF(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC2.reg ^= SLCD_FC2_OVF(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc2_reg_t hri_slcd_read_FC2_OVF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC2.reg; + tmp = (tmp & SLCD_FC2_OVF_Msk) >> SLCD_FC2_OVF_Pos; + return tmp; +} + +static inline void hri_slcd_set_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC2.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc2_reg_t hri_slcd_get_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->FC2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC2.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC2.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->FC2.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_fc2_reg_t hri_slcd_read_FC2_reg(const void *const hw) +{ + return ((Slcd *)hw)->FC2.reg; +} + +static inline void hri_slcd_set_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENL.reg |= SLCD_LPENL_LPEN(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_lpenl_reg_t hri_slcd_get_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->LPENL.reg; + tmp = (tmp & SLCD_LPENL_LPEN(mask)) >> SLCD_LPENL_LPEN_Pos; + return tmp; +} + +static inline void hri_slcd_write_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->LPENL.reg; + tmp &= ~SLCD_LPENL_LPEN_Msk; + tmp |= SLCD_LPENL_LPEN(data); + ((Slcd *)hw)->LPENL.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENL.reg &= ~SLCD_LPENL_LPEN(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENL.reg ^= SLCD_LPENL_LPEN(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_lpenl_reg_t hri_slcd_read_LPENL_LPEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->LPENL.reg; + tmp = (tmp & SLCD_LPENL_LPEN_Msk) >> SLCD_LPENL_LPEN_Pos; + return tmp; +} + +static inline void hri_slcd_set_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENL.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_lpenl_reg_t hri_slcd_get_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->LPENL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENL.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENL.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENL.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_lpenl_reg_t hri_slcd_read_LPENL_reg(const void *const hw) +{ + return ((Slcd *)hw)->LPENL.reg; +} + +static inline void hri_slcd_set_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENH.reg |= SLCD_LPENH_LPEN(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_lpenh_reg_t hri_slcd_get_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->LPENH.reg; + tmp = (tmp & SLCD_LPENH_LPEN(mask)) >> SLCD_LPENH_LPEN_Pos; + return tmp; +} + +static inline void hri_slcd_write_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->LPENH.reg; + tmp &= ~SLCD_LPENH_LPEN_Msk; + tmp |= SLCD_LPENH_LPEN(data); + ((Slcd *)hw)->LPENH.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENH.reg &= ~SLCD_LPENH_LPEN(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENH.reg ^= SLCD_LPENH_LPEN(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_lpenh_reg_t hri_slcd_read_LPENH_LPEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->LPENH.reg; + tmp = (tmp & SLCD_LPENH_LPEN_Msk) >> SLCD_LPENH_LPEN_Pos; + return tmp; +} + +static inline void hri_slcd_set_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENH.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_lpenh_reg_t hri_slcd_get_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->LPENH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENH.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENH.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->LPENH.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_lpenh_reg_t hri_slcd_read_LPENH_reg(const void *const hw) +{ + return ((Slcd *)hw)->LPENH.reg; +} + +static inline void hri_slcd_set_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL0.reg |= SLCD_SDATAL0_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal0_reg_t hri_slcd_get_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL0.reg; + tmp = (tmp & SLCD_SDATAL0_SDATA(mask)) >> SLCD_SDATAL0_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAL0.reg; + tmp &= ~SLCD_SDATAL0_SDATA_Msk; + tmp |= SLCD_SDATAL0_SDATA(data); + ((Slcd *)hw)->SDATAL0.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL0.reg &= ~SLCD_SDATAL0_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL0.reg ^= SLCD_SDATAL0_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal0_reg_t hri_slcd_read_SDATAL0_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL0.reg; + tmp = (tmp & SLCD_SDATAL0_SDATA_Msk) >> SLCD_SDATAL0_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL0.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal0_reg_t hri_slcd_get_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL0.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL0.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL0.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal0_reg_t hri_slcd_read_SDATAL0_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAL0.reg; +} + +static inline void hri_slcd_set_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH0.reg |= SLCD_SDATAH0_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah0_reg_t hri_slcd_get_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH0.reg; + tmp = (tmp & SLCD_SDATAH0_SDATA(mask)) >> SLCD_SDATAH0_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAH0.reg; + tmp &= ~SLCD_SDATAH0_SDATA_Msk; + tmp |= SLCD_SDATAH0_SDATA(data); + ((Slcd *)hw)->SDATAH0.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH0.reg &= ~SLCD_SDATAH0_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH0.reg ^= SLCD_SDATAH0_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah0_reg_t hri_slcd_read_SDATAH0_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH0.reg; + tmp = (tmp & SLCD_SDATAH0_SDATA_Msk) >> SLCD_SDATAH0_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH0.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah0_reg_t hri_slcd_get_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH0.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH0.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH0.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah0_reg_t hri_slcd_read_SDATAH0_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAH0.reg; +} + +static inline void hri_slcd_set_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL1.reg |= SLCD_SDATAL1_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal1_reg_t hri_slcd_get_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL1.reg; + tmp = (tmp & SLCD_SDATAL1_SDATA(mask)) >> SLCD_SDATAL1_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAL1.reg; + tmp &= ~SLCD_SDATAL1_SDATA_Msk; + tmp |= SLCD_SDATAL1_SDATA(data); + ((Slcd *)hw)->SDATAL1.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL1.reg &= ~SLCD_SDATAL1_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL1.reg ^= SLCD_SDATAL1_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal1_reg_t hri_slcd_read_SDATAL1_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL1.reg; + tmp = (tmp & SLCD_SDATAL1_SDATA_Msk) >> SLCD_SDATAL1_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL1.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal1_reg_t hri_slcd_get_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL1.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL1.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL1.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal1_reg_t hri_slcd_read_SDATAL1_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAL1.reg; +} + +static inline void hri_slcd_set_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH1.reg |= SLCD_SDATAH1_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah1_reg_t hri_slcd_get_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH1.reg; + tmp = (tmp & SLCD_SDATAH1_SDATA(mask)) >> SLCD_SDATAH1_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAH1.reg; + tmp &= ~SLCD_SDATAH1_SDATA_Msk; + tmp |= SLCD_SDATAH1_SDATA(data); + ((Slcd *)hw)->SDATAH1.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH1.reg &= ~SLCD_SDATAH1_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH1.reg ^= SLCD_SDATAH1_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah1_reg_t hri_slcd_read_SDATAH1_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH1.reg; + tmp = (tmp & SLCD_SDATAH1_SDATA_Msk) >> SLCD_SDATAH1_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH1.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah1_reg_t hri_slcd_get_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH1.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH1.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH1.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah1_reg_t hri_slcd_read_SDATAH1_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAH1.reg; +} + +static inline void hri_slcd_set_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL2.reg |= SLCD_SDATAL2_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal2_reg_t hri_slcd_get_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL2.reg; + tmp = (tmp & SLCD_SDATAL2_SDATA(mask)) >> SLCD_SDATAL2_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAL2.reg; + tmp &= ~SLCD_SDATAL2_SDATA_Msk; + tmp |= SLCD_SDATAL2_SDATA(data); + ((Slcd *)hw)->SDATAL2.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL2.reg &= ~SLCD_SDATAL2_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL2.reg ^= SLCD_SDATAL2_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal2_reg_t hri_slcd_read_SDATAL2_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL2.reg; + tmp = (tmp & SLCD_SDATAL2_SDATA_Msk) >> SLCD_SDATAL2_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL2.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal2_reg_t hri_slcd_get_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL2.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL2.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL2.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal2_reg_t hri_slcd_read_SDATAL2_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAL2.reg; +} + +static inline void hri_slcd_set_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH2.reg |= SLCD_SDATAH2_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah2_reg_t hri_slcd_get_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH2.reg; + tmp = (tmp & SLCD_SDATAH2_SDATA(mask)) >> SLCD_SDATAH2_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAH2.reg; + tmp &= ~SLCD_SDATAH2_SDATA_Msk; + tmp |= SLCD_SDATAH2_SDATA(data); + ((Slcd *)hw)->SDATAH2.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH2.reg &= ~SLCD_SDATAH2_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH2.reg ^= SLCD_SDATAH2_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah2_reg_t hri_slcd_read_SDATAH2_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH2.reg; + tmp = (tmp & SLCD_SDATAH2_SDATA_Msk) >> SLCD_SDATAH2_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH2.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah2_reg_t hri_slcd_get_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH2.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH2.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH2.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah2_reg_t hri_slcd_read_SDATAH2_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAH2.reg; +} + +static inline void hri_slcd_set_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL3.reg |= SLCD_SDATAL3_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal3_reg_t hri_slcd_get_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL3.reg; + tmp = (tmp & SLCD_SDATAL3_SDATA(mask)) >> SLCD_SDATAL3_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAL3.reg; + tmp &= ~SLCD_SDATAL3_SDATA_Msk; + tmp |= SLCD_SDATAL3_SDATA(data); + ((Slcd *)hw)->SDATAL3.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL3.reg &= ~SLCD_SDATAL3_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL3.reg ^= SLCD_SDATAL3_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal3_reg_t hri_slcd_read_SDATAL3_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL3.reg; + tmp = (tmp & SLCD_SDATAL3_SDATA_Msk) >> SLCD_SDATAL3_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL3.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal3_reg_t hri_slcd_get_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL3.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL3.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL3.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL3.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal3_reg_t hri_slcd_read_SDATAL3_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAL3.reg; +} + +static inline void hri_slcd_set_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH3.reg |= SLCD_SDATAH3_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah3_reg_t hri_slcd_get_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH3.reg; + tmp = (tmp & SLCD_SDATAH3_SDATA(mask)) >> SLCD_SDATAH3_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAH3.reg; + tmp &= ~SLCD_SDATAH3_SDATA_Msk; + tmp |= SLCD_SDATAH3_SDATA(data); + ((Slcd *)hw)->SDATAH3.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH3.reg &= ~SLCD_SDATAH3_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH3.reg ^= SLCD_SDATAH3_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah3_reg_t hri_slcd_read_SDATAH3_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH3.reg; + tmp = (tmp & SLCD_SDATAH3_SDATA_Msk) >> SLCD_SDATAH3_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH3.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah3_reg_t hri_slcd_get_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH3.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH3.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH3.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH3.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah3_reg_t hri_slcd_read_SDATAH3_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAH3.reg; +} + +static inline void hri_slcd_set_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL4.reg |= SLCD_SDATAL4_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal4_reg_t hri_slcd_get_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL4.reg; + tmp = (tmp & SLCD_SDATAL4_SDATA(mask)) >> SLCD_SDATAL4_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAL4.reg; + tmp &= ~SLCD_SDATAL4_SDATA_Msk; + tmp |= SLCD_SDATAL4_SDATA(data); + ((Slcd *)hw)->SDATAL4.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL4.reg &= ~SLCD_SDATAL4_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL4.reg ^= SLCD_SDATAL4_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal4_reg_t hri_slcd_read_SDATAL4_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL4.reg; + tmp = (tmp & SLCD_SDATAL4_SDATA_Msk) >> SLCD_SDATAL4_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL4.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal4_reg_t hri_slcd_get_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL4.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL4.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL4.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL4.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal4_reg_t hri_slcd_read_SDATAL4_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAL4.reg; +} + +static inline void hri_slcd_set_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH4.reg |= SLCD_SDATAH4_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah4_reg_t hri_slcd_get_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH4.reg; + tmp = (tmp & SLCD_SDATAH4_SDATA(mask)) >> SLCD_SDATAH4_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAH4.reg; + tmp &= ~SLCD_SDATAH4_SDATA_Msk; + tmp |= SLCD_SDATAH4_SDATA(data); + ((Slcd *)hw)->SDATAH4.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH4.reg &= ~SLCD_SDATAH4_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH4.reg ^= SLCD_SDATAH4_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah4_reg_t hri_slcd_read_SDATAH4_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH4.reg; + tmp = (tmp & SLCD_SDATAH4_SDATA_Msk) >> SLCD_SDATAH4_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH4.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah4_reg_t hri_slcd_get_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH4.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH4.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH4.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH4.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah4_reg_t hri_slcd_read_SDATAH4_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAH4.reg; +} + +static inline void hri_slcd_set_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL5.reg |= SLCD_SDATAL5_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal5_reg_t hri_slcd_get_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL5.reg; + tmp = (tmp & SLCD_SDATAL5_SDATA(mask)) >> SLCD_SDATAL5_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAL5.reg; + tmp &= ~SLCD_SDATAL5_SDATA_Msk; + tmp |= SLCD_SDATAL5_SDATA(data); + ((Slcd *)hw)->SDATAL5.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL5.reg &= ~SLCD_SDATAL5_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL5.reg ^= SLCD_SDATAL5_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal5_reg_t hri_slcd_read_SDATAL5_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL5.reg; + tmp = (tmp & SLCD_SDATAL5_SDATA_Msk) >> SLCD_SDATAL5_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL5.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal5_reg_t hri_slcd_get_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL5.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL5.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL5.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL5.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal5_reg_t hri_slcd_read_SDATAL5_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAL5.reg; +} + +static inline void hri_slcd_set_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH5.reg |= SLCD_SDATAH5_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah5_reg_t hri_slcd_get_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH5.reg; + tmp = (tmp & SLCD_SDATAH5_SDATA(mask)) >> SLCD_SDATAH5_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAH5.reg; + tmp &= ~SLCD_SDATAH5_SDATA_Msk; + tmp |= SLCD_SDATAH5_SDATA(data); + ((Slcd *)hw)->SDATAH5.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH5.reg &= ~SLCD_SDATAH5_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH5.reg ^= SLCD_SDATAH5_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah5_reg_t hri_slcd_read_SDATAH5_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH5.reg; + tmp = (tmp & SLCD_SDATAH5_SDATA_Msk) >> SLCD_SDATAH5_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH5.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah5_reg_t hri_slcd_get_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH5.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH5.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH5.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH5.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah5_reg_t hri_slcd_read_SDATAH5_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAH5.reg; +} + +static inline void hri_slcd_set_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL6.reg |= SLCD_SDATAL6_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal6_reg_t hri_slcd_get_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL6.reg; + tmp = (tmp & SLCD_SDATAL6_SDATA(mask)) >> SLCD_SDATAL6_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAL6.reg; + tmp &= ~SLCD_SDATAL6_SDATA_Msk; + tmp |= SLCD_SDATAL6_SDATA(data); + ((Slcd *)hw)->SDATAL6.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL6.reg &= ~SLCD_SDATAL6_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL6.reg ^= SLCD_SDATAL6_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal6_reg_t hri_slcd_read_SDATAL6_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL6.reg; + tmp = (tmp & SLCD_SDATAL6_SDATA_Msk) >> SLCD_SDATAL6_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL6.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal6_reg_t hri_slcd_get_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL6.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL6.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL6.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL6.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal6_reg_t hri_slcd_read_SDATAL6_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAL6.reg; +} + +static inline void hri_slcd_set_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH6.reg |= SLCD_SDATAH6_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah6_reg_t hri_slcd_get_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH6.reg; + tmp = (tmp & SLCD_SDATAH6_SDATA(mask)) >> SLCD_SDATAH6_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAH6.reg; + tmp &= ~SLCD_SDATAH6_SDATA_Msk; + tmp |= SLCD_SDATAH6_SDATA(data); + ((Slcd *)hw)->SDATAH6.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH6.reg &= ~SLCD_SDATAH6_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH6.reg ^= SLCD_SDATAH6_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah6_reg_t hri_slcd_read_SDATAH6_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH6.reg; + tmp = (tmp & SLCD_SDATAH6_SDATA_Msk) >> SLCD_SDATAH6_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH6.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah6_reg_t hri_slcd_get_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH6.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH6.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH6.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH6.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah6_reg_t hri_slcd_read_SDATAH6_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAH6.reg; +} + +static inline void hri_slcd_set_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL7.reg |= SLCD_SDATAL7_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal7_reg_t hri_slcd_get_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL7.reg; + tmp = (tmp & SLCD_SDATAL7_SDATA(mask)) >> SLCD_SDATAL7_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAL7.reg; + tmp &= ~SLCD_SDATAL7_SDATA_Msk; + tmp |= SLCD_SDATAL7_SDATA(data); + ((Slcd *)hw)->SDATAL7.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL7.reg &= ~SLCD_SDATAL7_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL7.reg ^= SLCD_SDATAL7_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal7_reg_t hri_slcd_read_SDATAL7_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL7.reg; + tmp = (tmp & SLCD_SDATAL7_SDATA_Msk) >> SLCD_SDATAL7_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL7.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal7_reg_t hri_slcd_get_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAL7.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL7.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL7.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAL7.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatal7_reg_t hri_slcd_read_SDATAL7_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAL7.reg; +} + +static inline void hri_slcd_set_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH7.reg |= SLCD_SDATAH7_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah7_reg_t hri_slcd_get_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH7.reg; + tmp = (tmp & SLCD_SDATAH7_SDATA(mask)) >> SLCD_SDATAH7_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->SDATAH7.reg; + tmp &= ~SLCD_SDATAH7_SDATA_Msk; + tmp |= SLCD_SDATAH7_SDATA(data); + ((Slcd *)hw)->SDATAH7.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH7.reg &= ~SLCD_SDATAH7_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH7.reg ^= SLCD_SDATAH7_SDATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah7_reg_t hri_slcd_read_SDATAH7_SDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH7.reg; + tmp = (tmp & SLCD_SDATAH7_SDATA_Msk) >> SLCD_SDATAH7_SDATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH7.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah7_reg_t hri_slcd_get_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->SDATAH7.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH7.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH7.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->SDATAH7.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_sdatah7_reg_t hri_slcd_read_SDATAH7_reg(const void *const hw) +{ + return ((Slcd *)hw)->SDATAH7.reg; +} + +static inline void hri_slcd_set_BCFG_MODE_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_MODE; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_BCFG_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->BCFG.reg; + tmp = (tmp & SLCD_BCFG_MODE) >> SLCD_BCFG_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_BCFG_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->BCFG.reg; + tmp &= ~SLCD_BCFG_MODE; + tmp |= value << SLCD_BCFG_MODE_Pos; + ((Slcd *)hw)->BCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_BCFG_MODE_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_MODE; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_BCFG_MODE_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_MODE; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->BCFG.reg; + tmp = (tmp & SLCD_BCFG_FCS(mask)) >> SLCD_BCFG_FCS_Pos; + return tmp; +} + +static inline void hri_slcd_write_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->BCFG.reg; + tmp &= ~SLCD_BCFG_FCS_Msk; + tmp |= SLCD_BCFG_FCS(data); + ((Slcd *)hw)->BCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_FCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->BCFG.reg; + tmp = (tmp & SLCD_BCFG_FCS_Msk) >> SLCD_BCFG_FCS_Pos; + return tmp; +} + +static inline void hri_slcd_set_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_BSS0(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->BCFG.reg; + tmp = (tmp & SLCD_BCFG_BSS0(mask)) >> SLCD_BCFG_BSS0_Pos; + return tmp; +} + +static inline void hri_slcd_write_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->BCFG.reg; + tmp &= ~SLCD_BCFG_BSS0_Msk; + tmp |= SLCD_BCFG_BSS0(data); + ((Slcd *)hw)->BCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_BSS0(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_BSS0(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_BSS0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->BCFG.reg; + tmp = (tmp & SLCD_BCFG_BSS0_Msk) >> SLCD_BCFG_BSS0_Pos; + return tmp; +} + +static inline void hri_slcd_set_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_BSS1(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->BCFG.reg; + tmp = (tmp & SLCD_BCFG_BSS1(mask)) >> SLCD_BCFG_BSS1_Pos; + return tmp; +} + +static inline void hri_slcd_write_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->BCFG.reg; + tmp &= ~SLCD_BCFG_BSS1_Msk; + tmp |= SLCD_BCFG_BSS1(data); + ((Slcd *)hw)->BCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_BSS1(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_BSS1(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_BSS1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->BCFG.reg; + tmp = (tmp & SLCD_BCFG_BSS1_Msk) >> SLCD_BCFG_BSS1_Pos; + return tmp; +} + +static inline void hri_slcd_set_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->BCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->BCFG.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_reg(const void *const hw) +{ + return ((Slcd *)hw)->BCFG.reg; +} + +static inline void hri_slcd_set_CSRCFG_DIR_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_DIR; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CSRCFG_DIR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp = (tmp & SLCD_CSRCFG_DIR) >> SLCD_CSRCFG_DIR_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CSRCFG_DIR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp &= ~SLCD_CSRCFG_DIR; + tmp |= value << SLCD_CSRCFG_DIR_Pos; + ((Slcd *)hw)->CSRCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CSRCFG_DIR_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_DIR; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CSRCFG_DIR_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_DIR; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp = (tmp & SLCD_CSRCFG_FCS(mask)) >> SLCD_CSRCFG_FCS_Pos; + return tmp; +} + +static inline void hri_slcd_write_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp &= ~SLCD_CSRCFG_FCS_Msk; + tmp |= SLCD_CSRCFG_FCS(data); + ((Slcd *)hw)->CSRCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_FCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp = (tmp & SLCD_CSRCFG_FCS_Msk) >> SLCD_CSRCFG_FCS_Pos; + return tmp; +} + +static inline void hri_slcd_set_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_SIZE(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp = (tmp & SLCD_CSRCFG_SIZE(mask)) >> SLCD_CSRCFG_SIZE_Pos; + return tmp; +} + +static inline void hri_slcd_write_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp &= ~SLCD_CSRCFG_SIZE_Msk; + tmp |= SLCD_CSRCFG_SIZE(data); + ((Slcd *)hw)->CSRCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_SIZE(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_SIZE(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp = (tmp & SLCD_CSRCFG_SIZE_Msk) >> SLCD_CSRCFG_SIZE_Pos; + return tmp; +} + +static inline void hri_slcd_set_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_DATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp = (tmp & SLCD_CSRCFG_DATA(mask)) >> SLCD_CSRCFG_DATA_Pos; + return tmp; +} + +static inline void hri_slcd_write_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp &= ~SLCD_CSRCFG_DATA_Msk; + tmp |= SLCD_CSRCFG_DATA(data); + ((Slcd *)hw)->CSRCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_DATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_DATA(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp = (tmp & SLCD_CSRCFG_DATA_Msk) >> SLCD_CSRCFG_DATA_Pos; + return tmp; +} + +static inline void hri_slcd_set_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CSRCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CSRCFG.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_reg(const void *const hw) +{ + return ((Slcd *)hw)->CSRCFG.reg; +} + +static inline void hri_slcd_set_CMCFG_DEC_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMCFG.reg |= SLCD_CMCFG_DEC; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_CMCFG_DEC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->CMCFG.reg; + tmp = (tmp & SLCD_CMCFG_DEC) >> SLCD_CMCFG_DEC_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_CMCFG_DEC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CMCFG.reg; + tmp &= ~SLCD_CMCFG_DEC; + tmp |= value << SLCD_CMCFG_DEC_Pos; + ((Slcd *)hw)->CMCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CMCFG_DEC_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMCFG.reg &= ~SLCD_CMCFG_DEC; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CMCFG_DEC_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMCFG.reg ^= SLCD_CMCFG_DEC; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMCFG.reg |= SLCD_CMCFG_NSEG(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmcfg_reg_t hri_slcd_get_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->CMCFG.reg; + tmp = (tmp & SLCD_CMCFG_NSEG(mask)) >> SLCD_CMCFG_NSEG_Pos; + return tmp; +} + +static inline void hri_slcd_write_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t data) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CMCFG.reg; + tmp &= ~SLCD_CMCFG_NSEG_Msk; + tmp |= SLCD_CMCFG_NSEG(data); + ((Slcd *)hw)->CMCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMCFG.reg &= ~SLCD_CMCFG_NSEG(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMCFG.reg ^= SLCD_CMCFG_NSEG(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmcfg_reg_t hri_slcd_read_CMCFG_NSEG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->CMCFG.reg; + tmp = (tmp & SLCD_CMCFG_NSEG_Msk) >> SLCD_CMCFG_NSEG_Pos; + return tmp; +} + +static inline void hri_slcd_set_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMCFG.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmcfg_reg_t hri_slcd_get_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->CMCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMCFG.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMCFG.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMCFG.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmcfg_reg_t hri_slcd_read_CMCFG_reg(const void *const hw) +{ + return ((Slcd *)hw)->CMCFG.reg; +} + +static inline void hri_slcd_set_ACMCFG_MODE_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_MODE; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_slcd_get_ACMCFG_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_MODE) >> SLCD_ACMCFG_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_slcd_write_ACMCFG_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp &= ~SLCD_ACMCFG_MODE; + tmp |= value << SLCD_ACMCFG_MODE_Pos; + ((Slcd *)hw)->ACMCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_ACMCFG_MODE_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_MODE; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_ACMCFG_MODE_bit(const void *const hw) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_MODE; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_set_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NCOM(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_NCOM(mask)) >> SLCD_ACMCFG_NCOM_Pos; + return tmp; +} + +static inline void hri_slcd_write_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp &= ~SLCD_ACMCFG_NCOM_Msk; + tmp |= SLCD_ACMCFG_NCOM(data); + ((Slcd *)hw)->ACMCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NCOM(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NCOM(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NCOM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_NCOM_Msk) >> SLCD_ACMCFG_NCOM_Pos; + return tmp; +} + +static inline void hri_slcd_set_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NDIG(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_NDIG(mask)) >> SLCD_ACMCFG_NDIG_Pos; + return tmp; +} + +static inline void hri_slcd_write_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp &= ~SLCD_ACMCFG_NDIG_Msk; + tmp |= SLCD_ACMCFG_NDIG(data); + ((Slcd *)hw)->ACMCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NDIG(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NDIG(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NDIG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_NDIG_Msk) >> SLCD_ACMCFG_NDIG_Pos; + return tmp; +} + +static inline void hri_slcd_set_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_STEPS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_STEPS(mask)) >> SLCD_ACMCFG_STEPS_Pos; + return tmp; +} + +static inline void hri_slcd_write_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp &= ~SLCD_ACMCFG_STEPS_Msk; + tmp |= SLCD_ACMCFG_STEPS(data); + ((Slcd *)hw)->ACMCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_STEPS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_STEPS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_STEPS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_STEPS_Msk) >> SLCD_ACMCFG_STEPS_Pos; + return tmp; +} + +static inline void hri_slcd_set_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NDROW(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_NDROW(mask)) >> SLCD_ACMCFG_NDROW_Pos; + return tmp; +} + +static inline void hri_slcd_write_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp &= ~SLCD_ACMCFG_NDROW_Msk; + tmp |= SLCD_ACMCFG_NDROW(data); + ((Slcd *)hw)->ACMCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NDROW(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NDROW(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NDROW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_NDROW_Msk) >> SLCD_ACMCFG_NDROW_Pos; + return tmp; +} + +static inline void hri_slcd_set_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_STSEG(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_STSEG(mask)) >> SLCD_ACMCFG_STSEG_Pos; + return tmp; +} + +static inline void hri_slcd_write_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp &= ~SLCD_ACMCFG_STSEG_Msk; + tmp |= SLCD_ACMCFG_STSEG(data); + ((Slcd *)hw)->ACMCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_STSEG(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_STSEG(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_STSEG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_STSEG_Msk) >> SLCD_ACMCFG_STSEG_Pos; + return tmp; +} + +static inline void hri_slcd_set_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_FCS(mask)) >> SLCD_ACMCFG_FCS_Pos; + return tmp; +} + +static inline void hri_slcd_write_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp &= ~SLCD_ACMCFG_FCS_Msk; + tmp |= SLCD_ACMCFG_FCS(data); + ((Slcd *)hw)->ACMCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_FCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp = (tmp & SLCD_ACMCFG_FCS_Msk) >> SLCD_ACMCFG_FCS_Pos; + return tmp; +} + +static inline void hri_slcd_set_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->ACMCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ACMCFG.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_reg(const void *const hw) +{ + return ((Slcd *)hw)->ACMCFG.reg; +} + +static inline void hri_slcd_set_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ABMCFG.reg |= SLCD_ABMCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->ABMCFG.reg; + tmp = (tmp & SLCD_ABMCFG_FCS(mask)) >> SLCD_ABMCFG_FCS_Pos; + return tmp; +} + +static inline void hri_slcd_write_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t data) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->ABMCFG.reg; + tmp &= ~SLCD_ABMCFG_FCS_Msk; + tmp |= SLCD_ABMCFG_FCS(data); + ((Slcd *)hw)->ABMCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ABMCFG.reg &= ~SLCD_ABMCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ABMCFG.reg ^= SLCD_ABMCFG_FCS(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_FCS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->ABMCFG.reg; + tmp = (tmp & SLCD_ABMCFG_FCS_Msk) >> SLCD_ABMCFG_FCS_Pos; + return tmp; +} + +static inline void hri_slcd_set_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ABMCFG.reg |= SLCD_ABMCFG_SIZE(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->ABMCFG.reg; + tmp = (tmp & SLCD_ABMCFG_SIZE(mask)) >> SLCD_ABMCFG_SIZE_Pos; + return tmp; +} + +static inline void hri_slcd_write_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t data) +{ + uint8_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->ABMCFG.reg; + tmp &= ~SLCD_ABMCFG_SIZE_Msk; + tmp |= SLCD_ABMCFG_SIZE(data); + ((Slcd *)hw)->ABMCFG.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ABMCFG.reg &= ~SLCD_ABMCFG_SIZE(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ABMCFG.reg ^= SLCD_ABMCFG_SIZE(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_SIZE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->ABMCFG.reg; + tmp = (tmp & SLCD_ABMCFG_SIZE_Msk) >> SLCD_ABMCFG_SIZE_Pos; + return tmp; +} + +static inline void hri_slcd_set_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ABMCFG.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Slcd *)hw)->ABMCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ABMCFG.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ABMCFG.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ABMCFG.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_reg(const void *const hw) +{ + return ((Slcd *)hw)->ABMCFG.reg; +} + +static inline void hri_slcd_set_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMDMASK.reg |= SLCD_CMDMASK_SDMASK(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmdmask_reg_t hri_slcd_get_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CMDMASK.reg; + tmp = (tmp & SLCD_CMDMASK_SDMASK(mask)) >> SLCD_CMDMASK_SDMASK_Pos; + return tmp; +} + +static inline void hri_slcd_write_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t data) +{ + uint32_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CMDMASK.reg; + tmp &= ~SLCD_CMDMASK_SDMASK_Msk; + tmp |= SLCD_CMDMASK_SDMASK(data); + ((Slcd *)hw)->CMDMASK.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMDMASK.reg &= ~SLCD_CMDMASK_SDMASK(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMDMASK.reg ^= SLCD_CMDMASK_SDMASK(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmdmask_reg_t hri_slcd_read_CMDMASK_SDMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CMDMASK.reg; + tmp = (tmp & SLCD_CMDMASK_SDMASK_Msk) >> SLCD_CMDMASK_SDMASK_Pos; + return tmp; +} + +static inline void hri_slcd_set_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMDMASK.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmdmask_reg_t hri_slcd_get_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Slcd *)hw)->CMDMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMDMASK.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMDMASK.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMDMASK.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmdmask_reg_t hri_slcd_read_CMDMASK_reg(const void *const hw) +{ + return ((Slcd *)hw)->CMDMASK.reg; +} + +static inline void hri_slcd_set_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMINDEX.reg |= SLCD_CMINDEX_SINDEX(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CMINDEX.reg; + tmp = (tmp & SLCD_CMINDEX_SINDEX(mask)) >> SLCD_CMINDEX_SINDEX_Pos; + return tmp; +} + +static inline void hri_slcd_write_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t data) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CMINDEX.reg; + tmp &= ~SLCD_CMINDEX_SINDEX_Msk; + tmp |= SLCD_CMINDEX_SINDEX(data); + ((Slcd *)hw)->CMINDEX.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMINDEX.reg &= ~SLCD_CMINDEX_SINDEX(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMINDEX.reg ^= SLCD_CMINDEX_SINDEX(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_SINDEX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CMINDEX.reg; + tmp = (tmp & SLCD_CMINDEX_SINDEX_Msk) >> SLCD_CMINDEX_SINDEX_Pos; + return tmp; +} + +static inline void hri_slcd_set_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMINDEX.reg |= SLCD_CMINDEX_CINDEX(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CMINDEX.reg; + tmp = (tmp & SLCD_CMINDEX_CINDEX(mask)) >> SLCD_CMINDEX_CINDEX_Pos; + return tmp; +} + +static inline void hri_slcd_write_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t data) +{ + uint16_t tmp; + SLCD_CRITICAL_SECTION_ENTER(); + tmp = ((Slcd *)hw)->CMINDEX.reg; + tmp &= ~SLCD_CMINDEX_CINDEX_Msk; + tmp |= SLCD_CMINDEX_CINDEX(data); + ((Slcd *)hw)->CMINDEX.reg = tmp; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMINDEX.reg &= ~SLCD_CMINDEX_CINDEX(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMINDEX.reg ^= SLCD_CMINDEX_CINDEX(mask); + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_CINDEX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CMINDEX.reg; + tmp = (tmp & SLCD_CMINDEX_CINDEX_Msk) >> SLCD_CMINDEX_CINDEX_Pos; + return tmp; +} + +static inline void hri_slcd_set_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMINDEX.reg |= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + uint16_t tmp; + tmp = ((Slcd *)hw)->CMINDEX.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_slcd_write_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMINDEX.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_clear_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMINDEX.reg &= ~mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_toggle_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMINDEX.reg ^= mask; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_reg(const void *const hw) +{ + return ((Slcd *)hw)->CMINDEX.reg; +} + +static inline void hri_slcd_write_ISDATA_reg(const void *const hw, hri_slcd_isdata_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->ISDATA.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_slcd_write_CMDATA_reg(const void *const hw, hri_slcd_cmdata_reg_t data) +{ + SLCD_CRITICAL_SECTION_ENTER(); + ((Slcd *)hw)->CMDATA.reg = data; + SLCD_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SLCD_L22_H_INCLUDED */ +#endif /* _SAML22_SLCD_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_supc_l22.h b/watch-library/hardware/hri/hri_supc_l22.h new file mode 100644 index 00000000..9488ef0b --- /dev/null +++ b/watch-library/hardware/hri/hri_supc_l22.h @@ -0,0 +1,2532 @@ +/** + * \file + * + * \brief SAM SUPC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_SUPC_COMPONENT_ +#ifndef _HRI_SUPC_L22_H_INCLUDED_ +#define _HRI_SUPC_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) +#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SUPC_CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_supc_bbps_reg_t; +typedef uint32_t hri_supc_bkin_reg_t; +typedef uint32_t hri_supc_bkout_reg_t; +typedef uint32_t hri_supc_bod12_reg_t; +typedef uint32_t hri_supc_bod33_reg_t; +typedef uint32_t hri_supc_intenset_reg_t; +typedef uint32_t hri_supc_intflag_reg_t; +typedef uint32_t hri_supc_status_reg_t; +typedef uint32_t hri_supc_vref_reg_t; +typedef uint32_t hri_supc_vreg_reg_t; + +static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; +} + +static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; +} + +static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_INTFLAG_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY; +} + +static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; +} + +static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; +} + +static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; +} + +static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_interrupt_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY; +} + +static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) +{ + return ((Supc *)hw)->INTFLAG.reg; +} + +static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + ((Supc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; +} + +static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; +} + +static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; +} + +static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; +} + +static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; +} + +static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; +} + +static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; +} + +static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; +} + +static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; +} + +static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; +} + +static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; +} + +static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; +} + +static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; + } +} + +static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; +} + +static inline void hri_supc_set_INTEN_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY; +} + +static inline bool hri_supc_get_INTEN_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_APWSRDY) >> SUPC_INTENSET_APWSRDY_Pos; +} + +static inline void hri_supc_write_INTEN_APWSRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY; + } +} + +static inline void hri_supc_clear_INTEN_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY; +} + +static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; +} + +static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; +} + +static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; + } +} + +static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; +} + +static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENSET.reg = mask; +} + +static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) +{ + return ((Supc *)hw)->INTENSET.reg; +} + +static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) +{ + ((Supc *)hw)->INTENSET.reg = data; + ((Supc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_APWSRDY) >> SUPC_STATUS_APWSRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BBPS_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BBPS) >> SUPC_STATUS_BBPS_Pos; +} + +static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) +{ + return ((Supc *)hw)->STATUS.reg; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKIN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) +{ + return ((Supc *)hw)->BKIN.reg; +} + +static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ENABLE; + tmp |= value << SUPC_BOD33_ENABLE_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST) >> SUPC_BOD33_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_HYST; + tmp |= value << SUPC_BOD33_HYST_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_STDBYCFG; + tmp |= value << SUPC_BOD33_STDBYCFG_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNSTDBY; + tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNBKUP; + tmp |= value << SUPC_BOD33_RUNBKUP_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_ACTCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTCFG) >> SUPC_BOD33_ACTCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_ACTCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ACTCFG; + tmp |= value << SUPC_BOD33_ACTCFG_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_VMON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VMON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_VMON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VMON) >> SUPC_BOD33_VMON_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_VMON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_VMON; + tmp |= value << SUPC_BOD33_VMON_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_VMON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VMON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_VMON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VMON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ACTION_Msk; + tmp |= SUPC_BOD33_ACTION(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_PSEL_Msk; + tmp |= SUPC_BOD33_PSEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_LEVEL_Msk; + tmp |= SUPC_BOD33_LEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_BKUPLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_BKUPLEVEL(mask)) >> SUPC_BOD33_BKUPLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_BKUPLEVEL_Msk; + tmp |= SUPC_BOD33_BKUPLEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_BKUPLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_BKUPLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_BKUPLEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_BKUPLEVEL_Msk) >> SUPC_BOD33_BKUPLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD33.reg; +} + +static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ENABLE; + tmp |= value << SUPC_BOD12_ENABLE_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_HYST; + tmp |= value << SUPC_BOD12_HYST_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_STDBYCFG; + tmp |= value << SUPC_BOD12_STDBYCFG_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_RUNSTDBY; + tmp |= value << SUPC_BOD12_RUNSTDBY_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ACTCFG; + tmp |= value << SUPC_BOD12_ACTCFG_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ACTION_Msk; + tmp |= SUPC_BOD12_ACTION(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_PSEL_Msk; + tmp |= SUPC_BOD12_PSEL(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_LEVEL_Msk; + tmp |= SUPC_BOD12_LEVEL(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD12.reg; +} + +static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_ENABLE; + tmp |= value << SUPC_VREG_ENABLE_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_STDBYPL0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_STDBYPL0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_STDBYPL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_STDBYPL0) >> SUPC_VREG_STDBYPL0_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_STDBYPL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_STDBYPL0; + tmp |= value << SUPC_VREG_STDBYPL0_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_STDBYPL0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_STDBYPL0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_STDBYPL0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_STDBYPL0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_RUNSTDBY) >> SUPC_VREG_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_RUNSTDBY; + tmp |= value << SUPC_VREG_RUNSTDBY_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_LPEFF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_LPEFF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_LPEFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_LPEFF) >> SUPC_VREG_LPEFF_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_LPEFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_LPEFF; + tmp |= value << SUPC_VREG_LPEFF_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_LPEFF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_LPEFF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_LPEFF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_LPEFF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_SEL(mask)) >> SUPC_VREG_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_SEL_Msk; + tmp |= SUPC_VREG_SEL(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_SEL_Msk) >> SUPC_VREG_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSVSTEP(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSVSTEP(mask)) >> SUPC_VREG_VSVSTEP_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSVSTEP_Msk; + tmp |= SUPC_VREG_VSVSTEP(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSVSTEP(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSVSTEP(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSVSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSVSTEP_Msk) >> SUPC_VREG_VSVSTEP_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSPER_Msk; + tmp |= SUPC_VREG_VSPER(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) +{ + return ((Supc *)hw)->VREG.reg; +} + +static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSEN; + tmp |= value << SUPC_VREF_TSEN_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_VREFOE; + tmp |= value << SUPC_VREF_VREFOE_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSSEL; + tmp |= value << SUPC_VREF_TSSEL_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_RUNSTDBY; + tmp |= value << SUPC_VREF_RUNSTDBY_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_ONDEMAND; + tmp |= value << SUPC_VREF_ONDEMAND_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_SEL_Msk; + tmp |= SUPC_VREF_SEL(data); + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) +{ + return ((Supc *)hw)->VREF.reg; +} + +static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_WAKEEN; + tmp |= value << SUPC_BBPS_WAKEEN_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_PSOKEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_PSOKEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_PSOKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_PSOKEN) >> SUPC_BBPS_PSOKEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_PSOKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_PSOKEN; + tmp |= value << SUPC_BBPS_PSOKEN_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_PSOKEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_PSOKEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_PSOKEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_PSOKEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_CONF(mask)) >> SUPC_BBPS_CONF_Pos; + return tmp; +} + +static inline void hri_supc_write_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_CONF_Msk; + tmp |= SUPC_BBPS_CONF(data); + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_CONF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_CONF_Msk) >> SUPC_BBPS_CONF_Pos; + return tmp; +} + +static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) +{ + return ((Supc *)hw)->BBPS.reg; +} + +static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_EN_Msk; + tmp |= SUPC_BKOUT_EN(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_CLR_Msk; + tmp |= SUPC_BKOUT_CLR(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_SET_Msk; + tmp |= SUPC_BKOUT_SET(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_RTCTGL_Msk; + tmp |= SUPC_BKOUT_RTCTGL(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) +{ + return ((Supc *)hw)->BKOUT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SUPC_L22_H_INCLUDED */ +#endif /* _SAML22_SUPC_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_systemcontrol_l22.h b/watch-library/hardware/hri/hri_systemcontrol_l22.h new file mode 100644 index 00000000..9553d51a --- /dev/null +++ b/watch-library/hardware/hri/hri_systemcontrol_l22.h @@ -0,0 +1,498 @@ +/** + * \file + * + * \brief SAM SystemControl + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_SystemControl_COMPONENT_ +#ifndef _HRI_SystemControl_L22_H_INCLUDED_ +#define _HRI_SystemControl_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS) +#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SystemControl_CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systemcontrol_aircr_reg_t; +typedef uint32_t hri_systemcontrol_ccr_reg_t; +typedef uint32_t hri_systemcontrol_cpuid_reg_t; +typedef uint32_t hri_systemcontrol_dfsr_reg_t; +typedef uint32_t hri_systemcontrol_icsr_reg_t; +typedef uint32_t hri_systemcontrol_scr_reg_t; +typedef uint32_t hri_systemcontrol_shcsr_reg_t; +typedef uint32_t hri_systemcontrol_shpr2_reg_t; +typedef uint32_t hri_systemcontrol_shpr3_reg_t; +typedef uint32_t hri_systemcontrol_vtor_reg_t; + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4; +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20; +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CPUID.reg; +} + +static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw) +{ + return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_UNALIGN_TRP) >> 3; +} + +static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw) +{ + return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_STKALIGN) >> 9; +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw, + hri_systemcontrol_ccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CCR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CCR.reg; +} + +static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw, + hri_systemcontrol_icsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->ICSR.reg; +} + +static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw, + hri_systemcontrol_vtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->VTOR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->VTOR.reg; +} + +static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw, + hri_systemcontrol_aircr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->AIRCR.reg; +} + +static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw, + hri_systemcontrol_scr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SCR.reg; +} + +static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw, + hri_systemcontrol_shpr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR2.reg; +} + +static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw, + hri_systemcontrol_shpr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR3.reg; +} + +static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const hw, + hri_systemcontrol_shcsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHCSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHCSR.reg; +} + +static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const hw, + hri_systemcontrol_dfsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->DFSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->DFSR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SystemControl_L22_H_INCLUDED */ +#endif /* _SAML22_SystemControl_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_systick_l22.h b/watch-library/hardware/hri/hri_systick_l22.h new file mode 100644 index 00000000..aa09233f --- /dev/null +++ b/watch-library/hardware/hri/hri_systick_l22.h @@ -0,0 +1,219 @@ +/** + * \file + * + * \brief SAM SysTick + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_SysTick_COMPONENT_ +#ifndef _HRI_SysTick_L22_H_INCLUDED_ +#define _HRI_SysTick_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SysTick_CRITICAL_SECTIONS) +#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SysTick_CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systick_calib_reg_t; +typedef uint32_t hri_systick_csr_reg_t; +typedef uint32_t hri_systick_cvr_reg_t; +typedef uint32_t hri_systick_rvr_reg_t; + +static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_SKEW) >> 30; +} + +static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_NOREF) >> 31; +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS(mask)) >> 0; +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS_Msk) >> 0; +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw) +{ + return ((Systick *)hw)->CALIB.reg; +} + +static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw) +{ + return ((Systick *)hw)->CSR.reg; +} + +static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->RVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw) +{ + return ((Systick *)hw)->RVR.reg; +} + +static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw) +{ + return ((Systick *)hw)->CVR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SysTick_L22_H_INCLUDED */ +#endif /* _SAML22_SysTick_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_tc_l22.h b/watch-library/hardware/hri/hri_tc_l22.h new file mode 100644 index 00000000..8fab128c --- /dev/null +++ b/watch-library/hardware/hri/hri_tc_l22.h @@ -0,0 +1,2899 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_TC_COMPONENT_ +#ifndef _HRI_TC_L22_H_INCLUDED_ +#define _HRI_TC_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tc_evctrl_reg_t; +typedef uint16_t hri_tccount16_cc_reg_t; +typedef uint16_t hri_tccount16_ccbuf_reg_t; +typedef uint16_t hri_tccount16_count_reg_t; +typedef uint32_t hri_tc_ctrla_reg_t; +typedef uint32_t hri_tc_syncbusy_reg_t; +typedef uint32_t hri_tccount32_cc_reg_t; +typedef uint32_t hri_tccount32_ccbuf_reg_t; +typedef uint32_t hri_tccount32_count_reg_t; +typedef uint8_t hri_tc_ctrlbset_reg_t; +typedef uint8_t hri_tc_dbgctrl_reg_t; +typedef uint8_t hri_tc_drvctrl_reg_t; +typedef uint8_t hri_tc_intenset_reg_t; +typedef uint8_t hri_tc_intflag_reg_t; +typedef uint8_t hri_tc_status_reg_t; +typedef uint8_t hri_tc_wave_reg_t; +typedef uint8_t hri_tccount8_cc_reg_t; +typedef uint8_t hri_tccount8_ccbuf_reg_t; +typedef uint8_t hri_tccount8_count_reg_t; +typedef uint8_t hri_tccount8_per_reg_t; +typedef uint8_t hri_tccount8_perbuf_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; +} + +static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTFLAG.reg; +} + +static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; +} + +static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; +} + +static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; + } +} + +static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; +} + +static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; +} + +static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; + } +} + +static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; +} + +static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; +} + +static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); +} + +static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); +} + +static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.CTRLBSET.reg; +} + +static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; +} + +static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; +} + +static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; +} + +static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; +} + +static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; + } +} + +static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; +} + +static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; +} + +static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; +} + +static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; + } +} + +static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; +} + +static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; +} + +static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; +} + +static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; + } +} + +static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; +} + +static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; +} + +static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; +} + +static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; + } +} + +static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; +} + +static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = mask; +} + +static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTENSET.reg; +} + +static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = data; + ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; +} + +static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; +} + +static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; +} + +static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ENABLE; + tmp |= value << TC_CTRLA_ENABLE_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_RUNSTDBY; + tmp |= value << TC_CTRLA_RUNSTDBY_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ONDEMAND; + tmp |= value << TC_CTRLA_ONDEMAND_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ALOCK; + tmp |= value << TC_CTRLA_ALOCK_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN0; + tmp |= value << TC_CTRLA_CAPTEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN1; + tmp |= value << TC_CTRLA_CAPTEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN0; + tmp |= value << TC_CTRLA_COPEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN1; + tmp |= value << TC_CTRLA_COPEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_MODE_Msk; + tmp |= TC_CTRLA_MODE(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCSYNC_Msk; + tmp |= TC_CTRLA_PRESCSYNC(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCALER_Msk; + tmp |= TC_CTRLA_PRESCALER(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + return ((Tc *)hw)->COUNT16.CTRLA.reg; +} + +static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCINV; + tmp |= value << TC_EVCTRL_TCINV_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCEI; + tmp |= value << TC_EVCTRL_TCEI_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_OVFEO; + tmp |= value << TC_EVCTRL_OVFEO_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO0; + tmp |= value << TC_EVCTRL_MCEO0_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO1; + tmp |= value << TC_EVCTRL_MCEO1_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_EVACT_Msk; + tmp |= TC_EVCTRL_EVACT(data); + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.EVCTRL.reg; +} + +static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= ~TC_WAVE_WAVEGEN_Msk; + tmp |= TC_WAVE_WAVEGEN(data); + ((Tc *)hw)->COUNT16.WAVE.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.WAVE.reg; +} + +static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN0; + tmp |= value << TC_DRVCTRL_INVEN0_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN1; + tmp |= value << TC_DRVCTRL_INVEN1_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DRVCTRL.reg; +} + +static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= ~TC_DBGCTRL_DBGRUN; + tmp |= value << TC_DBGCTRL_DBGRUN_Pos; + ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DBGCTRL.reg; +} + +static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; + tmp |= TC_COUNT8_COUNT_COUNT(data); + ((Tc *)hw)->COUNT8.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT8.COUNT.reg; +} + +static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; + tmp |= TC_COUNT16_COUNT_COUNT(data); + ((Tc *)hw)->COUNT16.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT16.COUNT.reg; +} + +static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; + tmp |= TC_COUNT32_COUNT_COUNT(data); + ((Tc *)hw)->COUNT32.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT32.COUNT.reg; +} + +static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= ~TC_COUNT8_PER_PER_Msk; + tmp |= TC_COUNT8_PER_PER(data); + ((Tc *)hw)->COUNT8.PER.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + return ((Tc *)hw)->COUNT8.PER.reg; +} + +static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= ~TC_COUNT8_CC_CC_Msk; + tmp |= TC_COUNT8_CC_CC(data); + ((Tc *)hw)->COUNT8.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT8.CC[index].reg; +} + +static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= ~TC_COUNT16_CC_CC_Msk; + tmp |= TC_COUNT16_CC_CC(data); + ((Tc *)hw)->COUNT16.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT16.CC[index].reg; +} + +static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= ~TC_COUNT32_CC_CC_Msk; + tmp |= TC_COUNT32_CC_CC(data); + ((Tc *)hw)->COUNT32.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT32.CC[index].reg; +} + +static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; + tmp |= TC_COUNT8_PERBUF_PERBUF(data); + ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.PERBUF.reg; +} + +static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT8_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.CCBUF[index].reg; +} + +static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT16_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.CCBUF[index].reg; +} + +static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT32_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT32.CCBUF[index].reg; +} + +static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; +} + +static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; +} + +static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) +#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) +#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) +#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) +#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) +#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) +#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) +#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) +#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) +#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) +#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) +#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) +#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) +#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) +#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) +#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) +#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) +#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) +#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) +#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) +#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) +#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) +#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) +#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_L22_H_INCLUDED */ +#endif /* _SAML22_TC_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_tcc_l22.h b/watch-library/hardware/hri/hri_tcc_l22.h new file mode 100644 index 00000000..c10442af --- /dev/null +++ b/watch-library/hardware/hri/hri_tcc_l22.h @@ -0,0 +1,9462 @@ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_TCC_COMPONENT_ +#ifndef _HRI_TCC_L22_H_INCLUDED_ +#define _HRI_TCC_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TCC_CRITICAL_SECTIONS) +#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TCC_CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tcc_patt_reg_t; +typedef uint16_t hri_tcc_pattbuf_reg_t; +typedef uint32_t hri_tcc_cc_reg_t; +typedef uint32_t hri_tcc_ccbuf_reg_t; +typedef uint32_t hri_tcc_count_reg_t; +typedef uint32_t hri_tcc_ctrla_reg_t; +typedef uint32_t hri_tcc_drvctrl_reg_t; +typedef uint32_t hri_tcc_evctrl_reg_t; +typedef uint32_t hri_tcc_fctrla_reg_t; +typedef uint32_t hri_tcc_fctrlb_reg_t; +typedef uint32_t hri_tcc_intenset_reg_t; +typedef uint32_t hri_tcc_intflag_reg_t; +typedef uint32_t hri_tcc_per_reg_t; +typedef uint32_t hri_tcc_perbuf_reg_t; +typedef uint32_t hri_tcc_status_reg_t; +typedef uint32_t hri_tcc_syncbusy_reg_t; +typedef uint32_t hri_tcc_wave_reg_t; +typedef uint32_t hri_tcc_wexctrl_reg_t; +typedef uint8_t hri_tcc_ctrlbset_reg_t; +typedef uint8_t hri_tcc_dbgctrl_reg_t; + +static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + while (((Tcc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + return ((Tcc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTFLAG.reg; +} + +static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + ((Tcc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; +} + +static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; +} + +static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; + } +} + +static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; +} + +static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); +} + +static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); +} + +static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLBSET.reg; +} + +static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = data; + ((Tcc *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; +} + +static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; +} + +static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; + } +} + +static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; +} + +static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; +} + +static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; +} + +static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; + } +} + +static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; +} + +static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; +} + +static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; +} + +static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; + } +} + +static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; +} + +static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; +} + +static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; +} + +static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; + } +} + +static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; +} + +static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; +} + +static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; +} + +static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; + } +} + +static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; +} + +static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; +} + +static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; +} + +static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; + } +} + +static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; +} + +static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; +} + +static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; +} + +static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; +} + +static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; +} + +static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; +} + +static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; +} + +static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; +} + +static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; +} + +static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; +} + +static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; +} + +static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; + } +} + +static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; +} + +static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; +} + +static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; +} + +static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; + } +} + +static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; +} + +static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; +} + +static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; +} + +static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; + } +} + +static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; +} + +static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; +} + +static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; +} + +static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; + } +} + +static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; +} + +static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENSET.reg = mask; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTENSET.reg; +} + +static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) +{ + ((Tcc *)hw)->INTENSET.reg = data; + ((Tcc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tcc *)hw)->SYNCBUSY.reg; +} + +static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ENABLE; + tmp |= value << TCC_CTRLA_ENABLE_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RUNSTDBY; + tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ALOCK; + tmp |= value << TCC_CTRLA_ALOCK_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_MSYNC; + tmp |= value << TCC_CTRLA_MSYNC_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_DMAOS; + tmp |= value << TCC_CTRLA_DMAOS_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN0; + tmp |= value << TCC_CTRLA_CPTEN0_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN1; + tmp |= value << TCC_CTRLA_CPTEN1_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN2; + tmp |= value << TCC_CTRLA_CPTEN2_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN3; + tmp |= value << TCC_CTRLA_CPTEN3_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RESOLUTION_Msk; + tmp |= TCC_CTRLA_RESOLUTION(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCALER_Msk; + tmp |= TCC_CTRLA_PRESCALER(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; + tmp |= TCC_CTRLA_PRESCSYNC(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + return ((Tcc *)hw)->CTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_KEEP; + tmp |= value << TCC_FCTRLA_KEEP_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_QUAL; + tmp |= value << TCC_FCTRLA_QUAL_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_RESTART; + tmp |= value << TCC_FCTRLA_RESTART_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKPRESC; + tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_SRC_Msk; + tmp |= TCC_FCTRLA_SRC(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANK_Msk; + tmp |= TCC_FCTRLA_BLANK(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_HALT_Msk; + tmp |= TCC_FCTRLA_HALT(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CHSEL_Msk; + tmp |= TCC_FCTRLA_CHSEL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CAPTURE_Msk; + tmp |= TCC_FCTRLA_CAPTURE(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; + tmp |= TCC_FCTRLA_BLANKVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; + tmp |= TCC_FCTRLA_FILTERVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_KEEP; + tmp |= value << TCC_FCTRLB_KEEP_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_QUAL; + tmp |= value << TCC_FCTRLB_QUAL_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_RESTART; + tmp |= value << TCC_FCTRLB_RESTART_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKPRESC; + tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_SRC_Msk; + tmp |= TCC_FCTRLB_SRC(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANK_Msk; + tmp |= TCC_FCTRLB_BLANK(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_HALT_Msk; + tmp |= TCC_FCTRLB_HALT(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CHSEL_Msk; + tmp |= TCC_FCTRLB_CHSEL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CAPTURE_Msk; + tmp |= TCC_FCTRLB_CAPTURE(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; + tmp |= TCC_FCTRLB_BLANKVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; + tmp |= TCC_FCTRLB_FILTERVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLB.reg; +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN0; + tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN1; + tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN2; + tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN3; + tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_OTMX_Msk; + tmp |= TCC_WEXCTRL_OTMX(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTLS_Msk; + tmp |= TCC_WEXCTRL_DTLS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTHS_Msk; + tmp |= TCC_WEXCTRL_DTHS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->WEXCTRL.reg; +} + +static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE0; + tmp |= value << TCC_DRVCTRL_NRE0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE1; + tmp |= value << TCC_DRVCTRL_NRE1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE2; + tmp |= value << TCC_DRVCTRL_NRE2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE3; + tmp |= value << TCC_DRVCTRL_NRE3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE4; + tmp |= value << TCC_DRVCTRL_NRE4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE5; + tmp |= value << TCC_DRVCTRL_NRE5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE6; + tmp |= value << TCC_DRVCTRL_NRE6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE7; + tmp |= value << TCC_DRVCTRL_NRE7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV0; + tmp |= value << TCC_DRVCTRL_NRV0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV1; + tmp |= value << TCC_DRVCTRL_NRV1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV2; + tmp |= value << TCC_DRVCTRL_NRV2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV3; + tmp |= value << TCC_DRVCTRL_NRV3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV4; + tmp |= value << TCC_DRVCTRL_NRV4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV5; + tmp |= value << TCC_DRVCTRL_NRV5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV6; + tmp |= value << TCC_DRVCTRL_NRV6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV7; + tmp |= value << TCC_DRVCTRL_NRV7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN0; + tmp |= value << TCC_DRVCTRL_INVEN0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN1; + tmp |= value << TCC_DRVCTRL_INVEN1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN2; + tmp |= value << TCC_DRVCTRL_INVEN2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN3; + tmp |= value << TCC_DRVCTRL_INVEN3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN4; + tmp |= value << TCC_DRVCTRL_INVEN4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN5; + tmp |= value << TCC_DRVCTRL_INVEN5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN6; + tmp |= value << TCC_DRVCTRL_INVEN6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN7; + tmp |= value << TCC_DRVCTRL_INVEN7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL0(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL1(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DRVCTRL.reg; +} + +static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_DBGRUN; + tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_FDDBD; + tmp |= value << TCC_DBGCTRL_FDDBD_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DBGCTRL.reg; +} + +static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_OVFEO; + tmp |= value << TCC_EVCTRL_OVFEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TRGEO; + tmp |= value << TCC_EVCTRL_TRGEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTEO; + tmp |= value << TCC_EVCTRL_CNTEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV0; + tmp |= value << TCC_EVCTRL_TCINV0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV1; + tmp |= value << TCC_EVCTRL_TCINV1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI0; + tmp |= value << TCC_EVCTRL_TCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI1; + tmp |= value << TCC_EVCTRL_TCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI0; + tmp |= value << TCC_EVCTRL_MCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI1; + tmp |= value << TCC_EVCTRL_MCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI2; + tmp |= value << TCC_EVCTRL_MCEI2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI3; + tmp |= value << TCC_EVCTRL_MCEI3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO0; + tmp |= value << TCC_EVCTRL_MCEO0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO1; + tmp |= value << TCC_EVCTRL_MCEO1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO2; + tmp |= value << TCC_EVCTRL_MCEO2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO3; + tmp |= value << TCC_EVCTRL_MCEO3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT0_Msk; + tmp |= TCC_EVCTRL_EVACT0(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT1_Msk; + tmp |= TCC_EVCTRL_EVACT1(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTSEL_Msk; + tmp |= TCC_EVCTRL_CNTSEL(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->EVCTRL.reg; +} + +static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE0; + tmp |= value << TCC_PATT_PGE0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE1; + tmp |= value << TCC_PATT_PGE1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE2; + tmp |= value << TCC_PATT_PGE2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE3; + tmp |= value << TCC_PATT_PGE3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE4; + tmp |= value << TCC_PATT_PGE4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE5; + tmp |= value << TCC_PATT_PGE5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE6; + tmp |= value << TCC_PATT_PGE6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE7; + tmp |= value << TCC_PATT_PGE7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV0; + tmp |= value << TCC_PATT_PGV0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV1; + tmp |= value << TCC_PATT_PGV1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV2; + tmp |= value << TCC_PATT_PGV2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV3; + tmp |= value << TCC_PATT_PGV3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV4; + tmp |= value << TCC_PATT_PGV4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV5; + tmp |= value << TCC_PATT_PGV5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV6; + tmp |= value << TCC_PATT_PGV6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV7; + tmp |= value << TCC_PATT_PGV7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + uint16_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->PATT.reg; +} + +static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CIPEREN; + tmp |= value << TCC_WAVE_CIPEREN_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN0; + tmp |= value << TCC_WAVE_CICCEN0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN1; + tmp |= value << TCC_WAVE_CICCEN1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN2; + tmp |= value << TCC_WAVE_CICCEN2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN3; + tmp |= value << TCC_WAVE_CICCEN3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL0; + tmp |= value << TCC_WAVE_POL0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL1; + tmp |= value << TCC_WAVE_POL1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL2; + tmp |= value << TCC_WAVE_POL2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL3; + tmp |= value << TCC_WAVE_POL3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP0; + tmp |= value << TCC_WAVE_SWAP0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP1; + tmp |= value << TCC_WAVE_SWAP1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP2; + tmp |= value << TCC_WAVE_SWAP2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP3; + tmp |= value << TCC_WAVE_SWAP3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_WAVEGEN_Msk; + tmp |= TCC_WAVE_WAVEGEN(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_RAMP_Msk; + tmp |= TCC_WAVE_RAMP(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->WAVE.reg; +} + +static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_DITHER_Msk; + tmp |= TCC_PER_DITH4_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_DITHER_Msk; + tmp |= TCC_PER_DITH5_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_DITHER_Msk; + tmp |= TCC_PER_DITH6_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_DITHER_Msk; + tmp |= TCC_CC_DITH4_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_DITHER_Msk; + tmp |= TCC_CC_DITH5_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_DITHER_Msk; + tmp |= TCC_CC_DITH6_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB0; + tmp |= value << TCC_PATTBUF_PGEB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB1; + tmp |= value << TCC_PATTBUF_PGEB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB2; + tmp |= value << TCC_PATTBUF_PGEB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB3; + tmp |= value << TCC_PATTBUF_PGEB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB4; + tmp |= value << TCC_PATTBUF_PGEB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB5; + tmp |= value << TCC_PATTBUF_PGEB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB6; + tmp |= value << TCC_PATTBUF_PGEB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB7; + tmp |= value << TCC_PATTBUF_PGEB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB0; + tmp |= value << TCC_PATTBUF_PGVB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB1; + tmp |= value << TCC_PATTBUF_PGVB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB2; + tmp |= value << TCC_PATTBUF_PGVB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB3; + tmp |= value << TCC_PATTBUF_PGVB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB4; + tmp |= value << TCC_PATTBUF_PGVB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB5; + tmp |= value << TCC_PATTBUF_PGVB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB6; + tmp |= value << TCC_PATTBUF_PGVB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB7; + tmp |= value << TCC_PATTBUF_PGVB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATTBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; +} + +static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; +} + +static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; +} + +static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TCC_L22_H_INCLUDED */ +#endif /* _SAML22_TCC_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_trng_l22.h b/watch-library/hardware/hri/hri_trng_l22.h new file mode 100644 index 00000000..8aad3aca --- /dev/null +++ b/watch-library/hardware/hri/hri_trng_l22.h @@ -0,0 +1,380 @@ +/** + * \file + * + * \brief SAM TRNG + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_TRNG_COMPONENT_ +#ifndef _HRI_TRNG_L22_H_INCLUDED_ +#define _HRI_TRNG_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) +#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TRNG_CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_trng_data_reg_t; +typedef uint8_t hri_trng_ctrla_reg_t; +typedef uint8_t hri_trng_evctrl_reg_t; +typedef uint8_t hri_trng_intenset_reg_t; +typedef uint8_t hri_trng_intflag_reg_t; + +static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) +{ + return ((Trng *)hw)->INTFLAG.reg; +} + +static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + ((Trng *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; +} + +static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; +} + +static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; + } else { + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; + } +} + +static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; +} + +static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENSET.reg = mask; +} + +static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) +{ + return ((Trng *)hw)->INTENSET.reg; +} + +static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) +{ + ((Trng *)hw)->INTENSET.reg = data; + ((Trng *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENCLR.reg = mask; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Trng *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) +{ + return ((Trng *)hw)->DATA.reg; +} + +static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_ENABLE; + tmp |= value << TRNG_CTRLA_ENABLE_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_RUNSTDBY; + tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) +{ + return ((Trng *)hw)->CTRLA.reg; +} + +static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= ~TRNG_EVCTRL_DATARDYEO; + tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; + ((Trng *)hw)->EVCTRL.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) +{ + return ((Trng *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TRNG_L22_H_INCLUDED */ +#endif /* _SAML22_TRNG_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_usb_l22.h b/watch-library/hardware/hri/hri_usb_l22.h new file mode 100644 index 00000000..57a9419d --- /dev/null +++ b/watch-library/hardware/hri/hri_usb_l22.h @@ -0,0 +1,4713 @@ +/** + * \file + * + * \brief SAM USB + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_USB_COMPONENT_ +#ifndef _HRI_USB_L22_H_INCLUDED_ +#define _HRI_USB_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_USB_CRITICAL_SECTIONS) +#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define USB_CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_usb_padcal_reg_t; +typedef uint16_t hri_usbdesc_bank_extreg_reg_t; +typedef uint16_t hri_usbdescriptordevice_extreg_reg_t; +typedef uint16_t hri_usbdevice_ctrlb_reg_t; +typedef uint16_t hri_usbdevice_epintsmry_reg_t; +typedef uint16_t hri_usbdevice_fnum_reg_t; +typedef uint16_t hri_usbdevice_intenset_reg_t; +typedef uint16_t hri_usbdevice_intflag_reg_t; +typedef uint32_t hri_usb_descadd_reg_t; +typedef uint32_t hri_usbdesc_bank_addr_reg_t; +typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; +typedef uint32_t hri_usbdescriptordevice_addr_reg_t; +typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t; +typedef uint8_t hri_usb_ctrla_reg_t; +typedef uint8_t hri_usb_fsmstatus_reg_t; +typedef uint8_t hri_usb_qosctrl_reg_t; +typedef uint8_t hri_usb_syncbusy_reg_t; +typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; +typedef uint8_t hri_usbdescriptordevice_status_bk_reg_t; +typedef uint8_t hri_usbdevice_dadd_reg_t; +typedef uint8_t hri_usbdevice_epcfg_reg_t; +typedef uint8_t hri_usbdevice_epintenset_reg_t; +typedef uint8_t hri_usbdevice_epintflag_reg_t; +typedef uint8_t hri_usbdevice_epstatus_reg_t; +typedef uint8_t hri_usbdevice_status_reg_t; +typedef uint8_t hri_usbendpoint_epcfg_reg_t; +typedef uint8_t hri_usbendpoint_epintenset_reg_t; +typedef uint8_t hri_usbendpoint_epintflag_reg_t; +typedef uint8_t hri_usbendpoint_epstatus_reg_t; + +static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbendpoint_epintflag_reg_t +hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintflag_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbendpoint_epstatus_reg_t +hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbendpoint_epintenset_reg_t +hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbdevice_epintflag_reg_t +hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbdevice_epintenset_reg_t +hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, + hri_usbdevice_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTFLAG.reg; +} + +static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; + } +} + +static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; + } +} + +static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; + } +} + +static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = mask; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, + hri_usbdevice_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTENSET.reg; +} + +static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = data; + ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; +} + +static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.STATUS.reg; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, + hri_usb_fsmstatus_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.FSMSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FSMSTATUS.reg; +} + +static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FNUM.reg; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, + hri_usbdevice_epintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; +} + +static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_SWRST; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= ~USB_CTRLA_ENABLE; + tmp |= value << USB_CTRLA_ENABLE_Pos; + ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= ~USB_CTRLA_RUNSTDBY; + tmp |= value << USB_CTRLA_RUNSTDBY_Pos; + ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= ~USB_CTRLA_MODE; + tmp |= value << USB_CTRLA_MODE_Pos; + ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg |= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg = data; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw) +{ + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + return ((Usb *)hw)->DEVICE.CTRLA.reg; +} + +static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_CQOS_Msk; + tmp |= USB_QOSCTRL_CQOS(data); + ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_DQOS_Msk; + tmp |= USB_QOSCTRL_DQOS(data); + ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.QOSCTRL.reg; +} + +static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_DETACH; + tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_UPRSM; + tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_NREPLY; + tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTJ; + tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTK; + tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; + tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_OPMODE2; + tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_GNAK; + tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; + tmp |= USB_DEVICE_CTRLB_SPDCONF(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; + tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.CTRLB.reg; +} + +static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_ADDEN; + tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, + hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_DADD_Msk; + tmp |= USB_DEVICE_DADD_DADD(data); + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DADD.reg; +} + +static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg |= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp &= ~USB_DESCADD_DESCADD_Msk; + tmp |= USB_DESCADD_DESCADD(data); + ((Usb *)hw)->DEVICE.DESCADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DESCADD.reg; +} + +static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSP_Msk; + tmp |= USB_PADCAL_TRANSP(data); + ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSN_Msk; + tmp |= USB_PADCAL_TRANSN(data); + ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= ~USB_PADCAL_TRIM_Msk; + tmp |= USB_PADCAL_TRIM(data); + ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.PADCAL.reg; +} + +static inline void hri_usbdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->EXTREG.reg; +} + +static inline bool hri_usbdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdescbank_get_STATUS_BK_reg(const void *const hw, + hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void +hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) + >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) +#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_USB_L22_H_INCLUDED */ +#endif /* _SAML22_USB_COMPONENT_ */ diff --git a/watch-library/hardware/hri/hri_wdt_l22.h b/watch-library/hardware/hri/hri_wdt_l22.h new file mode 100644 index 00000000..4794b254 --- /dev/null +++ b/watch-library/hardware/hri/hri_wdt_l22.h @@ -0,0 +1,617 @@ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML22_WDT_COMPONENT_ +#ifndef _HRI_WDT_L22_H_INCLUDED_ +#define _HRI_WDT_L22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_wdt_syncbusy_reg_t; +typedef uint8_t hri_wdt_clear_reg_t; +typedef uint8_t hri_wdt_config_reg_t; +typedef uint8_t hri_wdt_ctrla_reg_t; +typedef uint8_t hri_wdt_ewctrl_reg_t; +typedef uint8_t hri_wdt_intenset_reg_t; +typedef uint8_t hri_wdt_intflag_reg_t; + +static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + while (((Wdt *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + return ((Wdt *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTFLAG.reg; +} + +static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + ((Wdt *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; +} + +static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; +} + +static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; + } else { + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; + } +} + +static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; +} + +static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENSET.reg = mask; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTENSET.reg; +} + +static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) +{ + ((Wdt *)hw)->INTENSET.reg = data; + ((Wdt *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Wdt *)hw)->SYNCBUSY.reg; +} + +static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ENABLE; + tmp |= value << WDT_CTRLA_ENABLE_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_WEN; + tmp |= value << WDT_CTRLA_WEN_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ALWAYSON; + tmp |= value << WDT_CTRLA_ALWAYSON_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) +{ + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + return ((Wdt *)hw)->CTRLA.reg; +} + +static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_PER_Msk; + tmp |= WDT_CONFIG_PER(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_WINDOW_Msk; + tmp |= WDT_CONFIG_WINDOW(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) +{ + return ((Wdt *)hw)->CONFIG.reg; +} + +static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; + tmp |= WDT_EWCTRL_EWOFFSET(data); + ((Wdt *)hw)->EWCTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->EWCTRL.reg; +} + +static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CLEAR.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); + WDT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_L22_H_INCLUDED */ +#endif /* _SAML22_WDT_COMPONENT_ */ diff --git a/watch-library/hardware/hw/driver_init.c b/watch-library/hardware/hw/driver_init.c new file mode 100644 index 00000000..09723bec --- /dev/null +++ b/watch-library/hardware/hw/driver_init.c @@ -0,0 +1,96 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include + +struct slcd_sync_descriptor SEGMENT_LCD_0; + +struct i2c_m_sync_desc I2C_0; + +void I2C_0_PORT_init(void) { + + gpio_set_pin_pull_mode(SDA, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(SDA, PINMUX_PB30C_SERCOM1_PAD0); + + gpio_set_pin_pull_mode(SCL, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(SCL, PINMUX_PB31C_SERCOM1_PAD1); +} + +void I2C_0_CLOCK_init(void) { + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_mclk_set_APBCMASK_SERCOM1_bit(MCLK); +} + +void I2C_0_init(void) { + I2C_0_CLOCK_init(); + i2c_m_sync_init(&I2C_0, SERCOM1); + I2C_0_PORT_init(); +} + +void delay_driver_init(void) { + delay_init(SysTick); +} + +void SEGMENT_LCD_0_PORT_init(void) { + gpio_set_pin_function(SLCD0, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD1, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD2, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD3, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD4, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD5, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD6, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD7, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD8, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD9, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD10, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD11, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD12, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD13, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD14, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD15, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD16, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD17, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD18, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD19, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD20, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD21, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD22, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD23, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD24, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD25, GPIO_PIN_FUNCTION_B); + gpio_set_pin_function(SLCD26, GPIO_PIN_FUNCTION_B); +} + +/** + * \brief SLCD initialization function + * + * Enables SLCD peripheral, clocks and initializes SLCD driver + */ +void SEGMENT_LCD_0_init(void) { + hri_mclk_set_APBCMASK_SLCD_bit(SLCD); + slcd_sync_init(&SEGMENT_LCD_0, SLCD); + SEGMENT_LCD_0_PORT_init(); +} diff --git a/watch-library/hardware/hw/driver_init.h b/watch-library/hardware/hw/driver_init.h new file mode 100644 index 00000000..d1c33218 --- /dev/null +++ b/watch-library/hardware/hw/driver_init.h @@ -0,0 +1,59 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_INCLUDED +#define DRIVER_INIT_INCLUDED + +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 +#define GPIO_PIN_FUNCTION_E 4 +#define GPIO_PIN_FUNCTION_F 5 +#define GPIO_PIN_FUNCTION_G 6 +#define GPIO_PIN_FUNCTION_H 7 +#define GPIO_PIN_FUNCTION_I 8 + +#include "pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern struct adc_sync_descriptor ADC_0; + +extern struct i2c_m_sync_desc I2C_0; + +extern struct slcd_sync_descriptor SEGMENT_LCD_0; + +void I2C_0_CLOCK_init(void); +void I2C_0_init(void); +void I2C_0_PORT_init(void); + +void delay_driver_init(void); + +void EXTERNAL_IRQ_0_init(void); + +void SEGMENT_LCD_0_PORT_init(void); +void SEGMENT_LCD_0_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_INCLUDED diff --git a/watch-library/hardware/include/component-version.h b/watch-library/hardware/include/component-version.h new file mode 100644 index 00000000..a84744e9 --- /dev/null +++ b/watch-library/hardware/include/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 2 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 10002 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 77 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.2" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2018-08-31 15:05:02" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/watch-library/hardware/include/component/ac.h b/watch-library/hardware/include/component/ac.h new file mode 100644 index 00000000..e1df65fa --- /dev/null +++ b/watch-library/hardware/include/component/ac.h @@ -0,0 +1,586 @@ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_AC_COMPONENT_ +#define _SAML22_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAML22_AC Analog Comparators */ +/*@{*/ + +#define AC_U2245 +#define REV_AC 0x101 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ + uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ +#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ +#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) +#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) +#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) +#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ +#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ + +#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ +#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ + uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t OUT:2; /*!< bit: 28..29 Output */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ +#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_LOW_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_MEDLOW_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Medium low speed */ +#define AC_COMPCTRL_SPEED_MEDHIGH_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Medium high speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_MEDLOW (AC_COMPCTRL_SPEED_MEDLOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_MEDHIGH (AC_COMPCTRL_SPEED_MEDHIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ +#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) +#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST70_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 70mV */ +#define AC_COMPCTRL_HYST_HYST90_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 90mV */ +#define AC_COMPCTRL_HYST_HYST110_Val _U_(0x3) /**< \brief (AC_COMPCTRL) 110mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST70 (AC_COMPCTRL_HYST_HYST70_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST90 (AC_COMPCTRL_HYST_HYST90_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST110 (AC_COMPCTRL_HYST_HYST110_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ + uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ + uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :3; /*!< bit: 0.. 2 Reserved */ + uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} AC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ + +#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ +#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ +#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ +#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) +#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) +#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) +#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ + __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ + RoReg8 Reserved1[0x1]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ + RoReg8 Reserved2[0x2]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved3[0x8]; + __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML22_AC_COMPONENT_ */ diff --git a/watch-library/hardware/include/component/adc.h b/watch-library/hardware/include/component/adc.h new file mode 100644 index 00000000..f51dc639 --- /dev/null +++ b/watch-library/hardware/include/component/adc.h @@ -0,0 +1,748 @@ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_ADC_COMPONENT_ +#define _SAML22_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAML22_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2247 +#define REV_ADC 0x210 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run During Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run During Standby */ +#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ +#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_MASK _U_(0xC3) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */ +#define ADC_CTRLB_PRESCALER_Msk (_U_(0x7) << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) +#define ADC_CTRLB_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */ +#define ADC_CTRLB_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ +#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_MASK _U_(0x07) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x1) /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x3) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC2_Val _U_(0x5) /**< \brief (ADC_REFCTRL) VCCANA */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ + uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ + uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ + uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ +#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ +#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ +#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */ +#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ +#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ +#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ +#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ +#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ +#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ +#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SEQSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */ +#define ADC_SEQSTATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */ + +#define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */ +#define ADC_SEQSTATUS_SEQSTATE_Msk (_U_(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos) +#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos)) +#define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */ +#define ADC_SEQSTATUS_SEQBUSY (_U_(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos) +#define ADC_SEQSTATUS_MASK _U_(0x9F) /**< \brief (ADC_SEQSTATUS) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) CTAT output */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal GND */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MASK _U_(0x1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :1; /*!< bit: 6 Reserved */ + uint16_t R2R:1; /*!< bit: 7 Rail-to-Rail mode enable */ + uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t DUALSEL:2; /*!< bit: 12..13 Dual Mode Trigger Selection */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */ +#define ADC_CTRLC_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLC reset_value) Control C */ + +#define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */ +#define ADC_CTRLC_DIFFMODE (_U_(0x1) << ADC_CTRLC_DIFFMODE_Pos) +#define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */ +#define ADC_CTRLC_LEFTADJ (_U_(0x1) << ADC_CTRLC_LEFTADJ_Pos) +#define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */ +#define ADC_CTRLC_FREERUN (_U_(0x1) << ADC_CTRLC_FREERUN_Pos) +#define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */ +#define ADC_CTRLC_CORREN (_U_(0x1) << ADC_CTRLC_CORREN_Pos) +#define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */ +#define ADC_CTRLC_RESSEL_Msk (_U_(0x3) << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos)) +#define ADC_CTRLC_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLC) 12-bit result */ +#define ADC_CTRLC_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLC) For averaging mode output */ +#define ADC_CTRLC_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLC) 10-bit result */ +#define ADC_CTRLC_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLC) 8-bit result */ +#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_R2R_Pos 7 /**< \brief (ADC_CTRLC) Rail-to-Rail mode enable */ +#define ADC_CTRLC_R2R (_U_(0x1) << ADC_CTRLC_R2R_Pos) +#define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */ +#define ADC_CTRLC_WINMODE_Msk (_U_(0x7) << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos)) +#define ADC_CTRLC_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLC) No window mode (default) */ +#define ADC_CTRLC_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLC) RESULT > WINLT */ +#define ADC_CTRLC_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLC) RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_DUALSEL_Pos 12 /**< \brief (ADC_CTRLC) Dual Mode Trigger Selection */ +#define ADC_CTRLC_DUALSEL_Msk (_U_(0x3) << ADC_CTRLC_DUALSEL_Pos) +#define ADC_CTRLC_DUALSEL(value) (ADC_CTRLC_DUALSEL_Msk & ((value) << ADC_CTRLC_DUALSEL_Pos)) +#define ADC_CTRLC_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLC_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLC) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLC_DUALSEL_BOTH (ADC_CTRLC_DUALSEL_BOTH_Val << ADC_CTRLC_DUALSEL_Pos) +#define ADC_CTRLC_DUALSEL_INTERLEAVE (ADC_CTRLC_DUALSEL_INTERLEAVE_Val << ADC_CTRLC_DUALSEL_Pos) +#define ADC_CTRLC_MASK _U_(0x37BF) /**< \brief (ADC_CTRLC) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ +#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */ + uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */ +#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ +#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ + uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ + uint16_t INPUTCTRL:1; /*!< bit: 2 INPUTCTRL Synchronization Busy */ + uint16_t CTRLC:1; /*!< bit: 3 CTRLC Synchronization Busy */ + uint16_t AVGCTRL:1; /*!< bit: 4 AVGCTRL Synchronization Busy */ + uint16_t SAMPCTRL:1; /*!< bit: 5 SAMPCTRL Synchronization Busy */ + uint16_t WINLT:1; /*!< bit: 6 WINLT Synchronization Busy */ + uint16_t WINUT:1; /*!< bit: 7 WINUT Synchronization Busy */ + uint16_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */ + uint16_t OFFSETCORR:1; /*!< bit: 9 OFFSETCTRL Synchronization Busy */ + uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ + +#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ +#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ +#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_CTRLC_Pos 3 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */ +#define ADC_SYNCBUSY_CTRLC (_U_(0x1) << ADC_SYNCBUSY_CTRLC_Pos) +#define ADC_SYNCBUSY_AVGCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_WINLT_Pos 6 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */ +#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINUT_Pos 7 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */ +#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */ +#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_OFFSETCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */ +#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK _U_(0x07FF) /**< \brief (ADC_SYNCBUSY) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */ +#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */ +#define ADC_SEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */ + +#define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */ +#define ADC_SEQCTRL_SEQEN_Msk (_U_(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos) +#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos)) +#define ADC_SEQCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_SEQCTRL) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ +#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ +#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_MASK _U_(0x0707) /**< \brief (ADC_CALIB) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */ + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */ + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */ + __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */ + RoReg8 Reserved1[0x2]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */ + RoReg8 Reserved2[0x3]; + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */ + RoReg8 Reserved3[0x3]; + __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */ + RoReg8 Reserved4[0x2]; + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */ + RoReg8 Reserved5[0x2]; + __IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML22_ADC_COMPONENT_ */ diff --git a/watch-library/hardware/include/component/aes.h b/watch-library/hardware/include/component/aes.h new file mode 100644 index 00000000..439ce987 --- /dev/null +++ b/watch-library/hardware/include/component/aes.h @@ -0,0 +1,325 @@ +/** + * \file + * + * \brief Component description for AES + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_AES_COMPONENT_ +#define _SAML22_AES_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AES */ +/* ========================================================================== */ +/** \addtogroup SAML22_AES Advanced Encryption Standard */ +/*@{*/ + +#define AES_U2238 +#define REV_AES 0x210 + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ + uint32_t CFBS:3; /*!< bit: 5.. 7 CFB Types */ + uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Keysize */ + uint32_t CIPHER:1; /*!< bit: 10 Cipher mode */ + uint32_t STARTMODE:1; /*!< bit: 11 Start mode */ + uint32_t LOD:1; /*!< bit: 12 LOD Enable */ + uint32_t KEYGEN:1; /*!< bit: 13 Last key generation */ + uint32_t XORKEY:1; /*!< bit: 14 Xor Key operation */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CTYPE:4; /*!< bit: 16..19 Counter measure types */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AES_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ +#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ + +#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ +#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) +#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ +#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) +#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ +#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) +#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) CFB Types */ +#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) +#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Keysize */ +#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) +#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher mode */ +#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start mode */ +#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) LOD Enable */ +#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last key generation */ +#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) Xor Key operation */ +#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter measure types */ +#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) +#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START:1; /*!< bit: 0 Manual Start */ + uint8_t NEWMSG:1; /*!< bit: 1 New message */ + uint8_t EOM:1; /*!< bit: 2 End of message */ + uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ +#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ + +#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Manual Start */ +#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) +#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ +#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) +#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ +#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) +#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ +#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) +#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ +#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete */ +#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete */ +#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) +#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ +#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ + +#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete */ +#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) +#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete */ +#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) +#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ +#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ + +#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ +#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) +#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ +#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) +#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DATABUFPTR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ +#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ + +#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) +#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W 8) Debug control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ +#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ + +#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ +#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) +#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_KEYWORD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ +#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ +#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ +#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ +#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INTVECTV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ +#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ +#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_HASHKEY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ +#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ +#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_GHASH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ +#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ +#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_CIPLEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ +#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ +#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_RANDSEED_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ +#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ +#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ + +/** \brief AES hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ + __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ + __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */ + RoReg8 Reserved1[0x2]; + __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ + RoReg8 Reserved2[0xC]; + __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ + __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ + RoReg8 Reserved3[0x10]; + __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ + __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ + RoReg8 Reserved4[0x4]; + __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ + __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML22_AES_COMPONENT_ */ diff --git a/watch-library/hardware/include/component/ccl.h b/watch-library/hardware/include/component/ccl.h new file mode 100644 index 00000000..ce10ebc6 --- /dev/null +++ b/watch-library/hardware/include/component/ccl.h @@ -0,0 +1,188 @@ +/** + * \file + * + * \brief Component description for CCL + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_CCL_COMPONENT_ +#define _SAML22_CCL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CCL */ +/* ========================================================================== */ +/** \addtogroup SAML22_CCL Configurable Custom Logic */ +/*@{*/ + +#define CCL_U2225 +#define REV_CCL 0x101 + +/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ +#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ + +#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ +#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ +#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ +#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ + +#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ +#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ + uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ + uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ + uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ + uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ + uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ + uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CCL_LUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ + +#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ +#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ +#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ +#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ +#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event in put source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM inout source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ +#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ +#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ +#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ +#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ +#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ +#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ + +/** \brief CCL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ + RoReg8 Reserved2[0x2]; + __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ +} Ccl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML22_CCL_COMPONENT_ */ diff --git a/watch-library/hardware/include/component/dmac.h b/watch-library/hardware/include/component/dmac.h new file mode 100644 index 00000000..85b2ce02 --- /dev/null +++ b/watch-library/hardware/include/component/dmac.h @@ -0,0 +1,1117 @@ +/** + * \file + * + * \brief Component description for DMAC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_DMAC_COMPONENT_ +#define _SAML22_DMAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DMAC */ +/* ========================================================================== */ +/** \addtogroup SAML22_DMAC Direct Memory Access Controller */ +/*@{*/ + +#define DMAC_U2223 +#define REV_DMAC 0x222 + +/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ +#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ + +#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ +#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) +#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ +#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) +#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ +#define DMAC_CTRL_CRCENABLE (_U_(0x1) << DMAC_CTRL_CRCENABLE_Pos) +#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ +#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) +#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ +#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) +#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ +#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) +#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ +#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) +#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ +#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) +#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) +#define DMAC_CTRL_MASK _U_(0x0F07) /**< \brief (DMAC_CTRL) MASK Register */ + +/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CRCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ +#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ + +#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ +#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ +#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) +#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ +#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) +#define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) No action */ +#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ +#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_MASK _U_(0x3F0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ + +/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCDATAIN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ +#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ + +#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ +#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) +#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) +#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ + +/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCCHKSUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ +#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ + +#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ +#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) +#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) +#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ + +/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CRCSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ +#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ + +#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ +#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) +#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ +#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) +#define DMAC_CRCSTATUS_MASK _U_(0x03) /**< \brief (DMAC_CRCSTATUS) MASK Register */ + +/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ +#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ + +#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ +#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) +#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ + +/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ + uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ + uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_QOSCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ +#define DMAC_QOSCTRL_RESETVALUE _U_(0x2A) /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ + +#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ +#define DMAC_QOSCTRL_WRBQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) +#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_WRBQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_WRBQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ +#define DMAC_QOSCTRL_FQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) +#define DMAC_QOSCTRL_FQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_FQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_FQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_FQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ +#define DMAC_QOSCTRL_DQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) +#define DMAC_QOSCTRL_DQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_DQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_DQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_DQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_MASK _U_(0x3F) /**< \brief (DMAC_QOSCTRL) MASK Register */ + +/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ + uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ + uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ + uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:16; /*!< bit: 0..15 Channel x Software Trigger */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_SWTRIGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ +#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ + +#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) +#define DMAC_SWTRIGCTRL_MASK _U_(0x0000FFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ + +/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ + uint32_t :3; /*!< bit: 4.. 6 Reserved */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ + uint32_t :3; /*!< bit: 20..22 Reserved */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ + uint32_t :3; /*!< bit: 28..30 Reserved */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PRICTRL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ +#define DMAC_PRICTRL0_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ + +#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos) +#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) +#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) +#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos) +#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) +#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) +#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos) +#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) +#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) +#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos) +#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) +#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) +#define DMAC_PRICTRL0_MASK _U_(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */ + +/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :2; /*!< bit: 11..12 Reserved */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_INTPEND_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ +#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ + +#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ +#define DMAC_INTPEND_ID_Msk (_U_(0xF) << DMAC_INTPEND_ID_Pos) +#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) +#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ +#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) +#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ +#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) +#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ +#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) +#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ +#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) +#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ +#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) +#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ +#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) +#define DMAC_INTPEND_MASK _U_(0xE70F) /**< \brief (DMAC_INTPEND) MASK Register */ + +/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ + uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ + uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ + uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:16; /*!< bit: 0..15 Channel x Pending Interrupt */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ +#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ + +#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) +#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) +#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) +#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) +#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) +#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) +#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) +#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) +#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) +#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) +#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) +#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) +#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos) +#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos) +#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos) +#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos) +#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFF) << DMAC_INTSTATUS_CHINT_Pos) +#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) +#define DMAC_INTSTATUS_MASK _U_(0x0000FFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ + +/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ + uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ + uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ + uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:16; /*!< bit: 0..15 Busy Channel x */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BUSYCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ +#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ + +#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ +#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) +#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ +#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) +#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ +#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) +#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ +#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) +#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ +#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) +#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ +#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) +#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ +#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) +#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ +#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) +#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ +#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) +#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ +#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) +#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ +#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) +#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ +#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) +#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ +#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos) +#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ +#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos) +#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ +#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos) +#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ +#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos) +#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ +#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFF) << DMAC_BUSYCH_BUSYCH_Pos) +#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) +#define DMAC_BUSYCH_MASK _U_(0x0000FFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ + +/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ + uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ + uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ + uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:16; /*!< bit: 0..15 Pending Channel x */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PENDCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ +#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ + +#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ +#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) +#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ +#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) +#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ +#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) +#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ +#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) +#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ +#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) +#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ +#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) +#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ +#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) +#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ +#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) +#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ +#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) +#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ +#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) +#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ +#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) +#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ +#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) +#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ +#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos) +#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ +#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos) +#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ +#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos) +#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ +#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos) +#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ +#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFF) << DMAC_PENDCH_PENDCH_Pos) +#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) +#define DMAC_PENDCH_MASK _U_(0x0000FFFF) /**< \brief (DMAC_PENDCH) MASK Register */ + +/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_ACTIVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ +#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ + +#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) +#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) +#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) +#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) +#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) +#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) +#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ +#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) +#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) +#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ +#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) +#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ +#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) +#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) +#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ + +/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BASEADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ +#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ + +#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ +#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) +#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) +#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ + +/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_WRBADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ +#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ + +#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ +#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) +#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) +#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ + +/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHID_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ +#define DMAC_CHID_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHID reset_value) Channel ID */ + +#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ +#define DMAC_CHID_ID_Msk (_U_(0xF) << DMAC_CHID_ID_Pos) +#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) +#define DMAC_CHID_MASK _U_(0x0F) /**< \brief (DMAC_CHID) MASK Register */ + +/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Channel run in standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ +#define DMAC_CHCTRLA_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ + +#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ +#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) +#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ +#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) +#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel run in standby */ +#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) +#define DMAC_CHCTRLA_MASK _U_(0x43) /**< \brief (DMAC_CHCTRLA) MASK Register */ + +/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ + uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ + uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ + uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ + uint32_t :8; /*!< bit: 14..21 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ + uint32_t CMD:2; /*!< bit: 24..25 Software Command */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ +#define DMAC_CHCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ + +#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ +#define DMAC_CHCTRLB_EVACT_Msk (_U_(0x7) << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) +#define DMAC_CHCTRLB_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ +#define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ +#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ +#define DMAC_CHCTRLB_EVIE (_U_(0x1) << DMAC_CHCTRLB_EVIE_Pos) +#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ +#define DMAC_CHCTRLB_EVOE (_U_(0x1) << DMAC_CHCTRLB_EVOE_Pos) +#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ +#define DMAC_CHCTRLB_LVL_Msk (_U_(0x3) << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) +#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ +#define DMAC_CHCTRLB_TRIGSRC_Msk (_U_(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) +#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ +#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ +#define DMAC_CHCTRLB_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) +#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ +#define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ +#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ +#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) +#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_MASK _U_(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */ + +/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ +#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ + +#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) +#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) +#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) +#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ + +/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ +#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ + +#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) +#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) +#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) +#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ + +/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ + __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ + __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ +#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ + +#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ +#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) +#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ +#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) +#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ +#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) +#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ + +/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ +#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ + +#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ +#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) +#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ +#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) +#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ +#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) +#define DMAC_CHSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CHSTATUS) MASK Register */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_BTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ +#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ + +#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ +#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) +#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ +#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ +#define DMAC_BTCTRL_EVOSEL_BEAT_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ +#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) +#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ +#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) +#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ +#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) +#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/watch-library/hardware/include/core_cmFunc.h b/watch-library/hardware/include/core_cmFunc.h new file mode 100755 index 00000000..a1bd88c2 --- /dev/null +++ b/watch-library/hardware/include/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/watch-library/hardware/include/core_cmInstr.h b/watch-library/hardware/include/core_cmInstr.h new file mode 100755 index 00000000..cfdea144 --- /dev/null +++ b/watch-library/hardware/include/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300)) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/watch-library/hardware/include/instance/ac.h b/watch-library/hardware/include/instance/ac.h new file mode 100644 index 00000000..d2bf7fb9 --- /dev/null +++ b/watch-library/hardware/include/instance/ac.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Instance description for AC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_AC_INSTANCE_ +#define _SAML22_AC_INSTANCE_ + +/* ========== Register definition for AC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AC_CTRLA (0x42003400) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (0x42003401) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (0x42003402) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (0x42003404) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (0x42003405) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (0x42003406) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (0x42003407) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (0x42003408) /**< \brief (AC) Status B */ +#define REG_AC_DBGCTRL (0x42003409) /**< \brief (AC) Debug Control */ +#define REG_AC_WINCTRL (0x4200340A) /**< \brief (AC) Window Control */ +#define REG_AC_SCALER0 (0x4200340C) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (0x4200340D) /**< \brief (AC) Scaler 1 */ +#define REG_AC_COMPCTRL0 (0x42003410) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (0x42003414) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SYNCBUSY (0x42003420) /**< \brief (AC) Synchronization Busy */ +#else +#define REG_AC_CTRLA (*(RwReg8 *)0x42003400UL) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (*(WoReg8 *)0x42003401UL) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (*(RwReg16*)0x42003402UL) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (*(RwReg8 *)0x42003404UL) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (*(RwReg8 *)0x42003405UL) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (*(RwReg8 *)0x42003406UL) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (*(RoReg8 *)0x42003407UL) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (*(RoReg8 *)0x42003408UL) /**< \brief (AC) Status B */ +#define REG_AC_DBGCTRL (*(RwReg8 *)0x42003409UL) /**< \brief (AC) Debug Control */ +#define REG_AC_WINCTRL (*(RwReg8 *)0x4200340AUL) /**< \brief (AC) Window Control */ +#define REG_AC_SCALER0 (*(RwReg8 *)0x4200340CUL) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (*(RwReg8 *)0x4200340DUL) /**< \brief (AC) Scaler 1 */ +#define REG_AC_COMPCTRL0 (*(RwReg *)0x42003410UL) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (*(RwReg *)0x42003414UL) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SYNCBUSY (*(RoReg *)0x42003420UL) /**< \brief (AC) Synchronization Busy */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for AC peripheral ========== */ +#define AC_COMPCTRL_MUXNEG_OPAMP 7 // OPAMP selection for MUXNEG +#define AC_GCLK_ID 26 // Index of Generic Clock +#define AC_NUM_CMP 2 // Number of comparators +#define AC_PAIRS 1 // Number of pairs of comparators + +#endif /* _SAML22_AC_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/adc.h b/watch-library/hardware/include/instance/adc.h new file mode 100644 index 00000000..593cf070 --- /dev/null +++ b/watch-library/hardware/include/instance/adc.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief Instance description for ADC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_ADC_INSTANCE_ +#define _SAML22_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CTRLA (0x42003000) /**< \brief (ADC) Control A */ +#define REG_ADC_CTRLB (0x42003001) /**< \brief (ADC) Control B */ +#define REG_ADC_REFCTRL (0x42003002) /**< \brief (ADC) Reference Control */ +#define REG_ADC_EVCTRL (0x42003003) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (0x42003004) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (0x42003005) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (0x42003006) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_SEQSTATUS (0x42003007) /**< \brief (ADC) Sequence Status */ +#define REG_ADC_INPUTCTRL (0x42003008) /**< \brief (ADC) Input Control */ +#define REG_ADC_CTRLC (0x4200300A) /**< \brief (ADC) Control C */ +#define REG_ADC_AVGCTRL (0x4200300C) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (0x4200300D) /**< \brief (ADC) Sample Time Control */ +#define REG_ADC_WINLT (0x4200300E) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (0x42003010) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (0x42003012) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (0x42003014) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_SWTRIG (0x42003018) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_DBGCTRL (0x4200301C) /**< \brief (ADC) Debug Control */ +#define REG_ADC_SYNCBUSY (0x42003020) /**< \brief (ADC) Synchronization Busy */ +#define REG_ADC_RESULT (0x42003024) /**< \brief (ADC) Result */ +#define REG_ADC_SEQCTRL (0x42003028) /**< \brief (ADC) Sequence Control */ +#define REG_ADC_CALIB (0x4200302C) /**< \brief (ADC) Calibration */ +#else +#define REG_ADC_CTRLA (*(RwReg8 *)0x42003000UL) /**< \brief (ADC) Control A */ +#define REG_ADC_CTRLB (*(RwReg8 *)0x42003001UL) /**< \brief (ADC) Control B */ +#define REG_ADC_REFCTRL (*(RwReg8 *)0x42003002UL) /**< \brief (ADC) Reference Control */ +#define REG_ADC_EVCTRL (*(RwReg8 *)0x42003003UL) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (*(RwReg8 *)0x42003004UL) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (*(RwReg8 *)0x42003005UL) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (*(RwReg8 *)0x42003006UL) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_SEQSTATUS (*(RoReg8 *)0x42003007UL) /**< \brief (ADC) Sequence Status */ +#define REG_ADC_INPUTCTRL (*(RwReg16*)0x42003008UL) /**< \brief (ADC) Input Control */ +#define REG_ADC_CTRLC (*(RwReg16*)0x4200300AUL) /**< \brief (ADC) Control C */ +#define REG_ADC_AVGCTRL (*(RwReg8 *)0x4200300CUL) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x4200300DUL) /**< \brief (ADC) Sample Time Control */ +#define REG_ADC_WINLT (*(RwReg16*)0x4200300EUL) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (*(RwReg16*)0x42003010UL) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (*(RwReg16*)0x42003012UL) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42003014UL) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_SWTRIG (*(RwReg8 *)0x42003018UL) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200301CUL) /**< \brief (ADC) Debug Control */ +#define REG_ADC_SYNCBUSY (*(RoReg16*)0x42003020UL) /**< \brief (ADC) Synchronization Busy */ +#define REG_ADC_RESULT (*(RoReg16*)0x42003024UL) /**< \brief (ADC) Result */ +#define REG_ADC_SEQCTRL (*(RwReg *)0x42003028UL) /**< \brief (ADC) Sequence Control */ +#define REG_ADC_CALIB (*(RwReg16*)0x4200302CUL) /**< \brief (ADC) Calibration */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for ADC peripheral ========== */ +#define ADC_DMAC_ID_RESRDY 31 // index of DMA RESRDY trigger +#define ADC_EXTCHANNEL_MSB 19 // Number of external channels +#define ADC_GCLK_ID 25 // index of Generic Clock +#define ADC_INT_CH30 2 // Select OPAMP or CTAT on Channel 30 +#define ADC_MASTER_SLAVE_MODE 0 // ADC Master/Slave Mode + +#endif /* _SAML22_ADC_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/aes.h b/watch-library/hardware/include/instance/aes.h new file mode 100644 index 00000000..1d39e171 --- /dev/null +++ b/watch-library/hardware/include/instance/aes.h @@ -0,0 +1,102 @@ +/** + * \file + * + * \brief Instance description for AES + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_AES_INSTANCE_ +#define _SAML22_AES_INSTANCE_ + +/* ========== Register definition for AES peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AES_CTRLA (0x42004000) /**< \brief (AES) Control A */ +#define REG_AES_CTRLB (0x42004004) /**< \brief (AES) Control B */ +#define REG_AES_INTENCLR (0x42004005) /**< \brief (AES) Interrupt Enable Clear */ +#define REG_AES_INTENSET (0x42004006) /**< \brief (AES) Interrupt Enable Set */ +#define REG_AES_INTFLAG (0x42004007) /**< \brief (AES) Interrupt Flag Status */ +#define REG_AES_DATABUFPTR (0x42004008) /**< \brief (AES) Data buffer pointer */ +#define REG_AES_DBGCTRL (0x42004009) /**< \brief (AES) Debug control */ +#define REG_AES_KEYWORD0 (0x4200400C) /**< \brief (AES) Keyword 0 */ +#define REG_AES_KEYWORD1 (0x42004010) /**< \brief (AES) Keyword 1 */ +#define REG_AES_KEYWORD2 (0x42004014) /**< \brief (AES) Keyword 2 */ +#define REG_AES_KEYWORD3 (0x42004018) /**< \brief (AES) Keyword 3 */ +#define REG_AES_KEYWORD4 (0x4200401C) /**< \brief (AES) Keyword 4 */ +#define REG_AES_KEYWORD5 (0x42004020) /**< \brief (AES) Keyword 5 */ +#define REG_AES_KEYWORD6 (0x42004024) /**< \brief (AES) Keyword 6 */ +#define REG_AES_KEYWORD7 (0x42004028) /**< \brief (AES) Keyword 7 */ +#define REG_AES_INDATA (0x42004038) /**< \brief (AES) Indata */ +#define REG_AES_INTVECTV0 (0x4200403C) /**< \brief (AES) Initialisation Vector 0 */ +#define REG_AES_INTVECTV1 (0x42004040) /**< \brief (AES) Initialisation Vector 1 */ +#define REG_AES_INTVECTV2 (0x42004044) /**< \brief (AES) Initialisation Vector 2 */ +#define REG_AES_INTVECTV3 (0x42004048) /**< \brief (AES) Initialisation Vector 3 */ +#define REG_AES_HASHKEY0 (0x4200405C) /**< \brief (AES) Hash key 0 */ +#define REG_AES_HASHKEY1 (0x42004060) /**< \brief (AES) Hash key 1 */ +#define REG_AES_HASHKEY2 (0x42004064) /**< \brief (AES) Hash key 2 */ +#define REG_AES_HASHKEY3 (0x42004068) /**< \brief (AES) Hash key 3 */ +#define REG_AES_GHASH0 (0x4200406C) /**< \brief (AES) Galois Hash 0 */ +#define REG_AES_GHASH1 (0x42004070) /**< \brief (AES) Galois Hash 1 */ +#define REG_AES_GHASH2 (0x42004074) /**< \brief (AES) Galois Hash 2 */ +#define REG_AES_GHASH3 (0x42004078) /**< \brief (AES) Galois Hash 3 */ +#define REG_AES_CIPLEN (0x42004080) /**< \brief (AES) Cipher Length */ +#define REG_AES_RANDSEED (0x42004084) /**< \brief (AES) Random Seed */ +#else +#define REG_AES_CTRLA (*(RwReg *)0x42004000UL) /**< \brief (AES) Control A */ +#define REG_AES_CTRLB (*(RwReg8 *)0x42004004UL) /**< \brief (AES) Control B */ +#define REG_AES_INTENCLR (*(RwReg8 *)0x42004005UL) /**< \brief (AES) Interrupt Enable Clear */ +#define REG_AES_INTENSET (*(RwReg8 *)0x42004006UL) /**< \brief (AES) Interrupt Enable Set */ +#define REG_AES_INTFLAG (*(RwReg8 *)0x42004007UL) /**< \brief (AES) Interrupt Flag Status */ +#define REG_AES_DATABUFPTR (*(RwReg8 *)0x42004008UL) /**< \brief (AES) Data buffer pointer */ +#define REG_AES_DBGCTRL (*(WoReg8 *)0x42004009UL) /**< \brief (AES) Debug control */ +#define REG_AES_KEYWORD0 (*(WoReg *)0x4200400CUL) /**< \brief (AES) Keyword 0 */ +#define REG_AES_KEYWORD1 (*(WoReg *)0x42004010UL) /**< \brief (AES) Keyword 1 */ +#define REG_AES_KEYWORD2 (*(WoReg *)0x42004014UL) /**< \brief (AES) Keyword 2 */ +#define REG_AES_KEYWORD3 (*(WoReg *)0x42004018UL) /**< \brief (AES) Keyword 3 */ +#define REG_AES_KEYWORD4 (*(WoReg *)0x4200401CUL) /**< \brief (AES) Keyword 4 */ +#define REG_AES_KEYWORD5 (*(WoReg *)0x42004020UL) /**< \brief (AES) Keyword 5 */ +#define REG_AES_KEYWORD6 (*(WoReg *)0x42004024UL) /**< \brief (AES) Keyword 6 */ +#define REG_AES_KEYWORD7 (*(WoReg *)0x42004028UL) /**< \brief (AES) Keyword 7 */ +#define REG_AES_INDATA (*(RwReg *)0x42004038UL) /**< \brief (AES) Indata */ +#define REG_AES_INTVECTV0 (*(WoReg *)0x4200403CUL) /**< \brief (AES) Initialisation Vector 0 */ +#define REG_AES_INTVECTV1 (*(WoReg *)0x42004040UL) /**< \brief (AES) Initialisation Vector 1 */ +#define REG_AES_INTVECTV2 (*(WoReg *)0x42004044UL) /**< \brief (AES) Initialisation Vector 2 */ +#define REG_AES_INTVECTV3 (*(WoReg *)0x42004048UL) /**< \brief (AES) Initialisation Vector 3 */ +#define REG_AES_HASHKEY0 (*(RwReg *)0x4200405CUL) /**< \brief (AES) Hash key 0 */ +#define REG_AES_HASHKEY1 (*(RwReg *)0x42004060UL) /**< \brief (AES) Hash key 1 */ +#define REG_AES_HASHKEY2 (*(RwReg *)0x42004064UL) /**< \brief (AES) Hash key 2 */ +#define REG_AES_HASHKEY3 (*(RwReg *)0x42004068UL) /**< \brief (AES) Hash key 3 */ +#define REG_AES_GHASH0 (*(RwReg *)0x4200406CUL) /**< \brief (AES) Galois Hash 0 */ +#define REG_AES_GHASH1 (*(RwReg *)0x42004070UL) /**< \brief (AES) Galois Hash 1 */ +#define REG_AES_GHASH2 (*(RwReg *)0x42004074UL) /**< \brief (AES) Galois Hash 2 */ +#define REG_AES_GHASH3 (*(RwReg *)0x42004078UL) /**< \brief (AES) Galois Hash 3 */ +#define REG_AES_CIPLEN (*(RwReg *)0x42004080UL) /**< \brief (AES) Cipher Length */ +#define REG_AES_RANDSEED (*(RwReg *)0x42004084UL) /**< \brief (AES) Random Seed */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for AES peripheral ========== */ +#define AES_DMAC_ID_RD 36 // DMA DATA Read trigger +#define AES_DMAC_ID_WR 35 // DMA DATA Write trigger + +#endif /* _SAML22_AES_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/ccl.h b/watch-library/hardware/include/instance/ccl.h new file mode 100644 index 00000000..b1e6e8e5 --- /dev/null +++ b/watch-library/hardware/include/instance/ccl.h @@ -0,0 +1,58 @@ +/** + * \file + * + * \brief Instance description for CCL + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_CCL_INSTANCE_ +#define _SAML22_CCL_INSTANCE_ + +/* ========== Register definition for CCL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CCL_CTRL (0x42004800) /**< \brief (CCL) Control */ +#define REG_CCL_SEQCTRL0 (0x42004804) /**< \brief (CCL) SEQ Control x 0 */ +#define REG_CCL_SEQCTRL1 (0x42004805) /**< \brief (CCL) SEQ Control x 1 */ +#define REG_CCL_LUTCTRL0 (0x42004808) /**< \brief (CCL) LUT Control x 0 */ +#define REG_CCL_LUTCTRL1 (0x4200480C) /**< \brief (CCL) LUT Control x 1 */ +#define REG_CCL_LUTCTRL2 (0x42004810) /**< \brief (CCL) LUT Control x 2 */ +#define REG_CCL_LUTCTRL3 (0x42004814) /**< \brief (CCL) LUT Control x 3 */ +#else +#define REG_CCL_CTRL (*(RwReg8 *)0x42004800UL) /**< \brief (CCL) Control */ +#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42004804UL) /**< \brief (CCL) SEQ Control x 0 */ +#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42004805UL) /**< \brief (CCL) SEQ Control x 1 */ +#define REG_CCL_LUTCTRL0 (*(RwReg *)0x42004808UL) /**< \brief (CCL) LUT Control x 0 */ +#define REG_CCL_LUTCTRL1 (*(RwReg *)0x4200480CUL) /**< \brief (CCL) LUT Control x 1 */ +#define REG_CCL_LUTCTRL2 (*(RwReg *)0x42004810UL) /**< \brief (CCL) LUT Control x 2 */ +#define REG_CCL_LUTCTRL3 (*(RwReg *)0x42004814UL) /**< \brief (CCL) LUT Control x 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for CCL peripheral ========== */ +#define CCL_GCLK_ID 28 // GCLK index for CCL +#define CCL_IO_NUM 12 // Numer of input pins +#define CCL_LUT_NUM 4 // Number of LUT in a CCL +#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL + +#endif /* _SAML22_CCL_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/dmac.h b/watch-library/hardware/include/instance/dmac.h new file mode 100644 index 00000000..2b7580d2 --- /dev/null +++ b/watch-library/hardware/include/instance/dmac.h @@ -0,0 +1,98 @@ +/** + * \file + * + * \brief Instance description for DMAC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_DMAC_INSTANCE_ +#define _SAML22_DMAC_INSTANCE_ + +/* ========== Register definition for DMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC_CTRL (0x41008000) /**< \brief (DMAC) Control */ +#define REG_DMAC_CRCCTRL (0x41008002) /**< \brief (DMAC) CRC Control */ +#define REG_DMAC_CRCDATAIN (0x41008004) /**< \brief (DMAC) CRC Data Input */ +#define REG_DMAC_CRCCHKSUM (0x41008008) /**< \brief (DMAC) CRC Checksum */ +#define REG_DMAC_CRCSTATUS (0x4100800C) /**< \brief (DMAC) CRC Status */ +#define REG_DMAC_DBGCTRL (0x4100800D) /**< \brief (DMAC) Debug Control */ +#define REG_DMAC_QOSCTRL (0x4100800E) /**< \brief (DMAC) QOS Control */ +#define REG_DMAC_SWTRIGCTRL (0x41008010) /**< \brief (DMAC) Software Trigger Control */ +#define REG_DMAC_PRICTRL0 (0x41008014) /**< \brief (DMAC) Priority Control 0 */ +#define REG_DMAC_INTPEND (0x41008020) /**< \brief (DMAC) Interrupt Pending */ +#define REG_DMAC_INTSTATUS (0x41008024) /**< \brief (DMAC) Interrupt Status */ +#define REG_DMAC_BUSYCH (0x41008028) /**< \brief (DMAC) Busy Channels */ +#define REG_DMAC_PENDCH (0x4100802C) /**< \brief (DMAC) Pending Channels */ +#define REG_DMAC_ACTIVE (0x41008030) /**< \brief (DMAC) Active Channel and Levels */ +#define REG_DMAC_BASEADDR (0x41008034) /**< \brief (DMAC) Descriptor Memory Section Base Address */ +#define REG_DMAC_WRBADDR (0x41008038) /**< \brief (DMAC) Write-Back Memory Section Base Address */ +#define REG_DMAC_CHID (0x4100803F) /**< \brief (DMAC) Channel ID */ +#define REG_DMAC_CHCTRLA (0x41008040) /**< \brief (DMAC) Channel Control A */ +#define REG_DMAC_CHCTRLB (0x41008044) /**< \brief (DMAC) Channel Control B */ +#define REG_DMAC_CHINTENCLR (0x4100804C) /**< \brief (DMAC) Channel Interrupt Enable Clear */ +#define REG_DMAC_CHINTENSET (0x4100804D) /**< \brief (DMAC) Channel Interrupt Enable Set */ +#define REG_DMAC_CHINTFLAG (0x4100804E) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ +#define REG_DMAC_CHSTATUS (0x4100804F) /**< \brief (DMAC) Channel Status */ +#else +#define REG_DMAC_CTRL (*(RwReg16*)0x41008000UL) /**< \brief (DMAC) Control */ +#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41008002UL) /**< \brief (DMAC) CRC Control */ +#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41008004UL) /**< \brief (DMAC) CRC Data Input */ +#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41008008UL) /**< \brief (DMAC) CRC Checksum */ +#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100800CUL) /**< \brief (DMAC) CRC Status */ +#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100800DUL) /**< \brief (DMAC) Debug Control */ +#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100800EUL) /**< \brief (DMAC) QOS Control */ +#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41008010UL) /**< \brief (DMAC) Software Trigger Control */ +#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41008014UL) /**< \brief (DMAC) Priority Control 0 */ +#define REG_DMAC_INTPEND (*(RwReg16*)0x41008020UL) /**< \brief (DMAC) Interrupt Pending */ +#define REG_DMAC_INTSTATUS (*(RoReg *)0x41008024UL) /**< \brief (DMAC) Interrupt Status */ +#define REG_DMAC_BUSYCH (*(RoReg *)0x41008028UL) /**< \brief (DMAC) Busy Channels */ +#define REG_DMAC_PENDCH (*(RoReg *)0x4100802CUL) /**< \brief (DMAC) Pending Channels */ +#define REG_DMAC_ACTIVE (*(RoReg *)0x41008030UL) /**< \brief (DMAC) Active Channel and Levels */ +#define REG_DMAC_BASEADDR (*(RwReg *)0x41008034UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */ +#define REG_DMAC_WRBADDR (*(RwReg *)0x41008038UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */ +#define REG_DMAC_CHID (*(RwReg8 *)0x4100803FUL) /**< \brief (DMAC) Channel ID */ +#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41008040UL) /**< \brief (DMAC) Channel Control A */ +#define REG_DMAC_CHCTRLB (*(RwReg *)0x41008044UL) /**< \brief (DMAC) Channel Control B */ +#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100804CUL) /**< \brief (DMAC) Channel Interrupt Enable Clear */ +#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100804DUL) /**< \brief (DMAC) Channel Interrupt Enable Set */ +#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100804EUL) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ +#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100804FUL) /**< \brief (DMAC) Channel Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DMAC peripheral ========== */ +#define DMAC_CH_BITS 4 // Number of bits to select channel +#define DMAC_CH_NUM 16 // Number of channels +#define DMAC_CLK_AHB_ID 3 // AHB clock index +#define DMAC_EVIN_NUM 4 // Number of input events +#define DMAC_EVOUT_NUM 4 // Number of output events +#define DMAC_LVL_BITS 2 // Number of bit to select level priority +#define DMAC_LVL_NUM 4 // Enable priority level number +#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value +#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value +#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value +#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source +#define DMAC_TRIG_NUM 40 // Number of peripheral triggers + +#endif /* _SAML22_DMAC_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/dsu.h b/watch-library/hardware/include/instance/dsu.h new file mode 100644 index 00000000..8c13d4f1 --- /dev/null +++ b/watch-library/hardware/include/instance/dsu.h @@ -0,0 +1,95 @@ +/** + * \file + * + * \brief Instance description for DSU + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_DSU_INSTANCE_ +#define _SAML22_DSU_INSTANCE_ + +/* ========== Register definition for DSU peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */ +#define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */ +#define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */ +#define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */ +#define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */ +#define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */ +#define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */ +#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */ +#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */ +#define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */ +#define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */ +#define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */ +#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */ +#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */ +#define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */ +#define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */ +#define REG_DSU_PID5 (0x41003FD4) /**< \brief (DSU) Peripheral Identification 5 */ +#define REG_DSU_PID6 (0x41003FD8) /**< \brief (DSU) Peripheral Identification 6 */ +#define REG_DSU_PID7 (0x41003FDC) /**< \brief (DSU) Peripheral Identification 7 */ +#define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */ +#define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */ +#define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */ +#define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */ +#define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */ +#define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */ +#define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */ +#define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */ +#else +#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */ +#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */ +#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */ +#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */ +#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */ +#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */ +#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */ +#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */ +#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */ +#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */ +#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */ +#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */ +#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */ +#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */ +#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */ +#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */ +#define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identification 5 */ +#define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identification 6 */ +#define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identification 7 */ +#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */ +#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */ +#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */ +#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */ +#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */ +#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */ +#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */ +#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DSU peripheral ========== */ +#define DSU_CLK_AHB_ID 5 + +#endif /* _SAML22_DSU_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/eic.h b/watch-library/hardware/include/instance/eic.h new file mode 100644 index 00000000..31a5a31f --- /dev/null +++ b/watch-library/hardware/include/instance/eic.h @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Instance description for EIC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_EIC_INSTANCE_ +#define _SAML22_EIC_INSTANCE_ + +/* ========== Register definition for EIC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EIC_CTRLA (0x40002800) /**< \brief (EIC) Control */ +#define REG_EIC_NMICTRL (0x40002801) /**< \brief (EIC) NMI Control */ +#define REG_EIC_NMIFLAG (0x40002802) /**< \brief (EIC) NMI Interrupt Flag */ +#define REG_EIC_SYNCBUSY (0x40002804) /**< \brief (EIC) Syncbusy register */ +#define REG_EIC_EVCTRL (0x40002808) /**< \brief (EIC) Event Control */ +#define REG_EIC_INTENCLR (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */ +#define REG_EIC_INTENSET (0x40002810) /**< \brief (EIC) Interrupt Enable Set */ +#define REG_EIC_INTFLAG (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */ +#define REG_EIC_ASYNCH (0x40002818) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ +#define REG_EIC_CONFIG0 (0x4000281C) /**< \brief (EIC) Configuration 0 */ +#define REG_EIC_CONFIG1 (0x40002820) /**< \brief (EIC) Configuration 1 */ +#else +#define REG_EIC_CTRLA (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control */ +#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) NMI Control */ +#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802UL) /**< \brief (EIC) NMI Interrupt Flag */ +#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804UL) /**< \brief (EIC) Syncbusy register */ +#define REG_EIC_EVCTRL (*(RwReg *)0x40002808UL) /**< \brief (EIC) Event Control */ +#define REG_EIC_INTENCLR (*(RwReg *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */ +#define REG_EIC_INTENSET (*(RwReg *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */ +#define REG_EIC_INTFLAG (*(RwReg *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */ +#define REG_EIC_ASYNCH (*(RwReg *)0x40002818UL) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ +#define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CUL) /**< \brief (EIC) Configuration 0 */ +#define REG_EIC_CONFIG1 (*(RwReg *)0x40002820UL) /**< \brief (EIC) Configuration 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EIC peripheral ========== */ +#define EIC_EXTINT_NUM 16 +#define EIC_GCLK_ID 3 +#define EIC_NUMBER_OF_CONFIG_REGS 2 +#define EIC_NUMBER_OF_INTERRUPTS 16 + +#endif /* _SAML22_EIC_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/evsys.h b/watch-library/hardware/include/instance/evsys.h new file mode 100644 index 00000000..a78277ac --- /dev/null +++ b/watch-library/hardware/include/instance/evsys.h @@ -0,0 +1,250 @@ +/** + * \file + * + * \brief Instance description for EVSYS + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_EVSYS_INSTANCE_ +#define _SAML22_EVSYS_INSTANCE_ + +/* ========== Register definition for EVSYS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EVSYS_CTRLA (0x42000000) /**< \brief (EVSYS) Control */ +#define REG_EVSYS_CHSTATUS (0x4200000C) /**< \brief (EVSYS) Channel Status */ +#define REG_EVSYS_INTENCLR (0x42000010) /**< \brief (EVSYS) Interrupt Enable Clear */ +#define REG_EVSYS_INTENSET (0x42000014) /**< \brief (EVSYS) Interrupt Enable Set */ +#define REG_EVSYS_INTFLAG (0x42000018) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ +#define REG_EVSYS_SWEVT (0x4200001C) /**< \brief (EVSYS) Software Event */ +#define REG_EVSYS_CHANNEL0 (0x42000020) /**< \brief (EVSYS) Channel 0 */ +#define REG_EVSYS_CHANNEL1 (0x42000024) /**< \brief (EVSYS) Channel 1 */ +#define REG_EVSYS_CHANNEL2 (0x42000028) /**< \brief (EVSYS) Channel 2 */ +#define REG_EVSYS_CHANNEL3 (0x4200002C) /**< \brief (EVSYS) Channel 3 */ +#define REG_EVSYS_CHANNEL4 (0x42000030) /**< \brief (EVSYS) Channel 4 */ +#define REG_EVSYS_CHANNEL5 (0x42000034) /**< \brief (EVSYS) Channel 5 */ +#define REG_EVSYS_CHANNEL6 (0x42000038) /**< \brief (EVSYS) Channel 6 */ +#define REG_EVSYS_CHANNEL7 (0x4200003C) /**< \brief (EVSYS) Channel 7 */ +#define REG_EVSYS_USER0 (0x42000080) /**< \brief (EVSYS) User Multiplexer 0 */ +#define REG_EVSYS_USER1 (0x42000084) /**< \brief (EVSYS) User Multiplexer 1 */ +#define REG_EVSYS_USER2 (0x42000088) /**< \brief (EVSYS) User Multiplexer 2 */ +#define REG_EVSYS_USER3 (0x4200008C) /**< \brief (EVSYS) User Multiplexer 3 */ +#define REG_EVSYS_USER4 (0x42000090) /**< \brief (EVSYS) User Multiplexer 4 */ +#define REG_EVSYS_USER5 (0x42000094) /**< \brief (EVSYS) User Multiplexer 5 */ +#define REG_EVSYS_USER6 (0x42000098) /**< \brief (EVSYS) User Multiplexer 6 */ +#define REG_EVSYS_USER7 (0x4200009C) /**< \brief (EVSYS) User Multiplexer 7 */ +#define REG_EVSYS_USER8 (0x420000A0) /**< \brief (EVSYS) User Multiplexer 8 */ +#define REG_EVSYS_USER9 (0x420000A4) /**< \brief (EVSYS) User Multiplexer 9 */ +#define REG_EVSYS_USER10 (0x420000A8) /**< \brief (EVSYS) User Multiplexer 10 */ +#define REG_EVSYS_USER11 (0x420000AC) /**< \brief (EVSYS) User Multiplexer 11 */ +#define REG_EVSYS_USER12 (0x420000B0) /**< \brief (EVSYS) User Multiplexer 12 */ +#define REG_EVSYS_USER13 (0x420000B4) /**< \brief (EVSYS) User Multiplexer 13 */ +#define REG_EVSYS_USER14 (0x420000B8) /**< \brief (EVSYS) User Multiplexer 14 */ +#define REG_EVSYS_USER15 (0x420000BC) /**< \brief (EVSYS) User Multiplexer 15 */ +#define REG_EVSYS_USER16 (0x420000C0) /**< \brief (EVSYS) User Multiplexer 16 */ +#define REG_EVSYS_USER17 (0x420000C4) /**< \brief (EVSYS) User Multiplexer 17 */ +#define REG_EVSYS_USER18 (0x420000C8) /**< \brief (EVSYS) User Multiplexer 18 */ +#define REG_EVSYS_USER19 (0x420000CC) /**< \brief (EVSYS) User Multiplexer 19 */ +#define REG_EVSYS_USER20 (0x420000D0) /**< \brief (EVSYS) User Multiplexer 20 */ +#define REG_EVSYS_USER21 (0x420000D4) /**< \brief (EVSYS) User Multiplexer 21 */ +#define REG_EVSYS_USER22 (0x420000D8) /**< \brief (EVSYS) User Multiplexer 22 */ +#define REG_EVSYS_USER23 (0x420000DC) /**< \brief (EVSYS) User Multiplexer 23 */ +#define REG_EVSYS_USER24 (0x420000E0) /**< \brief (EVSYS) User Multiplexer 24 */ +#define REG_EVSYS_USER25 (0x420000E4) /**< \brief (EVSYS) User Multiplexer 25 */ +#define REG_EVSYS_USER26 (0x420000E8) /**< \brief (EVSYS) User Multiplexer 26 */ +#define REG_EVSYS_USER27 (0x420000EC) /**< \brief (EVSYS) User Multiplexer 27 */ +#define REG_EVSYS_USER28 (0x420000F0) /**< \brief (EVSYS) User Multiplexer 28 */ +#define REG_EVSYS_USER29 (0x420000F4) /**< \brief (EVSYS) User Multiplexer 29 */ +#define REG_EVSYS_USER30 (0x420000F8) /**< \brief (EVSYS) User Multiplexer 30 */ +#else +#define REG_EVSYS_CTRLA (*(RwReg8 *)0x42000000UL) /**< \brief (EVSYS) Control */ +#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200000CUL) /**< \brief (EVSYS) Channel Status */ +#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000010UL) /**< \brief (EVSYS) Interrupt Enable Clear */ +#define REG_EVSYS_INTENSET (*(RwReg *)0x42000014UL) /**< \brief (EVSYS) Interrupt Enable Set */ +#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000018UL) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ +#define REG_EVSYS_SWEVT (*(WoReg *)0x4200001CUL) /**< \brief (EVSYS) Software Event */ +#define REG_EVSYS_CHANNEL0 (*(RwReg *)0x42000020UL) /**< \brief (EVSYS) Channel 0 */ +#define REG_EVSYS_CHANNEL1 (*(RwReg *)0x42000024UL) /**< \brief (EVSYS) Channel 1 */ +#define REG_EVSYS_CHANNEL2 (*(RwReg *)0x42000028UL) /**< \brief (EVSYS) Channel 2 */ +#define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4200002CUL) /**< \brief (EVSYS) Channel 3 */ +#define REG_EVSYS_CHANNEL4 (*(RwReg *)0x42000030UL) /**< \brief (EVSYS) Channel 4 */ +#define REG_EVSYS_CHANNEL5 (*(RwReg *)0x42000034UL) /**< \brief (EVSYS) Channel 5 */ +#define REG_EVSYS_CHANNEL6 (*(RwReg *)0x42000038UL) /**< \brief (EVSYS) Channel 6 */ +#define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4200003CUL) /**< \brief (EVSYS) Channel 7 */ +#define REG_EVSYS_USER0 (*(RwReg *)0x42000080UL) /**< \brief (EVSYS) User Multiplexer 0 */ +#define REG_EVSYS_USER1 (*(RwReg *)0x42000084UL) /**< \brief (EVSYS) User Multiplexer 1 */ +#define REG_EVSYS_USER2 (*(RwReg *)0x42000088UL) /**< \brief (EVSYS) User Multiplexer 2 */ +#define REG_EVSYS_USER3 (*(RwReg *)0x4200008CUL) /**< \brief (EVSYS) User Multiplexer 3 */ +#define REG_EVSYS_USER4 (*(RwReg *)0x42000090UL) /**< \brief (EVSYS) User Multiplexer 4 */ +#define REG_EVSYS_USER5 (*(RwReg *)0x42000094UL) /**< \brief (EVSYS) User Multiplexer 5 */ +#define REG_EVSYS_USER6 (*(RwReg *)0x42000098UL) /**< \brief (EVSYS) User Multiplexer 6 */ +#define REG_EVSYS_USER7 (*(RwReg *)0x4200009CUL) /**< \brief (EVSYS) User Multiplexer 7 */ +#define REG_EVSYS_USER8 (*(RwReg *)0x420000A0UL) /**< \brief (EVSYS) User Multiplexer 8 */ +#define REG_EVSYS_USER9 (*(RwReg *)0x420000A4UL) /**< \brief (EVSYS) User Multiplexer 9 */ +#define REG_EVSYS_USER10 (*(RwReg *)0x420000A8UL) /**< \brief (EVSYS) User Multiplexer 10 */ +#define REG_EVSYS_USER11 (*(RwReg *)0x420000ACUL) /**< \brief (EVSYS) User Multiplexer 11 */ +#define REG_EVSYS_USER12 (*(RwReg *)0x420000B0UL) /**< \brief (EVSYS) User Multiplexer 12 */ +#define REG_EVSYS_USER13 (*(RwReg *)0x420000B4UL) /**< \brief (EVSYS) User Multiplexer 13 */ +#define REG_EVSYS_USER14 (*(RwReg *)0x420000B8UL) /**< \brief (EVSYS) User Multiplexer 14 */ +#define REG_EVSYS_USER15 (*(RwReg *)0x420000BCUL) /**< \brief (EVSYS) User Multiplexer 15 */ +#define REG_EVSYS_USER16 (*(RwReg *)0x420000C0UL) /**< \brief (EVSYS) User Multiplexer 16 */ +#define REG_EVSYS_USER17 (*(RwReg *)0x420000C4UL) /**< \brief (EVSYS) User Multiplexer 17 */ +#define REG_EVSYS_USER18 (*(RwReg *)0x420000C8UL) /**< \brief (EVSYS) User Multiplexer 18 */ +#define REG_EVSYS_USER19 (*(RwReg *)0x420000CCUL) /**< \brief (EVSYS) User Multiplexer 19 */ +#define REG_EVSYS_USER20 (*(RwReg *)0x420000D0UL) /**< \brief (EVSYS) User Multiplexer 20 */ +#define REG_EVSYS_USER21 (*(RwReg *)0x420000D4UL) /**< \brief (EVSYS) User Multiplexer 21 */ +#define REG_EVSYS_USER22 (*(RwReg *)0x420000D8UL) /**< \brief (EVSYS) User Multiplexer 22 */ +#define REG_EVSYS_USER23 (*(RwReg *)0x420000DCUL) /**< \brief (EVSYS) User Multiplexer 23 */ +#define REG_EVSYS_USER24 (*(RwReg *)0x420000E0UL) /**< \brief (EVSYS) User Multiplexer 24 */ +#define REG_EVSYS_USER25 (*(RwReg *)0x420000E4UL) /**< \brief (EVSYS) User Multiplexer 25 */ +#define REG_EVSYS_USER26 (*(RwReg *)0x420000E8UL) /**< \brief (EVSYS) User Multiplexer 26 */ +#define REG_EVSYS_USER27 (*(RwReg *)0x420000ECUL) /**< \brief (EVSYS) User Multiplexer 27 */ +#define REG_EVSYS_USER28 (*(RwReg *)0x420000F0UL) /**< \brief (EVSYS) User Multiplexer 28 */ +#define REG_EVSYS_USER29 (*(RwReg *)0x420000F4UL) /**< \brief (EVSYS) User Multiplexer 29 */ +#define REG_EVSYS_USER30 (*(RwReg *)0x420000F8UL) /**< \brief (EVSYS) User Multiplexer 30 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EVSYS peripheral ========== */ +#define EVSYS_CHANNELS 8 // Number of Channels +#define EVSYS_CHANNELS_BITS 3 // Number of bits to select Channel +#define EVSYS_CHANNELS_MSB 7 // Number of Channels - 1 +#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators +#define EVSYS_GCLK_ID_0 7 +#define EVSYS_GCLK_ID_1 8 +#define EVSYS_GCLK_ID_2 9 +#define EVSYS_GCLK_ID_3 10 +#define EVSYS_GCLK_ID_4 11 +#define EVSYS_GCLK_ID_5 12 +#define EVSYS_GCLK_ID_6 13 +#define EVSYS_GCLK_ID_7 14 +#define EVSYS_GCLK_ID_LSB 7 +#define EVSYS_GCLK_ID_MSB 14 +#define EVSYS_GCLK_ID_SIZE 8 +#define EVSYS_GENERATORS 71 // Total Number of Event Generators +#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator +#define EVSYS_USERS 31 // Total Number of Event Users +#define EVSYS_USERS_BITS 5 // Number of bits to select Event User + +// GENERATORS +#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL 1 +#define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 2 +#define EVSYS_ID_GEN_RTC_CMP_0 3 +#define EVSYS_ID_GEN_RTC_CMP_1 4 +#define EVSYS_ID_GEN_RTC_TAMPER 5 +#define EVSYS_ID_GEN_RTC_OVF 6 +#define EVSYS_ID_GEN_RTC_PER_0 7 +#define EVSYS_ID_GEN_RTC_PER_1 8 +#define EVSYS_ID_GEN_RTC_PER_2 9 +#define EVSYS_ID_GEN_RTC_PER_3 10 +#define EVSYS_ID_GEN_RTC_PER_4 11 +#define EVSYS_ID_GEN_RTC_PER_5 12 +#define EVSYS_ID_GEN_RTC_PER_6 13 +#define EVSYS_ID_GEN_RTC_PER_7 14 +#define EVSYS_ID_GEN_EIC_EXTINT_0 15 +#define EVSYS_ID_GEN_EIC_EXTINT_1 16 +#define EVSYS_ID_GEN_EIC_EXTINT_2 17 +#define EVSYS_ID_GEN_EIC_EXTINT_3 18 +#define EVSYS_ID_GEN_EIC_EXTINT_4 19 +#define EVSYS_ID_GEN_EIC_EXTINT_5 20 +#define EVSYS_ID_GEN_EIC_EXTINT_6 21 +#define EVSYS_ID_GEN_EIC_EXTINT_7 22 +#define EVSYS_ID_GEN_EIC_EXTINT_8 23 +#define EVSYS_ID_GEN_EIC_EXTINT_9 24 +#define EVSYS_ID_GEN_EIC_EXTINT_10 25 +#define EVSYS_ID_GEN_EIC_EXTINT_11 26 +#define EVSYS_ID_GEN_EIC_EXTINT_12 27 +#define EVSYS_ID_GEN_EIC_EXTINT_13 28 +#define EVSYS_ID_GEN_EIC_EXTINT_14 29 +#define EVSYS_ID_GEN_EIC_EXTINT_15 30 +#define EVSYS_ID_GEN_DMAC_CH_0 31 +#define EVSYS_ID_GEN_DMAC_CH_1 32 +#define EVSYS_ID_GEN_DMAC_CH_2 33 +#define EVSYS_ID_GEN_DMAC_CH_3 34 +#define EVSYS_ID_GEN_TCC0_OVF 35 +#define EVSYS_ID_GEN_TCC0_TRG 36 +#define EVSYS_ID_GEN_TCC0_CNT 37 +#define EVSYS_ID_GEN_TCC0_MCX_0 38 +#define EVSYS_ID_GEN_TCC0_MCX_1 39 +#define EVSYS_ID_GEN_TCC0_MCX_2 40 +#define EVSYS_ID_GEN_TCC0_MCX_3 41 +#define EVSYS_ID_GEN_TC0_OVF 42 +#define EVSYS_ID_GEN_TC0_MCX_0 43 +#define EVSYS_ID_GEN_TC0_MCX_1 44 +#define EVSYS_ID_GEN_TC1_OVF 45 +#define EVSYS_ID_GEN_TC1_MCX_0 46 +#define EVSYS_ID_GEN_TC1_MCX_1 47 +#define EVSYS_ID_GEN_TC2_OVF 48 +#define EVSYS_ID_GEN_TC2_MCX_0 49 +#define EVSYS_ID_GEN_TC2_MCX_1 50 +#define EVSYS_ID_GEN_TC3_OVF 51 +#define EVSYS_ID_GEN_TC3_MCX_0 52 +#define EVSYS_ID_GEN_TC3_MCX_1 53 +#define EVSYS_ID_GEN_ADC_RESRDY 54 +#define EVSYS_ID_GEN_ADC_WINMON 55 +#define EVSYS_ID_GEN_AC_COMP_0 56 +#define EVSYS_ID_GEN_AC_COMP_1 57 +#define EVSYS_ID_GEN_AC_WIN_0 58 +#define EVSYS_ID_GEN_SLCD_FC0OVERFLOW 61 +#define EVSYS_ID_GEN_SLCD_FC1OVERFLOW 62 +#define EVSYS_ID_GEN_SLCD_FC2OVERFLOW 63 +#define EVSYS_ID_GEN_SLCD_DT 64 +#define EVSYS_ID_GEN_TRNG_READY 65 +#define EVSYS_ID_GEN_CCL_LUTOUT_0 66 +#define EVSYS_ID_GEN_CCL_LUTOUT_1 67 +#define EVSYS_ID_GEN_CCL_LUTOUT_2 68 +#define EVSYS_ID_GEN_CCL_LUTOUT_3 69 +#define EVSYS_ID_GEN_PAC_ACCERR 70 + +// USERS +#define EVSYS_ID_USER_RTC_TAMPER 0 +#define EVSYS_ID_USER_PORT_EV_0 1 +#define EVSYS_ID_USER_PORT_EV_1 2 +#define EVSYS_ID_USER_PORT_EV_2 3 +#define EVSYS_ID_USER_PORT_EV_3 4 +#define EVSYS_ID_USER_DMAC_CH_0 5 +#define EVSYS_ID_USER_DMAC_CH_1 6 +#define EVSYS_ID_USER_DMAC_CH_2 7 +#define EVSYS_ID_USER_DMAC_CH_3 8 +#define EVSYS_ID_USER_TCC0_EV_0 9 +#define EVSYS_ID_USER_TCC0_EV_1 10 +#define EVSYS_ID_USER_TCC0_MC_0 11 +#define EVSYS_ID_USER_TCC0_MC_1 12 +#define EVSYS_ID_USER_TCC0_MC_2 13 +#define EVSYS_ID_USER_TCC0_MC_3 14 +#define EVSYS_ID_USER_TC0_EVU 15 +#define EVSYS_ID_USER_TC1_EVU 16 +#define EVSYS_ID_USER_TC2_EVU 17 +#define EVSYS_ID_USER_TC3_EVU 18 +#define EVSYS_ID_USER_ADC_START 19 +#define EVSYS_ID_USER_ADC_SYNC 20 +#define EVSYS_ID_USER_AC_SOC_0 21 +#define EVSYS_ID_USER_AC_SOC_1 22 +#define EVSYS_ID_USER_CCL_LUTIN_0 24 +#define EVSYS_ID_USER_CCL_LUTIN_1 25 +#define EVSYS_ID_USER_CCL_LUTIN_2 26 +#define EVSYS_ID_USER_CCL_LUTIN_3 27 +#define EVSYS_ID_USER_MTB_START 29 +#define EVSYS_ID_USER_MTB_STOP 30 + +#endif /* _SAML22_EVSYS_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/freqm.h b/watch-library/hardware/include/instance/freqm.h new file mode 100644 index 00000000..4c2e2102 --- /dev/null +++ b/watch-library/hardware/include/instance/freqm.h @@ -0,0 +1,60 @@ +/** + * \file + * + * \brief Instance description for FREQM + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_FREQM_INSTANCE_ +#define _SAML22_FREQM_INSTANCE_ + +/* ========== Register definition for FREQM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FREQM_CTRLA (0x40002C00) /**< \brief (FREQM) Control A Register */ +#define REG_FREQM_CTRLB (0x40002C01) /**< \brief (FREQM) Control B Register */ +#define REG_FREQM_CFGA (0x40002C02) /**< \brief (FREQM) Config A register */ +#define REG_FREQM_INTENCLR (0x40002C08) /**< \brief (FREQM) Interrupt Enable Clear Register */ +#define REG_FREQM_INTENSET (0x40002C09) /**< \brief (FREQM) Interrupt Enable Set Register */ +#define REG_FREQM_INTFLAG (0x40002C0A) /**< \brief (FREQM) Interrupt Flag Register */ +#define REG_FREQM_STATUS (0x40002C0B) /**< \brief (FREQM) Status Register */ +#define REG_FREQM_SYNCBUSY (0x40002C0C) /**< \brief (FREQM) Synchronization Busy Register */ +#define REG_FREQM_VALUE (0x40002C10) /**< \brief (FREQM) Count Value Register */ +#else +#define REG_FREQM_CTRLA (*(RwReg8 *)0x40002C00UL) /**< \brief (FREQM) Control A Register */ +#define REG_FREQM_CTRLB (*(WoReg8 *)0x40002C01UL) /**< \brief (FREQM) Control B Register */ +#define REG_FREQM_CFGA (*(RwReg16*)0x40002C02UL) /**< \brief (FREQM) Config A register */ +#define REG_FREQM_INTENCLR (*(RwReg8 *)0x40002C08UL) /**< \brief (FREQM) Interrupt Enable Clear Register */ +#define REG_FREQM_INTENSET (*(RwReg8 *)0x40002C09UL) /**< \brief (FREQM) Interrupt Enable Set Register */ +#define REG_FREQM_INTFLAG (*(RwReg8 *)0x40002C0AUL) /**< \brief (FREQM) Interrupt Flag Register */ +#define REG_FREQM_STATUS (*(RwReg8 *)0x40002C0BUL) /**< \brief (FREQM) Status Register */ +#define REG_FREQM_SYNCBUSY (*(RoReg *)0x40002C0CUL) /**< \brief (FREQM) Synchronization Busy Register */ +#define REG_FREQM_VALUE (*(RoReg *)0x40002C10UL) /**< \brief (FREQM) Count Value Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for FREQM peripheral ========== */ +#define FREQM_GCLK_ID_MSR 4 // Index of measure generic clock +#define FREQM_GCLK_ID_REF 5 // Index of reference generic clock + +#endif /* _SAML22_FREQM_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/gclk.h b/watch-library/hardware/include/instance/gclk.h new file mode 100644 index 00000000..869d77c6 --- /dev/null +++ b/watch-library/hardware/include/instance/gclk.h @@ -0,0 +1,130 @@ +/** + * \file + * + * \brief Instance description for GCLK + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_GCLK_INSTANCE_ +#define _SAML22_GCLK_INSTANCE_ + +/* ========== Register definition for GCLK peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GCLK_CTRLA (0x40001C00) /**< \brief (GCLK) Control */ +#define REG_GCLK_SYNCBUSY (0x40001C04) /**< \brief (GCLK) Synchronization Busy */ +#define REG_GCLK_GENCTRL0 (0x40001C20) /**< \brief (GCLK) Generic Clock Generator Control 0 */ +#define REG_GCLK_GENCTRL1 (0x40001C24) /**< \brief (GCLK) Generic Clock Generator Control 1 */ +#define REG_GCLK_GENCTRL2 (0x40001C28) /**< \brief (GCLK) Generic Clock Generator Control 2 */ +#define REG_GCLK_GENCTRL3 (0x40001C2C) /**< \brief (GCLK) Generic Clock Generator Control 3 */ +#define REG_GCLK_GENCTRL4 (0x40001C30) /**< \brief (GCLK) Generic Clock Generator Control 4 */ +#define REG_GCLK_PCHCTRL0 (0x40001C80) /**< \brief (GCLK) Peripheral Clock Control 0 */ +#define REG_GCLK_PCHCTRL1 (0x40001C84) /**< \brief (GCLK) Peripheral Clock Control 1 */ +#define REG_GCLK_PCHCTRL2 (0x40001C88) /**< \brief (GCLK) Peripheral Clock Control 2 */ +#define REG_GCLK_PCHCTRL3 (0x40001C8C) /**< \brief (GCLK) Peripheral Clock Control 3 */ +#define REG_GCLK_PCHCTRL4 (0x40001C90) /**< \brief (GCLK) Peripheral Clock Control 4 */ +#define REG_GCLK_PCHCTRL5 (0x40001C94) /**< \brief (GCLK) Peripheral Clock Control 5 */ +#define REG_GCLK_PCHCTRL6 (0x40001C98) /**< \brief (GCLK) Peripheral Clock Control 6 */ +#define REG_GCLK_PCHCTRL7 (0x40001C9C) /**< \brief (GCLK) Peripheral Clock Control 7 */ +#define REG_GCLK_PCHCTRL8 (0x40001CA0) /**< \brief (GCLK) Peripheral Clock Control 8 */ +#define REG_GCLK_PCHCTRL9 (0x40001CA4) /**< \brief (GCLK) Peripheral Clock Control 9 */ +#define REG_GCLK_PCHCTRL10 (0x40001CA8) /**< \brief (GCLK) Peripheral Clock Control 10 */ +#define REG_GCLK_PCHCTRL11 (0x40001CAC) /**< \brief (GCLK) Peripheral Clock Control 11 */ +#define REG_GCLK_PCHCTRL12 (0x40001CB0) /**< \brief (GCLK) Peripheral Clock Control 12 */ +#define REG_GCLK_PCHCTRL13 (0x40001CB4) /**< \brief (GCLK) Peripheral Clock Control 13 */ +#define REG_GCLK_PCHCTRL14 (0x40001CB8) /**< \brief (GCLK) Peripheral Clock Control 14 */ +#define REG_GCLK_PCHCTRL15 (0x40001CBC) /**< \brief (GCLK) Peripheral Clock Control 15 */ +#define REG_GCLK_PCHCTRL16 (0x40001CC0) /**< \brief (GCLK) Peripheral Clock Control 16 */ +#define REG_GCLK_PCHCTRL17 (0x40001CC4) /**< \brief (GCLK) Peripheral Clock Control 17 */ +#define REG_GCLK_PCHCTRL18 (0x40001CC8) /**< \brief (GCLK) Peripheral Clock Control 18 */ +#define REG_GCLK_PCHCTRL19 (0x40001CCC) /**< \brief (GCLK) Peripheral Clock Control 19 */ +#define REG_GCLK_PCHCTRL20 (0x40001CD0) /**< \brief (GCLK) Peripheral Clock Control 20 */ +#define REG_GCLK_PCHCTRL21 (0x40001CD4) /**< \brief (GCLK) Peripheral Clock Control 21 */ +#define REG_GCLK_PCHCTRL22 (0x40001CD8) /**< \brief (GCLK) Peripheral Clock Control 22 */ +#define REG_GCLK_PCHCTRL23 (0x40001CDC) /**< \brief (GCLK) Peripheral Clock Control 23 */ +#define REG_GCLK_PCHCTRL24 (0x40001CE0) /**< \brief (GCLK) Peripheral Clock Control 24 */ +#define REG_GCLK_PCHCTRL25 (0x40001CE4) /**< \brief (GCLK) Peripheral Clock Control 25 */ +#define REG_GCLK_PCHCTRL26 (0x40001CE8) /**< \brief (GCLK) Peripheral Clock Control 26 */ +#define REG_GCLK_PCHCTRL27 (0x40001CEC) /**< \brief (GCLK) Peripheral Clock Control 27 */ +#define REG_GCLK_PCHCTRL28 (0x40001CF0) /**< \brief (GCLK) Peripheral Clock Control 28 */ +#define REG_GCLK_PCHCTRL29 (0x40001CF4) /**< \brief (GCLK) Peripheral Clock Control 29 */ +#else +#define REG_GCLK_CTRLA (*(RwReg8 *)0x40001C00UL) /**< \brief (GCLK) Control */ +#define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001C04UL) /**< \brief (GCLK) Synchronization Busy */ +#define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001C20UL) /**< \brief (GCLK) Generic Clock Generator Control 0 */ +#define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001C24UL) /**< \brief (GCLK) Generic Clock Generator Control 1 */ +#define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001C28UL) /**< \brief (GCLK) Generic Clock Generator Control 2 */ +#define REG_GCLK_GENCTRL3 (*(RwReg *)0x40001C2CUL) /**< \brief (GCLK) Generic Clock Generator Control 3 */ +#define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001C30UL) /**< \brief (GCLK) Generic Clock Generator Control 4 */ +#define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001C80UL) /**< \brief (GCLK) Peripheral Clock Control 0 */ +#define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001C84UL) /**< \brief (GCLK) Peripheral Clock Control 1 */ +#define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001C88UL) /**< \brief (GCLK) Peripheral Clock Control 2 */ +#define REG_GCLK_PCHCTRL3 (*(RwReg *)0x40001C8CUL) /**< \brief (GCLK) Peripheral Clock Control 3 */ +#define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001C90UL) /**< \brief (GCLK) Peripheral Clock Control 4 */ +#define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001C94UL) /**< \brief (GCLK) Peripheral Clock Control 5 */ +#define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001C98UL) /**< \brief (GCLK) Peripheral Clock Control 6 */ +#define REG_GCLK_PCHCTRL7 (*(RwReg *)0x40001C9CUL) /**< \brief (GCLK) Peripheral Clock Control 7 */ +#define REG_GCLK_PCHCTRL8 (*(RwReg *)0x40001CA0UL) /**< \brief (GCLK) Peripheral Clock Control 8 */ +#define REG_GCLK_PCHCTRL9 (*(RwReg *)0x40001CA4UL) /**< \brief (GCLK) Peripheral Clock Control 9 */ +#define REG_GCLK_PCHCTRL10 (*(RwReg *)0x40001CA8UL) /**< \brief (GCLK) Peripheral Clock Control 10 */ +#define REG_GCLK_PCHCTRL11 (*(RwReg *)0x40001CACUL) /**< \brief (GCLK) Peripheral Clock Control 11 */ +#define REG_GCLK_PCHCTRL12 (*(RwReg *)0x40001CB0UL) /**< \brief (GCLK) Peripheral Clock Control 12 */ +#define REG_GCLK_PCHCTRL13 (*(RwReg *)0x40001CB4UL) /**< \brief (GCLK) Peripheral Clock Control 13 */ +#define REG_GCLK_PCHCTRL14 (*(RwReg *)0x40001CB8UL) /**< \brief (GCLK) Peripheral Clock Control 14 */ +#define REG_GCLK_PCHCTRL15 (*(RwReg *)0x40001CBCUL) /**< \brief (GCLK) Peripheral Clock Control 15 */ +#define REG_GCLK_PCHCTRL16 (*(RwReg *)0x40001CC0UL) /**< \brief (GCLK) Peripheral Clock Control 16 */ +#define REG_GCLK_PCHCTRL17 (*(RwReg *)0x40001CC4UL) /**< \brief (GCLK) Peripheral Clock Control 17 */ +#define REG_GCLK_PCHCTRL18 (*(RwReg *)0x40001CC8UL) /**< \brief (GCLK) Peripheral Clock Control 18 */ +#define REG_GCLK_PCHCTRL19 (*(RwReg *)0x40001CCCUL) /**< \brief (GCLK) Peripheral Clock Control 19 */ +#define REG_GCLK_PCHCTRL20 (*(RwReg *)0x40001CD0UL) /**< \brief (GCLK) Peripheral Clock Control 20 */ +#define REG_GCLK_PCHCTRL21 (*(RwReg *)0x40001CD4UL) /**< \brief (GCLK) Peripheral Clock Control 21 */ +#define REG_GCLK_PCHCTRL22 (*(RwReg *)0x40001CD8UL) /**< \brief (GCLK) Peripheral Clock Control 22 */ +#define REG_GCLK_PCHCTRL23 (*(RwReg *)0x40001CDCUL) /**< \brief (GCLK) Peripheral Clock Control 23 */ +#define REG_GCLK_PCHCTRL24 (*(RwReg *)0x40001CE0UL) /**< \brief (GCLK) Peripheral Clock Control 24 */ +#define REG_GCLK_PCHCTRL25 (*(RwReg *)0x40001CE4UL) /**< \brief (GCLK) Peripheral Clock Control 25 */ +#define REG_GCLK_PCHCTRL26 (*(RwReg *)0x40001CE8UL) /**< \brief (GCLK) Peripheral Clock Control 26 */ +#define REG_GCLK_PCHCTRL27 (*(RwReg *)0x40001CECUL) /**< \brief (GCLK) Peripheral Clock Control 27 */ +#define REG_GCLK_PCHCTRL28 (*(RwReg *)0x40001CF0UL) /**< \brief (GCLK) Peripheral Clock Control 28 */ +#define REG_GCLK_PCHCTRL29 (*(RwReg *)0x40001CF4UL) /**< \brief (GCLK) Peripheral Clock Control 29 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for GCLK peripheral ========== */ +#define GCLK_GENDIV_BITS 16 +#define GCLK_GEN_BITS 3 +#define GCLK_GEN_NUM 5 // Number of Generic Clock Generators +#define GCLK_GEN_NUM_MSB 4 // Number of Generic Clock Generators - 1 +#define GCLK_GEN_SOURCE_NUM_MSB 7 // Number of Generic Clock Sources - 1 +#define GCLK_NUM 30 // Number of Generic Clock Users +#define GCLK_SOURCE_BITS 3 +#define GCLK_SOURCE_DFLL48M 6 +#define GCLK_SOURCE_DPLL96M 7 +#define GCLK_SOURCE_GCLKGEN1 2 +#define GCLK_SOURCE_GCLKIN 1 +#define GCLK_SOURCE_NUM 8 // Number of Generic Clock Sources +#define GCLK_SOURCE_OSCULP32K 3 +#define GCLK_SOURCE_OSC16M 5 +#define GCLK_SOURCE_XOSC 0 +#define GCLK_SOURCE_XOSC32K 4 + +#endif /* _SAML22_GCLK_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/mclk.h b/watch-library/hardware/include/instance/mclk.h new file mode 100644 index 00000000..32af4f13 --- /dev/null +++ b/watch-library/hardware/include/instance/mclk.h @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief Instance description for MCLK + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_MCLK_INSTANCE_ +#define _SAML22_MCLK_INSTANCE_ + +/* ========== Register definition for MCLK peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MCLK_INTENCLR (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */ +#define REG_MCLK_INTENSET (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */ +#define REG_MCLK_INTFLAG (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */ +#define REG_MCLK_CPUDIV (0x40000804) /**< \brief (MCLK) CPU Clock Division */ +#define REG_MCLK_BUPDIV (0x40000806) /**< \brief (MCLK) Backup Clock Division */ +#define REG_MCLK_AHBMASK (0x40000810) /**< \brief (MCLK) AHB Mask */ +#define REG_MCLK_APBAMASK (0x40000814) /**< \brief (MCLK) APBA Mask */ +#define REG_MCLK_APBBMASK (0x40000818) /**< \brief (MCLK) APBB Mask */ +#define REG_MCLK_APBCMASK (0x4000081C) /**< \brief (MCLK) APBC Mask */ +#else +#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */ +#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */ +#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */ +#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804UL) /**< \brief (MCLK) CPU Clock Division */ +#define REG_MCLK_BUPDIV (*(RwReg8 *)0x40000806UL) /**< \brief (MCLK) Backup Clock Division */ +#define REG_MCLK_AHBMASK (*(RwReg *)0x40000810UL) /**< \brief (MCLK) AHB Mask */ +#define REG_MCLK_APBAMASK (*(RwReg *)0x40000814UL) /**< \brief (MCLK) APBA Mask */ +#define REG_MCLK_APBBMASK (*(RwReg *)0x40000818UL) /**< \brief (MCLK) APBB Mask */ +#define REG_MCLK_APBCMASK (*(RwReg *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for MCLK peripheral ========== */ +#define MCLK_BUPDIV_IMPLEMENTED 1 +#define MCLK_CTRLA_MCSEL_GCLK 1 +#define MCLK_CTRLA_MCSEL_OSC8M 0 +#define MCLK_MCLK_CLK_APB_NUM 3 +#define MCLK_SYSTEM_CLOCK 1000000 // System Clock Frequency at Reset + +#endif /* _SAML22_MCLK_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/mtb.h b/watch-library/hardware/include/instance/mtb.h new file mode 100644 index 00000000..02e67161 --- /dev/null +++ b/watch-library/hardware/include/instance/mtb.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief Instance description for MTB + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_MTB_INSTANCE_ +#define _SAML22_MTB_INSTANCE_ + +/* ========== Register definition for MTB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MTB_POSITION (0x4100A000) /**< \brief (MTB) MTB Position */ +#define REG_MTB_MASTER (0x4100A004) /**< \brief (MTB) MTB Master */ +#define REG_MTB_FLOW (0x4100A008) /**< \brief (MTB) MTB Flow */ +#define REG_MTB_BASE (0x4100A00C) /**< \brief (MTB) MTB Base */ +#define REG_MTB_ITCTRL (0x4100AF00) /**< \brief (MTB) MTB Integration Mode Control */ +#define REG_MTB_CLAIMSET (0x4100AFA0) /**< \brief (MTB) MTB Claim Set */ +#define REG_MTB_CLAIMCLR (0x4100AFA4) /**< \brief (MTB) MTB Claim Clear */ +#define REG_MTB_LOCKACCESS (0x4100AFB0) /**< \brief (MTB) MTB Lock Access */ +#define REG_MTB_LOCKSTATUS (0x4100AFB4) /**< \brief (MTB) MTB Lock Status */ +#define REG_MTB_AUTHSTATUS (0x4100AFB8) /**< \brief (MTB) MTB Authentication Status */ +#define REG_MTB_DEVARCH (0x4100AFBC) /**< \brief (MTB) MTB Device Architecture */ +#define REG_MTB_DEVID (0x4100AFC8) /**< \brief (MTB) MTB Device Configuration */ +#define REG_MTB_DEVTYPE (0x4100AFCC) /**< \brief (MTB) MTB Device Type */ +#define REG_MTB_PID4 (0x4100AFD0) /**< \brief (MTB) Peripheral Identification 4 */ +#define REG_MTB_PID5 (0x4100AFD4) /**< \brief (MTB) Peripheral Identification 5 */ +#define REG_MTB_PID6 (0x4100AFD8) /**< \brief (MTB) Peripheral Identification 6 */ +#define REG_MTB_PID7 (0x4100AFDC) /**< \brief (MTB) Peripheral Identification 7 */ +#define REG_MTB_PID0 (0x4100AFE0) /**< \brief (MTB) Peripheral Identification 0 */ +#define REG_MTB_PID1 (0x4100AFE4) /**< \brief (MTB) Peripheral Identification 1 */ +#define REG_MTB_PID2 (0x4100AFE8) /**< \brief (MTB) Peripheral Identification 2 */ +#define REG_MTB_PID3 (0x4100AFEC) /**< \brief (MTB) Peripheral Identification 3 */ +#define REG_MTB_CID0 (0x4100AFF0) /**< \brief (MTB) Component Identification 0 */ +#define REG_MTB_CID1 (0x4100AFF4) /**< \brief (MTB) Component Identification 1 */ +#define REG_MTB_CID2 (0x4100AFF8) /**< \brief (MTB) Component Identification 2 */ +#define REG_MTB_CID3 (0x4100AFFC) /**< \brief (MTB) Component Identification 3 */ +#else +#define REG_MTB_POSITION (*(RwReg *)0x4100A000UL) /**< \brief (MTB) MTB Position */ +#define REG_MTB_MASTER (*(RwReg *)0x4100A004UL) /**< \brief (MTB) MTB Master */ +#define REG_MTB_FLOW (*(RwReg *)0x4100A008UL) /**< \brief (MTB) MTB Flow */ +#define REG_MTB_BASE (*(RoReg *)0x4100A00CUL) /**< \brief (MTB) MTB Base */ +#define REG_MTB_ITCTRL (*(RwReg *)0x4100AF00UL) /**< \brief (MTB) MTB Integration Mode Control */ +#define REG_MTB_CLAIMSET (*(RwReg *)0x4100AFA0UL) /**< \brief (MTB) MTB Claim Set */ +#define REG_MTB_CLAIMCLR (*(RwReg *)0x4100AFA4UL) /**< \brief (MTB) MTB Claim Clear */ +#define REG_MTB_LOCKACCESS (*(RwReg *)0x4100AFB0UL) /**< \brief (MTB) MTB Lock Access */ +#define REG_MTB_LOCKSTATUS (*(RoReg *)0x4100AFB4UL) /**< \brief (MTB) MTB Lock Status */ +#define REG_MTB_AUTHSTATUS (*(RoReg *)0x4100AFB8UL) /**< \brief (MTB) MTB Authentication Status */ +#define REG_MTB_DEVARCH (*(RoReg *)0x4100AFBCUL) /**< \brief (MTB) MTB Device Architecture */ +#define REG_MTB_DEVID (*(RoReg *)0x4100AFC8UL) /**< \brief (MTB) MTB Device Configuration */ +#define REG_MTB_DEVTYPE (*(RoReg *)0x4100AFCCUL) /**< \brief (MTB) MTB Device Type */ +#define REG_MTB_PID4 (*(RoReg *)0x4100AFD0UL) /**< \brief (MTB) Peripheral Identification 4 */ +#define REG_MTB_PID5 (*(RoReg *)0x4100AFD4UL) /**< \brief (MTB) Peripheral Identification 5 */ +#define REG_MTB_PID6 (*(RoReg *)0x4100AFD8UL) /**< \brief (MTB) Peripheral Identification 6 */ +#define REG_MTB_PID7 (*(RoReg *)0x4100AFDCUL) /**< \brief (MTB) Peripheral Identification 7 */ +#define REG_MTB_PID0 (*(RoReg *)0x4100AFE0UL) /**< \brief (MTB) Peripheral Identification 0 */ +#define REG_MTB_PID1 (*(RoReg *)0x4100AFE4UL) /**< \brief (MTB) Peripheral Identification 1 */ +#define REG_MTB_PID2 (*(RoReg *)0x4100AFE8UL) /**< \brief (MTB) Peripheral Identification 2 */ +#define REG_MTB_PID3 (*(RoReg *)0x4100AFECUL) /**< \brief (MTB) Peripheral Identification 3 */ +#define REG_MTB_CID0 (*(RoReg *)0x4100AFF0UL) /**< \brief (MTB) Component Identification 0 */ +#define REG_MTB_CID1 (*(RoReg *)0x4100AFF4UL) /**< \brief (MTB) Component Identification 1 */ +#define REG_MTB_CID2 (*(RoReg *)0x4100AFF8UL) /**< \brief (MTB) Component Identification 2 */ +#define REG_MTB_CID3 (*(RoReg *)0x4100AFFCUL) /**< \brief (MTB) Component Identification 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAML22_MTB_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/nvmctrl.h b/watch-library/hardware/include/instance/nvmctrl.h new file mode 100644 index 00000000..89adf7ee --- /dev/null +++ b/watch-library/hardware/include/instance/nvmctrl.h @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief Instance description for NVMCTRL + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_NVMCTRL_INSTANCE_ +#define _SAML22_NVMCTRL_INSTANCE_ + +/* ========== Register definition for NVMCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */ +#define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */ +#define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */ +#define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */ +#define REG_NVMCTRL_INTENSET (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */ +#define REG_NVMCTRL_INTFLAG (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ +#define REG_NVMCTRL_STATUS (0x41004018) /**< \brief (NVMCTRL) Status */ +#define REG_NVMCTRL_ADDR (0x4100401C) /**< \brief (NVMCTRL) Address */ +#define REG_NVMCTRL_LOCK (0x41004020) /**< \brief (NVMCTRL) Lock Section */ +#else +#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */ +#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004UL) /**< \brief (NVMCTRL) Control B */ +#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */ +#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */ +#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */ +#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ +#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */ +#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CUL) /**< \brief (NVMCTRL) Address */ +#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for NVMCTRL peripheral ========== */ +#define NVMCTRL_AUX0_ADDRESS 0x00804000 +#define NVMCTRL_AUX1_ADDRESS 0x00806000 +#define NVMCTRL_AUX2_ADDRESS 0x00808000 +#define NVMCTRL_AUX3_ADDRESS 0x0080A000 +#define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register +#define NVMCTRL_CLK_AHB_ID_PICACHU 10 // Index of PICACHU AHB Clock +#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF +#define NVMCTRL_FLASH_SIZE 262144 +#define NVMCTRL_GCLK_ID 29 // Index of Generic Clock for test +#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 +#define NVMCTRL_USER_PAGE_OFFSET 0x00800000 +#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF +#define NVMCTRL_RWWEE_PAGES 128 +#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area + +#endif /* _SAML22_NVMCTRL_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/osc32kctrl.h b/watch-library/hardware/include/instance/osc32kctrl.h new file mode 100644 index 00000000..6edc7597 --- /dev/null +++ b/watch-library/hardware/include/instance/osc32kctrl.h @@ -0,0 +1,61 @@ +/** + * \file + * + * \brief Instance description for OSC32KCTRL + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_OSC32KCTRL_INSTANCE_ +#define _SAML22_OSC32KCTRL_INSTANCE_ + +/* ========== Register definition for OSC32KCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_OSC32KCTRL_INTENCLR (0x40001400) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ +#define REG_OSC32KCTRL_INTENSET (0x40001404) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ +#define REG_OSC32KCTRL_INTFLAG (0x40001408) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ +#define REG_OSC32KCTRL_STATUS (0x4000140C) /**< \brief (OSC32KCTRL) Power and Clocks Status */ +#define REG_OSC32KCTRL_RTCCTRL (0x40001410) /**< \brief (OSC32KCTRL) RTC Clock Selection */ +#define REG_OSC32KCTRL_SLCDCTRL (0x40001411) /**< \brief (OSC32KCTRL) SLCD Clock Selection */ +#define REG_OSC32KCTRL_XOSC32K (0x40001414) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_OSC32KCTRL_CFDCTRL (0x40001416) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */ +#define REG_OSC32KCTRL_EVCTRL (0x40001417) /**< \brief (OSC32KCTRL) Event Control */ +#define REG_OSC32KCTRL_OSCULP32K (0x4000141C) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#else +#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001400UL) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ +#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ +#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001408UL) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ +#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000140CUL) /**< \brief (OSC32KCTRL) Power and Clocks Status */ +#define REG_OSC32KCTRL_RTCCTRL (*(RwReg8 *)0x40001410UL) /**< \brief (OSC32KCTRL) RTC Clock Selection */ +#define REG_OSC32KCTRL_SLCDCTRL (*(RwReg8 *)0x40001411UL) /**< \brief (OSC32KCTRL) SLCD Clock Selection */ +#define REG_OSC32KCTRL_XOSC32K (*(RwReg16*)0x40001414UL) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_OSC32KCTRL_CFDCTRL (*(RwReg8 *)0x40001416UL) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */ +#define REG_OSC32KCTRL_EVCTRL (*(RwReg8 *)0x40001417UL) /**< \brief (OSC32KCTRL) Event Control */ +#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000141CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for OSC32KCTRL peripheral ========== */ +#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6 + +#endif /* _SAML22_OSC32KCTRL_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/oscctrl.h b/watch-library/hardware/include/instance/oscctrl.h new file mode 100644 index 00000000..bd390207 --- /dev/null +++ b/watch-library/hardware/include/instance/oscctrl.h @@ -0,0 +1,86 @@ +/** + * \file + * + * \brief Instance description for OSCCTRL + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_OSCCTRL_INSTANCE_ +#define _SAML22_OSCCTRL_INSTANCE_ + +/* ========== Register definition for OSCCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_OSCCTRL_INTENCLR (0x40001000) /**< \brief (OSCCTRL) Interrupt Enable Clear */ +#define REG_OSCCTRL_INTENSET (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Set */ +#define REG_OSCCTRL_INTFLAG (0x40001008) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ +#define REG_OSCCTRL_STATUS (0x4000100C) /**< \brief (OSCCTRL) Power and Clocks Status */ +#define REG_OSCCTRL_XOSCCTRL (0x40001010) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_OSCCTRL_CFDPRESC (0x40001012) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */ +#define REG_OSCCTRL_EVCTRL (0x40001013) /**< \brief (OSCCTRL) Event Control */ +#define REG_OSCCTRL_OSC16MCTRL (0x40001014) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ +#define REG_OSCCTRL_DFLLCTRL (0x40001018) /**< \brief (OSCCTRL) DFLL48M Control */ +#define REG_OSCCTRL_DFLLVAL (0x4000101C) /**< \brief (OSCCTRL) DFLL48M Value */ +#define REG_OSCCTRL_DFLLMUL (0x40001020) /**< \brief (OSCCTRL) DFLL48M Multiplier */ +#define REG_OSCCTRL_DFLLSYNC (0x40001024) /**< \brief (OSCCTRL) DFLL48M Synchronization */ +#define REG_OSCCTRL_DPLLCTRLA (0x40001028) /**< \brief (OSCCTRL) DPLL Control */ +#define REG_OSCCTRL_DPLLRATIO (0x4000102C) /**< \brief (OSCCTRL) DPLL Ratio Control */ +#define REG_OSCCTRL_DPLLCTRLB (0x40001030) /**< \brief (OSCCTRL) Digital Core Configuration */ +#define REG_OSCCTRL_DPLLPRESC (0x40001034) /**< \brief (OSCCTRL) DPLL Prescaler */ +#define REG_OSCCTRL_DPLLSYNCBUSY (0x40001038) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ +#define REG_OSCCTRL_DPLLSTATUS (0x4000103C) /**< \brief (OSCCTRL) DPLL Status */ +#else +#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001000UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */ +#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Set */ +#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ +#define REG_OSCCTRL_STATUS (*(RoReg *)0x4000100CUL) /**< \brief (OSCCTRL) Power and Clocks Status */ +#define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40001010UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_OSCCTRL_CFDPRESC (*(RwReg8 *)0x40001012UL) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */ +#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001013UL) /**< \brief (OSCCTRL) Event Control */ +#define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40001014UL) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ +#define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40001018UL) /**< \brief (OSCCTRL) DFLL48M Control */ +#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x4000101CUL) /**< \brief (OSCCTRL) DFLL48M Value */ +#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001020UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */ +#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40001024UL) /**< \brief (OSCCTRL) DFLL48M Synchronization */ +#define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40001028UL) /**< \brief (OSCCTRL) DPLL Control */ +#define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x4000102CUL) /**< \brief (OSCCTRL) DPLL Ratio Control */ +#define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40001030UL) /**< \brief (OSCCTRL) Digital Core Configuration */ +#define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40001034UL) /**< \brief (OSCCTRL) DPLL Prescaler */ +#define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40001038UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ +#define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x4000103CUL) /**< \brief (OSCCTRL) DPLL Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for OSCCTRL peripheral ========== */ +#define OSCCTRL_DFLL48M_COARSE_MSB 5 +#define OSCCTRL_DFLL48M_FINE_MSB 9 +#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 +#define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL +#define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K +#define OSCCTRL_CFD_VERSION 0x100 +#define OSCCTRL_DFLL48M_VERSION 0x320 +#define OSCCTRL_FDPLL_VERSION 0x211 +#define OSCCTRL_OSC16M_VERSION 0x101 +#define OSCCTRL_XOSC_VERSION 0x201 + +#endif /* _SAML22_OSCCTRL_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/pac.h b/watch-library/hardware/include/instance/pac.h new file mode 100644 index 00000000..cc3d94d5 --- /dev/null +++ b/watch-library/hardware/include/instance/pac.h @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Instance description for PAC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_PAC_INSTANCE_ +#define _SAML22_PAC_INSTANCE_ + +/* ========== Register definition for PAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC_WRCTRL (0x40000000) /**< \brief (PAC) Write control */ +#define REG_PAC_EVCTRL (0x40000004) /**< \brief (PAC) Event control */ +#define REG_PAC_INTENCLR (0x40000008) /**< \brief (PAC) Interrupt enable clear */ +#define REG_PAC_INTENSET (0x40000009) /**< \brief (PAC) Interrupt enable set */ +#define REG_PAC_INTFLAGAHB (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */ +#define REG_PAC_INTFLAGA (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ +#define REG_PAC_INTFLAGB (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ +#define REG_PAC_INTFLAGC (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ +#define REG_PAC_STATUSA (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */ +#define REG_PAC_STATUSB (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */ +#define REG_PAC_STATUSC (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */ +#else +#define REG_PAC_WRCTRL (*(RwReg *)0x40000000UL) /**< \brief (PAC) Write control */ +#define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */ +#define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */ +#define REG_PAC_INTENSET (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */ +#define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */ +#define REG_PAC_INTFLAGA (*(RwReg *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ +#define REG_PAC_INTFLAGB (*(RwReg *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ +#define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ +#define REG_PAC_STATUSA (*(RoReg *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */ +#define REG_PAC_STATUSB (*(RoReg *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */ +#define REG_PAC_STATUSC (*(RoReg *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC peripheral ========== */ +#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock +#define PAC_CLK_AHB_ID 7 // AHB clock index +#define PAC_HPB_NUM 3 // Number of bridges AHB/APB +#define PAC_INTFLAG_NUM 4 // Number of intflag registers + +#endif /* _SAML22_PAC_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/pm.h b/watch-library/hardware/include/instance/pm.h new file mode 100644 index 00000000..6ca464f2 --- /dev/null +++ b/watch-library/hardware/include/instance/pm.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief Instance description for PM + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_PM_INSTANCE_ +#define _SAML22_PM_INSTANCE_ + +/* ========== Register definition for PM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PM_CTRLA (0x40000400) /**< \brief (PM) Control A */ +#define REG_PM_SLEEPCFG (0x40000401) /**< \brief (PM) Sleep Configuration */ +#define REG_PM_PLCFG (0x40000402) /**< \brief (PM) Performance Level Configuration */ +#define REG_PM_INTENCLR (0x40000404) /**< \brief (PM) Interrupt Enable Clear */ +#define REG_PM_INTENSET (0x40000405) /**< \brief (PM) Interrupt Enable Set */ +#define REG_PM_INTFLAG (0x40000406) /**< \brief (PM) Interrupt Flag Status and Clear */ +#define REG_PM_STDBYCFG (0x40000408) /**< \brief (PM) Standby Configuration */ +#else +#define REG_PM_CTRLA (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control A */ +#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Configuration */ +#define REG_PM_PLCFG (*(RwReg8 *)0x40000402UL) /**< \brief (PM) Performance Level Configuration */ +#define REG_PM_INTENCLR (*(RwReg8 *)0x40000404UL) /**< \brief (PM) Interrupt Enable Clear */ +#define REG_PM_INTENSET (*(RwReg8 *)0x40000405UL) /**< \brief (PM) Interrupt Enable Set */ +#define REG_PM_INTFLAG (*(RwReg8 *)0x40000406UL) /**< \brief (PM) Interrupt Flag Status and Clear */ +#define REG_PM_STDBYCFG (*(RwReg16*)0x40000408UL) /**< \brief (PM) Standby Configuration */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PM peripheral ========== */ +#define PM_BIAS_RAM_HS 1 // one if RAM HS can be back biased +#define PM_PD_NUM 0 // Number of switchable Power Domain + +#endif /* _SAML22_PM_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/port.h b/watch-library/hardware/include/instance/port.h new file mode 100644 index 00000000..6ec1564d --- /dev/null +++ b/watch-library/hardware/include/instance/port.h @@ -0,0 +1,155 @@ +/** + * \file + * + * \brief Instance description for PORT + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_PORT_INSTANCE_ +#define _SAML22_PORT_INSTANCE_ + +/* ========== Register definition for PORT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PORT_DIR0 (0x41006000) /**< \brief (PORT) Data Direction 0 */ +#define REG_PORT_DIRCLR0 (0x41006004) /**< \brief (PORT) Data Direction Clear 0 */ +#define REG_PORT_DIRSET0 (0x41006008) /**< \brief (PORT) Data Direction Set 0 */ +#define REG_PORT_DIRTGL0 (0x4100600C) /**< \brief (PORT) Data Direction Toggle 0 */ +#define REG_PORT_OUT0 (0x41006010) /**< \brief (PORT) Data Output Value 0 */ +#define REG_PORT_OUTCLR0 (0x41006014) /**< \brief (PORT) Data Output Value Clear 0 */ +#define REG_PORT_OUTSET0 (0x41006018) /**< \brief (PORT) Data Output Value Set 0 */ +#define REG_PORT_OUTTGL0 (0x4100601C) /**< \brief (PORT) Data Output Value Toggle 0 */ +#define REG_PORT_IN0 (0x41006020) /**< \brief (PORT) Data Input Value 0 */ +#define REG_PORT_CTRL0 (0x41006024) /**< \brief (PORT) Control 0 */ +#define REG_PORT_WRCONFIG0 (0x41006028) /**< \brief (PORT) Write Configuration 0 */ +#define REG_PORT_EVCTRL0 (0x4100602C) /**< \brief (PORT) Event Input Control 0 */ +#define REG_PORT_PMUX0 (0x41006030) /**< \brief (PORT) Peripheral Multiplexing 0 */ +#define REG_PORT_PINCFG0 (0x41006040) /**< \brief (PORT) Pin Configuration 0 */ +#define REG_PORT_DIR1 (0x41006080) /**< \brief (PORT) Data Direction 1 */ +#define REG_PORT_DIRCLR1 (0x41006084) /**< \brief (PORT) Data Direction Clear 1 */ +#define REG_PORT_DIRSET1 (0x41006088) /**< \brief (PORT) Data Direction Set 1 */ +#define REG_PORT_DIRTGL1 (0x4100608C) /**< \brief (PORT) Data Direction Toggle 1 */ +#define REG_PORT_OUT1 (0x41006090) /**< \brief (PORT) Data Output Value 1 */ +#define REG_PORT_OUTCLR1 (0x41006094) /**< \brief (PORT) Data Output Value Clear 1 */ +#define REG_PORT_OUTSET1 (0x41006098) /**< \brief (PORT) Data Output Value Set 1 */ +#define REG_PORT_OUTTGL1 (0x4100609C) /**< \brief (PORT) Data Output Value Toggle 1 */ +#define REG_PORT_IN1 (0x410060A0) /**< \brief (PORT) Data Input Value 1 */ +#define REG_PORT_CTRL1 (0x410060A4) /**< \brief (PORT) Control 1 */ +#define REG_PORT_WRCONFIG1 (0x410060A8) /**< \brief (PORT) Write Configuration 1 */ +#define REG_PORT_EVCTRL1 (0x410060AC) /**< \brief (PORT) Event Input Control 1 */ +#define REG_PORT_PMUX1 (0x410060B0) /**< \brief (PORT) Peripheral Multiplexing 1 */ +#define REG_PORT_PINCFG1 (0x410060C0) /**< \brief (PORT) Pin Configuration 1 */ +#define REG_PORT_DIR2 (0x41006100) /**< \brief (PORT) Data Direction 2 */ +#define REG_PORT_DIRCLR2 (0x41006104) /**< \brief (PORT) Data Direction Clear 2 */ +#define REG_PORT_DIRSET2 (0x41006108) /**< \brief (PORT) Data Direction Set 2 */ +#define REG_PORT_DIRTGL2 (0x4100610C) /**< \brief (PORT) Data Direction Toggle 2 */ +#define REG_PORT_OUT2 (0x41006110) /**< \brief (PORT) Data Output Value 2 */ +#define REG_PORT_OUTCLR2 (0x41006114) /**< \brief (PORT) Data Output Value Clear 2 */ +#define REG_PORT_OUTSET2 (0x41006118) /**< \brief (PORT) Data Output Value Set 2 */ +#define REG_PORT_OUTTGL2 (0x4100611C) /**< \brief (PORT) Data Output Value Toggle 2 */ +#define REG_PORT_IN2 (0x41006120) /**< \brief (PORT) Data Input Value 2 */ +#define REG_PORT_CTRL2 (0x41006124) /**< \brief (PORT) Control 2 */ +#define REG_PORT_WRCONFIG2 (0x41006128) /**< \brief (PORT) Write Configuration 2 */ +#define REG_PORT_EVCTRL2 (0x4100612C) /**< \brief (PORT) Event Input Control 2 */ +#define REG_PORT_PMUX2 (0x41006130) /**< \brief (PORT) Peripheral Multiplexing 2 */ +#define REG_PORT_PINCFG2 (0x41006140) /**< \brief (PORT) Pin Configuration 2 */ +#else +#define REG_PORT_DIR0 (*(RwReg *)0x41006000UL) /**< \brief (PORT) Data Direction 0 */ +#define REG_PORT_DIRCLR0 (*(RwReg *)0x41006004UL) /**< \brief (PORT) Data Direction Clear 0 */ +#define REG_PORT_DIRSET0 (*(RwReg *)0x41006008UL) /**< \brief (PORT) Data Direction Set 0 */ +#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100600CUL) /**< \brief (PORT) Data Direction Toggle 0 */ +#define REG_PORT_OUT0 (*(RwReg *)0x41006010UL) /**< \brief (PORT) Data Output Value 0 */ +#define REG_PORT_OUTCLR0 (*(RwReg *)0x41006014UL) /**< \brief (PORT) Data Output Value Clear 0 */ +#define REG_PORT_OUTSET0 (*(RwReg *)0x41006018UL) /**< \brief (PORT) Data Output Value Set 0 */ +#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100601CUL) /**< \brief (PORT) Data Output Value Toggle 0 */ +#define REG_PORT_IN0 (*(RoReg *)0x41006020UL) /**< \brief (PORT) Data Input Value 0 */ +#define REG_PORT_CTRL0 (*(RwReg *)0x41006024UL) /**< \brief (PORT) Control 0 */ +#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41006028UL) /**< \brief (PORT) Write Configuration 0 */ +#define REG_PORT_EVCTRL0 (*(RwReg *)0x4100602CUL) /**< \brief (PORT) Event Input Control 0 */ +#define REG_PORT_PMUX0 (*(RwReg8 *)0x41006030UL) /**< \brief (PORT) Peripheral Multiplexing 0 */ +#define REG_PORT_PINCFG0 (*(RwReg8 *)0x41006040UL) /**< \brief (PORT) Pin Configuration 0 */ +#define REG_PORT_DIR1 (*(RwReg *)0x41006080UL) /**< \brief (PORT) Data Direction 1 */ +#define REG_PORT_DIRCLR1 (*(RwReg *)0x41006084UL) /**< \brief (PORT) Data Direction Clear 1 */ +#define REG_PORT_DIRSET1 (*(RwReg *)0x41006088UL) /**< \brief (PORT) Data Direction Set 1 */ +#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100608CUL) /**< \brief (PORT) Data Direction Toggle 1 */ +#define REG_PORT_OUT1 (*(RwReg *)0x41006090UL) /**< \brief (PORT) Data Output Value 1 */ +#define REG_PORT_OUTCLR1 (*(RwReg *)0x41006094UL) /**< \brief (PORT) Data Output Value Clear 1 */ +#define REG_PORT_OUTSET1 (*(RwReg *)0x41006098UL) /**< \brief (PORT) Data Output Value Set 1 */ +#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100609CUL) /**< \brief (PORT) Data Output Value Toggle 1 */ +#define REG_PORT_IN1 (*(RoReg *)0x410060A0UL) /**< \brief (PORT) Data Input Value 1 */ +#define REG_PORT_CTRL1 (*(RwReg *)0x410060A4UL) /**< \brief (PORT) Control 1 */ +#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410060A8UL) /**< \brief (PORT) Write Configuration 1 */ +#define REG_PORT_EVCTRL1 (*(RwReg *)0x410060ACUL) /**< \brief (PORT) Event Input Control 1 */ +#define REG_PORT_PMUX1 (*(RwReg8 *)0x410060B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */ +#define REG_PORT_PINCFG1 (*(RwReg8 *)0x410060C0UL) /**< \brief (PORT) Pin Configuration 1 */ +#define REG_PORT_DIR2 (*(RwReg *)0x41006100UL) /**< \brief (PORT) Data Direction 2 */ +#define REG_PORT_DIRCLR2 (*(RwReg *)0x41006104UL) /**< \brief (PORT) Data Direction Clear 2 */ +#define REG_PORT_DIRSET2 (*(RwReg *)0x41006108UL) /**< \brief (PORT) Data Direction Set 2 */ +#define REG_PORT_DIRTGL2 (*(RwReg *)0x4100610CUL) /**< \brief (PORT) Data Direction Toggle 2 */ +#define REG_PORT_OUT2 (*(RwReg *)0x41006110UL) /**< \brief (PORT) Data Output Value 2 */ +#define REG_PORT_OUTCLR2 (*(RwReg *)0x41006114UL) /**< \brief (PORT) Data Output Value Clear 2 */ +#define REG_PORT_OUTSET2 (*(RwReg *)0x41006118UL) /**< \brief (PORT) Data Output Value Set 2 */ +#define REG_PORT_OUTTGL2 (*(RwReg *)0x4100611CUL) /**< \brief (PORT) Data Output Value Toggle 2 */ +#define REG_PORT_IN2 (*(RoReg *)0x41006120UL) /**< \brief (PORT) Data Input Value 2 */ +#define REG_PORT_CTRL2 (*(RwReg *)0x41006124UL) /**< \brief (PORT) Control 2 */ +#define REG_PORT_WRCONFIG2 (*(WoReg *)0x41006128UL) /**< \brief (PORT) Write Configuration 2 */ +#define REG_PORT_EVCTRL2 (*(RwReg *)0x4100612CUL) /**< \brief (PORT) Event Input Control 2 */ +#define REG_PORT_PMUX2 (*(RwReg8 *)0x41006130UL) /**< \brief (PORT) Peripheral Multiplexing 2 */ +#define REG_PORT_PINCFG2 (*(RwReg8 *)0x41006140UL) /**< \brief (PORT) Pin Configuration 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PORT peripheral ========== */ +#define PORT_BITS 93 +#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_DIR_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_DRVSTR 1 // DRVSTR supported +#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_DRVSTR_IMPLEMENTED { 0xC8FFFFFF, 0xC3FFFBFF, 0x1F3FF0EF } +#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F03F0EF } +#define PORT_EV_NUM 4 +#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_INEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_ODRAIN 0 // ODRAIN supported +#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_OUT_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_PIN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_PMUXBIT0_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } +#define PORT_PMUXBIT1_IMPLEMENTED { 0xCBFFFFF7, 0xC3FFFB0F, 0x1B003C03 } +#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } +#define PORT_PMUXBIT2_IMPLEMENTED { 0x4BFFFF34, 0xC3FFFB0F, 0x1F000003 } +#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_PMUXBIT3_IMPLEMENTED { 0xC3CF0FF0, 0x00C3CBC7, 0x18300000 } +#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } +#define PORT_PMUXEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_PULLEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } +#define PORT_SLEWLIM 0 // SLEWLIM supported +#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } + +#endif /* _SAML22_PORT_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/ptc.h b/watch-library/hardware/include/instance/ptc.h new file mode 100644 index 00000000..03c6b30d --- /dev/null +++ b/watch-library/hardware/include/instance/ptc.h @@ -0,0 +1,43 @@ +/** + * \file + * + * \brief Instance description for PTC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_PTC_INSTANCE_ +#define _SAML22_PTC_INSTANCE_ + +/* ========== Instance parameters for PTC peripheral ========== */ +#define PTC_DMAC_ID_EOC 37 // Index of DMA EOC trigger +#define PTC_DMAC_ID_SEQ 38 // Index of DMA SEQ trigger +#define PTC_DMAC_ID_WCOMP 39 // Index of DMA WCOMP trigger +#define PTC_GCLK_ID 27 // Index of Generic Clock +#define PTC_LINES_MSB 31 +#define PTC_LINES_NUM 32 // Number of PTC lines +#define PTC_Y_LINES_MSB 23 +#define PTC_Y_LINES_NUM 24 // Number of Y lines + +#endif /* _SAML22_PTC_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/rstc.h b/watch-library/hardware/include/instance/rstc.h new file mode 100644 index 00000000..e6186fd4 --- /dev/null +++ b/watch-library/hardware/include/instance/rstc.h @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Instance description for RSTC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_RSTC_INSTANCE_ +#define _SAML22_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RSTC_RCAUSE (0x40000C00) /**< \brief (RSTC) Reset Cause */ +#define REG_RSTC_BKUPEXIT (0x40000C02) /**< \brief (RSTC) Backup Exit Source */ +#else +#define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000C00UL) /**< \brief (RSTC) Reset Cause */ +#define REG_RSTC_BKUPEXIT (*(RoReg8 *)0x40000C02UL) /**< \brief (RSTC) Backup Exit Source */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for RSTC peripheral ========== */ +#define RSTC_BACKUP_IMPLEMENTED 1 +#define RSTC_NUMBER_OF_EXTWAKE 0 // number of external wakeup line + +#endif /* _SAML22_RSTC_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/rtc.h b/watch-library/hardware/include/instance/rtc.h new file mode 100644 index 00000000..5c6bf72d --- /dev/null +++ b/watch-library/hardware/include/instance/rtc.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Instance description for RTC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_RTC_INSTANCE_ +#define _SAML22_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_DBGCTRL (0x4000240E) /**< \brief (RTC) Debug Control */ +#define REG_RTC_FREQCORR (0x40002414) /**< \brief (RTC) Frequency Correction */ +#define REG_RTC_GP0 (0x40002440) /**< \brief (RTC) General Purpose 0 */ +#define REG_RTC_GP1 (0x40002444) /**< \brief (RTC) General Purpose 1 */ +#define REG_RTC_TAMPCTRL (0x40002460) /**< \brief (RTC) Tamper Control */ +#define REG_RTC_TAMPID (0x40002468) /**< \brief (RTC) Tamper ID */ +#define REG_RTC_BKUP0 (0x40002480) /**< \brief (RTC) Backup 0 */ +#define REG_RTC_BKUP1 (0x40002484) /**< \brief (RTC) Backup 1 */ +#define REG_RTC_BKUP2 (0x40002488) /**< \brief (RTC) Backup 2 */ +#define REG_RTC_BKUP3 (0x4000248C) /**< \brief (RTC) Backup 3 */ +#define REG_RTC_BKUP4 (0x40002490) /**< \brief (RTC) Backup 4 */ +#define REG_RTC_BKUP5 (0x40002494) /**< \brief (RTC) Backup 5 */ +#define REG_RTC_BKUP6 (0x40002498) /**< \brief (RTC) Backup 6 */ +#define REG_RTC_BKUP7 (0x4000249C) /**< \brief (RTC) Backup 7 */ +#define REG_RTC_MODE0_CTRLA (0x40002400) /**< \brief (RTC) MODE0 Control A */ +#define REG_RTC_MODE0_CTRLB (0x40002402) /**< \brief (RTC) MODE0 Control B */ +#define REG_RTC_MODE0_EVCTRL (0x40002404) /**< \brief (RTC) MODE0 Event Control */ +#define REG_RTC_MODE0_INTENCLR (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ +#define REG_RTC_MODE0_INTENSET (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */ +#define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */ +#define REG_RTC_MODE0_COUNT (0x40002418) /**< \brief (RTC) MODE0 Counter Value */ +#define REG_RTC_MODE0_COMP0 (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */ +#define REG_RTC_MODE0_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE0 Timestamp */ +#define REG_RTC_MODE1_CTRLA (0x40002400) /**< \brief (RTC) MODE1 Control A */ +#define REG_RTC_MODE1_CTRLB (0x40002402) /**< \brief (RTC) MODE1 Control B */ +#define REG_RTC_MODE1_EVCTRL (0x40002404) /**< \brief (RTC) MODE1 Event Control */ +#define REG_RTC_MODE1_INTENCLR (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ +#define REG_RTC_MODE1_INTENSET (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */ +#define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */ +#define REG_RTC_MODE1_COUNT (0x40002418) /**< \brief (RTC) MODE1 Counter Value */ +#define REG_RTC_MODE1_PER (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */ +#define REG_RTC_MODE1_COMP0 (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */ +#define REG_RTC_MODE1_COMP1 (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */ +#define REG_RTC_MODE1_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE1 Timestamp */ +#define REG_RTC_MODE2_CTRLA (0x40002400) /**< \brief (RTC) MODE2 Control A */ +#define REG_RTC_MODE2_CTRLB (0x40002402) /**< \brief (RTC) MODE2 Control B */ +#define REG_RTC_MODE2_EVCTRL (0x40002404) /**< \brief (RTC) MODE2 Event Control */ +#define REG_RTC_MODE2_INTENCLR (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ +#define REG_RTC_MODE2_INTENSET (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */ +#define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */ +#define REG_RTC_MODE2_CLOCK (0x40002418) /**< \brief (RTC) MODE2 Clock Value */ +#define REG_RTC_MODE2_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE2 Timestamp */ +#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ +#define REG_RTC_MODE2_ALARM_MASK0 (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ +#else +#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */ +#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */ +#define REG_RTC_GP0 (*(RwReg *)0x40002440UL) /**< \brief (RTC) General Purpose 0 */ +#define REG_RTC_GP1 (*(RwReg *)0x40002444UL) /**< \brief (RTC) General Purpose 1 */ +#define REG_RTC_TAMPCTRL (*(RwReg *)0x40002460UL) /**< \brief (RTC) Tamper Control */ +#define REG_RTC_TAMPID (*(RwReg *)0x40002468UL) /**< \brief (RTC) Tamper ID */ +#define REG_RTC_BKUP0 (*(RwReg *)0x40002480UL) /**< \brief (RTC) Backup 0 */ +#define REG_RTC_BKUP1 (*(RwReg *)0x40002484UL) /**< \brief (RTC) Backup 1 */ +#define REG_RTC_BKUP2 (*(RwReg *)0x40002488UL) /**< \brief (RTC) Backup 2 */ +#define REG_RTC_BKUP3 (*(RwReg *)0x4000248CUL) /**< \brief (RTC) Backup 3 */ +#define REG_RTC_BKUP4 (*(RwReg *)0x40002490UL) /**< \brief (RTC) Backup 4 */ +#define REG_RTC_BKUP5 (*(RwReg *)0x40002494UL) /**< \brief (RTC) Backup 5 */ +#define REG_RTC_BKUP6 (*(RwReg *)0x40002498UL) /**< \brief (RTC) Backup 6 */ +#define REG_RTC_BKUP7 (*(RwReg *)0x4000249CUL) /**< \brief (RTC) Backup 7 */ +#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */ +#define REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE0 Control B */ +#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */ +#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ +#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */ +#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */ +#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */ +#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */ +#define REG_RTC_MODE0_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE0 Timestamp */ +#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */ +#define REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE1 Control B */ +#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */ +#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ +#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */ +#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */ +#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */ +#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */ +#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */ +#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */ +#define REG_RTC_MODE1_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE1 Timestamp */ +#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */ +#define REG_RTC_MODE2_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE2 Control B */ +#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */ +#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ +#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */ +#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */ +#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */ +#define REG_RTC_MODE2_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE2 Timestamp */ +#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ +#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for RTC peripheral ========== */ +#define RTC_ALARM_NUM 1 // Number of Alarms +#define RTC_BKUP_NUM 8 // Number of Backup Registers +#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators +#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators +#define RTC_DMAC_ID_TIMESTAMP 1 // DMA RTC timestamp trigger +#define RTC_GPR_NUM 2 // Number of General-Purpose Registers +#define RTC_PER_NUM 8 // Number of Periodic Intervals +#define RTC_TAMPER_NUM 5 // Number of Tamper Inputs + +#endif /* _SAML22_RTC_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/sercom0.h b/watch-library/hardware/include/instance/sercom0.h new file mode 100644 index 00000000..7160d497 --- /dev/null +++ b/watch-library/hardware/include/instance/sercom0.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Instance description for SERCOM0 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM0_INSTANCE_ +#define _SAML22_SERCOM0_INSTANCE_ + +/* ========== Register definition for SERCOM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM0_I2CM_CTRLA (0x42000400) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (0x42000404) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (0x4200040C) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (0x42000414) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (0x42000416) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (0x42000418) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (0x4200041A) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) I2CM Synchronization Busy */ +#define REG_SERCOM0_I2CM_ADDR (0x42000424) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (0x42000428) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (0x42000430) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (0x42000400) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (0x42000404) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (0x42000414) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (0x42000416) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (0x42000418) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (0x4200041A) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) I2CS Synchronization Busy */ +#define REG_SERCOM0_I2CS_ADDR (0x42000424) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (0x42000428) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (0x42000400) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (0x42000404) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (0x4200040C) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (0x42000414) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (0x42000416) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (0x42000418) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (0x4200041A) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) SPI Synchronization Busy */ +#define REG_SERCOM0_SPI_ADDR (0x42000424) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (0x42000428) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (0x42000430) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (0x42000400) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (0x42000404) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_CTRLC (0x42000408) /**< \brief (SERCOM0) USART Control C */ +#define REG_SERCOM0_USART_BAUD (0x4200040C) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (0x4200040E) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (0x42000414) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (0x42000416) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (0x42000418) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (0x4200041A) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) USART Synchronization Busy */ +#define REG_SERCOM0_USART_RXERRCNT (0x42000420) /**< \brief (SERCOM0) USART Receive Error Count */ +#define REG_SERCOM0_USART_DATA (0x42000428) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (0x42000430) /**< \brief (SERCOM0) USART Debug Control */ +#else +#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200040CUL) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) I2CM Synchronization Busy */ +#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) I2CS Synchronization Busy */ +#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200040CUL) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) SPI Synchronization Busy */ +#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000428UL) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_CTRLC (*(RwReg *)0x42000408UL) /**< \brief (SERCOM0) USART Control C */ +#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200040CUL) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200040EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) USART Synchronization Busy */ +#define REG_SERCOM0_USART_RXERRCNT (*(RoReg8 *)0x42000420UL) /**< \brief (SERCOM0) USART Receive Error Count */ +#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000428UL) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM0 peripheral ========== */ +#define SERCOM0_DMAC_ID_RX 2 // Index of DMA RX trigger +#define SERCOM0_DMAC_ID_TX 3 // Index of DMA TX trigger +#define SERCOM0_GCLK_ID_CORE 16 +#define SERCOM0_GCLK_ID_SLOW 15 +#define SERCOM0_INT_MSB 6 +#define SERCOM0_PMSB 3 +#define SERCOM0_SPI 1 // SPI mode implemented? +#define SERCOM0_TWIM 0 // TWI Master mode implemented? +#define SERCOM0_TWIS 0 // TWI Slave mode implemented? +#define SERCOM0_TWI_HSMODE 0 // TWI HighSpeed mode implemented? +#define SERCOM0_USART 1 // USART mode implemented? +#define SERCOM0_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM0_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM0_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM0_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/sercom1.h b/watch-library/hardware/include/instance/sercom1.h new file mode 100644 index 00000000..1c0176ef --- /dev/null +++ b/watch-library/hardware/include/instance/sercom1.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Instance description for SERCOM1 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM1_INSTANCE_ +#define _SAML22_SERCOM1_INSTANCE_ + +/* ========== Register definition for SERCOM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM1_I2CM_CTRLA (0x42000800) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (0x42000804) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (0x4200080C) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (0x42000814) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (0x42000816) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (0x42000818) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (0x4200081A) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) I2CM Synchronization Busy */ +#define REG_SERCOM1_I2CM_ADDR (0x42000824) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (0x42000828) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (0x42000830) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (0x42000800) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (0x42000804) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (0x42000814) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (0x42000816) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (0x42000818) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (0x4200081A) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) I2CS Synchronization Busy */ +#define REG_SERCOM1_I2CS_ADDR (0x42000824) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (0x42000828) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (0x42000800) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (0x42000804) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (0x4200080C) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (0x42000814) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (0x42000816) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (0x42000818) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (0x4200081A) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) SPI Synchronization Busy */ +#define REG_SERCOM1_SPI_ADDR (0x42000824) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (0x42000828) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (0x42000830) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (0x42000800) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (0x42000804) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_CTRLC (0x42000808) /**< \brief (SERCOM1) USART Control C */ +#define REG_SERCOM1_USART_BAUD (0x4200080C) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (0x4200080E) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (0x42000814) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (0x42000816) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (0x42000818) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (0x4200081A) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) USART Synchronization Busy */ +#define REG_SERCOM1_USART_RXERRCNT (0x42000820) /**< \brief (SERCOM1) USART Receive Error Count */ +#define REG_SERCOM1_USART_DATA (0x42000828) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (0x42000830) /**< \brief (SERCOM1) USART Debug Control */ +#else +#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4200080CUL) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) I2CM Synchronization Busy */ +#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) I2CS Synchronization Busy */ +#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) SPI Synchronization Busy */ +#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000828UL) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x42000808UL) /**< \brief (SERCOM1) USART Control C */ +#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4200080CUL) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) USART Synchronization Busy */ +#define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x42000820UL) /**< \brief (SERCOM1) USART Receive Error Count */ +#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000828UL) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM1 peripheral ========== */ +#define SERCOM1_DMAC_ID_RX 4 // Index of DMA RX trigger +#define SERCOM1_DMAC_ID_TX 5 // Index of DMA TX trigger +#define SERCOM1_GCLK_ID_CORE 17 +#define SERCOM1_GCLK_ID_SLOW 15 +#define SERCOM1_INT_MSB 6 +#define SERCOM1_PMSB 3 +#define SERCOM1_SPI 1 // SPI mode implemented? +#define SERCOM1_TWIM 1 // TWI Master mode implemented? +#define SERCOM1_TWIS 1 // TWI Slave mode implemented? +#define SERCOM1_TWI_HSMODE 1 // TWI HighSpeed mode implemented? +#define SERCOM1_USART 1 // USART mode implemented? +#define SERCOM1_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM1_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM1_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM1_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/sercom2.h b/watch-library/hardware/include/instance/sercom2.h new file mode 100644 index 00000000..6c8458cc --- /dev/null +++ b/watch-library/hardware/include/instance/sercom2.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Instance description for SERCOM2 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM2_INSTANCE_ +#define _SAML22_SERCOM2_INSTANCE_ + +/* ========== Register definition for SERCOM2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM2_I2CM_CTRLA (0x42000C00) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (0x42000C04) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (0x42000C0C) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (0x42000C14) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (0x42000C16) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (0x42000C18) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (0x42000C1A) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) I2CM Synchronization Busy */ +#define REG_SERCOM2_I2CM_ADDR (0x42000C24) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (0x42000C28) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (0x42000C00) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (0x42000C04) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (0x42000C14) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (0x42000C16) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (0x42000C18) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (0x42000C1A) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) I2CS Synchronization Busy */ +#define REG_SERCOM2_I2CS_ADDR (0x42000C24) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (0x42000C28) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (0x42000C00) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (0x42000C04) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (0x42000C0C) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (0x42000C14) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (0x42000C16) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (0x42000C18) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (0x42000C1A) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) SPI Synchronization Busy */ +#define REG_SERCOM2_SPI_ADDR (0x42000C24) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (0x42000C28) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (0x42000C00) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (0x42000C04) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_CTRLC (0x42000C08) /**< \brief (SERCOM2) USART Control C */ +#define REG_SERCOM2_USART_BAUD (0x42000C0C) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (0x42000C0E) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (0x42000C14) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (0x42000C16) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (0x42000C18) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (0x42000C1A) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) USART Synchronization Busy */ +#define REG_SERCOM2_USART_RXERRCNT (0x42000C20) /**< \brief (SERCOM2) USART Receive Error Count */ +#define REG_SERCOM2_USART_DATA (0x42000C28) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) USART Debug Control */ +#else +#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x42000C0CUL) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) I2CM Synchronization Busy */ +#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) I2CS Synchronization Busy */ +#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) SPI Synchronization Busy */ +#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42000C28UL) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_CTRLC (*(RwReg *)0x42000C08UL) /**< \brief (SERCOM2) USART Control C */ +#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x42000C0CUL) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) USART Synchronization Busy */ +#define REG_SERCOM2_USART_RXERRCNT (*(RoReg8 *)0x42000C20UL) /**< \brief (SERCOM2) USART Receive Error Count */ +#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42000C28UL) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM2 peripheral ========== */ +#define SERCOM2_DMAC_ID_RX 6 // Index of DMA RX trigger +#define SERCOM2_DMAC_ID_TX 7 // Index of DMA TX trigger +#define SERCOM2_GCLK_ID_CORE 18 +#define SERCOM2_GCLK_ID_SLOW 15 +#define SERCOM2_INT_MSB 6 +#define SERCOM2_PMSB 3 +#define SERCOM2_SPI 1 // SPI mode implemented? +#define SERCOM2_TWIM 1 // TWI Master mode implemented? +#define SERCOM2_TWIS 1 // TWI Slave mode implemented? +#define SERCOM2_TWI_HSMODE 0 // TWI HighSpeed mode implemented? +#define SERCOM2_USART 1 // USART mode implemented? +#define SERCOM2_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM2_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM2_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM2_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/sercom3.h b/watch-library/hardware/include/instance/sercom3.h new file mode 100644 index 00000000..f7256e22 --- /dev/null +++ b/watch-library/hardware/include/instance/sercom3.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Instance description for SERCOM3 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM3_INSTANCE_ +#define _SAML22_SERCOM3_INSTANCE_ + +/* ========== Register definition for SERCOM3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM3_I2CM_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (0x4200100C) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CM Synchronization Busy */ +#define REG_SERCOM3_I2CM_ADDR (0x42001024) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (0x42001028) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (0x42001030) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CS Synchronization Busy */ +#define REG_SERCOM3_I2CS_ADDR (0x42001024) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (0x42001028) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (0x42001000) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (0x42001004) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (0x4200100C) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (0x42001014) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (0x42001016) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (0x42001018) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (0x4200101A) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) SPI Synchronization Busy */ +#define REG_SERCOM3_SPI_ADDR (0x42001024) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (0x42001028) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (0x42001030) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (0x42001000) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (0x42001004) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_CTRLC (0x42001008) /**< \brief (SERCOM3) USART Control C */ +#define REG_SERCOM3_USART_BAUD (0x4200100C) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (0x4200100E) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (0x42001014) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (0x42001016) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (0x42001018) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (0x4200101A) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) USART Synchronization Busy */ +#define REG_SERCOM3_USART_RXERRCNT (0x42001020) /**< \brief (SERCOM3) USART Receive Error Count */ +#define REG_SERCOM3_USART_DATA (0x42001028) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (0x42001030) /**< \brief (SERCOM3) USART Debug Control */ +#else +#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200100CUL) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CM Synchronization Busy */ +#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CS Synchronization Busy */ +#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) SPI Synchronization Busy */ +#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001028UL) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_CTRLC (*(RwReg *)0x42001008UL) /**< \brief (SERCOM3) USART Control C */ +#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200100CUL) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) USART Synchronization Busy */ +#define REG_SERCOM3_USART_RXERRCNT (*(RoReg8 *)0x42001020UL) /**< \brief (SERCOM3) USART Receive Error Count */ +#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001028UL) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM3 peripheral ========== */ +#define SERCOM3_DMAC_ID_RX 8 // Index of DMA RX trigger +#define SERCOM3_DMAC_ID_TX 9 // Index of DMA TX trigger +#define SERCOM3_GCLK_ID_CORE 19 +#define SERCOM3_GCLK_ID_SLOW 15 +#define SERCOM3_INT_MSB 6 +#define SERCOM3_PMSB 3 +#define SERCOM3_SPI 1 // SPI mode implemented? +#define SERCOM3_TWIM 1 // TWI Master mode implemented? +#define SERCOM3_TWIS 1 // TWI Slave mode implemented? +#define SERCOM3_TWI_HSMODE 0 // TWI HighSpeed mode implemented? +#define SERCOM3_USART 1 // USART mode implemented? +#define SERCOM3_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM3_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM3_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM3_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/sercom4.h b/watch-library/hardware/include/instance/sercom4.h new file mode 100644 index 00000000..d5f5d736 --- /dev/null +++ b/watch-library/hardware/include/instance/sercom4.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Instance description for SERCOM4 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM4_INSTANCE_ +#define _SAML22_SERCOM4_INSTANCE_ + +/* ========== Register definition for SERCOM4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM4_I2CM_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (0x4200140C) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CM Synchronization Busy */ +#define REG_SERCOM4_I2CM_ADDR (0x42001424) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (0x42001428) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (0x42001430) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CS Synchronization Busy */ +#define REG_SERCOM4_I2CS_ADDR (0x42001424) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (0x42001428) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (0x42001400) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (0x42001404) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (0x4200140C) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (0x42001414) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (0x42001416) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (0x42001418) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (0x4200141A) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) SPI Synchronization Busy */ +#define REG_SERCOM4_SPI_ADDR (0x42001424) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (0x42001428) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (0x42001430) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (0x42001400) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (0x42001404) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_CTRLC (0x42001408) /**< \brief (SERCOM4) USART Control C */ +#define REG_SERCOM4_USART_BAUD (0x4200140C) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (0x4200140E) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (0x42001414) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (0x42001416) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (0x42001418) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (0x4200141A) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) USART Synchronization Busy */ +#define REG_SERCOM4_USART_RXERRCNT (0x42001420) /**< \brief (SERCOM4) USART Receive Error Count */ +#define REG_SERCOM4_USART_DATA (0x42001428) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (0x42001430) /**< \brief (SERCOM4) USART Debug Control */ +#else +#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200140CUL) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CM Synchronization Busy */ +#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CS Synchronization Busy */ +#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) SPI Synchronization Busy */ +#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001428UL) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_CTRLC (*(RwReg *)0x42001408UL) /**< \brief (SERCOM4) USART Control C */ +#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200140CUL) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) USART Synchronization Busy */ +#define REG_SERCOM4_USART_RXERRCNT (*(RoReg8 *)0x42001420UL) /**< \brief (SERCOM4) USART Receive Error Count */ +#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001428UL) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM4 peripheral ========== */ +#define SERCOM4_DMAC_ID_RX 10 // Index of DMA RX trigger +#define SERCOM4_DMAC_ID_TX 11 // Index of DMA TX trigger +#define SERCOM4_GCLK_ID_CORE 20 +#define SERCOM4_GCLK_ID_SLOW 15 +#define SERCOM4_INT_MSB 6 +#define SERCOM4_PMSB 3 +#define SERCOM4_SPI 1 // SPI mode implemented? +#define SERCOM4_TWIM 1 // TWI Master mode implemented? +#define SERCOM4_TWIS 1 // TWI Slave mode implemented? +#define SERCOM4_TWI_HSMODE 0 // TWI HighSpeed mode implemented? +#define SERCOM4_USART 1 // USART mode implemented? +#define SERCOM4_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM4_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM4_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM4_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/sercom5.h b/watch-library/hardware/include/instance/sercom5.h new file mode 100644 index 00000000..93214cf3 --- /dev/null +++ b/watch-library/hardware/include/instance/sercom5.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Instance description for SERCOM5 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SERCOM5_INSTANCE_ +#define _SAML22_SERCOM5_INSTANCE_ + +/* ========== Register definition for SERCOM5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM5_I2CM_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (0x4200180C) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CM Synchronization Busy */ +#define REG_SERCOM5_I2CM_ADDR (0x42001824) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (0x42001828) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (0x42001830) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CS Synchronization Busy */ +#define REG_SERCOM5_I2CS_ADDR (0x42001824) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (0x42001828) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (0x42001800) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (0x42001804) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (0x4200180C) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (0x42001814) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (0x42001816) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (0x42001818) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (0x4200181A) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) SPI Synchronization Busy */ +#define REG_SERCOM5_SPI_ADDR (0x42001824) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (0x42001828) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (0x42001830) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (0x42001800) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (0x42001804) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_CTRLC (0x42001808) /**< \brief (SERCOM5) USART Control C */ +#define REG_SERCOM5_USART_BAUD (0x4200180C) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (0x4200180E) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (0x42001814) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (0x42001816) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (0x42001818) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (0x4200181A) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) USART Synchronization Busy */ +#define REG_SERCOM5_USART_RXERRCNT (0x42001820) /**< \brief (SERCOM5) USART Receive Error Count */ +#define REG_SERCOM5_USART_DATA (0x42001828) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (0x42001830) /**< \brief (SERCOM5) USART Debug Control */ +#else +#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4200180CUL) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CM Synchronization Busy */ +#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CS Synchronization Busy */ +#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) SPI Synchronization Busy */ +#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001828UL) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_CTRLC (*(RwReg *)0x42001808UL) /**< \brief (SERCOM5) USART Control C */ +#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4200180CUL) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) USART Synchronization Busy */ +#define REG_SERCOM5_USART_RXERRCNT (*(RoReg8 *)0x42001820UL) /**< \brief (SERCOM5) USART Receive Error Count */ +#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001828UL) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM5 peripheral ========== */ +#define SERCOM5_DMAC_ID_RX 12 // Index of DMA RX trigger +#define SERCOM5_DMAC_ID_TX 13 // Index of DMA TX trigger +#define SERCOM5_GCLK_ID_CORE 21 +#define SERCOM5_GCLK_ID_SLOW 15 +#define SERCOM5_INT_MSB 3 +#define SERCOM5_PMSB 3 +#define SERCOM5_SPI 1 // SPI mode implemented? +#define SERCOM5_TWIM 1 // TWI Master mode implemented? +#define SERCOM5_TWIS 1 // TWI Slave mode implemented? +#define SERCOM5_TWI_HSMODE 1 // TWI HighSpeed mode implemented? +#define SERCOM5_USART 1 // USART mode implemented? +#define SERCOM5_USART_ISO7816 1 // USART ISO7816 mode implemented? +#define SERCOM5_USART_LIN_MASTER 0 // USART LIN Master mode implemented? +#define SERCOM5_USART_RS485 1 // USART RS485 mode implemented? + +#endif /* _SAML22_SERCOM5_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/slcd.h b/watch-library/hardware/include/instance/slcd.h new file mode 100644 index 00000000..c4785831 --- /dev/null +++ b/watch-library/hardware/include/instance/slcd.h @@ -0,0 +1,126 @@ +/** + * \file + * + * \brief Instance description for SLCD + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SLCD_INSTANCE_ +#define _SAML22_SLCD_INSTANCE_ + +/* ========== Register definition for SLCD peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SLCD_CTRLA (0x42003C00) /**< \brief (SLCD) Control A */ +#define REG_SLCD_CTRLB (0x42003C04) /**< \brief (SLCD) Control B */ +#define REG_SLCD_CTRLC (0x42003C06) /**< \brief (SLCD) Control C */ +#define REG_SLCD_CTRLD (0x42003C08) /**< \brief (SLCD) Control D */ +#define REG_SLCD_EVCTRL (0x42003C0C) /**< \brief (SLCD) Event Control */ +#define REG_SLCD_INTENCLR (0x42003C0D) /**< \brief (SLCD) Interrupt Enable Clear */ +#define REG_SLCD_INTENSET (0x42003C0E) /**< \brief (SLCD) Interrupt Enable Set */ +#define REG_SLCD_INTFLAG (0x42003C0F) /**< \brief (SLCD) Interrupt Flag Status and Clear */ +#define REG_SLCD_STATUS (0x42003C10) /**< \brief (SLCD) Status */ +#define REG_SLCD_SYNCBUSY (0x42003C14) /**< \brief (SLCD) Synchronization Busy */ +#define REG_SLCD_FC0 (0x42003C18) /**< \brief (SLCD) Frame Counter 0 Configuration */ +#define REG_SLCD_FC1 (0x42003C19) /**< \brief (SLCD) Frame Counter 1 Configuration */ +#define REG_SLCD_FC2 (0x42003C1A) /**< \brief (SLCD) Frame Counter 2 Configuration */ +#define REG_SLCD_LPENL (0x42003C1C) /**< \brief (SLCD) LCD Pin Enable Low */ +#define REG_SLCD_LPENH (0x42003C20) /**< \brief (SLCD) LCD Pin Enable High */ +#define REG_SLCD_SDATAL0 (0x42003C24) /**< \brief (SLCD) Segments Data Low for COM0 Line */ +#define REG_SLCD_SDATAH0 (0x42003C28) /**< \brief (SLCD) Segments Data High for COM0 Line */ +#define REG_SLCD_SDATAL1 (0x42003C2C) /**< \brief (SLCD) Segments Data Low for COM1 Line */ +#define REG_SLCD_SDATAH1 (0x42003C30) /**< \brief (SLCD) Segments Data High for COM1 Line */ +#define REG_SLCD_SDATAL2 (0x42003C34) /**< \brief (SLCD) Segments Data Low for COM2 Line */ +#define REG_SLCD_SDATAH2 (0x42003C38) /**< \brief (SLCD) Segments Data High for COM2 Line */ +#define REG_SLCD_SDATAL3 (0x42003C3C) /**< \brief (SLCD) Segments Data Low for COM3 Line */ +#define REG_SLCD_SDATAH3 (0x42003C40) /**< \brief (SLCD) Segments Data High for COM3 Line */ +#define REG_SLCD_SDATAL4 (0x42003C44) /**< \brief (SLCD) Segments Data Low for COM4 Line */ +#define REG_SLCD_SDATAH4 (0x42003C48) /**< \brief (SLCD) Segments Data High for COM4 Line */ +#define REG_SLCD_SDATAL5 (0x42003C4C) /**< \brief (SLCD) Segments Data Low for COM5 Line */ +#define REG_SLCD_SDATAH5 (0x42003C50) /**< \brief (SLCD) Segments Data High for COM5 Line */ +#define REG_SLCD_SDATAL6 (0x42003C54) /**< \brief (SLCD) Segments Data Low for COM6 Line */ +#define REG_SLCD_SDATAH6 (0x42003C58) /**< \brief (SLCD) Segments Data High for COM6 Line */ +#define REG_SLCD_SDATAL7 (0x42003C5C) /**< \brief (SLCD) Segments Data Low for COM7 Line */ +#define REG_SLCD_SDATAH7 (0x42003C60) /**< \brief (SLCD) Segments Data High for COM7 Line */ +#define REG_SLCD_ISDATA (0x42003C64) /**< \brief (SLCD) Indirect Segments Data Access */ +#define REG_SLCD_BCFG (0x42003C68) /**< \brief (SLCD) Blink Configuration */ +#define REG_SLCD_CSRCFG (0x42003C6C) /**< \brief (SLCD) Circular Shift Register Configuration */ +#define REG_SLCD_CMCFG (0x42003C70) /**< \brief (SLCD) Character Mapping Configuration */ +#define REG_SLCD_ACMCFG (0x42003C74) /**< \brief (SLCD) Automated Character Mapping Configuration */ +#define REG_SLCD_ABMCFG (0x42003C78) /**< \brief (SLCD) Automated Bit Mapping Configuration */ +#define REG_SLCD_CMDATA (0x42003C7C) /**< \brief (SLCD) Character Mapping Segments Data */ +#define REG_SLCD_CMDMASK (0x42003C80) /**< \brief (SLCD) Character Mapping Segments Data Mask */ +#define REG_SLCD_CMINDEX (0x42003C84) /**< \brief (SLCD) Character Mapping SEG/COM Index */ +#else +#define REG_SLCD_CTRLA (*(RwReg *)0x42003C00UL) /**< \brief (SLCD) Control A */ +#define REG_SLCD_CTRLB (*(RwReg16*)0x42003C04UL) /**< \brief (SLCD) Control B */ +#define REG_SLCD_CTRLC (*(RwReg16*)0x42003C06UL) /**< \brief (SLCD) Control C */ +#define REG_SLCD_CTRLD (*(RwReg8 *)0x42003C08UL) /**< \brief (SLCD) Control D */ +#define REG_SLCD_EVCTRL (*(RwReg8 *)0x42003C0CUL) /**< \brief (SLCD) Event Control */ +#define REG_SLCD_INTENCLR (*(RwReg8 *)0x42003C0DUL) /**< \brief (SLCD) Interrupt Enable Clear */ +#define REG_SLCD_INTENSET (*(RwReg8 *)0x42003C0EUL) /**< \brief (SLCD) Interrupt Enable Set */ +#define REG_SLCD_INTFLAG (*(RwReg8 *)0x42003C0FUL) /**< \brief (SLCD) Interrupt Flag Status and Clear */ +#define REG_SLCD_STATUS (*(RoReg8 *)0x42003C10UL) /**< \brief (SLCD) Status */ +#define REG_SLCD_SYNCBUSY (*(RoReg *)0x42003C14UL) /**< \brief (SLCD) Synchronization Busy */ +#define REG_SLCD_FC0 (*(RwReg8 *)0x42003C18UL) /**< \brief (SLCD) Frame Counter 0 Configuration */ +#define REG_SLCD_FC1 (*(RwReg8 *)0x42003C19UL) /**< \brief (SLCD) Frame Counter 1 Configuration */ +#define REG_SLCD_FC2 (*(RwReg8 *)0x42003C1AUL) /**< \brief (SLCD) Frame Counter 2 Configuration */ +#define REG_SLCD_LPENL (*(RwReg *)0x42003C1CUL) /**< \brief (SLCD) LCD Pin Enable Low */ +#define REG_SLCD_LPENH (*(RwReg *)0x42003C20UL) /**< \brief (SLCD) LCD Pin Enable High */ +#define REG_SLCD_SDATAL0 (*(RwReg *)0x42003C24UL) /**< \brief (SLCD) Segments Data Low for COM0 Line */ +#define REG_SLCD_SDATAH0 (*(RwReg *)0x42003C28UL) /**< \brief (SLCD) Segments Data High for COM0 Line */ +#define REG_SLCD_SDATAL1 (*(RwReg *)0x42003C2CUL) /**< \brief (SLCD) Segments Data Low for COM1 Line */ +#define REG_SLCD_SDATAH1 (*(RwReg *)0x42003C30UL) /**< \brief (SLCD) Segments Data High for COM1 Line */ +#define REG_SLCD_SDATAL2 (*(RwReg *)0x42003C34UL) /**< \brief (SLCD) Segments Data Low for COM2 Line */ +#define REG_SLCD_SDATAH2 (*(RwReg *)0x42003C38UL) /**< \brief (SLCD) Segments Data High for COM2 Line */ +#define REG_SLCD_SDATAL3 (*(RwReg *)0x42003C3CUL) /**< \brief (SLCD) Segments Data Low for COM3 Line */ +#define REG_SLCD_SDATAH3 (*(RwReg *)0x42003C40UL) /**< \brief (SLCD) Segments Data High for COM3 Line */ +#define REG_SLCD_SDATAL4 (*(RwReg *)0x42003C44UL) /**< \brief (SLCD) Segments Data Low for COM4 Line */ +#define REG_SLCD_SDATAH4 (*(RwReg *)0x42003C48UL) /**< \brief (SLCD) Segments Data High for COM4 Line */ +#define REG_SLCD_SDATAL5 (*(RwReg *)0x42003C4CUL) /**< \brief (SLCD) Segments Data Low for COM5 Line */ +#define REG_SLCD_SDATAH5 (*(RwReg *)0x42003C50UL) /**< \brief (SLCD) Segments Data High for COM5 Line */ +#define REG_SLCD_SDATAL6 (*(RwReg *)0x42003C54UL) /**< \brief (SLCD) Segments Data Low for COM6 Line */ +#define REG_SLCD_SDATAH6 (*(RwReg *)0x42003C58UL) /**< \brief (SLCD) Segments Data High for COM6 Line */ +#define REG_SLCD_SDATAL7 (*(RwReg *)0x42003C5CUL) /**< \brief (SLCD) Segments Data Low for COM7 Line */ +#define REG_SLCD_SDATAH7 (*(RwReg *)0x42003C60UL) /**< \brief (SLCD) Segments Data High for COM7 Line */ +#define REG_SLCD_ISDATA (*(WoReg *)0x42003C64UL) /**< \brief (SLCD) Indirect Segments Data Access */ +#define REG_SLCD_BCFG (*(RwReg *)0x42003C68UL) /**< \brief (SLCD) Blink Configuration */ +#define REG_SLCD_CSRCFG (*(RwReg *)0x42003C6CUL) /**< \brief (SLCD) Circular Shift Register Configuration */ +#define REG_SLCD_CMCFG (*(RwReg8 *)0x42003C70UL) /**< \brief (SLCD) Character Mapping Configuration */ +#define REG_SLCD_ACMCFG (*(RwReg *)0x42003C74UL) /**< \brief (SLCD) Automated Character Mapping Configuration */ +#define REG_SLCD_ABMCFG (*(RwReg8 *)0x42003C78UL) /**< \brief (SLCD) Automated Bit Mapping Configuration */ +#define REG_SLCD_CMDATA (*(WoReg *)0x42003C7CUL) /**< \brief (SLCD) Character Mapping Segments Data */ +#define REG_SLCD_CMDMASK (*(RwReg *)0x42003C80UL) /**< \brief (SLCD) Character Mapping Segments Data Mask */ +#define REG_SLCD_CMINDEX (*(RwReg16*)0x42003C84UL) /**< \brief (SLCD) Character Mapping SEG/COM Index */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SLCD peripheral ========== */ +#define SLCD_DMAC_ID_ABMDRDY 34 +#define SLCD_DMAC_ID_ACMDRDY 33 +#define SLCD_DMAC_ID_DMU 32 +#define SLCD_MAX_COM 8 // Max number of COM lines (4 or 8) +#define SLCD_MAX_SEG 44 // Max number of SEG lines (24 or 44) +#define SLCD_NB_LP 52 // Number of LCD pins ([28..64] or [48..64]) + +#endif /* _SAML22_SLCD_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/supc.h b/watch-library/hardware/include/instance/supc.h new file mode 100644 index 00000000..0800c5f3 --- /dev/null +++ b/watch-library/hardware/include/instance/supc.h @@ -0,0 +1,65 @@ +/** + * \file + * + * \brief Instance description for SUPC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_SUPC_INSTANCE_ +#define _SAML22_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SUPC_INTENCLR (0x40001800) /**< \brief (SUPC) Interrupt Enable Clear */ +#define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ +#define REG_SUPC_INTFLAG (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */ +#define REG_SUPC_STATUS (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */ +#define REG_SUPC_BOD33 (0x40001810) /**< \brief (SUPC) BOD33 Control */ +#define REG_SUPC_BOD12 (0x40001814) /**< \brief (SUPC) BOD12 Control */ +#define REG_SUPC_VREG (0x40001818) /**< \brief (SUPC) VREG Control */ +#define REG_SUPC_VREF (0x4000181C) /**< \brief (SUPC) VREF Control */ +#define REG_SUPC_BBPS (0x40001820) /**< \brief (SUPC) Battery Backup Power Switch */ +#define REG_SUPC_BKOUT (0x40001824) /**< \brief (SUPC) Backup Output Control */ +#define REG_SUPC_BKIN (0x40001828) /**< \brief (SUPC) Backup Input Control */ +#else +#define REG_SUPC_INTENCLR (*(RwReg *)0x40001800UL) /**< \brief (SUPC) Interrupt Enable Clear */ +#define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Set */ +#define REG_SUPC_INTFLAG (*(RwReg *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */ +#define REG_SUPC_STATUS (*(RoReg *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */ +#define REG_SUPC_BOD33 (*(RwReg *)0x40001810UL) /**< \brief (SUPC) BOD33 Control */ +#define REG_SUPC_BOD12 (*(RwReg *)0x40001814UL) /**< \brief (SUPC) BOD12 Control */ +#define REG_SUPC_VREG (*(RwReg *)0x40001818UL) /**< \brief (SUPC) VREG Control */ +#define REG_SUPC_VREF (*(RwReg *)0x4000181CUL) /**< \brief (SUPC) VREF Control */ +#define REG_SUPC_BBPS (*(RwReg *)0x40001820UL) /**< \brief (SUPC) Battery Backup Power Switch */ +#define REG_SUPC_BKOUT (*(RwReg *)0x40001824UL) /**< \brief (SUPC) Backup Output Control */ +#define REG_SUPC_BKIN (*(RoReg *)0x40001828UL) /**< \brief (SUPC) Backup Input Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SUPC peripheral ========== */ +#define SUPC_BOD12_CALIB_MSB 5 +#define SUPC_BOD33_CALIB_MSB 5 +#define SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number + +#endif /* _SAML22_SUPC_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/tc0.h b/watch-library/hardware/include/instance/tc0.h new file mode 100644 index 00000000..a50b87e9 --- /dev/null +++ b/watch-library/hardware/include/instance/tc0.h @@ -0,0 +1,109 @@ +/** + * \file + * + * \brief Instance description for TC0 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TC0_INSTANCE_ +#define _SAML22_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC0_CTRLA (0x42002000) /**< \brief (TC0) Control A */ +#define REG_TC0_CTRLBCLR (0x42002004) /**< \brief (TC0) Control B Clear */ +#define REG_TC0_CTRLBSET (0x42002005) /**< \brief (TC0) Control B Set */ +#define REG_TC0_EVCTRL (0x42002006) /**< \brief (TC0) Event Control */ +#define REG_TC0_INTENCLR (0x42002008) /**< \brief (TC0) Interrupt Enable Clear */ +#define REG_TC0_INTENSET (0x42002009) /**< \brief (TC0) Interrupt Enable Set */ +#define REG_TC0_INTFLAG (0x4200200A) /**< \brief (TC0) Interrupt Flag Status and Clear */ +#define REG_TC0_STATUS (0x4200200B) /**< \brief (TC0) Status */ +#define REG_TC0_WAVE (0x4200200C) /**< \brief (TC0) Waveform Generation Control */ +#define REG_TC0_DRVCTRL (0x4200200D) /**< \brief (TC0) Control C */ +#define REG_TC0_DBGCTRL (0x4200200F) /**< \brief (TC0) Debug Control */ +#define REG_TC0_SYNCBUSY (0x42002010) /**< \brief (TC0) Synchronization Status */ +#define REG_TC0_COUNT16_COUNT (0x42002014) /**< \brief (TC0) COUNT16 Count */ +#define REG_TC0_COUNT16_CC0 (0x4200201C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ +#define REG_TC0_COUNT16_CC1 (0x4200201E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ +#define REG_TC0_COUNT16_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT16_CCBUF1 (0x42002032) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT32_COUNT (0x42002014) /**< \brief (TC0) COUNT32 Count */ +#define REG_TC0_COUNT32_CC0 (0x4200201C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ +#define REG_TC0_COUNT32_CC1 (0x42002020) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ +#define REG_TC0_COUNT32_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT32_CCBUF1 (0x42002034) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT8_COUNT (0x42002014) /**< \brief (TC0) COUNT8 Count */ +#define REG_TC0_COUNT8_PER (0x4200201B) /**< \brief (TC0) COUNT8 Period */ +#define REG_TC0_COUNT8_CC0 (0x4200201C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ +#define REG_TC0_COUNT8_CC1 (0x4200201D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ +#define REG_TC0_COUNT8_PERBUF (0x4200202F) /**< \brief (TC0) COUNT8 Period Buffer */ +#define REG_TC0_COUNT8_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT8_CCBUF1 (0x42002031) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC0_CTRLA (*(RwReg *)0x42002000UL) /**< \brief (TC0) Control A */ +#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004UL) /**< \brief (TC0) Control B Clear */ +#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005UL) /**< \brief (TC0) Control B Set */ +#define REG_TC0_EVCTRL (*(RwReg16*)0x42002006UL) /**< \brief (TC0) Event Control */ +#define REG_TC0_INTENCLR (*(RwReg8 *)0x42002008UL) /**< \brief (TC0) Interrupt Enable Clear */ +#define REG_TC0_INTENSET (*(RwReg8 *)0x42002009UL) /**< \brief (TC0) Interrupt Enable Set */ +#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */ +#define REG_TC0_STATUS (*(RwReg8 *)0x4200200BUL) /**< \brief (TC0) Status */ +#define REG_TC0_WAVE (*(RwReg8 *)0x4200200CUL) /**< \brief (TC0) Waveform Generation Control */ +#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200200DUL) /**< \brief (TC0) Control C */ +#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200200FUL) /**< \brief (TC0) Debug Control */ +#define REG_TC0_SYNCBUSY (*(RoReg *)0x42002010UL) /**< \brief (TC0) Synchronization Status */ +#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002014UL) /**< \brief (TC0) COUNT16 Count */ +#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4200201CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ +#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ +#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x42002030UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x42002032UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002014UL) /**< \brief (TC0) COUNT32 Count */ +#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200201CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ +#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42002020UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ +#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42002030UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42002034UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002014UL) /**< \brief (TC0) COUNT8 Count */ +#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4200201BUL) /**< \brief (TC0) COUNT8 Period */ +#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4200201CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ +#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4200201DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ +#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4200202FUL) /**< \brief (TC0) COUNT8 Period Buffer */ +#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x42002030UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x42002031UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC0 peripheral ========== */ +#define TC0_CC_NUM 2 +#define TC0_DMAC_ID_MC_0 20 +#define TC0_DMAC_ID_MC_1 21 +#define TC0_DMAC_ID_MC_LSB 20 +#define TC0_DMAC_ID_MC_MSB 21 +#define TC0_DMAC_ID_MC_SIZE 2 +#define TC0_DMAC_ID_OVF 19 // Indexes of DMA Overflow trigger +#define TC0_EXT 0 +#define TC0_GCLK_ID 23 +#define TC0_MASTER 1 +#define TC0_OW_NUM 2 + +#endif /* _SAML22_TC0_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/tc1.h b/watch-library/hardware/include/instance/tc1.h new file mode 100644 index 00000000..9acada8a --- /dev/null +++ b/watch-library/hardware/include/instance/tc1.h @@ -0,0 +1,109 @@ +/** + * \file + * + * \brief Instance description for TC1 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TC1_INSTANCE_ +#define _SAML22_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC1_CTRLA (0x42002400) /**< \brief (TC1) Control A */ +#define REG_TC1_CTRLBCLR (0x42002404) /**< \brief (TC1) Control B Clear */ +#define REG_TC1_CTRLBSET (0x42002405) /**< \brief (TC1) Control B Set */ +#define REG_TC1_EVCTRL (0x42002406) /**< \brief (TC1) Event Control */ +#define REG_TC1_INTENCLR (0x42002408) /**< \brief (TC1) Interrupt Enable Clear */ +#define REG_TC1_INTENSET (0x42002409) /**< \brief (TC1) Interrupt Enable Set */ +#define REG_TC1_INTFLAG (0x4200240A) /**< \brief (TC1) Interrupt Flag Status and Clear */ +#define REG_TC1_STATUS (0x4200240B) /**< \brief (TC1) Status */ +#define REG_TC1_WAVE (0x4200240C) /**< \brief (TC1) Waveform Generation Control */ +#define REG_TC1_DRVCTRL (0x4200240D) /**< \brief (TC1) Control C */ +#define REG_TC1_DBGCTRL (0x4200240F) /**< \brief (TC1) Debug Control */ +#define REG_TC1_SYNCBUSY (0x42002410) /**< \brief (TC1) Synchronization Status */ +#define REG_TC1_COUNT16_COUNT (0x42002414) /**< \brief (TC1) COUNT16 Count */ +#define REG_TC1_COUNT16_CC0 (0x4200241C) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ +#define REG_TC1_COUNT16_CC1 (0x4200241E) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ +#define REG_TC1_COUNT16_CCBUF0 (0x42002430) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT16_CCBUF1 (0x42002432) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT32_COUNT (0x42002414) /**< \brief (TC1) COUNT32 Count */ +#define REG_TC1_COUNT32_CC0 (0x4200241C) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ +#define REG_TC1_COUNT32_CC1 (0x42002420) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ +#define REG_TC1_COUNT32_CCBUF0 (0x42002430) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT32_CCBUF1 (0x42002434) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT8_COUNT (0x42002414) /**< \brief (TC1) COUNT8 Count */ +#define REG_TC1_COUNT8_PER (0x4200241B) /**< \brief (TC1) COUNT8 Period */ +#define REG_TC1_COUNT8_CC0 (0x4200241C) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ +#define REG_TC1_COUNT8_CC1 (0x4200241D) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ +#define REG_TC1_COUNT8_PERBUF (0x4200242F) /**< \brief (TC1) COUNT8 Period Buffer */ +#define REG_TC1_COUNT8_CCBUF0 (0x42002430) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT8_CCBUF1 (0x42002431) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC1_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (TC1) Control A */ +#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42002404UL) /**< \brief (TC1) Control B Clear */ +#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42002405UL) /**< \brief (TC1) Control B Set */ +#define REG_TC1_EVCTRL (*(RwReg16*)0x42002406UL) /**< \brief (TC1) Event Control */ +#define REG_TC1_INTENCLR (*(RwReg8 *)0x42002408UL) /**< \brief (TC1) Interrupt Enable Clear */ +#define REG_TC1_INTENSET (*(RwReg8 *)0x42002409UL) /**< \brief (TC1) Interrupt Enable Set */ +#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200240AUL) /**< \brief (TC1) Interrupt Flag Status and Clear */ +#define REG_TC1_STATUS (*(RwReg8 *)0x4200240BUL) /**< \brief (TC1) Status */ +#define REG_TC1_WAVE (*(RwReg8 *)0x4200240CUL) /**< \brief (TC1) Waveform Generation Control */ +#define REG_TC1_DRVCTRL (*(RwReg8 *)0x4200240DUL) /**< \brief (TC1) Control C */ +#define REG_TC1_DBGCTRL (*(RwReg8 *)0x4200240FUL) /**< \brief (TC1) Debug Control */ +#define REG_TC1_SYNCBUSY (*(RoReg *)0x42002410UL) /**< \brief (TC1) Synchronization Status */ +#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42002414UL) /**< \brief (TC1) COUNT16 Count */ +#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x4200241CUL) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ +#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200241EUL) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ +#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x42002430UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x42002432UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42002414UL) /**< \brief (TC1) COUNT32 Count */ +#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x4200241CUL) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ +#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x42002420UL) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ +#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x42002430UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x42002434UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42002414UL) /**< \brief (TC1) COUNT8 Count */ +#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x4200241BUL) /**< \brief (TC1) COUNT8 Period */ +#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x4200241CUL) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ +#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x4200241DUL) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ +#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x4200242FUL) /**< \brief (TC1) COUNT8 Period Buffer */ +#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x42002430UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x42002431UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC1 peripheral ========== */ +#define TC1_CC_NUM 2 +#define TC1_DMAC_ID_MC_0 23 +#define TC1_DMAC_ID_MC_1 24 +#define TC1_DMAC_ID_MC_LSB 23 +#define TC1_DMAC_ID_MC_MSB 24 +#define TC1_DMAC_ID_MC_SIZE 2 +#define TC1_DMAC_ID_OVF 22 // Indexes of DMA Overflow trigger +#define TC1_EXT 0 +#define TC1_GCLK_ID 23 +#define TC1_MASTER 0 +#define TC1_OW_NUM 2 + +#endif /* _SAML22_TC1_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/tc2.h b/watch-library/hardware/include/instance/tc2.h new file mode 100644 index 00000000..13b8fb2a --- /dev/null +++ b/watch-library/hardware/include/instance/tc2.h @@ -0,0 +1,109 @@ +/** + * \file + * + * \brief Instance description for TC2 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TC2_INSTANCE_ +#define _SAML22_TC2_INSTANCE_ + +/* ========== Register definition for TC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC2_CTRLA (0x42002800) /**< \brief (TC2) Control A */ +#define REG_TC2_CTRLBCLR (0x42002804) /**< \brief (TC2) Control B Clear */ +#define REG_TC2_CTRLBSET (0x42002805) /**< \brief (TC2) Control B Set */ +#define REG_TC2_EVCTRL (0x42002806) /**< \brief (TC2) Event Control */ +#define REG_TC2_INTENCLR (0x42002808) /**< \brief (TC2) Interrupt Enable Clear */ +#define REG_TC2_INTENSET (0x42002809) /**< \brief (TC2) Interrupt Enable Set */ +#define REG_TC2_INTFLAG (0x4200280A) /**< \brief (TC2) Interrupt Flag Status and Clear */ +#define REG_TC2_STATUS (0x4200280B) /**< \brief (TC2) Status */ +#define REG_TC2_WAVE (0x4200280C) /**< \brief (TC2) Waveform Generation Control */ +#define REG_TC2_DRVCTRL (0x4200280D) /**< \brief (TC2) Control C */ +#define REG_TC2_DBGCTRL (0x4200280F) /**< \brief (TC2) Debug Control */ +#define REG_TC2_SYNCBUSY (0x42002810) /**< \brief (TC2) Synchronization Status */ +#define REG_TC2_COUNT16_COUNT (0x42002814) /**< \brief (TC2) COUNT16 Count */ +#define REG_TC2_COUNT16_CC0 (0x4200281C) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ +#define REG_TC2_COUNT16_CC1 (0x4200281E) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ +#define REG_TC2_COUNT16_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT16_CCBUF1 (0x42002832) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT32_COUNT (0x42002814) /**< \brief (TC2) COUNT32 Count */ +#define REG_TC2_COUNT32_CC0 (0x4200281C) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ +#define REG_TC2_COUNT32_CC1 (0x42002820) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ +#define REG_TC2_COUNT32_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT32_CCBUF1 (0x42002834) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT8_COUNT (0x42002814) /**< \brief (TC2) COUNT8 Count */ +#define REG_TC2_COUNT8_PER (0x4200281B) /**< \brief (TC2) COUNT8 Period */ +#define REG_TC2_COUNT8_CC0 (0x4200281C) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ +#define REG_TC2_COUNT8_CC1 (0x4200281D) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ +#define REG_TC2_COUNT8_PERBUF (0x4200282F) /**< \brief (TC2) COUNT8 Period Buffer */ +#define REG_TC2_COUNT8_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT8_CCBUF1 (0x42002831) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC2_CTRLA (*(RwReg *)0x42002800UL) /**< \brief (TC2) Control A */ +#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804UL) /**< \brief (TC2) Control B Clear */ +#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805UL) /**< \brief (TC2) Control B Set */ +#define REG_TC2_EVCTRL (*(RwReg16*)0x42002806UL) /**< \brief (TC2) Event Control */ +#define REG_TC2_INTENCLR (*(RwReg8 *)0x42002808UL) /**< \brief (TC2) Interrupt Enable Clear */ +#define REG_TC2_INTENSET (*(RwReg8 *)0x42002809UL) /**< \brief (TC2) Interrupt Enable Set */ +#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280AUL) /**< \brief (TC2) Interrupt Flag Status and Clear */ +#define REG_TC2_STATUS (*(RwReg8 *)0x4200280BUL) /**< \brief (TC2) Status */ +#define REG_TC2_WAVE (*(RwReg8 *)0x4200280CUL) /**< \brief (TC2) Waveform Generation Control */ +#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200280DUL) /**< \brief (TC2) Control C */ +#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200280FUL) /**< \brief (TC2) Debug Control */ +#define REG_TC2_SYNCBUSY (*(RoReg *)0x42002810UL) /**< \brief (TC2) Synchronization Status */ +#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42002814UL) /**< \brief (TC2) COUNT16 Count */ +#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4200281CUL) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ +#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200281EUL) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ +#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x42002830UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x42002832UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42002814UL) /**< \brief (TC2) COUNT32 Count */ +#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4200281CUL) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ +#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42002820UL) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ +#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x42002830UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x42002834UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002814UL) /**< \brief (TC2) COUNT8 Count */ +#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4200281BUL) /**< \brief (TC2) COUNT8 Period */ +#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4200281CUL) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ +#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4200281DUL) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ +#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4200282FUL) /**< \brief (TC2) COUNT8 Period Buffer */ +#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x42002830UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x42002831UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC2 peripheral ========== */ +#define TC2_CC_NUM 2 +#define TC2_DMAC_ID_MC_0 26 +#define TC2_DMAC_ID_MC_1 27 +#define TC2_DMAC_ID_MC_LSB 26 +#define TC2_DMAC_ID_MC_MSB 27 +#define TC2_DMAC_ID_MC_SIZE 2 +#define TC2_DMAC_ID_OVF 25 // Indexes of DMA Overflow trigger +#define TC2_EXT 0 +#define TC2_GCLK_ID 24 +#define TC2_MASTER 1 +#define TC2_OW_NUM 2 + +#endif /* _SAML22_TC2_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/tc3.h b/watch-library/hardware/include/instance/tc3.h new file mode 100644 index 00000000..7555903a --- /dev/null +++ b/watch-library/hardware/include/instance/tc3.h @@ -0,0 +1,109 @@ +/** + * \file + * + * \brief Instance description for TC3 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TC3_INSTANCE_ +#define _SAML22_TC3_INSTANCE_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC3_CTRLA (0x42002C00) /**< \brief (TC3) Control A */ +#define REG_TC3_CTRLBCLR (0x42002C04) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (0x42002C05) /**< \brief (TC3) Control B Set */ +#define REG_TC3_EVCTRL (0x42002C06) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (0x42002C08) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (0x42002C09) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (0x42002C0A) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (0x42002C0B) /**< \brief (TC3) Status */ +#define REG_TC3_WAVE (0x42002C0C) /**< \brief (TC3) Waveform Generation Control */ +#define REG_TC3_DRVCTRL (0x42002C0D) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (0x42002C0F) /**< \brief (TC3) Debug Control */ +#define REG_TC3_SYNCBUSY (0x42002C10) /**< \brief (TC3) Synchronization Status */ +#define REG_TC3_COUNT16_COUNT (0x42002C14) /**< \brief (TC3) COUNT16 Count */ +#define REG_TC3_COUNT16_CC0 (0x42002C1C) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ +#define REG_TC3_COUNT16_CC1 (0x42002C1E) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ +#define REG_TC3_COUNT16_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT16_CCBUF1 (0x42002C32) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT32_COUNT (0x42002C14) /**< \brief (TC3) COUNT32 Count */ +#define REG_TC3_COUNT32_CC0 (0x42002C1C) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ +#define REG_TC3_COUNT32_CC1 (0x42002C20) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ +#define REG_TC3_COUNT32_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT32_CCBUF1 (0x42002C34) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT8_COUNT (0x42002C14) /**< \brief (TC3) COUNT8 Count */ +#define REG_TC3_COUNT8_PER (0x42002C1B) /**< \brief (TC3) COUNT8 Period */ +#define REG_TC3_COUNT8_CC0 (0x42002C1C) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ +#define REG_TC3_COUNT8_CC1 (0x42002C1D) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ +#define REG_TC3_COUNT8_PERBUF (0x42002C2F) /**< \brief (TC3) COUNT8 Period Buffer */ +#define REG_TC3_COUNT8_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT8_CCBUF1 (0x42002C31) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC3_CTRLA (*(RwReg *)0x42002C00UL) /**< \brief (TC3) Control A */ +#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TC3) Control B Set */ +#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C06UL) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C08UL) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C09UL) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0AUL) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (*(RwReg8 *)0x42002C0BUL) /**< \brief (TC3) Status */ +#define REG_TC3_WAVE (*(RwReg8 *)0x42002C0CUL) /**< \brief (TC3) Waveform Generation Control */ +#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42002C0DUL) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C0FUL) /**< \brief (TC3) Debug Control */ +#define REG_TC3_SYNCBUSY (*(RoReg *)0x42002C10UL) /**< \brief (TC3) Synchronization Status */ +#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C14UL) /**< \brief (TC3) COUNT16 Count */ +#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C1CUL) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ +#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1EUL) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ +#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42002C30UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42002C32UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C14UL) /**< \brief (TC3) COUNT32 Count */ +#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C1CUL) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ +#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C20UL) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ +#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42002C30UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42002C34UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C14UL) /**< \brief (TC3) COUNT8 Count */ +#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C1BUL) /**< \brief (TC3) COUNT8 Period */ +#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C1CUL) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ +#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C1DUL) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ +#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42002C2FUL) /**< \brief (TC3) COUNT8 Period Buffer */ +#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42002C30UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42002C31UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC3 peripheral ========== */ +#define TC3_CC_NUM 2 +#define TC3_DMAC_ID_MC_0 29 +#define TC3_DMAC_ID_MC_1 30 +#define TC3_DMAC_ID_MC_LSB 29 +#define TC3_DMAC_ID_MC_MSB 30 +#define TC3_DMAC_ID_MC_SIZE 2 +#define TC3_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger +#define TC3_EXT 0 +#define TC3_GCLK_ID 24 +#define TC3_MASTER 0 +#define TC3_OW_NUM 2 + +#endif /* _SAML22_TC3_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/tcc0.h b/watch-library/hardware/include/instance/tcc0.h new file mode 100644 index 00000000..e5567d45 --- /dev/null +++ b/watch-library/hardware/include/instance/tcc0.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Instance description for TCC0 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TCC0_INSTANCE_ +#define _SAML22_TCC0_INSTANCE_ + +/* ========== Register definition for TCC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC0_CTRLA (0x42001C00) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (0x42001C04) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (0x42001C05) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (0x42001C08) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (0x42001C0C) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (0x42001C10) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (0x42001C14) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (0x42001C18) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (0x42001C1E) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (0x42001C20) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (0x42001C24) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (0x42001C28) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (0x42001C2C) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (0x42001C30) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (0x42001C34) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (0x42001C38) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (0x42001C3C) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (0x42001C40) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (0x42001C44) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (0x42001C48) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (0x42001C4C) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (0x42001C50) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTBUF (0x42001C64) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_PERBUF (0x42001C6C) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCBUF0 (0x42001C70) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCBUF1 (0x42001C74) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCBUF2 (0x42001C78) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCBUF3 (0x42001C7C) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#else +#define REG_TCC0_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42001C04UL) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42001C05UL) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42001C08UL) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (*(RwReg *)0x42001C0CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (*(RwReg *)0x42001C10UL) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (*(RwReg *)0x42001C14UL) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (*(RwReg *)0x42001C18UL) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x42001C1EUL) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (*(RwReg *)0x42001C20UL) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (*(RwReg *)0x42001C24UL) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (*(RwReg *)0x42001C28UL) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (*(RwReg *)0x42001C2CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (*(RwReg *)0x42001C30UL) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (*(RwReg *)0x42001C34UL) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (*(RwReg16*)0x42001C38UL) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (*(RwReg *)0x42001C3CUL) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (*(RwReg *)0x42001C40UL) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (*(RwReg *)0x42001C44UL) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (*(RwReg *)0x42001C48UL) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (*(RwReg *)0x42001C4CUL) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (*(RwReg *)0x42001C50UL) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTBUF (*(RwReg16*)0x42001C64UL) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_PERBUF (*(RwReg *)0x42001C6CUL) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCBUF0 (*(RwReg *)0x42001C70UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCBUF1 (*(RwReg *)0x42001C74UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCBUF2 (*(RwReg *)0x42001C78UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCBUF3 (*(RwReg *)0x42001C7CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC0 peripheral ========== */ +#define TCC0_CC_NUM 4 // Number of Compare/Capture units +#define TCC0_DITHERING 1 // Dithering feature implemented +#define TCC0_DMAC_ID_MC_0 15 +#define TCC0_DMAC_ID_MC_1 16 +#define TCC0_DMAC_ID_MC_2 17 +#define TCC0_DMAC_ID_MC_3 18 +#define TCC0_DMAC_ID_MC_LSB 15 +#define TCC0_DMAC_ID_MC_MSB 18 +#define TCC0_DMAC_ID_MC_SIZE 4 +#define TCC0_DMAC_ID_OVF 14 // DMA overflow/underflow/retrigger trigger +#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented +#define TCC0_EXT 31 // Coding of implemented extended features +#define TCC0_GCLK_ID 22 // Index of Generic Clock +#define TCC0_OTMX 1 // Output Matrix feature implemented +#define TCC0_OW_NUM 8 // Number of Output Waveforms +#define TCC0_PG 1 // Pattern Generation feature implemented +#define TCC0_SIZE 24 +#define TCC0_SWAP 1 // DTI outputs swap feature implemented +#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif /* _SAML22_TCC0_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/trng.h b/watch-library/hardware/include/instance/trng.h new file mode 100644 index 00000000..0f80f00a --- /dev/null +++ b/watch-library/hardware/include/instance/trng.h @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief Instance description for TRNG + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TRNG_INSTANCE_ +#define _SAML22_TRNG_INSTANCE_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TRNG_CTRLA (0x42004400) /**< \brief (TRNG) Control A */ +#define REG_TRNG_EVCTRL (0x42004404) /**< \brief (TRNG) Event Control */ +#define REG_TRNG_INTENCLR (0x42004408) /**< \brief (TRNG) Interrupt Enable Clear */ +#define REG_TRNG_INTENSET (0x42004409) /**< \brief (TRNG) Interrupt Enable Set */ +#define REG_TRNG_INTFLAG (0x4200440A) /**< \brief (TRNG) Interrupt Flag Status and Clear */ +#define REG_TRNG_DATA (0x42004420) /**< \brief (TRNG) Output Data */ +#else +#define REG_TRNG_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (TRNG) Control A */ +#define REG_TRNG_EVCTRL (*(RwReg8 *)0x42004404UL) /**< \brief (TRNG) Event Control */ +#define REG_TRNG_INTENCLR (*(RwReg8 *)0x42004408UL) /**< \brief (TRNG) Interrupt Enable Clear */ +#define REG_TRNG_INTENSET (*(RwReg8 *)0x42004409UL) /**< \brief (TRNG) Interrupt Enable Set */ +#define REG_TRNG_INTFLAG (*(RwReg8 *)0x4200440AUL) /**< \brief (TRNG) Interrupt Flag Status and Clear */ +#define REG_TRNG_DATA (*(RoReg *)0x42004420UL) /**< \brief (TRNG) Output Data */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAML22_TRNG_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/usb.h b/watch-library/hardware/include/instance/usb.h new file mode 100644 index 00000000..9060d62e --- /dev/null +++ b/watch-library/hardware/include/instance/usb.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief Instance description for USB + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_USB_INSTANCE_ +#define _SAML22_USB_INSTANCE_ + +/* ========== Register definition for USB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USB_CTRLA (0x41000000) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (0x41000002) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_QOSCTRL (0x41000003) /**< \brief (USB) USB Quality Of Service */ +#define REG_USB_FSMSTATUS (0x4100000D) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (0x41000024) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (0x41000028) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (0x41000008) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (0x4100000A) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (0x4100000C) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (0x41000010) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (0x41000014) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (0x41000018) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (0x4100001C) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (0x41000020) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41000100) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41000104) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41000105) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41000106) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41000107) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41000108) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41000109) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41000120) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41000124) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41000125) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41000126) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41000127) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41000128) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41000129) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41000140) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41000144) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41000145) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41000146) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41000147) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41000148) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41000149) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41000160) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41000164) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41000165) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41000166) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41000167) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41000168) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41000169) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41000180) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41000184) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41000185) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41000186) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41000187) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41000188) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41000189) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410001A0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410001A4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410001A5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410001A6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410001A7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410001A8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410001A9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410001C0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410001C4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410001C5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410001C6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410001C7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410001C8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410001C9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410001E0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410001E4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410001E5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410001E6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410001E7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410001E8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410001E9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#else +#define REG_USB_CTRLA (*(RwReg8 *)0x41000000UL) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41000002UL) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_QOSCTRL (*(RwReg8 *)0x41000003UL) /**< \brief (USB) USB Quality Of Service */ +#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100000DUL) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (*(RwReg *)0x41000024UL) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (*(RwReg16*)0x41000028UL) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41000008UL) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100000CUL) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41000010UL) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41000014UL) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41000018UL) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100001CUL) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41000020UL) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41000104UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41000105UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41000124UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41000125UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41000129UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41000140UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41000144UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41000145UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41000147UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41000148UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41000149UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41000160UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41000164UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41000165UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41000167UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41000168UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41000169UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41000180UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41000184UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41000185UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41000187UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41000188UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41000189UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410001A0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410001A4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410001A5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410001A7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410001A8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410001A9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410001C0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410001C4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410001C5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410001C7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410001C8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410001C9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410001E0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410001E4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410001E5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410001E6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410001E7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410001E8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410001E9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for USB peripheral ========== */ +#define USB_EPT_NBR 8 // Number of USB end points (obsolete) +#define USB_EPT_NUM 8 // Number of USB end points +#define USB_GCLK_ID 6 // Index of Generic Clock +#define USB_PIPE_NUM 0 // Number of USB pipes + +#endif /* _SAML22_USB_INSTANCE_ */ diff --git a/watch-library/hardware/include/instance/wdt.h b/watch-library/hardware/include/instance/wdt.h new file mode 100644 index 00000000..2bb1d1ba --- /dev/null +++ b/watch-library/hardware/include/instance/wdt.h @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_WDT_INSTANCE_ +#define _SAML22_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ +#else +#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAML22_WDT_INSTANCE_ */ diff --git a/watch-library/hardware/include/pio/saml22g16a.h b/watch-library/hardware/include/pio/saml22g16a.h new file mode 100644 index 00000000..2c4d2ee5 --- /dev/null +++ b/watch-library/hardware/include/pio/saml22g16a.h @@ -0,0 +1,947 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22G16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G16A_PIO_ +#define _SAML22G16A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 _L_(7) +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) +#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT _L_(7) +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 _L_(7) +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 _L_(7) +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 _L_(7) +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) +#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 _L_(7) +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 _L_(7) +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 _L_(7) +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 _L_(7) +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 _L_(7) +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 _L_(7) +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 _L_(7) +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 _L_(6) +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) +#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 _L_(6) +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM _L_(6) +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (_UL_(1) << 24) +#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP _L_(6) +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (_UL_(1) << 25) +#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) +#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) +#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) +#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) +#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) +#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) +#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) +#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) +#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 _L_(5) +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 _L_(4) +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 _L_(4) +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 _L_(5) +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 _L_(4) +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 _L_(4) +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 _L_(5) +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 _L_(5) +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 _L_(5) +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 _L_(5) +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 _L_(5) +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) +#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 _L_(5) +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 _L_(5) +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 _L_(5) +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) +#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 _L_(5) +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 _L_(5) +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) +#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 _L_(5) +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 _L_(5) +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) +#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 _L_(5) +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 _L_(4) +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 _L_(4) +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 _L_(4) +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 _L_(4) +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 _L_(4) +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) +#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 _L_(4) +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 _L_(4) +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 _L_(4) +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) +#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 _L_(4) +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 _L_(4) +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) +#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 _L_(4) +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 _L_(4) +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) +#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 _L_(4) +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 _L_(1) +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 _L_(1) +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 _L_(1) +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 _L_(1) +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 _L_(1) +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 _L_(1) +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 _L_(1) +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 _L_(1) +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) +#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 _L_(1) +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) +#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 _L_(1) +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) +#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA _L_(1) +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) +#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB _L_(1) +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 _L_(1) +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 _L_(1) +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) +#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 _L_(7) +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 _L_(7) +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 _L_(7) +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 _L_(7) +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 _L_(1) +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) +#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 _L_(1) +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) +#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 _L_(1) +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) +#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 _L_(1) +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) +#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 _L_(1) +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) +#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 _L_(1) +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) +#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 _L_(1) +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) +#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 _L_(1) +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) +#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 _L_(1) +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) +#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 _L_(1) +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) +#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 _L_(1) +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) +#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 _L_(1) +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) +#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 _L_(1) +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) +#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 _L_(1) +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) +#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 _L_(1) +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) +#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 _L_(1) +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) +#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 _L_(1) +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) +#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 _L_(1) +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) +#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 _L_(1) +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) +#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 _L_(1) +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) +#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 _L_(1) +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) +#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 _L_(1) +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) +#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 _L_(1) +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 _L_(8) +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 _L_(8) +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 _L_(8) +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 _L_(8) +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 _L_(8) +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) +#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 _L_(8) +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 _L_(8) +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) +#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 _L_(8) +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 _L_(8) +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 _L_(8) +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 _L_(8) +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 _L_(8) +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) +#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 _L_(8) +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) +#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 _L_(8) +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 _L_(8) +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) +#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 _L_(8) +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 _L_(8) +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 _L_(8) +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 _L_(8) +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 _L_(8) +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 _L_(8) +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 _L_(8) +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 _L_(8) +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 _L_(8) +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) + +#endif /* _SAML22G16A_PIO_ */ diff --git a/watch-library/hardware/include/pio/saml22g17a.h b/watch-library/hardware/include/pio/saml22g17a.h new file mode 100644 index 00000000..582cf91f --- /dev/null +++ b/watch-library/hardware/include/pio/saml22g17a.h @@ -0,0 +1,947 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22G17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G17A_PIO_ +#define _SAML22G17A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 _L_(7) +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) +#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT _L_(7) +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 _L_(7) +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 _L_(7) +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 _L_(7) +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) +#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 _L_(7) +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 _L_(7) +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 _L_(7) +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 _L_(7) +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 _L_(7) +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 _L_(7) +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 _L_(7) +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 _L_(6) +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) +#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 _L_(6) +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM _L_(6) +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (_UL_(1) << 24) +#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP _L_(6) +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (_UL_(1) << 25) +#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) +#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) +#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) +#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) +#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) +#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) +#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) +#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) +#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 _L_(5) +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 _L_(4) +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 _L_(4) +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 _L_(5) +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 _L_(4) +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 _L_(4) +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 _L_(5) +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 _L_(5) +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 _L_(5) +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 _L_(5) +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 _L_(5) +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) +#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 _L_(5) +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 _L_(5) +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 _L_(5) +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) +#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 _L_(5) +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 _L_(5) +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) +#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 _L_(5) +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 _L_(5) +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) +#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 _L_(5) +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 _L_(4) +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 _L_(4) +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 _L_(4) +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 _L_(4) +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 _L_(4) +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) +#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 _L_(4) +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 _L_(4) +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 _L_(4) +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) +#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 _L_(4) +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 _L_(4) +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) +#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 _L_(4) +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 _L_(4) +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) +#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 _L_(4) +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 _L_(1) +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 _L_(1) +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 _L_(1) +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 _L_(1) +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 _L_(1) +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 _L_(1) +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 _L_(1) +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 _L_(1) +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) +#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 _L_(1) +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) +#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 _L_(1) +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) +#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA _L_(1) +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) +#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB _L_(1) +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 _L_(1) +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 _L_(1) +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) +#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 _L_(7) +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 _L_(7) +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 _L_(7) +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 _L_(7) +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 _L_(1) +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) +#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 _L_(1) +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) +#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 _L_(1) +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) +#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 _L_(1) +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) +#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 _L_(1) +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) +#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 _L_(1) +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) +#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 _L_(1) +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) +#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 _L_(1) +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) +#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 _L_(1) +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) +#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 _L_(1) +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) +#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 _L_(1) +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) +#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 _L_(1) +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) +#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 _L_(1) +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) +#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 _L_(1) +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) +#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 _L_(1) +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) +#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 _L_(1) +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) +#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 _L_(1) +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) +#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 _L_(1) +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) +#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 _L_(1) +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) +#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 _L_(1) +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) +#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 _L_(1) +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) +#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 _L_(1) +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) +#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 _L_(1) +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 _L_(8) +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 _L_(8) +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 _L_(8) +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 _L_(8) +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 _L_(8) +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) +#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 _L_(8) +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 _L_(8) +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) +#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 _L_(8) +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 _L_(8) +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 _L_(8) +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 _L_(8) +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 _L_(8) +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) +#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 _L_(8) +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) +#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 _L_(8) +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 _L_(8) +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) +#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 _L_(8) +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 _L_(8) +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 _L_(8) +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 _L_(8) +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 _L_(8) +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 _L_(8) +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 _L_(8) +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 _L_(8) +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 _L_(8) +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) + +#endif /* _SAML22G17A_PIO_ */ diff --git a/watch-library/hardware/include/pio/saml22g18a.h b/watch-library/hardware/include/pio/saml22g18a.h new file mode 100644 index 00000000..3570da86 --- /dev/null +++ b/watch-library/hardware/include/pio/saml22g18a.h @@ -0,0 +1,947 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22G18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G18A_PIO_ +#define _SAML22G18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 _L_(7) +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) +#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT _L_(7) +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 _L_(7) +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 _L_(7) +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 _L_(7) +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) +#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 _L_(7) +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 _L_(7) +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 _L_(7) +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 _L_(7) +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 _L_(7) +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 _L_(7) +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 _L_(7) +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 _L_(6) +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) +#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 _L_(6) +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM _L_(6) +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (_UL_(1) << 24) +#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP _L_(6) +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (_UL_(1) << 25) +#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) +#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) +#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) +#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) +#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) +#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) +#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) +#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) +#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 _L_(5) +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 _L_(4) +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 _L_(4) +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 _L_(5) +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 _L_(4) +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 _L_(4) +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 _L_(5) +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 _L_(5) +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 _L_(5) +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 _L_(5) +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 _L_(5) +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) +#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 _L_(5) +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 _L_(5) +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 _L_(5) +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) +#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 _L_(5) +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 _L_(5) +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) +#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 _L_(5) +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 _L_(5) +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) +#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 _L_(5) +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 _L_(4) +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 _L_(4) +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 _L_(4) +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 _L_(4) +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 _L_(4) +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) +#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 _L_(4) +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 _L_(4) +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 _L_(4) +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) +#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 _L_(4) +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 _L_(4) +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) +#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 _L_(4) +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 _L_(4) +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) +#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 _L_(4) +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 _L_(1) +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 _L_(1) +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 _L_(1) +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 _L_(1) +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 _L_(1) +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 _L_(1) +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 _L_(1) +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 _L_(1) +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) +#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 _L_(1) +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) +#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 _L_(1) +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) +#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA _L_(1) +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) +#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB _L_(1) +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 _L_(1) +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 _L_(1) +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) +#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 _L_(7) +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 _L_(7) +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 _L_(7) +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 _L_(7) +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 _L_(1) +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) +#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 _L_(1) +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) +#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 _L_(1) +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) +#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 _L_(1) +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) +#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 _L_(1) +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) +#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 _L_(1) +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) +#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 _L_(1) +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) +#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 _L_(1) +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) +#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 _L_(1) +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) +#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 _L_(1) +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) +#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 _L_(1) +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) +#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 _L_(1) +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) +#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 _L_(1) +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) +#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 _L_(1) +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) +#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 _L_(1) +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) +#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 _L_(1) +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) +#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 _L_(1) +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) +#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 _L_(1) +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) +#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 _L_(1) +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) +#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 _L_(1) +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) +#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 _L_(1) +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) +#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 _L_(1) +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) +#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 _L_(1) +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 _L_(8) +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 _L_(8) +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 _L_(8) +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 _L_(8) +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 _L_(8) +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) +#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 _L_(8) +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 _L_(8) +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) +#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 _L_(8) +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 _L_(8) +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 _L_(8) +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 _L_(8) +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 _L_(8) +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) +#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 _L_(8) +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) +#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 _L_(8) +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 _L_(8) +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) +#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 _L_(8) +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 _L_(8) +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 _L_(8) +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 _L_(8) +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 _L_(8) +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 _L_(8) +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 _L_(8) +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 _L_(8) +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 _L_(8) +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) + +#endif /* _SAML22G18A_PIO_ */ diff --git a/watch-library/hardware/include/pio/saml22j16a.h b/watch-library/hardware/include/pio/saml22j16a.h new file mode 100644 index 00000000..055a2b55 --- /dev/null +++ b/watch-library/hardware/include/pio/saml22j16a.h @@ -0,0 +1,1265 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22J16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J16A_PIO_ +#define _SAML22J16A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 _L_(7) +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) +#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 _L_(7) +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) +#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK _L_(7) +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) +#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT _L_(7) +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 _L_(7) +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 _L_(7) +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 _L_(7) +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 _L_(7) +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) +#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 _L_(7) +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 _L_(7) +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 _L_(7) +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 _L_(7) +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 _L_(7) +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 _L_(7) +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 _L_(7) +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 _L_(7) +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 _L_(7) +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 _L_(7) +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 _L_(6) +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) +#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 _L_(6) +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) +#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 _L_(6) +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) +#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 _L_(5) +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) +#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT _L_(6) +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM _L_(6) +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (_UL_(1) << 24) +#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP _L_(6) +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (_UL_(1) << 25) +#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) +#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) +#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) +#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) +#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) +#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) +#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) +#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) +#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) +#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) +#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 _L_(5) +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 _L_(4) +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 _L_(4) +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 _L_(4) +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) +#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 _L_(5) +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 _L_(4) +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 _L_(4) +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 _L_(4) +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 _L_(5) +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 _L_(5) +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 _L_(5) +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 _L_(5) +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 _L_(5) +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) +#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 _L_(5) +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 _L_(5) +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 _L_(5) +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 _L_(5) +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) +#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 _L_(5) +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 _L_(5) +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 _L_(5) +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) +#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 _L_(5) +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) +#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 _L_(5) +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 _L_(5) +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) +#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 _L_(5) +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) +#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 _L_(5) +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 _L_(4) +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 _L_(4) +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 _L_(4) +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 _L_(4) +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 _L_(4) +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 _L_(4) +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 _L_(4) +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) +#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 _L_(4) +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 _L_(4) +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 _L_(4) +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 _L_(4) +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 _L_(4) +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 _L_(4) +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 _L_(4) +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 _L_(4) +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 _L_(4) +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 _L_(4) +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 _L_(4) +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 _L_(4) +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 _L_(4) +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 _L_(4) +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 _L_(1) +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 _L_(1) +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 _L_(1) +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 _L_(1) +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 _L_(1) +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 _L_(1) +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 _L_(1) +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 _L_(1) +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) +#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 _L_(1) +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) +#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 _L_(1) +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) +#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 _L_(1) +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) +#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 _L_(1) +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) +#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 _L_(1) +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) +#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 _L_(1) +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) +#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 _L_(1) +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) +#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 _L_(1) +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) +#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA _L_(1) +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) +#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB _L_(1) +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 _L_(1) +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 _L_(1) +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) +#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 _L_(1) +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) +#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 _L_(1) +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) +#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 _L_(7) +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 _L_(7) +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 _L_(7) +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 _L_(7) +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 _L_(1) +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) +#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 _L_(1) +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) +#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 _L_(1) +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) +#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 _L_(1) +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) +#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 _L_(1) +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) +#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 _L_(1) +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) +#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 _L_(1) +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) +#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 _L_(1) +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) +#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 _L_(1) +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) +#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 _L_(1) +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) +#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 _L_(1) +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) +#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 _L_(1) +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) +#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 _L_(1) +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) +#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 _L_(1) +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) +#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 _L_(1) +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) +#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 _L_(1) +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) +#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 _L_(1) +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) +#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 _L_(1) +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) +#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 _L_(1) +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) +#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 _L_(1) +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) +#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 _L_(1) +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) +#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 _L_(1) +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) +#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 _L_(1) +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) +#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 _L_(1) +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) +#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 _L_(1) +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) +#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 _L_(1) +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) +#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 _L_(1) +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) +#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 _L_(1) +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) +#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 _L_(1) +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) +#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 _L_(1) +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) +#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 _L_(1) +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 _L_(8) +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 _L_(8) +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 _L_(8) +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 _L_(8) +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 _L_(8) +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 _L_(8) +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 _L_(8) +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 _L_(8) +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 _L_(8) +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 _L_(8) +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 _L_(8) +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 _L_(8) +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 _L_(8) +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 _L_(8) +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 _L_(8) +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 _L_(8) +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 _L_(8) +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 _L_(8) +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 _L_(8) +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 _L_(8) +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) +#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 _L_(8) +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) +#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 _L_(8) +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 _L_(8) +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 _L_(8) +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 _L_(8) +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 _L_(8) +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 _L_(8) +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 _L_(8) +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 _L_(8) +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 _L_(8) +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 _L_(8) +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 _L_(8) +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) + +#endif /* _SAML22J16A_PIO_ */ diff --git a/watch-library/hardware/include/pio/saml22j17a.h b/watch-library/hardware/include/pio/saml22j17a.h new file mode 100644 index 00000000..9dae1d93 --- /dev/null +++ b/watch-library/hardware/include/pio/saml22j17a.h @@ -0,0 +1,1265 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22J17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J17A_PIO_ +#define _SAML22J17A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 _L_(7) +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) +#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 _L_(7) +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) +#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK _L_(7) +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) +#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT _L_(7) +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 _L_(7) +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 _L_(7) +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 _L_(7) +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 _L_(7) +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) +#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 _L_(7) +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 _L_(7) +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 _L_(7) +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 _L_(7) +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 _L_(7) +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 _L_(7) +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 _L_(7) +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 _L_(7) +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 _L_(7) +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 _L_(7) +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 _L_(6) +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) +#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 _L_(6) +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) +#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 _L_(6) +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) +#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 _L_(5) +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) +#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT _L_(6) +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM _L_(6) +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (_UL_(1) << 24) +#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP _L_(6) +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (_UL_(1) << 25) +#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) +#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) +#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) +#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) +#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) +#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) +#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) +#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) +#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) +#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) +#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 _L_(5) +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 _L_(4) +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 _L_(4) +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 _L_(4) +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) +#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 _L_(5) +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 _L_(4) +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 _L_(4) +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 _L_(4) +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 _L_(5) +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 _L_(5) +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 _L_(5) +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 _L_(5) +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 _L_(5) +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) +#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 _L_(5) +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 _L_(5) +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 _L_(5) +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 _L_(5) +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) +#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 _L_(5) +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 _L_(5) +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 _L_(5) +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) +#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 _L_(5) +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) +#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 _L_(5) +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 _L_(5) +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) +#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 _L_(5) +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) +#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 _L_(5) +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 _L_(4) +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 _L_(4) +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 _L_(4) +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 _L_(4) +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 _L_(4) +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 _L_(4) +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 _L_(4) +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) +#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 _L_(4) +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 _L_(4) +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 _L_(4) +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 _L_(4) +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 _L_(4) +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 _L_(4) +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 _L_(4) +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 _L_(4) +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 _L_(4) +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 _L_(4) +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 _L_(4) +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 _L_(4) +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 _L_(4) +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 _L_(4) +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 _L_(1) +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 _L_(1) +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 _L_(1) +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 _L_(1) +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 _L_(1) +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 _L_(1) +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 _L_(1) +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 _L_(1) +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) +#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 _L_(1) +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) +#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 _L_(1) +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) +#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 _L_(1) +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) +#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 _L_(1) +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) +#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 _L_(1) +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) +#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 _L_(1) +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) +#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 _L_(1) +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) +#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 _L_(1) +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) +#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA _L_(1) +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) +#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB _L_(1) +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 _L_(1) +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 _L_(1) +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) +#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 _L_(1) +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) +#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 _L_(1) +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) +#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 _L_(7) +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 _L_(7) +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 _L_(7) +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 _L_(7) +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 _L_(1) +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) +#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 _L_(1) +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) +#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 _L_(1) +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) +#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 _L_(1) +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) +#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 _L_(1) +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) +#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 _L_(1) +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) +#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 _L_(1) +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) +#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 _L_(1) +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) +#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 _L_(1) +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) +#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 _L_(1) +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) +#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 _L_(1) +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) +#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 _L_(1) +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) +#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 _L_(1) +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) +#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 _L_(1) +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) +#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 _L_(1) +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) +#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 _L_(1) +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) +#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 _L_(1) +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) +#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 _L_(1) +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) +#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 _L_(1) +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) +#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 _L_(1) +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) +#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 _L_(1) +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) +#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 _L_(1) +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) +#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 _L_(1) +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) +#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 _L_(1) +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) +#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 _L_(1) +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) +#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 _L_(1) +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) +#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 _L_(1) +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) +#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 _L_(1) +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) +#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 _L_(1) +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) +#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 _L_(1) +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) +#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 _L_(1) +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 _L_(8) +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 _L_(8) +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 _L_(8) +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 _L_(8) +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 _L_(8) +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 _L_(8) +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 _L_(8) +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 _L_(8) +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 _L_(8) +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 _L_(8) +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 _L_(8) +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 _L_(8) +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 _L_(8) +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 _L_(8) +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 _L_(8) +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 _L_(8) +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 _L_(8) +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 _L_(8) +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 _L_(8) +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 _L_(8) +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) +#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 _L_(8) +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) +#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 _L_(8) +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 _L_(8) +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 _L_(8) +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 _L_(8) +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 _L_(8) +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 _L_(8) +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 _L_(8) +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 _L_(8) +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 _L_(8) +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 _L_(8) +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 _L_(8) +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) + +#endif /* _SAML22J17A_PIO_ */ diff --git a/watch-library/hardware/include/pio/saml22j18a.h b/watch-library/hardware/include/pio/saml22j18a.h new file mode 100644 index 00000000..d2c8c3c7 --- /dev/null +++ b/watch-library/hardware/include/pio/saml22j18a.h @@ -0,0 +1,1265 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J18A_PIO_ +#define _SAML22J18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 _L_(7) +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) +#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 _L_(7) +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) +#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK _L_(7) +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) +#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT _L_(7) +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 _L_(7) +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 _L_(7) +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 _L_(7) +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 _L_(7) +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) +#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 _L_(7) +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 _L_(7) +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 _L_(7) +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 _L_(7) +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 _L_(7) +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 _L_(7) +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 _L_(7) +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 _L_(7) +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 _L_(7) +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 _L_(7) +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 _L_(6) +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) +#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 _L_(6) +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) +#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 _L_(6) +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) +#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 _L_(5) +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) +#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT _L_(6) +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM _L_(6) +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (_UL_(1) << 24) +#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP _L_(6) +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (_UL_(1) << 25) +#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) +#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) +#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) +#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) +#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) +#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) +#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) +#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) +#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) +#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) +#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 _L_(5) +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 _L_(4) +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 _L_(4) +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 _L_(4) +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) +#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 _L_(5) +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 _L_(4) +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 _L_(4) +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 _L_(4) +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 _L_(5) +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 _L_(5) +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 _L_(5) +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 _L_(5) +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 _L_(5) +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) +#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 _L_(5) +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 _L_(5) +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 _L_(5) +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 _L_(5) +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) +#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 _L_(5) +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 _L_(5) +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 _L_(5) +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) +#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 _L_(5) +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) +#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 _L_(5) +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 _L_(5) +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) +#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 _L_(5) +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) +#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 _L_(5) +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 _L_(4) +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 _L_(4) +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 _L_(4) +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 _L_(4) +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 _L_(4) +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 _L_(4) +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 _L_(4) +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) +#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 _L_(4) +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 _L_(4) +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 _L_(4) +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 _L_(4) +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 _L_(4) +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 _L_(4) +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 _L_(4) +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 _L_(4) +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 _L_(4) +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 _L_(4) +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 _L_(4) +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 _L_(4) +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 _L_(4) +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 _L_(4) +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 _L_(1) +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 _L_(1) +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 _L_(1) +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 _L_(1) +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 _L_(1) +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 _L_(1) +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 _L_(1) +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 _L_(1) +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) +#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 _L_(1) +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) +#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 _L_(1) +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) +#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 _L_(1) +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) +#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 _L_(1) +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) +#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 _L_(1) +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) +#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 _L_(1) +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) +#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 _L_(1) +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) +#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 _L_(1) +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) +#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA _L_(1) +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) +#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB _L_(1) +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 _L_(1) +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 _L_(1) +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) +#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 _L_(1) +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) +#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 _L_(1) +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) +#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 _L_(7) +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 _L_(7) +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 _L_(7) +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 _L_(7) +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 _L_(1) +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) +#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 _L_(1) +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) +#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 _L_(1) +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) +#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 _L_(1) +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) +#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 _L_(1) +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) +#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 _L_(1) +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) +#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 _L_(1) +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) +#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 _L_(1) +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) +#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 _L_(1) +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) +#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 _L_(1) +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) +#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 _L_(1) +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) +#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 _L_(1) +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) +#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 _L_(1) +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) +#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 _L_(1) +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) +#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 _L_(1) +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) +#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 _L_(1) +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) +#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 _L_(1) +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) +#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 _L_(1) +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) +#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 _L_(1) +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) +#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 _L_(1) +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) +#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 _L_(1) +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) +#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 _L_(1) +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) +#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 _L_(1) +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) +#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 _L_(1) +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) +#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 _L_(1) +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) +#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 _L_(1) +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) +#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 _L_(1) +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) +#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 _L_(1) +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) +#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 _L_(1) +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) +#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 _L_(1) +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) +#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 _L_(1) +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 _L_(8) +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 _L_(8) +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 _L_(8) +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 _L_(8) +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 _L_(8) +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 _L_(8) +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 _L_(8) +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 _L_(8) +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 _L_(8) +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 _L_(8) +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 _L_(8) +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 _L_(8) +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 _L_(8) +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 _L_(8) +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 _L_(8) +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 _L_(8) +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 _L_(8) +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 _L_(8) +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 _L_(8) +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 _L_(8) +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) +#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 _L_(8) +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) +#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 _L_(8) +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 _L_(8) +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 _L_(8) +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 _L_(8) +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 _L_(8) +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 _L_(8) +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 _L_(8) +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 _L_(8) +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 _L_(8) +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 _L_(8) +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 _L_(8) +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) + +#endif /* _SAML22J18A_PIO_ */ diff --git a/watch-library/hardware/include/pio/saml22n16a.h b/watch-library/hardware/include/pio/saml22n16a.h new file mode 100644 index 00000000..bd4c515f --- /dev/null +++ b/watch-library/hardware/include/pio/saml22n16a.h @@ -0,0 +1,1851 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22N16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N16A_PIO_ +#define _SAML22N16A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC08 72 /**< \brief Pin Number for PC08 */ +#define PORT_PC08 (_UL_(1) << 8) /**< \brief PORT Mask for PC08 */ +#define PIN_PC09 73 /**< \brief Pin Number for PC09 */ +#define PORT_PC09 (_UL_(1) << 9) /**< \brief PORT Mask for PC09 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 _L_(7) +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) +#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 _L_(7) +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) +#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK _L_(7) +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) +#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT _L_(7) +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 _L_(7) +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 _L_(7) +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 _L_(7) +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 _L_(7) +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) +#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 _L_(7) +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 _L_(7) +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 _L_(7) +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 _L_(7) +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 _L_(7) +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 _L_(7) +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 _L_(7) +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 _L_(7) +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 _L_(7) +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 _L_(7) +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 _L_(6) +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) +#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 _L_(6) +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) +#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 _L_(6) +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) +#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 _L_(5) +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) +#define PIN_PC00G_RTC_IN3 _L_(64) /**< \brief RTC signal: IN3 on PC00 mux G */ +#define MUX_PC00G_RTC_IN3 _L_(6) +#define PINMUX_PC00G_RTC_IN3 ((PIN_PC00G_RTC_IN3 << 16) | MUX_PC00G_RTC_IN3) +#define PORT_PC00G_RTC_IN3 (_UL_(1) << 0) +#define PIN_PC01G_RTC_IN4 _L_(65) /**< \brief RTC signal: IN4 on PC01 mux G */ +#define MUX_PC01G_RTC_IN4 _L_(6) +#define PINMUX_PC01G_RTC_IN4 ((PIN_PC01G_RTC_IN4 << 16) | MUX_PC01G_RTC_IN4) +#define PORT_PC01G_RTC_IN4 (_UL_(1) << 1) +#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT _L_(6) +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC08A_EIC_EXTINT0 _L_(72) /**< \brief EIC signal: EXTINT0 on PC08 mux A */ +#define MUX_PC08A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC08A_EIC_EXTINT0 ((PIN_PC08A_EIC_EXTINT0 << 16) | MUX_PC08A_EIC_EXTINT0) +#define PORT_PC08A_EIC_EXTINT0 (_UL_(1) << 8) +#define PIN_PC08A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC08 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT0 _L_(88) /**< \brief EIC signal: EXTINT0 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT0 ((PIN_PC24A_EIC_EXTINT0 << 16) | MUX_PC24A_EIC_EXTINT0) +#define PORT_PC24A_EIC_EXTINT0 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC09A_EIC_EXTINT1 _L_(73) /**< \brief EIC signal: EXTINT1 on PC09 mux A */ +#define MUX_PC09A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC09A_EIC_EXTINT1 ((PIN_PC09A_EIC_EXTINT1 << 16) | MUX_PC09A_EIC_EXTINT1) +#define PORT_PC09A_EIC_EXTINT1 (_UL_(1) << 9) +#define PIN_PC09A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC09 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT1 _L_(89) /**< \brief EIC signal: EXTINT1 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT1 ((PIN_PC25A_EIC_EXTINT1 << 16) | MUX_PC25A_EIC_EXTINT1) +#define PORT_PC25A_EIC_EXTINT1 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT2 _L_(74) /**< \brief EIC signal: EXTINT2 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT2 ((PIN_PC10A_EIC_EXTINT2 << 16) | MUX_PC10A_EIC_EXTINT2) +#define PORT_PC10A_EIC_EXTINT2 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT2 _L_(90) /**< \brief EIC signal: EXTINT2 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT2 ((PIN_PC26A_EIC_EXTINT2 << 16) | MUX_PC26A_EIC_EXTINT2) +#define PORT_PC26A_EIC_EXTINT2 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT3 _L_(75) /**< \brief EIC signal: EXTINT3 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT3 ((PIN_PC11A_EIC_EXTINT3 << 16) | MUX_PC11A_EIC_EXTINT3) +#define PORT_PC11A_EIC_EXTINT3 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT3 _L_(91) /**< \brief EIC signal: EXTINT3 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT3 ((PIN_PC27A_EIC_EXTINT3 << 16) | MUX_PC27A_EIC_EXTINT3) +#define PORT_PC27A_EIC_EXTINT3 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT4 _L_(76) /**< \brief EIC signal: EXTINT4 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT4 ((PIN_PC12A_EIC_EXTINT4 << 16) | MUX_PC12A_EIC_EXTINT4) +#define PORT_PC12A_EIC_EXTINT4 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT4 _L_(92) /**< \brief EIC signal: EXTINT4 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT4 ((PIN_PC28A_EIC_EXTINT4 << 16) | MUX_PC28A_EIC_EXTINT4) +#define PORT_PC28A_EIC_EXTINT4 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT5 _L_(77) /**< \brief EIC signal: EXTINT5 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT5 ((PIN_PC13A_EIC_EXTINT5 << 16) | MUX_PC13A_EIC_EXTINT5) +#define PORT_PC13A_EIC_EXTINT5 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT6 _L_(78) /**< \brief EIC signal: EXTINT6 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT6 ((PIN_PC14A_EIC_EXTINT6 << 16) | MUX_PC14A_EIC_EXTINT6) +#define PORT_PC14A_EIC_EXTINT6 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT7 _L_(79) /**< \brief EIC signal: EXTINT7 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT7 ((PIN_PC15A_EIC_EXTINT7 << 16) | MUX_PC15A_EIC_EXTINT7) +#define PORT_PC15A_EIC_EXTINT7 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT8 _L_(64) /**< \brief EIC signal: EXTINT8 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT8 ((PIN_PC00A_EIC_EXTINT8 << 16) | MUX_PC00A_EIC_EXTINT8) +#define PORT_PC00A_EIC_EXTINT8 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT8 _L_(80) /**< \brief EIC signal: EXTINT8 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT8 ((PIN_PC16A_EIC_EXTINT8 << 16) | MUX_PC16A_EIC_EXTINT8) +#define PORT_PC16A_EIC_EXTINT8 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT9 _L_(65) /**< \brief EIC signal: EXTINT9 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT9 ((PIN_PC01A_EIC_EXTINT9 << 16) | MUX_PC01A_EIC_EXTINT9) +#define PORT_PC01A_EIC_EXTINT9 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT9 _L_(81) /**< \brief EIC signal: EXTINT9 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT9 ((PIN_PC17A_EIC_EXTINT9 << 16) | MUX_PC17A_EIC_EXTINT9) +#define PORT_PC17A_EIC_EXTINT9 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT10 _L_(66) /**< \brief EIC signal: EXTINT10 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT10 ((PIN_PC02A_EIC_EXTINT10 << 16) | MUX_PC02A_EIC_EXTINT10) +#define PORT_PC02A_EIC_EXTINT10 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT10 _L_(82) /**< \brief EIC signal: EXTINT10 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT10 ((PIN_PC18A_EIC_EXTINT10 << 16) | MUX_PC18A_EIC_EXTINT10) +#define PORT_PC18A_EIC_EXTINT10 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT11 _L_(67) /**< \brief EIC signal: EXTINT11 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT11 ((PIN_PC03A_EIC_EXTINT11 << 16) | MUX_PC03A_EIC_EXTINT11) +#define PORT_PC03A_EIC_EXTINT11 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT11 _L_(83) /**< \brief EIC signal: EXTINT11 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT11 ((PIN_PC19A_EIC_EXTINT11 << 16) | MUX_PC19A_EIC_EXTINT11) +#define PORT_PC19A_EIC_EXTINT11 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT12 _L_(84) /**< \brief EIC signal: EXTINT12 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT12 ((PIN_PC20A_EIC_EXTINT12 << 16) | MUX_PC20A_EIC_EXTINT12) +#define PORT_PC20A_EIC_EXTINT12 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT13 _L_(69) /**< \brief EIC signal: EXTINT13 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT13 ((PIN_PC05A_EIC_EXTINT13 << 16) | MUX_PC05A_EIC_EXTINT13) +#define PORT_PC05A_EIC_EXTINT13 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT13 _L_(85) /**< \brief EIC signal: EXTINT13 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT13 ((PIN_PC21A_EIC_EXTINT13 << 16) | MUX_PC21A_EIC_EXTINT13) +#define PORT_PC21A_EIC_EXTINT13 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT14 _L_(70) /**< \brief EIC signal: EXTINT14 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT14 ((PIN_PC06A_EIC_EXTINT14 << 16) | MUX_PC06A_EIC_EXTINT14) +#define PORT_PC06A_EIC_EXTINT14 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT15 _L_(71) /**< \brief EIC signal: EXTINT15 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT15 ((PIN_PC07A_EIC_EXTINT15 << 16) | MUX_PC07A_EIC_EXTINT15) +#define PORT_PC07A_EIC_EXTINT15 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM _L_(6) +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (_UL_(1) << 24) +#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP _L_(6) +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (_UL_(1) << 25) +#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PC27D_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux D */ +#define MUX_PC27D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PC27D_SERCOM1_PAD0 ((PIN_PC27D_SERCOM1_PAD0 << 16) | MUX_PC27D_SERCOM1_PAD0) +#define PORT_PC27D_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC12C_SERCOM1_PAD0 _L_(76) /**< \brief SERCOM1 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM1_PAD0 ((PIN_PC12C_SERCOM1_PAD0 << 16) | MUX_PC12C_SERCOM1_PAD0) +#define PORT_PC12C_SERCOM1_PAD0 (_UL_(1) << 12) +#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PC28D_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux D */ +#define MUX_PC28D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PC28D_SERCOM1_PAD1 ((PIN_PC28D_SERCOM1_PAD1 << 16) | MUX_PC28D_SERCOM1_PAD1) +#define PORT_PC28D_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC13C_SERCOM1_PAD1 _L_(77) /**< \brief SERCOM1 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM1_PAD1 ((PIN_PC13C_SERCOM1_PAD1 << 16) | MUX_PC13C_SERCOM1_PAD1) +#define PORT_PC13C_SERCOM1_PAD1 (_UL_(1) << 13) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PC10C_SERCOM1_PAD2 _L_(74) /**< \brief SERCOM1 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM1_PAD2 ((PIN_PC10C_SERCOM1_PAD2 << 16) | MUX_PC10C_SERCOM1_PAD2) +#define PORT_PC10C_SERCOM1_PAD2 (_UL_(1) << 10) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PC11C_SERCOM1_PAD3 _L_(75) /**< \brief SERCOM1 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM1_PAD3 ((PIN_PC11C_SERCOM1_PAD3 << 16) | MUX_PC11C_SERCOM1_PAD3) +#define PORT_PC11C_SERCOM1_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) +#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) +#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) +#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) +#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) +#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PB18D_SERCOM3_PAD2 _L_(50) /**< \brief SERCOM3 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM3_PAD2 ((PIN_PB18D_SERCOM3_PAD2 << 16) | MUX_PB18D_SERCOM3_PAD2) +#define PORT_PB18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) +#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) +#define PIN_PB19D_SERCOM3_PAD3 _L_(51) /**< \brief SERCOM3 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM3_PAD3 ((PIN_PB19D_SERCOM3_PAD3 << 16) | MUX_PB19D_SERCOM3_PAD3) +#define PORT_PB19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA08D_SERCOM4_PAD0 _L_(8) /**< \brief SERCOM4 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA08D_SERCOM4_PAD0 ((PIN_PA08D_SERCOM4_PAD0 << 16) | MUX_PA08D_SERCOM4_PAD0) +#define PORT_PA08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM4_PAD0 _L_(56) /**< \brief SERCOM4 signal: PAD0 on PB24 mux D */ +#define MUX_PB24D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB24D_SERCOM4_PAD0 ((PIN_PB24D_SERCOM4_PAD0 << 16) | MUX_PB24D_SERCOM4_PAD0) +#define PORT_PB24D_SERCOM4_PAD0 (_UL_(1) << 24) +#define PIN_PA12C_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM4_PAD0 ((PIN_PA12C_SERCOM4_PAD0 << 16) | MUX_PA12C_SERCOM4_PAD0) +#define PORT_PA12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA09D_SERCOM4_PAD1 _L_(9) /**< \brief SERCOM4 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA09D_SERCOM4_PAD1 ((PIN_PA09D_SERCOM4_PAD1 << 16) | MUX_PA09D_SERCOM4_PAD1) +#define PORT_PA09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM4_PAD1 _L_(57) /**< \brief SERCOM4 signal: PAD1 on PB25 mux D */ +#define MUX_PB25D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB25D_SERCOM4_PAD1 ((PIN_PB25D_SERCOM4_PAD1 << 16) | MUX_PB25D_SERCOM4_PAD1) +#define PORT_PB25D_SERCOM4_PAD1 (_UL_(1) << 25) +#define PIN_PA13C_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM4_PAD1 ((PIN_PA13C_SERCOM4_PAD1 << 16) | MUX_PA13C_SERCOM4_PAD1) +#define PORT_PA13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM4_PAD2 _L_(10) /**< \brief SERCOM4 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM4_PAD2 ((PIN_PA10D_SERCOM4_PAD2 << 16) | MUX_PA10D_SERCOM4_PAD2) +#define PORT_PA10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM4_PAD2 _L_(88) /**< \brief SERCOM4 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM4_PAD2 ((PIN_PC24D_SERCOM4_PAD2 << 16) | MUX_PC24D_SERCOM4_PAD2) +#define PORT_PC24D_SERCOM4_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM4_PAD2 ((PIN_PA14C_SERCOM4_PAD2 << 16) | MUX_PA14C_SERCOM4_PAD2) +#define PORT_PA14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM4_PAD3 _L_(11) /**< \brief SERCOM4 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM4_PAD3 ((PIN_PA11D_SERCOM4_PAD3 << 16) | MUX_PA11D_SERCOM4_PAD3) +#define PORT_PA11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM4_PAD3 _L_(89) /**< \brief SERCOM4 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM4_PAD3 ((PIN_PC25D_SERCOM4_PAD3 << 16) | MUX_PC25D_SERCOM4_PAD3) +#define PORT_PC25D_SERCOM4_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM4_PAD3 ((PIN_PA15C_SERCOM4_PAD3 << 16) | MUX_PA15C_SERCOM4_PAD3) +#define PORT_PA15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) +#define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) +#define PIN_PA24D_SERCOM5_PAD0 _L_(24) /**< \brief SERCOM5 signal: PAD0 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD0 ((PIN_PA24D_SERCOM5_PAD0 << 16) | MUX_PA24D_SERCOM5_PAD0) +#define PORT_PA24D_SERCOM5_PAD0 (_UL_(1) << 24) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB20D_SERCOM5_PAD0 _L_(52) /**< \brief SERCOM5 signal: PAD0 on PB20 mux D */ +#define MUX_PB20D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB20D_SERCOM5_PAD0 ((PIN_PB20D_SERCOM5_PAD0 << 16) | MUX_PB20D_SERCOM5_PAD0) +#define PORT_PB20D_SERCOM5_PAD0 (_UL_(1) << 20) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) +#define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) +#define PIN_PA25D_SERCOM5_PAD1 _L_(25) /**< \brief SERCOM5 signal: PAD1 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD1 ((PIN_PA25D_SERCOM5_PAD1 << 16) | MUX_PA25D_SERCOM5_PAD1) +#define PORT_PA25D_SERCOM5_PAD1 (_UL_(1) << 25) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB21D_SERCOM5_PAD1 _L_(53) /**< \brief SERCOM5 signal: PAD1 on PB21 mux D */ +#define MUX_PB21D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB21D_SERCOM5_PAD1 ((PIN_PB21D_SERCOM5_PAD1 << 16) | MUX_PB21D_SERCOM5_PAD1) +#define PORT_PB21D_SERCOM5_PAD1 (_UL_(1) << 21) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 _L_(5) +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PB18F_TCC0_WO0 _L_(50) /**< \brief TCC0 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC0_WO0 _L_(5) +#define PINMUX_PB18F_TCC0_WO0 ((PIN_PB18F_TCC0_WO0 << 16) | MUX_PB18F_TCC0_WO0) +#define PORT_PB18F_TCC0_WO0 (_UL_(1) << 18) +#define PIN_PC24F_TCC0_WO0 _L_(88) /**< \brief TCC0 signal: WO0 on PC24 mux F */ +#define MUX_PC24F_TCC0_WO0 _L_(5) +#define PINMUX_PC24F_TCC0_WO0 ((PIN_PC24F_TCC0_WO0 << 16) | MUX_PC24F_TCC0_WO0) +#define PORT_PC24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 _L_(4) +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 _L_(4) +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 _L_(4) +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) +#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 _L_(5) +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PB19F_TCC0_WO1 _L_(51) /**< \brief TCC0 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC0_WO1 _L_(5) +#define PINMUX_PB19F_TCC0_WO1 ((PIN_PB19F_TCC0_WO1 << 16) | MUX_PB19F_TCC0_WO1) +#define PORT_PB19F_TCC0_WO1 (_UL_(1) << 19) +#define PIN_PC25F_TCC0_WO1 _L_(89) /**< \brief TCC0 signal: WO1 on PC25 mux F */ +#define MUX_PC25F_TCC0_WO1 _L_(5) +#define PINMUX_PC25F_TCC0_WO1 ((PIN_PC25F_TCC0_WO1 << 16) | MUX_PC25F_TCC0_WO1) +#define PORT_PC25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 _L_(4) +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 _L_(4) +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 _L_(4) +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 _L_(5) +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC0_WO2 _L_(52) /**< \brief TCC0 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC0_WO2 _L_(5) +#define PINMUX_PB20F_TCC0_WO2 ((PIN_PB20F_TCC0_WO2 << 16) | MUX_PB20F_TCC0_WO2) +#define PORT_PB20F_TCC0_WO2 (_UL_(1) << 20) +#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 _L_(5) +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PC26F_TCC0_WO2 _L_(90) /**< \brief TCC0 signal: WO2 on PC26 mux F */ +#define MUX_PC26F_TCC0_WO2 _L_(5) +#define PINMUX_PC26F_TCC0_WO2 ((PIN_PC26F_TCC0_WO2 << 16) | MUX_PC26F_TCC0_WO2) +#define PORT_PC26F_TCC0_WO2 (_UL_(1) << 26) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 _L_(5) +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC0_WO3 _L_(53) /**< \brief TCC0 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC0_WO3 _L_(5) +#define PINMUX_PB21F_TCC0_WO3 ((PIN_PB21F_TCC0_WO3 << 16) | MUX_PB21F_TCC0_WO3) +#define PORT_PB21F_TCC0_WO3 (_UL_(1) << 21) +#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 _L_(5) +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PC27F_TCC0_WO3 _L_(91) /**< \brief TCC0 signal: WO3 on PC27 mux F */ +#define MUX_PC27F_TCC0_WO3 _L_(5) +#define PINMUX_PC27F_TCC0_WO3 ((PIN_PC27F_TCC0_WO3 << 16) | MUX_PC27F_TCC0_WO3) +#define PORT_PC27F_TCC0_WO3 (_UL_(1) << 27) +#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 _L_(5) +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) +#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 _L_(5) +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PC28F_TCC0_WO4 _L_(92) /**< \brief TCC0 signal: WO4 on PC28 mux F */ +#define MUX_PC28F_TCC0_WO4 _L_(5) +#define PINMUX_PC28F_TCC0_WO4 ((PIN_PC28F_TCC0_WO4 << 16) | MUX_PC28F_TCC0_WO4) +#define PORT_PC28F_TCC0_WO4 (_UL_(1) << 28) +#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 _L_(5) +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 _L_(5) +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 _L_(5) +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) +#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 _L_(5) +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 _L_(5) +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 _L_(5) +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) +#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 _L_(5) +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) +#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 _L_(5) +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PB24F_TCC0_WO6 _L_(56) /**< \brief TCC0 signal: WO6 on PB24 mux F */ +#define MUX_PB24F_TCC0_WO6 _L_(5) +#define PINMUX_PB24F_TCC0_WO6 ((PIN_PB24F_TCC0_WO6 << 16) | MUX_PB24F_TCC0_WO6) +#define PORT_PB24F_TCC0_WO6 (_UL_(1) << 24) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 _L_(5) +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) +#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 _L_(5) +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) +#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 _L_(5) +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PB25F_TCC0_WO7 _L_(57) /**< \brief TCC0 signal: WO7 on PB25 mux F */ +#define MUX_PB25F_TCC0_WO7 _L_(5) +#define PINMUX_PB25F_TCC0_WO7 ((PIN_PB25F_TCC0_WO7 << 16) | MUX_PB25F_TCC0_WO7) +#define PORT_PB25F_TCC0_WO7 (_UL_(1) << 25) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 _L_(4) +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 _L_(4) +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 _L_(4) +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 _L_(4) +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 _L_(4) +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 _L_(4) +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 _L_(4) +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) +#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 _L_(4) +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 _L_(4) +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 _L_(4) +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 _L_(4) +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 _L_(4) +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 _L_(4) +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PC24E_TC2_WO0 _L_(88) /**< \brief TC2 signal: WO0 on PC24 mux E */ +#define MUX_PC24E_TC2_WO0 _L_(4) +#define PINMUX_PC24E_TC2_WO0 ((PIN_PC24E_TC2_WO0 << 16) | MUX_PC24E_TC2_WO0) +#define PORT_PC24E_TC2_WO0 (_UL_(1) << 24) +#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 _L_(4) +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 _L_(4) +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) +#define PIN_PC25E_TC2_WO1 _L_(89) /**< \brief TC2 signal: WO1 on PC25 mux E */ +#define MUX_PC25E_TC2_WO1 _L_(4) +#define PINMUX_PC25E_TC2_WO1 ((PIN_PC25E_TC2_WO1 << 16) | MUX_PC25E_TC2_WO1) +#define PORT_PC25E_TC2_WO1 (_UL_(1) << 25) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 _L_(4) +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 _L_(4) +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 _L_(4) +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) +#define PIN_PC26E_TC3_WO0 _L_(90) /**< \brief TC3 signal: WO0 on PC26 mux E */ +#define MUX_PC26E_TC3_WO0 _L_(4) +#define PINMUX_PC26E_TC3_WO0 ((PIN_PC26E_TC3_WO0 << 16) | MUX_PC26E_TC3_WO0) +#define PORT_PC26E_TC3_WO0 (_UL_(1) << 26) +#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 _L_(4) +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 _L_(4) +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 _L_(4) +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) +#define PIN_PC27E_TC3_WO1 _L_(91) /**< \brief TC3 signal: WO1 on PC27 mux E */ +#define MUX_PC27E_TC3_WO1 _L_(4) +#define PINMUX_PC27E_TC3_WO1 ((PIN_PC27E_TC3_WO1 << 16) | MUX_PC27E_TC3_WO1) +#define PORT_PC27E_TC3_WO1 (_UL_(1) << 27) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 _L_(1) +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 _L_(1) +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 _L_(1) +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 _L_(1) +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 _L_(1) +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 _L_(1) +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 _L_(1) +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 _L_(1) +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) +#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 _L_(1) +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) +#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 _L_(1) +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) +#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 _L_(1) +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) +#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 _L_(1) +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) +#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 _L_(1) +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) +#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 _L_(1) +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) +#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 _L_(1) +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) +#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 _L_(1) +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) +#define PIN_PC00B_ADC_AIN16 _L_(64) /**< \brief ADC signal: AIN16 on PC00 mux B */ +#define MUX_PC00B_ADC_AIN16 _L_(1) +#define PINMUX_PC00B_ADC_AIN16 ((PIN_PC00B_ADC_AIN16 << 16) | MUX_PC00B_ADC_AIN16) +#define PORT_PC00B_ADC_AIN16 (_UL_(1) << 0) +#define PIN_PC01B_ADC_AIN17 _L_(65) /**< \brief ADC signal: AIN17 on PC01 mux B */ +#define MUX_PC01B_ADC_AIN17 _L_(1) +#define PINMUX_PC01B_ADC_AIN17 ((PIN_PC01B_ADC_AIN17 << 16) | MUX_PC01B_ADC_AIN17) +#define PORT_PC01B_ADC_AIN17 (_UL_(1) << 1) +#define PIN_PC02B_ADC_AIN18 _L_(66) /**< \brief ADC signal: AIN18 on PC02 mux B */ +#define MUX_PC02B_ADC_AIN18 _L_(1) +#define PINMUX_PC02B_ADC_AIN18 ((PIN_PC02B_ADC_AIN18 << 16) | MUX_PC02B_ADC_AIN18) +#define PORT_PC02B_ADC_AIN18 (_UL_(1) << 2) +#define PIN_PC03B_ADC_AIN19 _L_(67) /**< \brief ADC signal: AIN19 on PC03 mux B */ +#define MUX_PC03B_ADC_AIN19 _L_(1) +#define PINMUX_PC03B_ADC_AIN19 ((PIN_PC03B_ADC_AIN19 << 16) | MUX_PC03B_ADC_AIN19) +#define PORT_PC03B_ADC_AIN19 (_UL_(1) << 3) +#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA _L_(1) +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) +#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB _L_(1) +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 _L_(1) +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 _L_(1) +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) +#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 _L_(1) +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) +#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 _L_(1) +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) +#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 _L_(7) +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 _L_(7) +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24H_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux H */ +#define MUX_PB24H_AC_CMP0 _L_(7) +#define PINMUX_PB24H_AC_CMP0 ((PIN_PB24H_AC_CMP0 << 16) | MUX_PB24H_AC_CMP0) +#define PORT_PB24H_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 _L_(7) +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 _L_(7) +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25H_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux H */ +#define MUX_PB25H_AC_CMP1 _L_(7) +#define PINMUX_PB25H_AC_CMP1 ((PIN_PB25H_AC_CMP1 << 16) | MUX_PB25H_AC_CMP1) +#define PORT_PB25H_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 _L_(1) +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) +#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 _L_(1) +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) +#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 _L_(1) +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) +#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 _L_(1) +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) +#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 _L_(1) +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) +#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 _L_(1) +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) +#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 _L_(1) +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) +#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 _L_(1) +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) +#define PIN_PC05B_SLCD_LP8 _L_(69) /**< \brief SLCD signal: LP8 on PC05 mux B */ +#define MUX_PC05B_SLCD_LP8 _L_(1) +#define PINMUX_PC05B_SLCD_LP8 ((PIN_PC05B_SLCD_LP8 << 16) | MUX_PC05B_SLCD_LP8) +#define PORT_PC05B_SLCD_LP8 (_UL_(1) << 5) +#define PIN_PC06B_SLCD_LP9 _L_(70) /**< \brief SLCD signal: LP9 on PC06 mux B */ +#define MUX_PC06B_SLCD_LP9 _L_(1) +#define PINMUX_PC06B_SLCD_LP9 ((PIN_PC06B_SLCD_LP9 << 16) | MUX_PC06B_SLCD_LP9) +#define PORT_PC06B_SLCD_LP9 (_UL_(1) << 6) +#define PIN_PC07B_SLCD_LP10 _L_(71) /**< \brief SLCD signal: LP10 on PC07 mux B */ +#define MUX_PC07B_SLCD_LP10 _L_(1) +#define PINMUX_PC07B_SLCD_LP10 ((PIN_PC07B_SLCD_LP10 << 16) | MUX_PC07B_SLCD_LP10) +#define PORT_PC07B_SLCD_LP10 (_UL_(1) << 7) +#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 _L_(1) +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) +#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 _L_(1) +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) +#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 _L_(1) +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) +#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 _L_(1) +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) +#define PIN_PC08B_SLCD_LP15 _L_(72) /**< \brief SLCD signal: LP15 on PC08 mux B */ +#define MUX_PC08B_SLCD_LP15 _L_(1) +#define PINMUX_PC08B_SLCD_LP15 ((PIN_PC08B_SLCD_LP15 << 16) | MUX_PC08B_SLCD_LP15) +#define PORT_PC08B_SLCD_LP15 (_UL_(1) << 8) +#define PIN_PC09B_SLCD_LP16 _L_(73) /**< \brief SLCD signal: LP16 on PC09 mux B */ +#define MUX_PC09B_SLCD_LP16 _L_(1) +#define PINMUX_PC09B_SLCD_LP16 ((PIN_PC09B_SLCD_LP16 << 16) | MUX_PC09B_SLCD_LP16) +#define PORT_PC09B_SLCD_LP16 (_UL_(1) << 9) +#define PIN_PC10B_SLCD_LP17 _L_(74) /**< \brief SLCD signal: LP17 on PC10 mux B */ +#define MUX_PC10B_SLCD_LP17 _L_(1) +#define PINMUX_PC10B_SLCD_LP17 ((PIN_PC10B_SLCD_LP17 << 16) | MUX_PC10B_SLCD_LP17) +#define PORT_PC10B_SLCD_LP17 (_UL_(1) << 10) +#define PIN_PC11B_SLCD_LP18 _L_(75) /**< \brief SLCD signal: LP18 on PC11 mux B */ +#define MUX_PC11B_SLCD_LP18 _L_(1) +#define PINMUX_PC11B_SLCD_LP18 ((PIN_PC11B_SLCD_LP18 << 16) | MUX_PC11B_SLCD_LP18) +#define PORT_PC11B_SLCD_LP18 (_UL_(1) << 11) +#define PIN_PC12B_SLCD_LP19 _L_(76) /**< \brief SLCD signal: LP19 on PC12 mux B */ +#define MUX_PC12B_SLCD_LP19 _L_(1) +#define PINMUX_PC12B_SLCD_LP19 ((PIN_PC12B_SLCD_LP19 << 16) | MUX_PC12B_SLCD_LP19) +#define PORT_PC12B_SLCD_LP19 (_UL_(1) << 12) +#define PIN_PC13B_SLCD_LP20 _L_(77) /**< \brief SLCD signal: LP20 on PC13 mux B */ +#define MUX_PC13B_SLCD_LP20 _L_(1) +#define PINMUX_PC13B_SLCD_LP20 ((PIN_PC13B_SLCD_LP20 << 16) | MUX_PC13B_SLCD_LP20) +#define PORT_PC13B_SLCD_LP20 (_UL_(1) << 13) +#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 _L_(1) +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) +#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 _L_(1) +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) +#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 _L_(1) +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) +#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 _L_(1) +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) +#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 _L_(1) +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) +#define PIN_PC14B_SLCD_LP26 _L_(78) /**< \brief SLCD signal: LP26 on PC14 mux B */ +#define MUX_PC14B_SLCD_LP26 _L_(1) +#define PINMUX_PC14B_SLCD_LP26 ((PIN_PC14B_SLCD_LP26 << 16) | MUX_PC14B_SLCD_LP26) +#define PORT_PC14B_SLCD_LP26 (_UL_(1) << 14) +#define PIN_PC15B_SLCD_LP27 _L_(79) /**< \brief SLCD signal: LP27 on PC15 mux B */ +#define MUX_PC15B_SLCD_LP27 _L_(1) +#define PINMUX_PC15B_SLCD_LP27 ((PIN_PC15B_SLCD_LP27 << 16) | MUX_PC15B_SLCD_LP27) +#define PORT_PC15B_SLCD_LP27 (_UL_(1) << 15) +#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 _L_(1) +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) +#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 _L_(1) +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) +#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 _L_(1) +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) +#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 _L_(1) +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) +#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 _L_(1) +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) +#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 _L_(1) +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) +#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 _L_(1) +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) +#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 _L_(1) +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) +#define PIN_PC16B_SLCD_LP36 _L_(80) /**< \brief SLCD signal: LP36 on PC16 mux B */ +#define MUX_PC16B_SLCD_LP36 _L_(1) +#define PINMUX_PC16B_SLCD_LP36 ((PIN_PC16B_SLCD_LP36 << 16) | MUX_PC16B_SLCD_LP36) +#define PORT_PC16B_SLCD_LP36 (_UL_(1) << 16) +#define PIN_PC17B_SLCD_LP37 _L_(81) /**< \brief SLCD signal: LP37 on PC17 mux B */ +#define MUX_PC17B_SLCD_LP37 _L_(1) +#define PINMUX_PC17B_SLCD_LP37 ((PIN_PC17B_SLCD_LP37 << 16) | MUX_PC17B_SLCD_LP37) +#define PORT_PC17B_SLCD_LP37 (_UL_(1) << 17) +#define PIN_PC18B_SLCD_LP38 _L_(82) /**< \brief SLCD signal: LP38 on PC18 mux B */ +#define MUX_PC18B_SLCD_LP38 _L_(1) +#define PINMUX_PC18B_SLCD_LP38 ((PIN_PC18B_SLCD_LP38 << 16) | MUX_PC18B_SLCD_LP38) +#define PORT_PC18B_SLCD_LP38 (_UL_(1) << 18) +#define PIN_PC19B_SLCD_LP39 _L_(83) /**< \brief SLCD signal: LP39 on PC19 mux B */ +#define MUX_PC19B_SLCD_LP39 _L_(1) +#define PINMUX_PC19B_SLCD_LP39 ((PIN_PC19B_SLCD_LP39 << 16) | MUX_PC19B_SLCD_LP39) +#define PORT_PC19B_SLCD_LP39 (_UL_(1) << 19) +#define PIN_PC20B_SLCD_LP40 _L_(84) /**< \brief SLCD signal: LP40 on PC20 mux B */ +#define MUX_PC20B_SLCD_LP40 _L_(1) +#define PINMUX_PC20B_SLCD_LP40 ((PIN_PC20B_SLCD_LP40 << 16) | MUX_PC20B_SLCD_LP40) +#define PORT_PC20B_SLCD_LP40 (_UL_(1) << 20) +#define PIN_PC21B_SLCD_LP41 _L_(85) /**< \brief SLCD signal: LP41 on PC21 mux B */ +#define MUX_PC21B_SLCD_LP41 _L_(1) +#define PINMUX_PC21B_SLCD_LP41 ((PIN_PC21B_SLCD_LP41 << 16) | MUX_PC21B_SLCD_LP41) +#define PORT_PC21B_SLCD_LP41 (_UL_(1) << 21) +#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 _L_(1) +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) +#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 _L_(1) +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) +#define PIN_PB18B_SLCD_LP44 _L_(50) /**< \brief SLCD signal: LP44 on PB18 mux B */ +#define MUX_PB18B_SLCD_LP44 _L_(1) +#define PINMUX_PB18B_SLCD_LP44 ((PIN_PB18B_SLCD_LP44 << 16) | MUX_PB18B_SLCD_LP44) +#define PORT_PB18B_SLCD_LP44 (_UL_(1) << 18) +#define PIN_PB19B_SLCD_LP45 _L_(51) /**< \brief SLCD signal: LP45 on PB19 mux B */ +#define MUX_PB19B_SLCD_LP45 _L_(1) +#define PINMUX_PB19B_SLCD_LP45 ((PIN_PB19B_SLCD_LP45 << 16) | MUX_PB19B_SLCD_LP45) +#define PORT_PB19B_SLCD_LP45 (_UL_(1) << 19) +#define PIN_PB20B_SLCD_LP46 _L_(52) /**< \brief SLCD signal: LP46 on PB20 mux B */ +#define MUX_PB20B_SLCD_LP46 _L_(1) +#define PINMUX_PB20B_SLCD_LP46 ((PIN_PB20B_SLCD_LP46 << 16) | MUX_PB20B_SLCD_LP46) +#define PORT_PB20B_SLCD_LP46 (_UL_(1) << 20) +#define PIN_PB21B_SLCD_LP47 _L_(53) /**< \brief SLCD signal: LP47 on PB21 mux B */ +#define MUX_PB21B_SLCD_LP47 _L_(1) +#define PINMUX_PB21B_SLCD_LP47 ((PIN_PB21B_SLCD_LP47 << 16) | MUX_PB21B_SLCD_LP47) +#define PORT_PB21B_SLCD_LP47 (_UL_(1) << 21) +#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 _L_(1) +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) +#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 _L_(1) +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) +#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 _L_(1) +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) +#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 _L_(1) +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 _L_(8) +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 _L_(8) +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 _L_(8) +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 _L_(8) +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 _L_(8) +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 _L_(8) +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 _L_(8) +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 _L_(8) +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 _L_(8) +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 _L_(8) +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 _L_(8) +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 _L_(8) +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27I_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux I */ +#define MUX_PC27I_CCL_IN4 _L_(8) +#define PINMUX_PC27I_CCL_IN4 ((PIN_PC27I_CCL_IN4 << 16) | MUX_PC27I_CCL_IN4) +#define PORT_PC27I_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 _L_(8) +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28I_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux I */ +#define MUX_PC28I_CCL_IN5 _L_(8) +#define PINMUX_PC28I_CCL_IN5 ((PIN_PC28I_CCL_IN5 << 16) | MUX_PC28I_CCL_IN5) +#define PORT_PC28I_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 _L_(8) +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 _L_(8) +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 _L_(8) +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 _L_(8) +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 _L_(8) +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 _L_(8) +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 _L_(8) +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20I_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux I */ +#define MUX_PC20I_CCL_IN9 _L_(8) +#define PINMUX_PC20I_CCL_IN9 ((PIN_PC20I_CCL_IN9 << 16) | MUX_PC20I_CCL_IN9) +#define PORT_PC20I_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 _L_(8) +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21I_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux I */ +#define MUX_PC21I_CCL_IN10 _L_(8) +#define PINMUX_PC21I_CCL_IN10 ((PIN_PC21I_CCL_IN10 << 16) | MUX_PC21I_CCL_IN10) +#define PORT_PC21I_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 _L_(8) +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 _L_(8) +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 _L_(8) +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 _L_(8) +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 _L_(8) +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 _L_(8) +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 _L_(8) +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 _L_(8) +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 _L_(8) +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 _L_(8) +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 _L_(8) +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) + +#endif /* _SAML22N16A_PIO_ */ diff --git a/watch-library/hardware/include/pio/saml22n17a.h b/watch-library/hardware/include/pio/saml22n17a.h new file mode 100644 index 00000000..b7c98cd0 --- /dev/null +++ b/watch-library/hardware/include/pio/saml22n17a.h @@ -0,0 +1,1851 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22N17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N17A_PIO_ +#define _SAML22N17A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC08 72 /**< \brief Pin Number for PC08 */ +#define PORT_PC08 (_UL_(1) << 8) /**< \brief PORT Mask for PC08 */ +#define PIN_PC09 73 /**< \brief Pin Number for PC09 */ +#define PORT_PC09 (_UL_(1) << 9) /**< \brief PORT Mask for PC09 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 _L_(7) +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) +#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 _L_(7) +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) +#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK _L_(7) +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) +#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT _L_(7) +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 _L_(7) +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 _L_(7) +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 _L_(7) +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 _L_(7) +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) +#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 _L_(7) +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 _L_(7) +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 _L_(7) +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 _L_(7) +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 _L_(7) +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 _L_(7) +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 _L_(7) +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 _L_(7) +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 _L_(7) +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 _L_(7) +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 _L_(6) +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) +#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 _L_(6) +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) +#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 _L_(6) +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) +#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 _L_(5) +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) +#define PIN_PC00G_RTC_IN3 _L_(64) /**< \brief RTC signal: IN3 on PC00 mux G */ +#define MUX_PC00G_RTC_IN3 _L_(6) +#define PINMUX_PC00G_RTC_IN3 ((PIN_PC00G_RTC_IN3 << 16) | MUX_PC00G_RTC_IN3) +#define PORT_PC00G_RTC_IN3 (_UL_(1) << 0) +#define PIN_PC01G_RTC_IN4 _L_(65) /**< \brief RTC signal: IN4 on PC01 mux G */ +#define MUX_PC01G_RTC_IN4 _L_(6) +#define PINMUX_PC01G_RTC_IN4 ((PIN_PC01G_RTC_IN4 << 16) | MUX_PC01G_RTC_IN4) +#define PORT_PC01G_RTC_IN4 (_UL_(1) << 1) +#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT _L_(6) +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC08A_EIC_EXTINT0 _L_(72) /**< \brief EIC signal: EXTINT0 on PC08 mux A */ +#define MUX_PC08A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC08A_EIC_EXTINT0 ((PIN_PC08A_EIC_EXTINT0 << 16) | MUX_PC08A_EIC_EXTINT0) +#define PORT_PC08A_EIC_EXTINT0 (_UL_(1) << 8) +#define PIN_PC08A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC08 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT0 _L_(88) /**< \brief EIC signal: EXTINT0 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT0 ((PIN_PC24A_EIC_EXTINT0 << 16) | MUX_PC24A_EIC_EXTINT0) +#define PORT_PC24A_EIC_EXTINT0 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC09A_EIC_EXTINT1 _L_(73) /**< \brief EIC signal: EXTINT1 on PC09 mux A */ +#define MUX_PC09A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC09A_EIC_EXTINT1 ((PIN_PC09A_EIC_EXTINT1 << 16) | MUX_PC09A_EIC_EXTINT1) +#define PORT_PC09A_EIC_EXTINT1 (_UL_(1) << 9) +#define PIN_PC09A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC09 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT1 _L_(89) /**< \brief EIC signal: EXTINT1 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT1 ((PIN_PC25A_EIC_EXTINT1 << 16) | MUX_PC25A_EIC_EXTINT1) +#define PORT_PC25A_EIC_EXTINT1 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT2 _L_(74) /**< \brief EIC signal: EXTINT2 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT2 ((PIN_PC10A_EIC_EXTINT2 << 16) | MUX_PC10A_EIC_EXTINT2) +#define PORT_PC10A_EIC_EXTINT2 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT2 _L_(90) /**< \brief EIC signal: EXTINT2 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT2 ((PIN_PC26A_EIC_EXTINT2 << 16) | MUX_PC26A_EIC_EXTINT2) +#define PORT_PC26A_EIC_EXTINT2 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT3 _L_(75) /**< \brief EIC signal: EXTINT3 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT3 ((PIN_PC11A_EIC_EXTINT3 << 16) | MUX_PC11A_EIC_EXTINT3) +#define PORT_PC11A_EIC_EXTINT3 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT3 _L_(91) /**< \brief EIC signal: EXTINT3 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT3 ((PIN_PC27A_EIC_EXTINT3 << 16) | MUX_PC27A_EIC_EXTINT3) +#define PORT_PC27A_EIC_EXTINT3 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT4 _L_(76) /**< \brief EIC signal: EXTINT4 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT4 ((PIN_PC12A_EIC_EXTINT4 << 16) | MUX_PC12A_EIC_EXTINT4) +#define PORT_PC12A_EIC_EXTINT4 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT4 _L_(92) /**< \brief EIC signal: EXTINT4 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT4 ((PIN_PC28A_EIC_EXTINT4 << 16) | MUX_PC28A_EIC_EXTINT4) +#define PORT_PC28A_EIC_EXTINT4 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT5 _L_(77) /**< \brief EIC signal: EXTINT5 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT5 ((PIN_PC13A_EIC_EXTINT5 << 16) | MUX_PC13A_EIC_EXTINT5) +#define PORT_PC13A_EIC_EXTINT5 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT6 _L_(78) /**< \brief EIC signal: EXTINT6 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT6 ((PIN_PC14A_EIC_EXTINT6 << 16) | MUX_PC14A_EIC_EXTINT6) +#define PORT_PC14A_EIC_EXTINT6 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT7 _L_(79) /**< \brief EIC signal: EXTINT7 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT7 ((PIN_PC15A_EIC_EXTINT7 << 16) | MUX_PC15A_EIC_EXTINT7) +#define PORT_PC15A_EIC_EXTINT7 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT8 _L_(64) /**< \brief EIC signal: EXTINT8 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT8 ((PIN_PC00A_EIC_EXTINT8 << 16) | MUX_PC00A_EIC_EXTINT8) +#define PORT_PC00A_EIC_EXTINT8 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT8 _L_(80) /**< \brief EIC signal: EXTINT8 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT8 ((PIN_PC16A_EIC_EXTINT8 << 16) | MUX_PC16A_EIC_EXTINT8) +#define PORT_PC16A_EIC_EXTINT8 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT9 _L_(65) /**< \brief EIC signal: EXTINT9 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT9 ((PIN_PC01A_EIC_EXTINT9 << 16) | MUX_PC01A_EIC_EXTINT9) +#define PORT_PC01A_EIC_EXTINT9 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT9 _L_(81) /**< \brief EIC signal: EXTINT9 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT9 ((PIN_PC17A_EIC_EXTINT9 << 16) | MUX_PC17A_EIC_EXTINT9) +#define PORT_PC17A_EIC_EXTINT9 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT10 _L_(66) /**< \brief EIC signal: EXTINT10 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT10 ((PIN_PC02A_EIC_EXTINT10 << 16) | MUX_PC02A_EIC_EXTINT10) +#define PORT_PC02A_EIC_EXTINT10 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT10 _L_(82) /**< \brief EIC signal: EXTINT10 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT10 ((PIN_PC18A_EIC_EXTINT10 << 16) | MUX_PC18A_EIC_EXTINT10) +#define PORT_PC18A_EIC_EXTINT10 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT11 _L_(67) /**< \brief EIC signal: EXTINT11 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT11 ((PIN_PC03A_EIC_EXTINT11 << 16) | MUX_PC03A_EIC_EXTINT11) +#define PORT_PC03A_EIC_EXTINT11 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT11 _L_(83) /**< \brief EIC signal: EXTINT11 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT11 ((PIN_PC19A_EIC_EXTINT11 << 16) | MUX_PC19A_EIC_EXTINT11) +#define PORT_PC19A_EIC_EXTINT11 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT12 _L_(84) /**< \brief EIC signal: EXTINT12 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT12 ((PIN_PC20A_EIC_EXTINT12 << 16) | MUX_PC20A_EIC_EXTINT12) +#define PORT_PC20A_EIC_EXTINT12 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT13 _L_(69) /**< \brief EIC signal: EXTINT13 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT13 ((PIN_PC05A_EIC_EXTINT13 << 16) | MUX_PC05A_EIC_EXTINT13) +#define PORT_PC05A_EIC_EXTINT13 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT13 _L_(85) /**< \brief EIC signal: EXTINT13 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT13 ((PIN_PC21A_EIC_EXTINT13 << 16) | MUX_PC21A_EIC_EXTINT13) +#define PORT_PC21A_EIC_EXTINT13 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT14 _L_(70) /**< \brief EIC signal: EXTINT14 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT14 ((PIN_PC06A_EIC_EXTINT14 << 16) | MUX_PC06A_EIC_EXTINT14) +#define PORT_PC06A_EIC_EXTINT14 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT15 _L_(71) /**< \brief EIC signal: EXTINT15 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT15 ((PIN_PC07A_EIC_EXTINT15 << 16) | MUX_PC07A_EIC_EXTINT15) +#define PORT_PC07A_EIC_EXTINT15 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM _L_(6) +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (_UL_(1) << 24) +#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP _L_(6) +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (_UL_(1) << 25) +#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PC27D_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux D */ +#define MUX_PC27D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PC27D_SERCOM1_PAD0 ((PIN_PC27D_SERCOM1_PAD0 << 16) | MUX_PC27D_SERCOM1_PAD0) +#define PORT_PC27D_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC12C_SERCOM1_PAD0 _L_(76) /**< \brief SERCOM1 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM1_PAD0 ((PIN_PC12C_SERCOM1_PAD0 << 16) | MUX_PC12C_SERCOM1_PAD0) +#define PORT_PC12C_SERCOM1_PAD0 (_UL_(1) << 12) +#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PC28D_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux D */ +#define MUX_PC28D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PC28D_SERCOM1_PAD1 ((PIN_PC28D_SERCOM1_PAD1 << 16) | MUX_PC28D_SERCOM1_PAD1) +#define PORT_PC28D_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC13C_SERCOM1_PAD1 _L_(77) /**< \brief SERCOM1 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM1_PAD1 ((PIN_PC13C_SERCOM1_PAD1 << 16) | MUX_PC13C_SERCOM1_PAD1) +#define PORT_PC13C_SERCOM1_PAD1 (_UL_(1) << 13) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PC10C_SERCOM1_PAD2 _L_(74) /**< \brief SERCOM1 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM1_PAD2 ((PIN_PC10C_SERCOM1_PAD2 << 16) | MUX_PC10C_SERCOM1_PAD2) +#define PORT_PC10C_SERCOM1_PAD2 (_UL_(1) << 10) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PC11C_SERCOM1_PAD3 _L_(75) /**< \brief SERCOM1 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM1_PAD3 ((PIN_PC11C_SERCOM1_PAD3 << 16) | MUX_PC11C_SERCOM1_PAD3) +#define PORT_PC11C_SERCOM1_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) +#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) +#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) +#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) +#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) +#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PB18D_SERCOM3_PAD2 _L_(50) /**< \brief SERCOM3 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM3_PAD2 ((PIN_PB18D_SERCOM3_PAD2 << 16) | MUX_PB18D_SERCOM3_PAD2) +#define PORT_PB18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) +#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) +#define PIN_PB19D_SERCOM3_PAD3 _L_(51) /**< \brief SERCOM3 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM3_PAD3 ((PIN_PB19D_SERCOM3_PAD3 << 16) | MUX_PB19D_SERCOM3_PAD3) +#define PORT_PB19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA08D_SERCOM4_PAD0 _L_(8) /**< \brief SERCOM4 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA08D_SERCOM4_PAD0 ((PIN_PA08D_SERCOM4_PAD0 << 16) | MUX_PA08D_SERCOM4_PAD0) +#define PORT_PA08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM4_PAD0 _L_(56) /**< \brief SERCOM4 signal: PAD0 on PB24 mux D */ +#define MUX_PB24D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB24D_SERCOM4_PAD0 ((PIN_PB24D_SERCOM4_PAD0 << 16) | MUX_PB24D_SERCOM4_PAD0) +#define PORT_PB24D_SERCOM4_PAD0 (_UL_(1) << 24) +#define PIN_PA12C_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM4_PAD0 ((PIN_PA12C_SERCOM4_PAD0 << 16) | MUX_PA12C_SERCOM4_PAD0) +#define PORT_PA12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA09D_SERCOM4_PAD1 _L_(9) /**< \brief SERCOM4 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA09D_SERCOM4_PAD1 ((PIN_PA09D_SERCOM4_PAD1 << 16) | MUX_PA09D_SERCOM4_PAD1) +#define PORT_PA09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM4_PAD1 _L_(57) /**< \brief SERCOM4 signal: PAD1 on PB25 mux D */ +#define MUX_PB25D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB25D_SERCOM4_PAD1 ((PIN_PB25D_SERCOM4_PAD1 << 16) | MUX_PB25D_SERCOM4_PAD1) +#define PORT_PB25D_SERCOM4_PAD1 (_UL_(1) << 25) +#define PIN_PA13C_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM4_PAD1 ((PIN_PA13C_SERCOM4_PAD1 << 16) | MUX_PA13C_SERCOM4_PAD1) +#define PORT_PA13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM4_PAD2 _L_(10) /**< \brief SERCOM4 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM4_PAD2 ((PIN_PA10D_SERCOM4_PAD2 << 16) | MUX_PA10D_SERCOM4_PAD2) +#define PORT_PA10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM4_PAD2 _L_(88) /**< \brief SERCOM4 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM4_PAD2 ((PIN_PC24D_SERCOM4_PAD2 << 16) | MUX_PC24D_SERCOM4_PAD2) +#define PORT_PC24D_SERCOM4_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM4_PAD2 ((PIN_PA14C_SERCOM4_PAD2 << 16) | MUX_PA14C_SERCOM4_PAD2) +#define PORT_PA14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM4_PAD3 _L_(11) /**< \brief SERCOM4 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM4_PAD3 ((PIN_PA11D_SERCOM4_PAD3 << 16) | MUX_PA11D_SERCOM4_PAD3) +#define PORT_PA11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM4_PAD3 _L_(89) /**< \brief SERCOM4 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM4_PAD3 ((PIN_PC25D_SERCOM4_PAD3 << 16) | MUX_PC25D_SERCOM4_PAD3) +#define PORT_PC25D_SERCOM4_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM4_PAD3 ((PIN_PA15C_SERCOM4_PAD3 << 16) | MUX_PA15C_SERCOM4_PAD3) +#define PORT_PA15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) +#define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) +#define PIN_PA24D_SERCOM5_PAD0 _L_(24) /**< \brief SERCOM5 signal: PAD0 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD0 ((PIN_PA24D_SERCOM5_PAD0 << 16) | MUX_PA24D_SERCOM5_PAD0) +#define PORT_PA24D_SERCOM5_PAD0 (_UL_(1) << 24) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB20D_SERCOM5_PAD0 _L_(52) /**< \brief SERCOM5 signal: PAD0 on PB20 mux D */ +#define MUX_PB20D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB20D_SERCOM5_PAD0 ((PIN_PB20D_SERCOM5_PAD0 << 16) | MUX_PB20D_SERCOM5_PAD0) +#define PORT_PB20D_SERCOM5_PAD0 (_UL_(1) << 20) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) +#define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) +#define PIN_PA25D_SERCOM5_PAD1 _L_(25) /**< \brief SERCOM5 signal: PAD1 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD1 ((PIN_PA25D_SERCOM5_PAD1 << 16) | MUX_PA25D_SERCOM5_PAD1) +#define PORT_PA25D_SERCOM5_PAD1 (_UL_(1) << 25) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB21D_SERCOM5_PAD1 _L_(53) /**< \brief SERCOM5 signal: PAD1 on PB21 mux D */ +#define MUX_PB21D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB21D_SERCOM5_PAD1 ((PIN_PB21D_SERCOM5_PAD1 << 16) | MUX_PB21D_SERCOM5_PAD1) +#define PORT_PB21D_SERCOM5_PAD1 (_UL_(1) << 21) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 _L_(5) +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PB18F_TCC0_WO0 _L_(50) /**< \brief TCC0 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC0_WO0 _L_(5) +#define PINMUX_PB18F_TCC0_WO0 ((PIN_PB18F_TCC0_WO0 << 16) | MUX_PB18F_TCC0_WO0) +#define PORT_PB18F_TCC0_WO0 (_UL_(1) << 18) +#define PIN_PC24F_TCC0_WO0 _L_(88) /**< \brief TCC0 signal: WO0 on PC24 mux F */ +#define MUX_PC24F_TCC0_WO0 _L_(5) +#define PINMUX_PC24F_TCC0_WO0 ((PIN_PC24F_TCC0_WO0 << 16) | MUX_PC24F_TCC0_WO0) +#define PORT_PC24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 _L_(4) +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 _L_(4) +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 _L_(4) +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) +#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 _L_(5) +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PB19F_TCC0_WO1 _L_(51) /**< \brief TCC0 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC0_WO1 _L_(5) +#define PINMUX_PB19F_TCC0_WO1 ((PIN_PB19F_TCC0_WO1 << 16) | MUX_PB19F_TCC0_WO1) +#define PORT_PB19F_TCC0_WO1 (_UL_(1) << 19) +#define PIN_PC25F_TCC0_WO1 _L_(89) /**< \brief TCC0 signal: WO1 on PC25 mux F */ +#define MUX_PC25F_TCC0_WO1 _L_(5) +#define PINMUX_PC25F_TCC0_WO1 ((PIN_PC25F_TCC0_WO1 << 16) | MUX_PC25F_TCC0_WO1) +#define PORT_PC25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 _L_(4) +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 _L_(4) +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 _L_(4) +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 _L_(5) +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC0_WO2 _L_(52) /**< \brief TCC0 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC0_WO2 _L_(5) +#define PINMUX_PB20F_TCC0_WO2 ((PIN_PB20F_TCC0_WO2 << 16) | MUX_PB20F_TCC0_WO2) +#define PORT_PB20F_TCC0_WO2 (_UL_(1) << 20) +#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 _L_(5) +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PC26F_TCC0_WO2 _L_(90) /**< \brief TCC0 signal: WO2 on PC26 mux F */ +#define MUX_PC26F_TCC0_WO2 _L_(5) +#define PINMUX_PC26F_TCC0_WO2 ((PIN_PC26F_TCC0_WO2 << 16) | MUX_PC26F_TCC0_WO2) +#define PORT_PC26F_TCC0_WO2 (_UL_(1) << 26) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 _L_(5) +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC0_WO3 _L_(53) /**< \brief TCC0 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC0_WO3 _L_(5) +#define PINMUX_PB21F_TCC0_WO3 ((PIN_PB21F_TCC0_WO3 << 16) | MUX_PB21F_TCC0_WO3) +#define PORT_PB21F_TCC0_WO3 (_UL_(1) << 21) +#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 _L_(5) +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PC27F_TCC0_WO3 _L_(91) /**< \brief TCC0 signal: WO3 on PC27 mux F */ +#define MUX_PC27F_TCC0_WO3 _L_(5) +#define PINMUX_PC27F_TCC0_WO3 ((PIN_PC27F_TCC0_WO3 << 16) | MUX_PC27F_TCC0_WO3) +#define PORT_PC27F_TCC0_WO3 (_UL_(1) << 27) +#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 _L_(5) +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) +#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 _L_(5) +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PC28F_TCC0_WO4 _L_(92) /**< \brief TCC0 signal: WO4 on PC28 mux F */ +#define MUX_PC28F_TCC0_WO4 _L_(5) +#define PINMUX_PC28F_TCC0_WO4 ((PIN_PC28F_TCC0_WO4 << 16) | MUX_PC28F_TCC0_WO4) +#define PORT_PC28F_TCC0_WO4 (_UL_(1) << 28) +#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 _L_(5) +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 _L_(5) +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 _L_(5) +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) +#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 _L_(5) +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 _L_(5) +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 _L_(5) +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) +#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 _L_(5) +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) +#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 _L_(5) +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PB24F_TCC0_WO6 _L_(56) /**< \brief TCC0 signal: WO6 on PB24 mux F */ +#define MUX_PB24F_TCC0_WO6 _L_(5) +#define PINMUX_PB24F_TCC0_WO6 ((PIN_PB24F_TCC0_WO6 << 16) | MUX_PB24F_TCC0_WO6) +#define PORT_PB24F_TCC0_WO6 (_UL_(1) << 24) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 _L_(5) +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) +#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 _L_(5) +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) +#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 _L_(5) +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PB25F_TCC0_WO7 _L_(57) /**< \brief TCC0 signal: WO7 on PB25 mux F */ +#define MUX_PB25F_TCC0_WO7 _L_(5) +#define PINMUX_PB25F_TCC0_WO7 ((PIN_PB25F_TCC0_WO7 << 16) | MUX_PB25F_TCC0_WO7) +#define PORT_PB25F_TCC0_WO7 (_UL_(1) << 25) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 _L_(4) +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 _L_(4) +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 _L_(4) +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 _L_(4) +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 _L_(4) +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 _L_(4) +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 _L_(4) +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) +#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 _L_(4) +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 _L_(4) +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 _L_(4) +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 _L_(4) +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 _L_(4) +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 _L_(4) +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PC24E_TC2_WO0 _L_(88) /**< \brief TC2 signal: WO0 on PC24 mux E */ +#define MUX_PC24E_TC2_WO0 _L_(4) +#define PINMUX_PC24E_TC2_WO0 ((PIN_PC24E_TC2_WO0 << 16) | MUX_PC24E_TC2_WO0) +#define PORT_PC24E_TC2_WO0 (_UL_(1) << 24) +#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 _L_(4) +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 _L_(4) +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) +#define PIN_PC25E_TC2_WO1 _L_(89) /**< \brief TC2 signal: WO1 on PC25 mux E */ +#define MUX_PC25E_TC2_WO1 _L_(4) +#define PINMUX_PC25E_TC2_WO1 ((PIN_PC25E_TC2_WO1 << 16) | MUX_PC25E_TC2_WO1) +#define PORT_PC25E_TC2_WO1 (_UL_(1) << 25) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 _L_(4) +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 _L_(4) +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 _L_(4) +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) +#define PIN_PC26E_TC3_WO0 _L_(90) /**< \brief TC3 signal: WO0 on PC26 mux E */ +#define MUX_PC26E_TC3_WO0 _L_(4) +#define PINMUX_PC26E_TC3_WO0 ((PIN_PC26E_TC3_WO0 << 16) | MUX_PC26E_TC3_WO0) +#define PORT_PC26E_TC3_WO0 (_UL_(1) << 26) +#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 _L_(4) +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 _L_(4) +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 _L_(4) +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) +#define PIN_PC27E_TC3_WO1 _L_(91) /**< \brief TC3 signal: WO1 on PC27 mux E */ +#define MUX_PC27E_TC3_WO1 _L_(4) +#define PINMUX_PC27E_TC3_WO1 ((PIN_PC27E_TC3_WO1 << 16) | MUX_PC27E_TC3_WO1) +#define PORT_PC27E_TC3_WO1 (_UL_(1) << 27) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 _L_(1) +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 _L_(1) +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 _L_(1) +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 _L_(1) +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 _L_(1) +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 _L_(1) +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 _L_(1) +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 _L_(1) +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) +#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 _L_(1) +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) +#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 _L_(1) +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) +#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 _L_(1) +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) +#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 _L_(1) +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) +#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 _L_(1) +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) +#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 _L_(1) +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) +#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 _L_(1) +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) +#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 _L_(1) +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) +#define PIN_PC00B_ADC_AIN16 _L_(64) /**< \brief ADC signal: AIN16 on PC00 mux B */ +#define MUX_PC00B_ADC_AIN16 _L_(1) +#define PINMUX_PC00B_ADC_AIN16 ((PIN_PC00B_ADC_AIN16 << 16) | MUX_PC00B_ADC_AIN16) +#define PORT_PC00B_ADC_AIN16 (_UL_(1) << 0) +#define PIN_PC01B_ADC_AIN17 _L_(65) /**< \brief ADC signal: AIN17 on PC01 mux B */ +#define MUX_PC01B_ADC_AIN17 _L_(1) +#define PINMUX_PC01B_ADC_AIN17 ((PIN_PC01B_ADC_AIN17 << 16) | MUX_PC01B_ADC_AIN17) +#define PORT_PC01B_ADC_AIN17 (_UL_(1) << 1) +#define PIN_PC02B_ADC_AIN18 _L_(66) /**< \brief ADC signal: AIN18 on PC02 mux B */ +#define MUX_PC02B_ADC_AIN18 _L_(1) +#define PINMUX_PC02B_ADC_AIN18 ((PIN_PC02B_ADC_AIN18 << 16) | MUX_PC02B_ADC_AIN18) +#define PORT_PC02B_ADC_AIN18 (_UL_(1) << 2) +#define PIN_PC03B_ADC_AIN19 _L_(67) /**< \brief ADC signal: AIN19 on PC03 mux B */ +#define MUX_PC03B_ADC_AIN19 _L_(1) +#define PINMUX_PC03B_ADC_AIN19 ((PIN_PC03B_ADC_AIN19 << 16) | MUX_PC03B_ADC_AIN19) +#define PORT_PC03B_ADC_AIN19 (_UL_(1) << 3) +#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA _L_(1) +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) +#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB _L_(1) +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 _L_(1) +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 _L_(1) +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) +#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 _L_(1) +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) +#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 _L_(1) +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) +#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 _L_(7) +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 _L_(7) +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24H_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux H */ +#define MUX_PB24H_AC_CMP0 _L_(7) +#define PINMUX_PB24H_AC_CMP0 ((PIN_PB24H_AC_CMP0 << 16) | MUX_PB24H_AC_CMP0) +#define PORT_PB24H_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 _L_(7) +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 _L_(7) +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25H_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux H */ +#define MUX_PB25H_AC_CMP1 _L_(7) +#define PINMUX_PB25H_AC_CMP1 ((PIN_PB25H_AC_CMP1 << 16) | MUX_PB25H_AC_CMP1) +#define PORT_PB25H_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 _L_(1) +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) +#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 _L_(1) +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) +#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 _L_(1) +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) +#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 _L_(1) +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) +#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 _L_(1) +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) +#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 _L_(1) +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) +#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 _L_(1) +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) +#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 _L_(1) +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) +#define PIN_PC05B_SLCD_LP8 _L_(69) /**< \brief SLCD signal: LP8 on PC05 mux B */ +#define MUX_PC05B_SLCD_LP8 _L_(1) +#define PINMUX_PC05B_SLCD_LP8 ((PIN_PC05B_SLCD_LP8 << 16) | MUX_PC05B_SLCD_LP8) +#define PORT_PC05B_SLCD_LP8 (_UL_(1) << 5) +#define PIN_PC06B_SLCD_LP9 _L_(70) /**< \brief SLCD signal: LP9 on PC06 mux B */ +#define MUX_PC06B_SLCD_LP9 _L_(1) +#define PINMUX_PC06B_SLCD_LP9 ((PIN_PC06B_SLCD_LP9 << 16) | MUX_PC06B_SLCD_LP9) +#define PORT_PC06B_SLCD_LP9 (_UL_(1) << 6) +#define PIN_PC07B_SLCD_LP10 _L_(71) /**< \brief SLCD signal: LP10 on PC07 mux B */ +#define MUX_PC07B_SLCD_LP10 _L_(1) +#define PINMUX_PC07B_SLCD_LP10 ((PIN_PC07B_SLCD_LP10 << 16) | MUX_PC07B_SLCD_LP10) +#define PORT_PC07B_SLCD_LP10 (_UL_(1) << 7) +#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 _L_(1) +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) +#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 _L_(1) +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) +#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 _L_(1) +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) +#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 _L_(1) +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) +#define PIN_PC08B_SLCD_LP15 _L_(72) /**< \brief SLCD signal: LP15 on PC08 mux B */ +#define MUX_PC08B_SLCD_LP15 _L_(1) +#define PINMUX_PC08B_SLCD_LP15 ((PIN_PC08B_SLCD_LP15 << 16) | MUX_PC08B_SLCD_LP15) +#define PORT_PC08B_SLCD_LP15 (_UL_(1) << 8) +#define PIN_PC09B_SLCD_LP16 _L_(73) /**< \brief SLCD signal: LP16 on PC09 mux B */ +#define MUX_PC09B_SLCD_LP16 _L_(1) +#define PINMUX_PC09B_SLCD_LP16 ((PIN_PC09B_SLCD_LP16 << 16) | MUX_PC09B_SLCD_LP16) +#define PORT_PC09B_SLCD_LP16 (_UL_(1) << 9) +#define PIN_PC10B_SLCD_LP17 _L_(74) /**< \brief SLCD signal: LP17 on PC10 mux B */ +#define MUX_PC10B_SLCD_LP17 _L_(1) +#define PINMUX_PC10B_SLCD_LP17 ((PIN_PC10B_SLCD_LP17 << 16) | MUX_PC10B_SLCD_LP17) +#define PORT_PC10B_SLCD_LP17 (_UL_(1) << 10) +#define PIN_PC11B_SLCD_LP18 _L_(75) /**< \brief SLCD signal: LP18 on PC11 mux B */ +#define MUX_PC11B_SLCD_LP18 _L_(1) +#define PINMUX_PC11B_SLCD_LP18 ((PIN_PC11B_SLCD_LP18 << 16) | MUX_PC11B_SLCD_LP18) +#define PORT_PC11B_SLCD_LP18 (_UL_(1) << 11) +#define PIN_PC12B_SLCD_LP19 _L_(76) /**< \brief SLCD signal: LP19 on PC12 mux B */ +#define MUX_PC12B_SLCD_LP19 _L_(1) +#define PINMUX_PC12B_SLCD_LP19 ((PIN_PC12B_SLCD_LP19 << 16) | MUX_PC12B_SLCD_LP19) +#define PORT_PC12B_SLCD_LP19 (_UL_(1) << 12) +#define PIN_PC13B_SLCD_LP20 _L_(77) /**< \brief SLCD signal: LP20 on PC13 mux B */ +#define MUX_PC13B_SLCD_LP20 _L_(1) +#define PINMUX_PC13B_SLCD_LP20 ((PIN_PC13B_SLCD_LP20 << 16) | MUX_PC13B_SLCD_LP20) +#define PORT_PC13B_SLCD_LP20 (_UL_(1) << 13) +#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 _L_(1) +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) +#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 _L_(1) +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) +#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 _L_(1) +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) +#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 _L_(1) +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) +#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 _L_(1) +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) +#define PIN_PC14B_SLCD_LP26 _L_(78) /**< \brief SLCD signal: LP26 on PC14 mux B */ +#define MUX_PC14B_SLCD_LP26 _L_(1) +#define PINMUX_PC14B_SLCD_LP26 ((PIN_PC14B_SLCD_LP26 << 16) | MUX_PC14B_SLCD_LP26) +#define PORT_PC14B_SLCD_LP26 (_UL_(1) << 14) +#define PIN_PC15B_SLCD_LP27 _L_(79) /**< \brief SLCD signal: LP27 on PC15 mux B */ +#define MUX_PC15B_SLCD_LP27 _L_(1) +#define PINMUX_PC15B_SLCD_LP27 ((PIN_PC15B_SLCD_LP27 << 16) | MUX_PC15B_SLCD_LP27) +#define PORT_PC15B_SLCD_LP27 (_UL_(1) << 15) +#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 _L_(1) +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) +#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 _L_(1) +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) +#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 _L_(1) +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) +#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 _L_(1) +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) +#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 _L_(1) +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) +#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 _L_(1) +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) +#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 _L_(1) +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) +#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 _L_(1) +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) +#define PIN_PC16B_SLCD_LP36 _L_(80) /**< \brief SLCD signal: LP36 on PC16 mux B */ +#define MUX_PC16B_SLCD_LP36 _L_(1) +#define PINMUX_PC16B_SLCD_LP36 ((PIN_PC16B_SLCD_LP36 << 16) | MUX_PC16B_SLCD_LP36) +#define PORT_PC16B_SLCD_LP36 (_UL_(1) << 16) +#define PIN_PC17B_SLCD_LP37 _L_(81) /**< \brief SLCD signal: LP37 on PC17 mux B */ +#define MUX_PC17B_SLCD_LP37 _L_(1) +#define PINMUX_PC17B_SLCD_LP37 ((PIN_PC17B_SLCD_LP37 << 16) | MUX_PC17B_SLCD_LP37) +#define PORT_PC17B_SLCD_LP37 (_UL_(1) << 17) +#define PIN_PC18B_SLCD_LP38 _L_(82) /**< \brief SLCD signal: LP38 on PC18 mux B */ +#define MUX_PC18B_SLCD_LP38 _L_(1) +#define PINMUX_PC18B_SLCD_LP38 ((PIN_PC18B_SLCD_LP38 << 16) | MUX_PC18B_SLCD_LP38) +#define PORT_PC18B_SLCD_LP38 (_UL_(1) << 18) +#define PIN_PC19B_SLCD_LP39 _L_(83) /**< \brief SLCD signal: LP39 on PC19 mux B */ +#define MUX_PC19B_SLCD_LP39 _L_(1) +#define PINMUX_PC19B_SLCD_LP39 ((PIN_PC19B_SLCD_LP39 << 16) | MUX_PC19B_SLCD_LP39) +#define PORT_PC19B_SLCD_LP39 (_UL_(1) << 19) +#define PIN_PC20B_SLCD_LP40 _L_(84) /**< \brief SLCD signal: LP40 on PC20 mux B */ +#define MUX_PC20B_SLCD_LP40 _L_(1) +#define PINMUX_PC20B_SLCD_LP40 ((PIN_PC20B_SLCD_LP40 << 16) | MUX_PC20B_SLCD_LP40) +#define PORT_PC20B_SLCD_LP40 (_UL_(1) << 20) +#define PIN_PC21B_SLCD_LP41 _L_(85) /**< \brief SLCD signal: LP41 on PC21 mux B */ +#define MUX_PC21B_SLCD_LP41 _L_(1) +#define PINMUX_PC21B_SLCD_LP41 ((PIN_PC21B_SLCD_LP41 << 16) | MUX_PC21B_SLCD_LP41) +#define PORT_PC21B_SLCD_LP41 (_UL_(1) << 21) +#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 _L_(1) +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) +#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 _L_(1) +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) +#define PIN_PB18B_SLCD_LP44 _L_(50) /**< \brief SLCD signal: LP44 on PB18 mux B */ +#define MUX_PB18B_SLCD_LP44 _L_(1) +#define PINMUX_PB18B_SLCD_LP44 ((PIN_PB18B_SLCD_LP44 << 16) | MUX_PB18B_SLCD_LP44) +#define PORT_PB18B_SLCD_LP44 (_UL_(1) << 18) +#define PIN_PB19B_SLCD_LP45 _L_(51) /**< \brief SLCD signal: LP45 on PB19 mux B */ +#define MUX_PB19B_SLCD_LP45 _L_(1) +#define PINMUX_PB19B_SLCD_LP45 ((PIN_PB19B_SLCD_LP45 << 16) | MUX_PB19B_SLCD_LP45) +#define PORT_PB19B_SLCD_LP45 (_UL_(1) << 19) +#define PIN_PB20B_SLCD_LP46 _L_(52) /**< \brief SLCD signal: LP46 on PB20 mux B */ +#define MUX_PB20B_SLCD_LP46 _L_(1) +#define PINMUX_PB20B_SLCD_LP46 ((PIN_PB20B_SLCD_LP46 << 16) | MUX_PB20B_SLCD_LP46) +#define PORT_PB20B_SLCD_LP46 (_UL_(1) << 20) +#define PIN_PB21B_SLCD_LP47 _L_(53) /**< \brief SLCD signal: LP47 on PB21 mux B */ +#define MUX_PB21B_SLCD_LP47 _L_(1) +#define PINMUX_PB21B_SLCD_LP47 ((PIN_PB21B_SLCD_LP47 << 16) | MUX_PB21B_SLCD_LP47) +#define PORT_PB21B_SLCD_LP47 (_UL_(1) << 21) +#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 _L_(1) +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) +#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 _L_(1) +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) +#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 _L_(1) +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) +#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 _L_(1) +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 _L_(8) +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 _L_(8) +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 _L_(8) +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 _L_(8) +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 _L_(8) +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 _L_(8) +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 _L_(8) +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 _L_(8) +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 _L_(8) +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 _L_(8) +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 _L_(8) +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 _L_(8) +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27I_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux I */ +#define MUX_PC27I_CCL_IN4 _L_(8) +#define PINMUX_PC27I_CCL_IN4 ((PIN_PC27I_CCL_IN4 << 16) | MUX_PC27I_CCL_IN4) +#define PORT_PC27I_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 _L_(8) +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28I_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux I */ +#define MUX_PC28I_CCL_IN5 _L_(8) +#define PINMUX_PC28I_CCL_IN5 ((PIN_PC28I_CCL_IN5 << 16) | MUX_PC28I_CCL_IN5) +#define PORT_PC28I_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 _L_(8) +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 _L_(8) +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 _L_(8) +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 _L_(8) +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 _L_(8) +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 _L_(8) +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 _L_(8) +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20I_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux I */ +#define MUX_PC20I_CCL_IN9 _L_(8) +#define PINMUX_PC20I_CCL_IN9 ((PIN_PC20I_CCL_IN9 << 16) | MUX_PC20I_CCL_IN9) +#define PORT_PC20I_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 _L_(8) +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21I_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux I */ +#define MUX_PC21I_CCL_IN10 _L_(8) +#define PINMUX_PC21I_CCL_IN10 ((PIN_PC21I_CCL_IN10 << 16) | MUX_PC21I_CCL_IN10) +#define PORT_PC21I_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 _L_(8) +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 _L_(8) +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 _L_(8) +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 _L_(8) +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 _L_(8) +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 _L_(8) +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 _L_(8) +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 _L_(8) +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 _L_(8) +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 _L_(8) +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 _L_(8) +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) + +#endif /* _SAML22N17A_PIO_ */ diff --git a/watch-library/hardware/include/pio/saml22n18a.h b/watch-library/hardware/include/pio/saml22n18a.h new file mode 100644 index 00000000..ad683b1d --- /dev/null +++ b/watch-library/hardware/include/pio/saml22n18a.h @@ -0,0 +1,1851 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML22N18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N18A_PIO_ +#define _SAML22N18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC08 72 /**< \brief Pin Number for PC08 */ +#define PORT_PC08 (_UL_(1) << 8) /**< \brief PORT Mask for PC08 */ +#define PIN_PC09 73 /**< \brief Pin Number for PC09 */ +#define PORT_PC09 (_UL_(1) << 9) /**< \brief PORT Mask for PC09 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 _L_(7) +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) +#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 _L_(7) +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) +#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK _L_(7) +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) +#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT _L_(7) +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 _L_(7) +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 _L_(7) +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 _L_(7) +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 _L_(7) +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) +#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 _L_(7) +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 _L_(7) +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 _L_(7) +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 _L_(7) +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 _L_(7) +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 _L_(7) +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 _L_(7) +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 _L_(7) +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 _L_(7) +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 _L_(7) +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) +/* ========== PORT definition for RTC peripheral ========== */ +#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ +#define MUX_PB00G_RTC_IN0 _L_(6) +#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) +#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) +#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ +#define MUX_PB02G_RTC_IN1 _L_(6) +#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) +#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) +#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ +#define MUX_PA02G_RTC_IN2 _L_(6) +#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) +#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) +#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ +#define MUX_PB01F_RTC_IN2 _L_(5) +#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) +#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) +#define PIN_PC00G_RTC_IN3 _L_(64) /**< \brief RTC signal: IN3 on PC00 mux G */ +#define MUX_PC00G_RTC_IN3 _L_(6) +#define PINMUX_PC00G_RTC_IN3 ((PIN_PC00G_RTC_IN3 << 16) | MUX_PC00G_RTC_IN3) +#define PORT_PC00G_RTC_IN3 (_UL_(1) << 0) +#define PIN_PC01G_RTC_IN4 _L_(65) /**< \brief RTC signal: IN4 on PC01 mux G */ +#define MUX_PC01G_RTC_IN4 _L_(6) +#define PINMUX_PC01G_RTC_IN4 ((PIN_PC01G_RTC_IN4 << 16) | MUX_PC01G_RTC_IN4) +#define PORT_PC01G_RTC_IN4 (_UL_(1) << 1) +#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ +#define MUX_PB01G_RTC_OUT _L_(6) +#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) +#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC08A_EIC_EXTINT0 _L_(72) /**< \brief EIC signal: EXTINT0 on PC08 mux A */ +#define MUX_PC08A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC08A_EIC_EXTINT0 ((PIN_PC08A_EIC_EXTINT0 << 16) | MUX_PC08A_EIC_EXTINT0) +#define PORT_PC08A_EIC_EXTINT0 (_UL_(1) << 8) +#define PIN_PC08A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC08 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT0 _L_(88) /**< \brief EIC signal: EXTINT0 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT0 ((PIN_PC24A_EIC_EXTINT0 << 16) | MUX_PC24A_EIC_EXTINT0) +#define PORT_PC24A_EIC_EXTINT0 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC09A_EIC_EXTINT1 _L_(73) /**< \brief EIC signal: EXTINT1 on PC09 mux A */ +#define MUX_PC09A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC09A_EIC_EXTINT1 ((PIN_PC09A_EIC_EXTINT1 << 16) | MUX_PC09A_EIC_EXTINT1) +#define PORT_PC09A_EIC_EXTINT1 (_UL_(1) << 9) +#define PIN_PC09A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC09 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT1 _L_(89) /**< \brief EIC signal: EXTINT1 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT1 ((PIN_PC25A_EIC_EXTINT1 << 16) | MUX_PC25A_EIC_EXTINT1) +#define PORT_PC25A_EIC_EXTINT1 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT2 _L_(74) /**< \brief EIC signal: EXTINT2 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT2 ((PIN_PC10A_EIC_EXTINT2 << 16) | MUX_PC10A_EIC_EXTINT2) +#define PORT_PC10A_EIC_EXTINT2 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT2 _L_(90) /**< \brief EIC signal: EXTINT2 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT2 ((PIN_PC26A_EIC_EXTINT2 << 16) | MUX_PC26A_EIC_EXTINT2) +#define PORT_PC26A_EIC_EXTINT2 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT3 _L_(75) /**< \brief EIC signal: EXTINT3 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT3 ((PIN_PC11A_EIC_EXTINT3 << 16) | MUX_PC11A_EIC_EXTINT3) +#define PORT_PC11A_EIC_EXTINT3 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT3 _L_(91) /**< \brief EIC signal: EXTINT3 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT3 ((PIN_PC27A_EIC_EXTINT3 << 16) | MUX_PC27A_EIC_EXTINT3) +#define PORT_PC27A_EIC_EXTINT3 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT4 _L_(76) /**< \brief EIC signal: EXTINT4 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT4 ((PIN_PC12A_EIC_EXTINT4 << 16) | MUX_PC12A_EIC_EXTINT4) +#define PORT_PC12A_EIC_EXTINT4 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT4 _L_(92) /**< \brief EIC signal: EXTINT4 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT4 ((PIN_PC28A_EIC_EXTINT4 << 16) | MUX_PC28A_EIC_EXTINT4) +#define PORT_PC28A_EIC_EXTINT4 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT5 _L_(77) /**< \brief EIC signal: EXTINT5 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT5 ((PIN_PC13A_EIC_EXTINT5 << 16) | MUX_PC13A_EIC_EXTINT5) +#define PORT_PC13A_EIC_EXTINT5 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT6 _L_(78) /**< \brief EIC signal: EXTINT6 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT6 ((PIN_PC14A_EIC_EXTINT6 << 16) | MUX_PC14A_EIC_EXTINT6) +#define PORT_PC14A_EIC_EXTINT6 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT7 _L_(79) /**< \brief EIC signal: EXTINT7 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT7 ((PIN_PC15A_EIC_EXTINT7 << 16) | MUX_PC15A_EIC_EXTINT7) +#define PORT_PC15A_EIC_EXTINT7 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT8 _L_(64) /**< \brief EIC signal: EXTINT8 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT8 ((PIN_PC00A_EIC_EXTINT8 << 16) | MUX_PC00A_EIC_EXTINT8) +#define PORT_PC00A_EIC_EXTINT8 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT8 _L_(80) /**< \brief EIC signal: EXTINT8 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT8 ((PIN_PC16A_EIC_EXTINT8 << 16) | MUX_PC16A_EIC_EXTINT8) +#define PORT_PC16A_EIC_EXTINT8 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT9 _L_(65) /**< \brief EIC signal: EXTINT9 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT9 ((PIN_PC01A_EIC_EXTINT9 << 16) | MUX_PC01A_EIC_EXTINT9) +#define PORT_PC01A_EIC_EXTINT9 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT9 _L_(81) /**< \brief EIC signal: EXTINT9 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT9 ((PIN_PC17A_EIC_EXTINT9 << 16) | MUX_PC17A_EIC_EXTINT9) +#define PORT_PC17A_EIC_EXTINT9 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT10 _L_(66) /**< \brief EIC signal: EXTINT10 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT10 ((PIN_PC02A_EIC_EXTINT10 << 16) | MUX_PC02A_EIC_EXTINT10) +#define PORT_PC02A_EIC_EXTINT10 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT10 _L_(82) /**< \brief EIC signal: EXTINT10 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT10 ((PIN_PC18A_EIC_EXTINT10 << 16) | MUX_PC18A_EIC_EXTINT10) +#define PORT_PC18A_EIC_EXTINT10 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT11 _L_(67) /**< \brief EIC signal: EXTINT11 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT11 ((PIN_PC03A_EIC_EXTINT11 << 16) | MUX_PC03A_EIC_EXTINT11) +#define PORT_PC03A_EIC_EXTINT11 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT11 _L_(83) /**< \brief EIC signal: EXTINT11 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT11 ((PIN_PC19A_EIC_EXTINT11 << 16) | MUX_PC19A_EIC_EXTINT11) +#define PORT_PC19A_EIC_EXTINT11 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT12 _L_(84) /**< \brief EIC signal: EXTINT12 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT12 ((PIN_PC20A_EIC_EXTINT12 << 16) | MUX_PC20A_EIC_EXTINT12) +#define PORT_PC20A_EIC_EXTINT12 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT13 _L_(69) /**< \brief EIC signal: EXTINT13 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT13 ((PIN_PC05A_EIC_EXTINT13 << 16) | MUX_PC05A_EIC_EXTINT13) +#define PORT_PC05A_EIC_EXTINT13 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT13 _L_(85) /**< \brief EIC signal: EXTINT13 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT13 ((PIN_PC21A_EIC_EXTINT13 << 16) | MUX_PC21A_EIC_EXTINT13) +#define PORT_PC21A_EIC_EXTINT13 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT14 _L_(70) /**< \brief EIC signal: EXTINT14 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT14 ((PIN_PC06A_EIC_EXTINT14 << 16) | MUX_PC06A_EIC_EXTINT14) +#define PORT_PC06A_EIC_EXTINT14 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT15 _L_(71) /**< \brief EIC signal: EXTINT15 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT15 ((PIN_PC07A_EIC_EXTINT15 << 16) | MUX_PC07A_EIC_EXTINT15) +#define PORT_PC07A_EIC_EXTINT15 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM _L_(6) +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (_UL_(1) << 24) +#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP _L_(6) +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (_UL_(1) << 25) +#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ +#define MUX_PB22G_USB_SOF_1KHZ _L_(6) +#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) +#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ +#define MUX_PA20C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) +#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ +#define MUX_PA21C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) +#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ +#define MUX_PA22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) +#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) +#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ +#define MUX_PA23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) +#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) +#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) +#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PC27D_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux D */ +#define MUX_PC27D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PC27D_SERCOM1_PAD0 ((PIN_PC27D_SERCOM1_PAD0 << 16) | MUX_PC27D_SERCOM1_PAD0) +#define PORT_PC27D_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC12C_SERCOM1_PAD0 _L_(76) /**< \brief SERCOM1 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM1_PAD0 ((PIN_PC12C_SERCOM1_PAD0 << 16) | MUX_PC12C_SERCOM1_PAD0) +#define PORT_PC12C_SERCOM1_PAD0 (_UL_(1) << 12) +#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) +#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PC28D_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux D */ +#define MUX_PC28D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PC28D_SERCOM1_PAD1 ((PIN_PC28D_SERCOM1_PAD1 << 16) | MUX_PC28D_SERCOM1_PAD1) +#define PORT_PC28D_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC13C_SERCOM1_PAD1 _L_(77) /**< \brief SERCOM1 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM1_PAD1 ((PIN_PC13C_SERCOM1_PAD1 << 16) | MUX_PC13C_SERCOM1_PAD1) +#define PORT_PC13C_SERCOM1_PAD1 (_UL_(1) << 13) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PC10C_SERCOM1_PAD2 _L_(74) /**< \brief SERCOM1 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM1_PAD2 ((PIN_PC10C_SERCOM1_PAD2 << 16) | MUX_PC10C_SERCOM1_PAD2) +#define PORT_PC10C_SERCOM1_PAD2 (_UL_(1) << 10) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PC11C_SERCOM1_PAD3 _L_(75) /**< \brief SERCOM1 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM1_PAD3 ((PIN_PC11C_SERCOM1_PAD3 << 16) | MUX_PC11C_SERCOM1_PAD3) +#define PORT_PC11C_SERCOM1_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) +#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) +#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) +#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) +#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) +#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) +#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) +#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) +#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) +#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) +#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) +#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) +#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) +#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) +#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) +#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) +#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) +#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) +#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ +#define MUX_PB02C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) +#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) +#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) +#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) +#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) +#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) +#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ +#define MUX_PB03C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) +#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) +#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) +#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) +#define PIN_PB18D_SERCOM3_PAD2 _L_(50) /**< \brief SERCOM3 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM3_PAD2 ((PIN_PB18D_SERCOM3_PAD2 << 16) | MUX_PB18D_SERCOM3_PAD2) +#define PORT_PB18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ +#define MUX_PB00C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) +#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) +#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) +#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) +#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) +#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) +#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) +#define PIN_PB19D_SERCOM3_PAD3 _L_(51) /**< \brief SERCOM3 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM3_PAD3 ((PIN_PB19D_SERCOM3_PAD3 << 16) | MUX_PB19D_SERCOM3_PAD3) +#define PORT_PB19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ +#define MUX_PB01C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) +#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA08D_SERCOM4_PAD0 _L_(8) /**< \brief SERCOM4 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA08D_SERCOM4_PAD0 ((PIN_PA08D_SERCOM4_PAD0 << 16) | MUX_PA08D_SERCOM4_PAD0) +#define PORT_PA08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM4_PAD0 _L_(56) /**< \brief SERCOM4 signal: PAD0 on PB24 mux D */ +#define MUX_PB24D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB24D_SERCOM4_PAD0 ((PIN_PB24D_SERCOM4_PAD0 << 16) | MUX_PB24D_SERCOM4_PAD0) +#define PORT_PB24D_SERCOM4_PAD0 (_UL_(1) << 24) +#define PIN_PA12C_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM4_PAD0 ((PIN_PA12C_SERCOM4_PAD0 << 16) | MUX_PA12C_SERCOM4_PAD0) +#define PORT_PA12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA09D_SERCOM4_PAD1 _L_(9) /**< \brief SERCOM4 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA09D_SERCOM4_PAD1 ((PIN_PA09D_SERCOM4_PAD1 << 16) | MUX_PA09D_SERCOM4_PAD1) +#define PORT_PA09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM4_PAD1 _L_(57) /**< \brief SERCOM4 signal: PAD1 on PB25 mux D */ +#define MUX_PB25D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB25D_SERCOM4_PAD1 ((PIN_PB25D_SERCOM4_PAD1 << 16) | MUX_PB25D_SERCOM4_PAD1) +#define PORT_PB25D_SERCOM4_PAD1 (_UL_(1) << 25) +#define PIN_PA13C_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM4_PAD1 ((PIN_PA13C_SERCOM4_PAD1 << 16) | MUX_PA13C_SERCOM4_PAD1) +#define PORT_PA13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM4_PAD2 _L_(10) /**< \brief SERCOM4 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM4_PAD2 ((PIN_PA10D_SERCOM4_PAD2 << 16) | MUX_PA10D_SERCOM4_PAD2) +#define PORT_PA10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM4_PAD2 _L_(88) /**< \brief SERCOM4 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM4_PAD2 ((PIN_PC24D_SERCOM4_PAD2 << 16) | MUX_PC24D_SERCOM4_PAD2) +#define PORT_PC24D_SERCOM4_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM4_PAD2 ((PIN_PA14C_SERCOM4_PAD2 << 16) | MUX_PA14C_SERCOM4_PAD2) +#define PORT_PA14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM4_PAD3 _L_(11) /**< \brief SERCOM4 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM4_PAD3 ((PIN_PA11D_SERCOM4_PAD3 << 16) | MUX_PA11D_SERCOM4_PAD3) +#define PORT_PA11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM4_PAD3 _L_(89) /**< \brief SERCOM4 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM4_PAD3 ((PIN_PC25D_SERCOM4_PAD3 << 16) | MUX_PC25D_SERCOM4_PAD3) +#define PORT_PC25D_SERCOM4_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM4_PAD3 ((PIN_PA15C_SERCOM4_PAD3 << 16) | MUX_PA15C_SERCOM4_PAD3) +#define PORT_PA15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) +#define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) +#define PIN_PA24D_SERCOM5_PAD0 _L_(24) /**< \brief SERCOM5 signal: PAD0 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD0 ((PIN_PA24D_SERCOM5_PAD0 << 16) | MUX_PA24D_SERCOM5_PAD0) +#define PORT_PA24D_SERCOM5_PAD0 (_UL_(1) << 24) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB20D_SERCOM5_PAD0 _L_(52) /**< \brief SERCOM5 signal: PAD0 on PB20 mux D */ +#define MUX_PB20D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB20D_SERCOM5_PAD0 ((PIN_PB20D_SERCOM5_PAD0 << 16) | MUX_PB20D_SERCOM5_PAD0) +#define PORT_PB20D_SERCOM5_PAD0 (_UL_(1) << 20) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) +#define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) +#define PIN_PA25D_SERCOM5_PAD1 _L_(25) /**< \brief SERCOM5 signal: PAD1 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD1 ((PIN_PA25D_SERCOM5_PAD1 << 16) | MUX_PA25D_SERCOM5_PAD1) +#define PORT_PA25D_SERCOM5_PAD1 (_UL_(1) << 25) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB21D_SERCOM5_PAD1 _L_(53) /**< \brief SERCOM5 signal: PAD1 on PB21 mux D */ +#define MUX_PB21D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB21D_SERCOM5_PAD1 ((PIN_PB21D_SERCOM5_PAD1 << 16) | MUX_PB21D_SERCOM5_PAD1) +#define PORT_PB21D_SERCOM5_PAD1 (_UL_(1) << 21) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ +#define MUX_PA24F_TCC0_WO0 _L_(5) +#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) +#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PB18F_TCC0_WO0 _L_(50) /**< \brief TCC0 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC0_WO0 _L_(5) +#define PINMUX_PB18F_TCC0_WO0 ((PIN_PB18F_TCC0_WO0 << 16) | MUX_PB18F_TCC0_WO0) +#define PORT_PB18F_TCC0_WO0 (_UL_(1) << 18) +#define PIN_PC24F_TCC0_WO0 _L_(88) /**< \brief TCC0 signal: WO0 on PC24 mux F */ +#define MUX_PC24F_TCC0_WO0 _L_(5) +#define PINMUX_PC24F_TCC0_WO0 ((PIN_PC24F_TCC0_WO0 << 16) | MUX_PC24F_TCC0_WO0) +#define PORT_PC24F_TCC0_WO0 (_UL_(1) << 24) +#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 _L_(4) +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 _L_(4) +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 _L_(4) +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) +#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ +#define MUX_PA25F_TCC0_WO1 _L_(5) +#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) +#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PB19F_TCC0_WO1 _L_(51) /**< \brief TCC0 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC0_WO1 _L_(5) +#define PINMUX_PB19F_TCC0_WO1 ((PIN_PB19F_TCC0_WO1 << 16) | MUX_PB19F_TCC0_WO1) +#define PORT_PB19F_TCC0_WO1 (_UL_(1) << 19) +#define PIN_PC25F_TCC0_WO1 _L_(89) /**< \brief TCC0 signal: WO1 on PC25 mux F */ +#define MUX_PC25F_TCC0_WO1 _L_(5) +#define PINMUX_PC25F_TCC0_WO1 ((PIN_PC25F_TCC0_WO1 << 16) | MUX_PC25F_TCC0_WO1) +#define PORT_PC25F_TCC0_WO1 (_UL_(1) << 25) +#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 _L_(4) +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 _L_(4) +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 _L_(4) +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 _L_(5) +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC0_WO2 _L_(52) /**< \brief TCC0 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC0_WO2 _L_(5) +#define PINMUX_PB20F_TCC0_WO2 ((PIN_PB20F_TCC0_WO2 << 16) | MUX_PB20F_TCC0_WO2) +#define PORT_PB20F_TCC0_WO2 (_UL_(1) << 20) +#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ +#define MUX_PB22F_TCC0_WO2 _L_(5) +#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) +#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PC26F_TCC0_WO2 _L_(90) /**< \brief TCC0 signal: WO2 on PC26 mux F */ +#define MUX_PC26F_TCC0_WO2 _L_(5) +#define PINMUX_PC26F_TCC0_WO2 ((PIN_PC26F_TCC0_WO2 << 16) | MUX_PC26F_TCC0_WO2) +#define PORT_PC26F_TCC0_WO2 (_UL_(1) << 26) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 _L_(5) +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC0_WO3 _L_(53) /**< \brief TCC0 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC0_WO3 _L_(5) +#define PINMUX_PB21F_TCC0_WO3 ((PIN_PB21F_TCC0_WO3 << 16) | MUX_PB21F_TCC0_WO3) +#define PORT_PB21F_TCC0_WO3 (_UL_(1) << 21) +#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ +#define MUX_PB23F_TCC0_WO3 _L_(5) +#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) +#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PC27F_TCC0_WO3 _L_(91) /**< \brief TCC0 signal: WO3 on PC27 mux F */ +#define MUX_PC27F_TCC0_WO3 _L_(5) +#define PINMUX_PC27F_TCC0_WO3 ((PIN_PC27F_TCC0_WO3 << 16) | MUX_PC27F_TCC0_WO3) +#define PORT_PC27F_TCC0_WO3 (_UL_(1) << 27) +#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 _L_(5) +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) +#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 _L_(5) +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PC28F_TCC0_WO4 _L_(92) /**< \brief TCC0 signal: WO4 on PC28 mux F */ +#define MUX_PC28F_TCC0_WO4 _L_(5) +#define PINMUX_PC28F_TCC0_WO4 ((PIN_PC28F_TCC0_WO4 << 16) | MUX_PC28F_TCC0_WO4) +#define PORT_PC28F_TCC0_WO4 (_UL_(1) << 28) +#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 _L_(5) +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 _L_(5) +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 _L_(5) +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) +#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ +#define MUX_PA27F_TCC0_WO5 _L_(5) +#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) +#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 _L_(5) +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 _L_(5) +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) +#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 _L_(5) +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) +#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 _L_(5) +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PB24F_TCC0_WO6 _L_(56) /**< \brief TCC0 signal: WO6 on PB24 mux F */ +#define MUX_PB24F_TCC0_WO6 _L_(5) +#define PINMUX_PB24F_TCC0_WO6 ((PIN_PB24F_TCC0_WO6 << 16) | MUX_PB24F_TCC0_WO6) +#define PORT_PB24F_TCC0_WO6 (_UL_(1) << 24) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 _L_(5) +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) +#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 _L_(5) +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) +#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 _L_(5) +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PB25F_TCC0_WO7 _L_(57) /**< \brief TCC0 signal: WO7 on PB25 mux F */ +#define MUX_PB25F_TCC0_WO7 _L_(5) +#define PINMUX_PB25F_TCC0_WO7 ((PIN_PB25F_TCC0_WO7 << 16) | MUX_PB25F_TCC0_WO7) +#define PORT_PB25F_TCC0_WO7 (_UL_(1) << 25) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 _L_(4) +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 _L_(4) +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 _L_(4) +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 _L_(4) +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 _L_(4) +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 _L_(4) +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 _L_(4) +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) +#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 _L_(4) +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 _L_(4) +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 _L_(4) +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 _L_(4) +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 _L_(4) +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 _L_(4) +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PC24E_TC2_WO0 _L_(88) /**< \brief TC2 signal: WO0 on PC24 mux E */ +#define MUX_PC24E_TC2_WO0 _L_(4) +#define PINMUX_PC24E_TC2_WO0 ((PIN_PC24E_TC2_WO0 << 16) | MUX_PC24E_TC2_WO0) +#define PORT_PC24E_TC2_WO0 (_UL_(1) << 24) +#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 _L_(4) +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 _L_(4) +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) +#define PIN_PC25E_TC2_WO1 _L_(89) /**< \brief TC2 signal: WO1 on PC25 mux E */ +#define MUX_PC25E_TC2_WO1 _L_(4) +#define PINMUX_PC25E_TC2_WO1 ((PIN_PC25E_TC2_WO1 << 16) | MUX_PC25E_TC2_WO1) +#define PORT_PC25E_TC2_WO1 (_UL_(1) << 25) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 _L_(4) +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 _L_(4) +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 _L_(4) +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) +#define PIN_PC26E_TC3_WO0 _L_(90) /**< \brief TC3 signal: WO0 on PC26 mux E */ +#define MUX_PC26E_TC3_WO0 _L_(4) +#define PINMUX_PC26E_TC3_WO0 ((PIN_PC26E_TC3_WO0 << 16) | MUX_PC26E_TC3_WO0) +#define PORT_PC26E_TC3_WO0 (_UL_(1) << 26) +#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 _L_(4) +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 _L_(4) +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 _L_(4) +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) +#define PIN_PC27E_TC3_WO1 _L_(91) /**< \brief TC3 signal: WO1 on PC27 mux E */ +#define MUX_PC27E_TC3_WO1 _L_(4) +#define PINMUX_PC27E_TC3_WO1 ((PIN_PC27E_TC3_WO1 << 16) | MUX_PC27E_TC3_WO1) +#define PORT_PC27E_TC3_WO1 (_UL_(1) << 27) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 _L_(1) +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 _L_(1) +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 _L_(1) +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 _L_(1) +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 _L_(1) +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 _L_(1) +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 _L_(1) +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 _L_(1) +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) +#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 _L_(1) +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) +#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 _L_(1) +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) +#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 _L_(1) +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) +#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 _L_(1) +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) +#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 _L_(1) +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) +#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 _L_(1) +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) +#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 _L_(1) +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) +#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 _L_(1) +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) +#define PIN_PC00B_ADC_AIN16 _L_(64) /**< \brief ADC signal: AIN16 on PC00 mux B */ +#define MUX_PC00B_ADC_AIN16 _L_(1) +#define PINMUX_PC00B_ADC_AIN16 ((PIN_PC00B_ADC_AIN16 << 16) | MUX_PC00B_ADC_AIN16) +#define PORT_PC00B_ADC_AIN16 (_UL_(1) << 0) +#define PIN_PC01B_ADC_AIN17 _L_(65) /**< \brief ADC signal: AIN17 on PC01 mux B */ +#define MUX_PC01B_ADC_AIN17 _L_(1) +#define PINMUX_PC01B_ADC_AIN17 ((PIN_PC01B_ADC_AIN17 << 16) | MUX_PC01B_ADC_AIN17) +#define PORT_PC01B_ADC_AIN17 (_UL_(1) << 1) +#define PIN_PC02B_ADC_AIN18 _L_(66) /**< \brief ADC signal: AIN18 on PC02 mux B */ +#define MUX_PC02B_ADC_AIN18 _L_(1) +#define PINMUX_PC02B_ADC_AIN18 ((PIN_PC02B_ADC_AIN18 << 16) | MUX_PC02B_ADC_AIN18) +#define PORT_PC02B_ADC_AIN18 (_UL_(1) << 2) +#define PIN_PC03B_ADC_AIN19 _L_(67) /**< \brief ADC signal: AIN19 on PC03 mux B */ +#define MUX_PC03B_ADC_AIN19 _L_(1) +#define PINMUX_PC03B_ADC_AIN19 ((PIN_PC03B_ADC_AIN19 << 16) | MUX_PC03B_ADC_AIN19) +#define PORT_PC03B_ADC_AIN19 (_UL_(1) << 3) +#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ +#define MUX_PA03B_ADC_VREFA _L_(1) +#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) +#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) +#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ +#define MUX_PA02B_ADC_VREFB _L_(1) +#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) +#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_AC_AIN0 _L_(1) +#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) +#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_AC_AIN1 _L_(1) +#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) +#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) +#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ +#define MUX_PB04B_AC_AIN2 _L_(1) +#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) +#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) +#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ +#define MUX_PB05B_AC_AIN3 _L_(1) +#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) +#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) +#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 _L_(7) +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 _L_(7) +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24H_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux H */ +#define MUX_PB24H_AC_CMP0 _L_(7) +#define PINMUX_PB24H_AC_CMP0 ((PIN_PB24H_AC_CMP0 << 16) | MUX_PB24H_AC_CMP0) +#define PORT_PB24H_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 _L_(7) +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 _L_(7) +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25H_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux H */ +#define MUX_PB25H_AC_CMP1 _L_(7) +#define PINMUX_PB25H_AC_CMP1 ((PIN_PB25H_AC_CMP1 << 16) | MUX_PB25H_AC_CMP1) +#define PORT_PB25H_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for SLCD peripheral ========== */ +#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ +#define MUX_PB06B_SLCD_LP0 _L_(1) +#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) +#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) +#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ +#define MUX_PB07B_SLCD_LP1 _L_(1) +#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) +#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) +#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ +#define MUX_PB08B_SLCD_LP2 _L_(1) +#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) +#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) +#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ +#define MUX_PB09B_SLCD_LP3 _L_(1) +#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) +#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) +#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ +#define MUX_PA04B_SLCD_LP4 _L_(1) +#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) +#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) +#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ +#define MUX_PA05B_SLCD_LP5 _L_(1) +#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) +#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) +#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ +#define MUX_PA06B_SLCD_LP6 _L_(1) +#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) +#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) +#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ +#define MUX_PA07B_SLCD_LP7 _L_(1) +#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) +#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) +#define PIN_PC05B_SLCD_LP8 _L_(69) /**< \brief SLCD signal: LP8 on PC05 mux B */ +#define MUX_PC05B_SLCD_LP8 _L_(1) +#define PINMUX_PC05B_SLCD_LP8 ((PIN_PC05B_SLCD_LP8 << 16) | MUX_PC05B_SLCD_LP8) +#define PORT_PC05B_SLCD_LP8 (_UL_(1) << 5) +#define PIN_PC06B_SLCD_LP9 _L_(70) /**< \brief SLCD signal: LP9 on PC06 mux B */ +#define MUX_PC06B_SLCD_LP9 _L_(1) +#define PINMUX_PC06B_SLCD_LP9 ((PIN_PC06B_SLCD_LP9 << 16) | MUX_PC06B_SLCD_LP9) +#define PORT_PC06B_SLCD_LP9 (_UL_(1) << 6) +#define PIN_PC07B_SLCD_LP10 _L_(71) /**< \brief SLCD signal: LP10 on PC07 mux B */ +#define MUX_PC07B_SLCD_LP10 _L_(1) +#define PINMUX_PC07B_SLCD_LP10 ((PIN_PC07B_SLCD_LP10 << 16) | MUX_PC07B_SLCD_LP10) +#define PORT_PC07B_SLCD_LP10 (_UL_(1) << 7) +#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ +#define MUX_PA08B_SLCD_LP11 _L_(1) +#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) +#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) +#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ +#define MUX_PA09B_SLCD_LP12 _L_(1) +#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) +#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) +#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ +#define MUX_PA10B_SLCD_LP13 _L_(1) +#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) +#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) +#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ +#define MUX_PA11B_SLCD_LP14 _L_(1) +#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) +#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) +#define PIN_PC08B_SLCD_LP15 _L_(72) /**< \brief SLCD signal: LP15 on PC08 mux B */ +#define MUX_PC08B_SLCD_LP15 _L_(1) +#define PINMUX_PC08B_SLCD_LP15 ((PIN_PC08B_SLCD_LP15 << 16) | MUX_PC08B_SLCD_LP15) +#define PORT_PC08B_SLCD_LP15 (_UL_(1) << 8) +#define PIN_PC09B_SLCD_LP16 _L_(73) /**< \brief SLCD signal: LP16 on PC09 mux B */ +#define MUX_PC09B_SLCD_LP16 _L_(1) +#define PINMUX_PC09B_SLCD_LP16 ((PIN_PC09B_SLCD_LP16 << 16) | MUX_PC09B_SLCD_LP16) +#define PORT_PC09B_SLCD_LP16 (_UL_(1) << 9) +#define PIN_PC10B_SLCD_LP17 _L_(74) /**< \brief SLCD signal: LP17 on PC10 mux B */ +#define MUX_PC10B_SLCD_LP17 _L_(1) +#define PINMUX_PC10B_SLCD_LP17 ((PIN_PC10B_SLCD_LP17 << 16) | MUX_PC10B_SLCD_LP17) +#define PORT_PC10B_SLCD_LP17 (_UL_(1) << 10) +#define PIN_PC11B_SLCD_LP18 _L_(75) /**< \brief SLCD signal: LP18 on PC11 mux B */ +#define MUX_PC11B_SLCD_LP18 _L_(1) +#define PINMUX_PC11B_SLCD_LP18 ((PIN_PC11B_SLCD_LP18 << 16) | MUX_PC11B_SLCD_LP18) +#define PORT_PC11B_SLCD_LP18 (_UL_(1) << 11) +#define PIN_PC12B_SLCD_LP19 _L_(76) /**< \brief SLCD signal: LP19 on PC12 mux B */ +#define MUX_PC12B_SLCD_LP19 _L_(1) +#define PINMUX_PC12B_SLCD_LP19 ((PIN_PC12B_SLCD_LP19 << 16) | MUX_PC12B_SLCD_LP19) +#define PORT_PC12B_SLCD_LP19 (_UL_(1) << 12) +#define PIN_PC13B_SLCD_LP20 _L_(77) /**< \brief SLCD signal: LP20 on PC13 mux B */ +#define MUX_PC13B_SLCD_LP20 _L_(1) +#define PINMUX_PC13B_SLCD_LP20 ((PIN_PC13B_SLCD_LP20 << 16) | MUX_PC13B_SLCD_LP20) +#define PORT_PC13B_SLCD_LP20 (_UL_(1) << 13) +#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ +#define MUX_PB11B_SLCD_LP21 _L_(1) +#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) +#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) +#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ +#define MUX_PB12B_SLCD_LP22 _L_(1) +#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) +#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) +#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ +#define MUX_PB13B_SLCD_LP23 _L_(1) +#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) +#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) +#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ +#define MUX_PB14B_SLCD_LP24 _L_(1) +#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) +#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) +#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ +#define MUX_PB15B_SLCD_LP25 _L_(1) +#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) +#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) +#define PIN_PC14B_SLCD_LP26 _L_(78) /**< \brief SLCD signal: LP26 on PC14 mux B */ +#define MUX_PC14B_SLCD_LP26 _L_(1) +#define PINMUX_PC14B_SLCD_LP26 ((PIN_PC14B_SLCD_LP26 << 16) | MUX_PC14B_SLCD_LP26) +#define PORT_PC14B_SLCD_LP26 (_UL_(1) << 14) +#define PIN_PC15B_SLCD_LP27 _L_(79) /**< \brief SLCD signal: LP27 on PC15 mux B */ +#define MUX_PC15B_SLCD_LP27 _L_(1) +#define PINMUX_PC15B_SLCD_LP27 ((PIN_PC15B_SLCD_LP27 << 16) | MUX_PC15B_SLCD_LP27) +#define PORT_PC15B_SLCD_LP27 (_UL_(1) << 15) +#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ +#define MUX_PA12B_SLCD_LP28 _L_(1) +#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) +#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) +#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ +#define MUX_PA13B_SLCD_LP29 _L_(1) +#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) +#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) +#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ +#define MUX_PA14B_SLCD_LP30 _L_(1) +#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) +#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) +#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ +#define MUX_PA15B_SLCD_LP31 _L_(1) +#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) +#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) +#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ +#define MUX_PA16B_SLCD_LP32 _L_(1) +#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) +#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) +#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ +#define MUX_PA17B_SLCD_LP33 _L_(1) +#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) +#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) +#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ +#define MUX_PA18B_SLCD_LP34 _L_(1) +#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) +#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) +#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ +#define MUX_PA19B_SLCD_LP35 _L_(1) +#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) +#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) +#define PIN_PC16B_SLCD_LP36 _L_(80) /**< \brief SLCD signal: LP36 on PC16 mux B */ +#define MUX_PC16B_SLCD_LP36 _L_(1) +#define PINMUX_PC16B_SLCD_LP36 ((PIN_PC16B_SLCD_LP36 << 16) | MUX_PC16B_SLCD_LP36) +#define PORT_PC16B_SLCD_LP36 (_UL_(1) << 16) +#define PIN_PC17B_SLCD_LP37 _L_(81) /**< \brief SLCD signal: LP37 on PC17 mux B */ +#define MUX_PC17B_SLCD_LP37 _L_(1) +#define PINMUX_PC17B_SLCD_LP37 ((PIN_PC17B_SLCD_LP37 << 16) | MUX_PC17B_SLCD_LP37) +#define PORT_PC17B_SLCD_LP37 (_UL_(1) << 17) +#define PIN_PC18B_SLCD_LP38 _L_(82) /**< \brief SLCD signal: LP38 on PC18 mux B */ +#define MUX_PC18B_SLCD_LP38 _L_(1) +#define PINMUX_PC18B_SLCD_LP38 ((PIN_PC18B_SLCD_LP38 << 16) | MUX_PC18B_SLCD_LP38) +#define PORT_PC18B_SLCD_LP38 (_UL_(1) << 18) +#define PIN_PC19B_SLCD_LP39 _L_(83) /**< \brief SLCD signal: LP39 on PC19 mux B */ +#define MUX_PC19B_SLCD_LP39 _L_(1) +#define PINMUX_PC19B_SLCD_LP39 ((PIN_PC19B_SLCD_LP39 << 16) | MUX_PC19B_SLCD_LP39) +#define PORT_PC19B_SLCD_LP39 (_UL_(1) << 19) +#define PIN_PC20B_SLCD_LP40 _L_(84) /**< \brief SLCD signal: LP40 on PC20 mux B */ +#define MUX_PC20B_SLCD_LP40 _L_(1) +#define PINMUX_PC20B_SLCD_LP40 ((PIN_PC20B_SLCD_LP40 << 16) | MUX_PC20B_SLCD_LP40) +#define PORT_PC20B_SLCD_LP40 (_UL_(1) << 20) +#define PIN_PC21B_SLCD_LP41 _L_(85) /**< \brief SLCD signal: LP41 on PC21 mux B */ +#define MUX_PC21B_SLCD_LP41 _L_(1) +#define PINMUX_PC21B_SLCD_LP41 ((PIN_PC21B_SLCD_LP41 << 16) | MUX_PC21B_SLCD_LP41) +#define PORT_PC21B_SLCD_LP41 (_UL_(1) << 21) +#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ +#define MUX_PB16B_SLCD_LP42 _L_(1) +#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) +#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) +#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ +#define MUX_PB17B_SLCD_LP43 _L_(1) +#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) +#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) +#define PIN_PB18B_SLCD_LP44 _L_(50) /**< \brief SLCD signal: LP44 on PB18 mux B */ +#define MUX_PB18B_SLCD_LP44 _L_(1) +#define PINMUX_PB18B_SLCD_LP44 ((PIN_PB18B_SLCD_LP44 << 16) | MUX_PB18B_SLCD_LP44) +#define PORT_PB18B_SLCD_LP44 (_UL_(1) << 18) +#define PIN_PB19B_SLCD_LP45 _L_(51) /**< \brief SLCD signal: LP45 on PB19 mux B */ +#define MUX_PB19B_SLCD_LP45 _L_(1) +#define PINMUX_PB19B_SLCD_LP45 ((PIN_PB19B_SLCD_LP45 << 16) | MUX_PB19B_SLCD_LP45) +#define PORT_PB19B_SLCD_LP45 (_UL_(1) << 19) +#define PIN_PB20B_SLCD_LP46 _L_(52) /**< \brief SLCD signal: LP46 on PB20 mux B */ +#define MUX_PB20B_SLCD_LP46 _L_(1) +#define PINMUX_PB20B_SLCD_LP46 ((PIN_PB20B_SLCD_LP46 << 16) | MUX_PB20B_SLCD_LP46) +#define PORT_PB20B_SLCD_LP46 (_UL_(1) << 20) +#define PIN_PB21B_SLCD_LP47 _L_(53) /**< \brief SLCD signal: LP47 on PB21 mux B */ +#define MUX_PB21B_SLCD_LP47 _L_(1) +#define PINMUX_PB21B_SLCD_LP47 ((PIN_PB21B_SLCD_LP47 << 16) | MUX_PB21B_SLCD_LP47) +#define PORT_PB21B_SLCD_LP47 (_UL_(1) << 21) +#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ +#define MUX_PA20B_SLCD_LP48 _L_(1) +#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) +#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) +#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ +#define MUX_PA21B_SLCD_LP49 _L_(1) +#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) +#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) +#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ +#define MUX_PA22B_SLCD_LP50 _L_(1) +#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) +#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) +#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ +#define MUX_PA23B_SLCD_LP51 _L_(1) +#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) +#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 _L_(8) +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 _L_(8) +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 _L_(8) +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 _L_(8) +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 _L_(8) +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 _L_(8) +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 _L_(8) +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 _L_(8) +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 _L_(8) +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 _L_(8) +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 _L_(8) +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 _L_(8) +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27I_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux I */ +#define MUX_PC27I_CCL_IN4 _L_(8) +#define PINMUX_PC27I_CCL_IN4 ((PIN_PC27I_CCL_IN4 << 16) | MUX_PC27I_CCL_IN4) +#define PORT_PC27I_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 _L_(8) +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28I_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux I */ +#define MUX_PC28I_CCL_IN5 _L_(8) +#define PINMUX_PC28I_CCL_IN5 ((PIN_PC28I_CCL_IN5 << 16) | MUX_PC28I_CCL_IN5) +#define PORT_PC28I_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 _L_(8) +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 _L_(8) +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 _L_(8) +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 _L_(8) +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 _L_(8) +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 _L_(8) +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 _L_(8) +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20I_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux I */ +#define MUX_PC20I_CCL_IN9 _L_(8) +#define PINMUX_PC20I_CCL_IN9 ((PIN_PC20I_CCL_IN9 << 16) | MUX_PC20I_CCL_IN9) +#define PORT_PC20I_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 _L_(8) +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21I_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux I */ +#define MUX_PC21I_CCL_IN10 _L_(8) +#define PINMUX_PC21I_CCL_IN10 ((PIN_PC21I_CCL_IN10 << 16) | MUX_PC21I_CCL_IN10) +#define PORT_PC21I_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 _L_(8) +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 _L_(8) +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 _L_(8) +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 _L_(8) +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 _L_(8) +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 _L_(8) +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 _L_(8) +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 _L_(8) +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 _L_(8) +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 _L_(8) +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 _L_(8) +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) + +#endif /* _SAML22N18A_PIO_ */ diff --git a/watch-library/hardware/include/sam.h b/watch-library/hardware/include/sam.h new file mode 100644 index 00000000..c5702205 --- /dev/null +++ b/watch-library/hardware/include/sam.h @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief Top level header file + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SAM_ +#define _SAM_ + +#if defined(__SAML22G16A__) || defined(__ATSAML22G16A__) +#include "saml22g16a.h" +#elif defined(__SAML22G17A__) || defined(__ATSAML22G17A__) +#include "saml22g17a.h" +#elif defined(__SAML22G18A__) || defined(__ATSAML22G18A__) +#include "saml22g18a.h" +#elif defined(__SAML22J16A__) || defined(__ATSAML22J16A__) +#include "saml22j16a.h" +#elif defined(__SAML22J17A__) || defined(__ATSAML22J17A__) +#include "saml22j17a.h" +#elif defined(__SAML22J18A__) || defined(__ATSAML22J18A__) +#include "saml22j18a.h" +#elif defined(__SAML22N16A__) || defined(__ATSAML22N16A__) +#include "saml22n16a.h" +#elif defined(__SAML22N17A__) || defined(__ATSAML22N17A__) +#include "saml22n17a.h" +#elif defined(__SAML22N18A__) || defined(__ATSAML22N18A__) +#include "saml22n18a.h" +#else +#error Library does not support the specified device +#endif + +#endif /* _SAM_ */ diff --git a/watch-library/hardware/include/saml22.h b/watch-library/hardware/include/saml22.h new file mode 100644 index 00000000..d1a84287 --- /dev/null +++ b/watch-library/hardware/include/saml22.h @@ -0,0 +1,60 @@ +/** + * \file + * + * \brief Top header file for SAML22 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_ +#define _SAML22_ + +/** + * \defgroup SAML22_definitions SAML22 Device Definitions + * \brief SAML22 CMSIS Definitions. + */ + +#if defined(__SAML22G16A__) || defined(__ATSAML22G16A__) + #include "saml22g16a.h" +#elif defined(__SAML22G17A__) || defined(__ATSAML22G17A__) + #include "saml22g17a.h" +#elif defined(__SAML22G18A__) || defined(__ATSAML22G18A__) + #include "saml22g18a.h" +#elif defined(__SAML22J16A__) || defined(__ATSAML22J16A__) + #include "saml22j16a.h" +#elif defined(__SAML22J17A__) || defined(__ATSAML22J17A__) + #include "saml22j17a.h" +#elif defined(__SAML22J18A__) || defined(__ATSAML22J18A__) + #include "saml22j18a.h" +#elif defined(__SAML22N16A__) || defined(__ATSAML22N16A__) + #include "saml22n16a.h" +#elif defined(__SAML22N17A__) || defined(__ATSAML22N17A__) + #include "saml22n17a.h" +#elif defined(__SAML22N18A__) || defined(__ATSAML22N18A__) + #include "saml22n18a.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAML22_ */ diff --git a/watch-library/hardware/include/saml22g16a.h b/watch-library/hardware/include/saml22g16a.h new file mode 100644 index 00000000..d2690bd4 --- /dev/null +++ b/watch-library/hardware/include/saml22g16a.h @@ -0,0 +1,596 @@ +/** + * \file + * + * \brief Header file for SAML22G16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G16A_ +#define _SAML22G16A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22G16A_definitions SAML22G16A definitions + * This file defines all structures and symbols for SAML22G16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML22G16A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22G16A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML22G16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22G16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22G16A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22G16A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22G16A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22G16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22G16A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22G16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22G16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22G16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22G16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22G16A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAML22G16A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22G16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22G16A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22G16A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22G16A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22G16A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22G16A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22G16A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22G16A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22G16A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22G16A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ +/** \defgroup SAML22G16A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22g16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1082010C) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22G16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22G16A_H */ diff --git a/watch-library/hardware/include/saml22g17a.h b/watch-library/hardware/include/saml22g17a.h new file mode 100644 index 00000000..d3932fc0 --- /dev/null +++ b/watch-library/hardware/include/saml22g17a.h @@ -0,0 +1,596 @@ +/** + * \file + * + * \brief Header file for SAML22G17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G17A_ +#define _SAML22G17A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22G17A_definitions SAML22G17A definitions + * This file defines all structures and symbols for SAML22G17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML22G17A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22G17A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML22G17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22G17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22G17A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22G17A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22G17A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22G17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22G17A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22G17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22G17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22G17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22G17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22G17A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAML22G17A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22G17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22G17A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22G17A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22G17A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22G17A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22G17A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22G17A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22G17A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22G17A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22G17A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ +/** \defgroup SAML22G17A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22g17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1082010B) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22G17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22G17A_H */ diff --git a/watch-library/hardware/include/saml22g18a.h b/watch-library/hardware/include/saml22g18a.h new file mode 100644 index 00000000..588a3f1e --- /dev/null +++ b/watch-library/hardware/include/saml22g18a.h @@ -0,0 +1,596 @@ +/** + * \file + * + * \brief Header file for SAML22G18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22G18A_ +#define _SAML22G18A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22G18A_definitions SAML22G18A definitions + * This file defines all structures and symbols for SAML22G18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML22G18A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22G18A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML22G18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22G18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22G18A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22G18A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22G18A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22G18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22G18A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22G18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22G18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22G18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22G18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22G18A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAML22G18A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22G18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22G18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22G18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22G18A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22G18A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22G18A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22G18A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22G18A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22G18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22G18A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ +/** \defgroup SAML22G18A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22g18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1082010A) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22G18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22G18A_H */ diff --git a/watch-library/hardware/include/saml22j16a.h b/watch-library/hardware/include/saml22j16a.h new file mode 100644 index 00000000..35d65a1c --- /dev/null +++ b/watch-library/hardware/include/saml22j16a.h @@ -0,0 +1,596 @@ +/** + * \file + * + * \brief Header file for SAML22J16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J16A_ +#define _SAML22J16A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22J16A_definitions SAML22J16A definitions + * This file defines all structures and symbols for SAML22J16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML22J16A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22J16A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML22J16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22J16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22J16A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22J16A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22J16A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22J16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22J16A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22J16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22J16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22J16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22J16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22J16A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAML22J16A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22J16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22J16A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22J16A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22J16A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22J16A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22J16A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22J16A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22J16A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22J16A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22J16A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ +/** \defgroup SAML22J16A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22j16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10820107) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22J16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22J16A_H */ diff --git a/watch-library/hardware/include/saml22j17a.h b/watch-library/hardware/include/saml22j17a.h new file mode 100644 index 00000000..a1c95952 --- /dev/null +++ b/watch-library/hardware/include/saml22j17a.h @@ -0,0 +1,596 @@ +/** + * \file + * + * \brief Header file for SAML22J17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J17A_ +#define _SAML22J17A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22J17A_definitions SAML22J17A definitions + * This file defines all structures and symbols for SAML22J17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML22J17A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22J17A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML22J17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22J17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22J17A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22J17A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22J17A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22J17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22J17A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22J17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22J17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22J17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22J17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22J17A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAML22J17A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22J17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22J17A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22J17A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22J17A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22J17A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22J17A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22J17A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22J17A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22J17A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22J17A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ +/** \defgroup SAML22J17A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22j17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10820106) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22J17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22J17A_H */ diff --git a/watch-library/hardware/include/saml22j18a.h b/watch-library/hardware/include/saml22j18a.h new file mode 100644 index 00000000..8286db88 --- /dev/null +++ b/watch-library/hardware/include/saml22j18a.h @@ -0,0 +1,596 @@ +/** + * \file + * + * \brief Header file for SAML22J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22J18A_ +#define _SAML22J18A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22J18A_definitions SAML22J18A definitions + * This file defines all structures and symbols for SAML22J18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML22J18A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22J18A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML22J18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22J18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22J18A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22J18A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22J18A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22J18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22J18A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22J18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22J18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22J18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22J18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22J18A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAML22J18A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22J18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22J18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22J18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22J18A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22J18A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22J18A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22J18A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22J18A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22J18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22J18A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ +/** \defgroup SAML22J18A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22j18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10820105) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22J18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22J18A_H */ diff --git a/watch-library/hardware/include/saml22n16a.h b/watch-library/hardware/include/saml22n16a.h new file mode 100644 index 00000000..34ea155d --- /dev/null +++ b/watch-library/hardware/include/saml22n16a.h @@ -0,0 +1,608 @@ +/** + * \file + * + * \brief Header file for SAML22N16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N16A_ +#define _SAML22N16A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22N16A_definitions SAML22N16A definitions + * This file defines all structures and symbols for SAML22N16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML22N16A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22N16A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML22N16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22N16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22N16A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22N16A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22N16A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22N16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22N16A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22N16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22N16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22N16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22N16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22N16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAML22N16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAML22N16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAML22N16A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22N16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22N16A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22N16A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22N16A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22N16A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22N16A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22N16A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22N16A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22N16A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22N16A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ +/** \defgroup SAML22N16A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22n16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10820102) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22N16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22N16A_H */ diff --git a/watch-library/hardware/include/saml22n17a.h b/watch-library/hardware/include/saml22n17a.h new file mode 100644 index 00000000..7b3cd85a --- /dev/null +++ b/watch-library/hardware/include/saml22n17a.h @@ -0,0 +1,608 @@ +/** + * \file + * + * \brief Header file for SAML22N17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N17A_ +#define _SAML22N17A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22N17A_definitions SAML22N17A definitions + * This file defines all structures and symbols for SAML22N17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML22N17A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22N17A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML22N17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22N17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22N17A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22N17A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22N17A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22N17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22N17A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22N17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22N17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22N17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22N17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22N17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAML22N17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAML22N17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAML22N17A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22N17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22N17A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22N17A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22N17A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22N17A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22N17A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22N17A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22N17A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22N17A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22N17A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ +/** \defgroup SAML22N17A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22n17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10820101) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22N17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22N17A_H */ diff --git a/watch-library/hardware/include/saml22n18a.h b/watch-library/hardware/include/saml22n18a.h new file mode 100644 index 00000000..de160b83 --- /dev/null +++ b/watch-library/hardware/include/saml22n18a.h @@ -0,0 +1,608 @@ +/** + * \file + * + * \brief Header file for SAML22N18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22N18A_ +#define _SAML22N18A_ + +/** + * \ingroup SAML22_definitions + * \addtogroup SAML22N18A_definitions SAML22N18A definitions + * This file defines all structures and symbols for SAML22N18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML22N18A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML22N18A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML22N18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML22N18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML22N18A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAML22N18A Frequency Meter (FREQM) */ + USB_IRQn = 5, /**< 5 SAML22N18A Universal Serial Bus (USB) */ + NVMCTRL_IRQn = 6, /**< 6 SAML22N18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAML22N18A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAML22N18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAML22N18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAML22N18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAML22N18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAML22N18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAML22N18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAML22N18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAML22N18A Timer Counter Control (TCC0) */ + TC0_IRQn = 16, /**< 16 SAML22N18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 17, /**< 17 SAML22N18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 18, /**< 18 SAML22N18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 19, /**< 19 SAML22N18A Basic Timer Counter 3 (TC3) */ + ADC_IRQn = 20, /**< 20 SAML22N18A Analog Digital Converter (ADC) */ + AC_IRQn = 21, /**< 21 SAML22N18A Analog Comparators (AC) */ + PTC_IRQn = 22, /**< 22 SAML22N18A Peripheral Touch Controller (PTC) */ + SLCD_IRQn = 23, /**< 23 SAML22N18A Segment Liquid Crystal Display Controller (SLCD) */ + AES_IRQn = 24, /**< 24 SAML22N18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 25, /**< 25 SAML22N18A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnUSB_Handler; /* 5 Universal Serial Bus */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control */ + void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ + void* pfnADC_Handler; /* 20 Analog Digital Converter */ + void* pfnAC_Handler; /* 21 Analog Comparators */ + void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ + void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ + void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 25 True Random Generator */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void USB_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void PTC_Handler ( void ); +void SLCD_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml22.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/slcd.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/slcd.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 77 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ +#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ +#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ + +#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42003400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ +#define AES (0x42004000) /**< \brief (AES) APB Base Address */ +#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ +#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ +#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 27 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ +#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ +#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ +#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ +/** \defgroup SAML22N18A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml22n18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10820100) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML22N18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML22N18A_H */ diff --git a/watch-library/hardware/include/system_saml22.h b/watch-library/hardware/include/system_saml22.h new file mode 100644 index 00000000..e41bb831 --- /dev/null +++ b/watch-library/hardware/include/system_saml22.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAML22_H_INCLUDED_ +#define _SYSTEM_SAML22_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAML22_H_INCLUDED */ diff --git a/watch-library/hardware/linker/saml22j18.ld b/watch-library/hardware/linker/saml22j18.ld new file mode 100755 index 00000000..a9801509 --- /dev/null +++ b/watch-library/hardware/linker/saml22j18.ld @@ -0,0 +1,145 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAML22J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x2000, LENGTH = 0x00040000-0x2000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +ENTRY(Reset_Handler) + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/watch-library/hardware/main.c b/watch-library/hardware/main.c new file mode 100755 index 00000000..1fe751ef --- /dev/null +++ b/watch-library/hardware/main.c @@ -0,0 +1,85 @@ +/* + * MIT License + * + * Copyright (c) 2021 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +//----------------------------------------------------------------------------- +#include +#include +#include +#include +#include +#include "saml22.h" +#include "hal_init.h" +#include "pins.h" +#include "watch.h" +#include "tusb.h" + +int main(void) { + // ASF code. Initialize the MCU with configuration options from Atmel Studio. + init_mcu(); + + // check if we are plugged into USB power. + watch_enable_digital_input(VBUS_DET); + watch_enable_pull_down(VBUS_DET); + if (watch_get_pin_level(VBUS_DET)) { + // if so, enable USB functionality. + _watch_enable_usb(); + } + watch_disable_digital_input(VBUS_DET); + + // initialize the delay driver before any user code is called. + delay_driver_init(); + + // User code. Give the app a chance to initialize its data structures and state. + app_init(); + + // If the RTC is already enabled, we're either waking from BACKUP mode or a reset. + // Ideally we should check if the TAMPER or CMP0 (alarm) flags are set. + if (_watch_rtc_is_enabled()) { + // User code. Give the application a chance to restore state from backup registers. + app_wake_from_backup(); + + // disable the tamper interrupt and clear the tamper bit + hri_rtcmode0_clear_INTEN_TAMPER_bit(RTC); + hri_rtcmode0_clear_interrupt_TAMPER_bit(RTC); + } + + // Watch library code. Set initial parameters for the device and enable the RTC. + _watch_init(); + + // User code. Give the app a chance to enable and set up peripherals. + app_setup(); + + while (1) { + bool usb_enabled = hri_usbdevice_get_CTRLA_ENABLE_bit(USB); + bool can_sleep = app_loop(); + + if (can_sleep && !usb_enabled) { + app_prepare_for_standby(); + sleep(4); + app_wake_from_standby(); + } + } + + return 0; +} diff --git a/watch-library/hardware/startup_saml22.c b/watch-library/hardware/startup_saml22.c new file mode 100755 index 00000000..f4982564 --- /dev/null +++ b/watch-library/hardware/startup_saml22.c @@ -0,0 +1,225 @@ +/** + * \file + * + * \brief gcc starttup file for SAML22 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "saml22.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M0+ core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSC32KCTRL, OSCCTRL, PAC, PM, SUPC, TAL */ +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_USB +void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_SERCOM3 +void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SERCOM4 +void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SERCOM5 +void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_PTC +void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void SLCD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_AES +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TRNG +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pvReservedM12 = (void*) (0UL), /* Reserved */ + .pvReservedM11 = (void*) (0UL), /* Reserved */ + .pvReservedM10 = (void*) (0UL), /* Reserved */ + .pvReservedM9 = (void*) (0UL), /* Reserved */ + .pvReservedM8 = (void*) (0UL), /* Reserved */ + .pvReservedM7 = (void*) (0UL), /* Reserved */ + .pvReservedM6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pvReservedM4 = (void*) (0UL), /* Reserved */ + .pvReservedM3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSYSTEM_Handler = (void*) SYSTEM_Handler, /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 1 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-Time Counter */ + .pfnEIC_Handler = (void*) EIC_Handler, /* 3 External Interrupt Controller */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 4 Frequency Meter */ +#ifdef ID_USB + .pfnUSB_Handler = (void*) USB_Handler, /* 5 Universal Serial Bus */ +#else + .pvReserved5 = (void*) (0UL), /* 5 Reserved */ +#endif + .pfnNVMCTRL_Handler = (void*) NVMCTRL_Handler, /* 6 Non-Volatile Memory Controller */ + .pfnDMAC_Handler = (void*) DMAC_Handler, /* 7 Direct Memory Access Controller */ + .pfnEVSYS_Handler = (void*) EVSYS_Handler, /* 8 Event System Interface */ + .pfnSERCOM0_Handler = (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + .pfnSERCOM1_Handler = (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + .pfnSERCOM2_Handler = (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ +#ifdef ID_SERCOM3 + .pfnSERCOM3_Handler = (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ +#else + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ +#endif +#ifdef ID_SERCOM4 + .pfnSERCOM4_Handler = (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ +#else + .pvReserved13 = (void*) (0UL), /* 13 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_Handler = (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ +#else + .pvReserved14 = (void*) (0UL), /* 14 Reserved */ +#endif + .pfnTCC0_Handler = (void*) TCC0_Handler, /* 15 Timer Counter Control */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 16 Basic Timer Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 17 Basic Timer Counter 1 */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 18 Basic Timer Counter 2 */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 19 Basic Timer Counter 3 */ + .pfnADC_Handler = (void*) ADC_Handler, /* 20 Analog Digital Converter */ + .pfnAC_Handler = (void*) AC_Handler, /* 21 Analog Comparators */ +#ifdef ID_PTC + .pfnPTC_Handler = (void*) PTC_Handler, /* 22 Peripheral Touch Controller */ +#else + .pvReserved22 = (void*) (0UL), /* 22 Reserved */ +#endif + .pfnSLCD_Handler = (void*) SLCD_Handler, /* 23 Segment Liquid Crystal Display Controller */ +#ifdef ID_AES + .pfnAES_Handler = (void*) AES_Handler, /* 24 Advanced Encryption Standard */ +#else + .pvReserved24 = (void*) (0UL), /* 24 Reserved */ +#endif +#ifdef ID_TRNG + .pfnTRNG_Handler = (void*) TRNG_Handler /* 25 True Random Generator */ +#else + .pvReserved25 = (void*) (0UL) /* 25 Reserved */ +#endif +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/watch-library/hardware/watch/tusb_config.h b/watch-library/hardware/watch/tusb_config.h new file mode 100644 index 00000000..a22b2b99 --- /dev/null +++ b/watch-library/hardware/watch/tusb_config.h @@ -0,0 +1,91 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _TUSB_CONFIG_H_ +#define _TUSB_CONFIG_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +// defined by board.mk +#define CFG_TUSB_MCU OPT_MCU_SAML22 + +#define BOARD_DEVICE_RHPORT_NUM 0 +#define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_FULL_SPEED +#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | OPT_MODE_FULL_SPEED) + +#define CFG_TUSB_OS OPT_OS_NONE + +// disable TinyUSB debug. our printf method prints stuff to the USB console, so you just get infinite noise. +// if you need to debug tinyUSB issues, use the alternate _write function in watch_private.c to echo to the UART. +#define CFG_TUSB_DEBUG 0 + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +#define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN +#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// DEVICE CONFIGURATION +//-------------------------------------------------------------------- + +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +//------------- CLASS -------------// +#define CFG_TUD_CDC 1 +#define CFG_TUD_MSC 0 +#define CFG_TUD_HID 0 +#define CFG_TUD_MIDI 0 +#define CFG_TUD_VENDOR 0 + +// CDC FIFO size of TX and RX +#define CFG_TUD_CDC_RX_BUFSIZE (64) +#define CFG_TUD_CDC_TX_BUFSIZE (64) + +// CDC Endpoint transfer buffer size, more is faster +#define CFG_TUD_CDC_EP_BUFSIZE (64) + +#ifdef __cplusplus + } +#endif + +#endif /* _TUSB_CONFIG_H_ */ diff --git a/watch-library/hardware/watch/watch.c b/watch-library/hardware/watch/watch.c new file mode 100644 index 00000000..791fd974 --- /dev/null +++ b/watch-library/hardware/watch/watch.c @@ -0,0 +1,44 @@ +/* + * MIT License + * + * Copyright (c) 2021 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch.h" + +bool battery_is_low = false; + +// receives interrupts from MCLK, OSC32KCTRL, OSCCTRL, PAC, PM, SUPC and TAL, whatever that is. +void SYSTEM_Handler(void) { + if (SUPC->INTFLAG.bit.BOD33DET) { + battery_is_low = true; + SUPC->INTENCLR.bit.BOD33DET = 1; + SUPC->INTFLAG.reg &= ~SUPC_INTFLAG_BOD33DET; + } +} + +bool watch_is_battery_low(void) { + return battery_is_low; +} + +bool watch_is_buzzer_or_led_enabled(void){ + return hri_mclk_get_APBCMASK_TCC0_bit(MCLK); +} diff --git a/watch-library/hardware/watch/watch_adc.c b/watch-library/hardware/watch/watch_adc.c new file mode 100644 index 00000000..5ba7abdf --- /dev/null +++ b/watch-library/hardware/watch/watch_adc.c @@ -0,0 +1,179 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_adc.h" + +static void _watch_sync_adc(void) { + while (ADC->SYNCBUSY.reg); +} + +static uint16_t _watch_get_analog_value(uint16_t channel) { + if (ADC->INPUTCTRL.bit.MUXPOS != channel) { + ADC->INPUTCTRL.bit.MUXPOS = channel; + _watch_sync_adc(); + } + + ADC->SWTRIG.bit.START = 1; + while (!ADC->INTFLAG.bit.RESRDY); + + return ADC->RESULT.reg; +} + +void watch_enable_adc(void) { + MCLK->APBCMASK.reg |= MCLK_APBCMASK_ADC; + GCLK->PCHCTRL[ADC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN; + + uint16_t calib_reg = 0; + calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC_FUSES_BIASREFBUF_ADDR >> ADC_FUSES_BIASREFBUF_Pos)) | + ADC_CALIB_BIASCOMP((*(uint32_t *)ADC_FUSES_BIASCOMP_ADDR >> ADC_FUSES_BIASCOMP_Pos)); + + if (!ADC->SYNCBUSY.bit.SWRST) { + if (ADC->CTRLA.bit.ENABLE) { + ADC->CTRLA.bit.ENABLE = 0; + _watch_sync_adc(); + } + ADC->CTRLA.bit.SWRST = 1; + } + _watch_sync_adc(); + + if (USB->DEVICE.CTRLA.bit.ENABLE) { + // if USB is enabled, we are running an 8 MHz clock. + // divide by 16 for a 500kHz ADC clock. + ADC->CTRLB.bit.PRESCALER = ADC_CTRLB_PRESCALER_DIV16_Val; + } else { + // otherwise it's 4 Mhz. divide by 8 for a 500kHz ADC clock. + ADC->CTRLB.bit.PRESCALER = ADC_CTRLB_PRESCALER_DIV8_Val; + } + ADC->CALIB.reg = calib_reg; + ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC2_Val; + ADC->INPUTCTRL.bit.MUXNEG = ADC_INPUTCTRL_MUXNEG_GND_Val; + ADC->CTRLC.bit.RESSEL = ADC_CTRLC_RESSEL_16BIT_Val; + ADC->AVGCTRL.bit.SAMPLENUM = ADC_AVGCTRL_SAMPLENUM_16_Val; + ADC->SAMPCTRL.bit.SAMPLEN = 0; + ADC->INTENSET.reg = ADC_INTENSET_RESRDY; + ADC->CTRLA.bit.ENABLE = 1; + _watch_sync_adc(); + // throw away one measurement after reference change (the channel doesn't matter). + _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC); +} + +void watch_enable_analog_input(const uint8_t pin) { + gpio_set_pin_direction(pin, GPIO_DIRECTION_OFF); + switch (pin) { + case A0: + gpio_set_pin_function(pin, PINMUX_PB04B_ADC_AIN12); + break; + case A1: + gpio_set_pin_function(pin, PINMUX_PB01B_ADC_AIN9); + break; + case A2: + gpio_set_pin_function(pin, PINMUX_PB02B_ADC_AIN10); + break; + case A3: + gpio_set_pin_function(pin, PINMUX_PB03B_ADC_AIN11); + break; + case A4: + gpio_set_pin_function(pin, PINMUX_PB00B_ADC_AIN8); + break; + default: + return; + } +} + +uint16_t watch_get_analog_pin_level(const uint8_t pin) { + switch (pin) { + case A0: + return _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_AIN12_Val); + case A1: + return _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_AIN9_Val); + case A2: + return _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_AIN10_Val); + case A3: + return _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_AIN11_Val); + case A4: + return _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_AIN8_Val); + default: + return 0; + } +} + +void watch_set_analog_num_samples(uint16_t samples) { + // ignore any input that's not a power of 2 (i.e. only one bit set) + if (__builtin_popcount(samples) != 1) return; + // if only one bit is set, counting the trailing zeroes is equivalent to log2(samples) + uint8_t sample_val = __builtin_ctz(samples); + // make sure the desired value is within range and set it, if so. + if (sample_val <= ADC_AVGCTRL_SAMPLENUM_1024_Val) { + ADC->AVGCTRL.bit.SAMPLENUM = sample_val; + _watch_sync_adc(); + } +} + +void watch_set_analog_sampling_length(uint8_t cycles) { + // for clarity the API asks the user how many cycles they want the measurement to take. + // but the ADC always needs at least one cycle; it just wants to know how many *extra* cycles we want. + // so we subtract one from the user-provided value, and clamp to the maximum. + ADC->SAMPCTRL.bit.SAMPLEN = (cycles - 1) & 0x3F; + _watch_sync_adc(); +} + +void watch_set_analog_reference_voltage(watch_adc_reference_voltage reference) { + ADC->CTRLA.bit.ENABLE = 0; + + if (reference == ADC_REFERENCE_INTREF) SUPC->VREF.bit.VREFOE = 1; + else SUPC->VREF.bit.VREFOE = 0; + + ADC->REFCTRL.bit.REFSEL = reference; + ADC->CTRLA.bit.ENABLE = 1; + _watch_sync_adc(); + // throw away one measurement after reference change (the channel doesn't matter). + _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC); +} + +uint16_t watch_get_vcc_voltage(void) { + // stash the previous reference so we can restore it when we're done. + uint8_t oldref = ADC->REFCTRL.bit.REFSEL; + + // if we weren't already using the internal reference voltage, select it now. + if (oldref != ADC_REFERENCE_INTREF) watch_set_analog_reference_voltage(ADC_REFERENCE_INTREF); + + // get the data + uint32_t raw_val = _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val); + + // restore the old reference, if needed. + if (oldref != ADC_REFERENCE_INTREF) watch_set_analog_reference_voltage(oldref); + + return (uint16_t)((raw_val * 1000) / (1024 * 1 << ADC->AVGCTRL.bit.SAMPLENUM)); +} + +inline void watch_disable_analog_input(const uint8_t pin) { + gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF); +} + +inline void watch_disable_adc(void) { + ADC->CTRLA.bit.ENABLE = 0; + _watch_sync_adc(); + + MCLK->APBCMASK.reg &= ~MCLK_APBCMASK_ADC; +} diff --git a/watch-library/hardware/watch/watch_buzzer.c b/watch-library/hardware/watch/watch_buzzer.c new file mode 100644 index 00000000..a275b00d --- /dev/null +++ b/watch-library/hardware/watch/watch_buzzer.c @@ -0,0 +1,64 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_buzzer.h" + + inline void watch_enable_buzzer(void) { + if (!hri_tcc_get_CTRLA_reg(TCC0, TCC_CTRLA_ENABLE)) { + _watch_enable_tcc(); + } +} +inline void watch_set_buzzer_period(uint32_t period) { + hri_tcc_write_PERBUF_reg(TCC0, period); +} + +void watch_disable_buzzer(void) { + _watch_disable_tcc(); +} + +inline void watch_set_buzzer_on(void) { + gpio_set_pin_direction(BUZZER, GPIO_DIRECTION_OUT); + gpio_set_pin_function(BUZZER, WATCH_BUZZER_TCC_PINMUX); +} + +inline void watch_set_buzzer_off(void) { + gpio_set_pin_direction(BUZZER, GPIO_DIRECTION_OFF); + gpio_set_pin_function(BUZZER, GPIO_PIN_FUNCTION_OFF); +} + +// note: the buzzer uses a 1 MHz clock. these values were determined by dividing 1,000,000 by the target frequency. +// i.e. for a 440 Hz tone (A4 on the piano), 1MHz/440Hz = 2273 +const uint16_t NotePeriods[108] = {18182,17161,16197,15288,14430,13620,12857,12134,11453,10811,10204,9631,9091,8581,8099,7645,7216,6811,6428,6068,5727,5405,5102,4816,4545,4290,4050,3822,3608,3405,3214,3034,2863,2703,2551,2408,2273,2145,2025,1911,1804,1703,1607,1517,1432,1351,1276,1204,1136,1073,1012,956,902,851,804,758,716,676,638,602,568,536,506,478,451,426,402,379,358,338,319,301,284,268,253,239,225,213,201,190,179,169,159,150,142,134,127}; + +void watch_buzzer_play_note(BuzzerNote note, uint16_t duration_ms) { + if (note == BUZZER_NOTE_REST) { + watch_set_buzzer_off(); + } else { + hri_tcc_write_PERBUF_reg(TCC0, NotePeriods[note]); + hri_tcc_write_CCBUF_reg(TCC0, WATCH_BUZZER_TCC_CHANNEL, NotePeriods[note] / 2); + watch_set_buzzer_on(); + } + delay_ms(duration_ms); + watch_set_buzzer_off(); +} diff --git a/watch-library/hardware/watch/watch_deepsleep.c b/watch-library/hardware/watch/watch_deepsleep.c new file mode 100644 index 00000000..1813ff24 --- /dev/null +++ b/watch-library/hardware/watch/watch_deepsleep.c @@ -0,0 +1,209 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_extint.h" + +// this warning only appears when you `make BOARD=OSO-SWAT-A1-02`. it's annoying, +// but i'd rather have it warn us at build-time than fail silently at run-time. +// besides, no one but me really has any of these boards anyway. +#if BTN_ALARM != GPIO(GPIO_PORTA, 2) +#warning This board revision does not support external wake on BTN_ALARM, so watch_register_extwake_callback will not work with it. Use watch_register_interrupt_callback instead. +#endif + +void watch_register_extwake_callback(uint8_t pin, ext_irq_cb_t callback, bool level) { + uint32_t pinmux; + hri_rtc_tampctrl_reg_t config = RTC->MODE2.TAMPCTRL.reg; + + switch (pin) { + case A4: + a4_callback = callback; + pinmux = PINMUX_PB00G_RTC_IN0; + config &= ~(3 << RTC_TAMPCTRL_IN0ACT_Pos); + config &= ~(1 << RTC_TAMPCTRL_TAMLVL0_Pos); + config |= 1 << RTC_TAMPCTRL_IN0ACT_Pos; + config |= 1 << RTC_TAMPCTRL_DEBNC0_Pos; + if (level) config |= 1 << RTC_TAMPCTRL_TAMLVL0_Pos; + break; + case A2: + a2_callback = callback; + pinmux = PINMUX_PB02G_RTC_IN1; + config &= ~(3 << RTC_TAMPCTRL_IN1ACT_Pos); + config &= ~(1 << RTC_TAMPCTRL_TAMLVL1_Pos); + config |= 1 << RTC_TAMPCTRL_IN1ACT_Pos; + config |= 1 << RTC_TAMPCTRL_DEBNC1_Pos; + if (level) config |= 1 << RTC_TAMPCTRL_TAMLVL1_Pos; + break; + case BTN_ALARM: + gpio_set_pin_pull_mode(pin, GPIO_PULL_DOWN); + btn_alarm_callback = callback; + pinmux = PINMUX_PA02G_RTC_IN2; + config &= ~(3 << RTC_TAMPCTRL_IN2ACT_Pos); + config &= ~(1 << RTC_TAMPCTRL_TAMLVL2_Pos); + config |= 1 << RTC_TAMPCTRL_IN2ACT_Pos; + config |= 1 << RTC_TAMPCTRL_DEBNC2_Pos; + if (level) config |= 1 << RTC_TAMPCTRL_TAMLVL2_Pos; + break; + default: + return; + } + gpio_set_pin_direction(pin, GPIO_DIRECTION_IN); + gpio_set_pin_function(pin, pinmux); + + // disable the RTC + RTC->MODE2.CTRLA.bit.ENABLE = 0; + while (RTC->MODE2.SYNCBUSY.bit.ENABLE); + + // update the configuration + RTC->MODE2.TAMPCTRL.reg = config; + // re-enable the RTC + RTC->MODE2.CTRLA.bit.ENABLE = 1; + + NVIC_ClearPendingIRQ(RTC_IRQn); + NVIC_EnableIRQ(RTC_IRQn); + RTC->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; +} + +void watch_disable_extwake_interrupt(uint8_t pin) { + hri_rtc_tampctrl_reg_t config = hri_rtc_get_TAMPCTRL_reg(RTC, 0xFFFFFFFF); + + switch (pin) { + case A4: + a4_callback = NULL; + config &= ~(3 << RTC_TAMPCTRL_IN0ACT_Pos); + break; + case A2: + a2_callback = NULL; + config &= ~(3 << RTC_TAMPCTRL_IN1ACT_Pos); + break; + case BTN_ALARM: + btn_alarm_callback = NULL; + config &= ~(3 << RTC_TAMPCTRL_IN2ACT_Pos); + break; + default: + return; + } + + if (hri_rtcmode0_get_CTRLA_ENABLE_bit(RTC)) { + hri_rtcmode0_clear_CTRLA_ENABLE_bit(RTC); + hri_rtcmode0_wait_for_sync(RTC, RTC_MODE0_SYNCBUSY_ENABLE); + } + hri_rtc_write_TAMPCTRL_reg(RTC, config); + hri_rtcmode0_set_CTRLA_ENABLE_bit(RTC); +} + +void watch_store_backup_data(uint32_t data, uint8_t reg) { + if (reg < 8) { + RTC->MODE0.BKUP[reg].reg = data; + } +} + +uint32_t watch_get_backup_data(uint8_t reg) { + if (reg < 8) { + return RTC->MODE0.BKUP[reg].reg; + } + + return 0; +} + +static void _watch_disable_all_pins_except_rtc(void) { + uint32_t config = RTC->MODE0.TAMPCTRL.reg; + uint32_t portb_pins_to_disable = 0xFFFFFFFF; + + // if there's an action set on RTC/IN[0], leave PB00 configured + if (config & RTC_TAMPCTRL_IN0ACT_Msk) portb_pins_to_disable &= 0xFFFFFFFE; + // same with RTC/IN[1] and PB02 + if (config & RTC_TAMPCTRL_IN1ACT_Msk) portb_pins_to_disable &= 0xFFFFFFFB; + + // port A: always keep PA02 configured as-is; that's our ALARM button. + gpio_set_port_direction(0, 0xFFFFFFFB, GPIO_DIRECTION_OFF); + // port B: disable all pins we didn't save above. + gpio_set_port_direction(1, portb_pins_to_disable, GPIO_DIRECTION_OFF); +} + +static void _watch_disable_all_peripherals_except_slcd(void) { + _watch_disable_tcc(); + watch_disable_adc(); + watch_disable_external_interrupts(); + watch_disable_i2c(); + // TODO: replace this with a proper function when we remove the debug UART + SERCOM3->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + MCLK->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM3; +} + +void watch_enter_sleep_mode(void) { + // disable all other peripherals + _watch_disable_all_peripherals_except_slcd(); + + // disable tick interrupt + watch_rtc_disable_all_periodic_callbacks(); + + // disable brownout detector interrupt, which could inadvertently wake us up. + SUPC->INTENCLR.bit.BOD33DET = 1; + + // disable all pins + _watch_disable_all_pins_except_rtc(); + + // enter standby (4); we basically hang out here until an interrupt wakes us. + sleep(4); + + // and we awake! re-enable the brownout detector + SUPC->INTENSET.bit.BOD33DET = 1; + + // call app_setup so the app can re-enable everything we disabled. + app_setup(); + + // and call app_wake_from_standby (since main won't have a chance to do it) + app_wake_from_standby(); +} + +void watch_enter_deep_sleep_mode(void) { + // identical to sleep mode except we disable the LCD first. + slcd_sync_deinit(&SEGMENT_LCD_0); + hri_mclk_clear_APBCMASK_SLCD_bit(SLCD); + + watch_enter_sleep_mode(); +} + +void watch_enter_backup_mode(void) { + watch_rtc_disable_all_periodic_callbacks(); + _watch_disable_all_peripherals_except_slcd(); + slcd_sync_deinit(&SEGMENT_LCD_0); + hri_mclk_clear_APBCMASK_SLCD_bit(SLCD); + _watch_disable_all_pins_except_rtc(); + + // go into backup sleep mode (5). when we exit, the reset controller will take over. + sleep(5); +} + +// deprecated +void watch_enter_shallow_sleep(bool display_on) { + if (display_on) watch_enter_sleep_mode(); + else watch_enter_deep_sleep_mode(); +} + +// deprecated +void watch_enter_deep_sleep(void) { + watch_register_extwake_callback(BTN_ALARM, NULL, true); + watch_enter_backup_mode(); +} diff --git a/watch-library/hardware/watch/watch_extint.c b/watch-library/hardware/watch/watch_extint.c new file mode 100644 index 00000000..5924b646 --- /dev/null +++ b/watch-library/hardware/watch/watch_extint.c @@ -0,0 +1,111 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_extint.h" + +void watch_enable_external_interrupts(void) { + // Configure EIC to use GCLK3 (the 32.768 kHz crystal) + hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos)); + // Enable AHB clock for the EIC + hri_mclk_set_APBAMASK_EIC_bit(MCLK); + // call HAL's external interrupt init function + ext_irq_init(); +} + +void watch_disable_external_interrupts(void) { + ext_irq_deinit(); + hri_mclk_clear_APBAMASK_EIC_bit(MCLK); +} + +void watch_register_interrupt_callback(const uint8_t pin, ext_irq_cb_t callback, watch_interrupt_trigger trigger) { + uint8_t config_index; + uint8_t sense_pos; + switch (pin) { + case A0: + // for EIC channels 8-15, we need to set the SENSE value in CONFIG[1] + config_index = (WATCH_A0_EIC_CHANNEL > 7) ? 1 : 0; + // either way the index in CONFIG[n] must be 0-7 + sense_pos = 4 * (WATCH_A0_EIC_CHANNEL % 8); + break; + case A1: + config_index = (WATCH_A1_EIC_CHANNEL > 7) ? 1 : 0; + sense_pos = 4 * (WATCH_A1_EIC_CHANNEL % 8); + break; + case A2: + config_index = (WATCH_A2_EIC_CHANNEL > 7) ? 1 : 0; + sense_pos = 4 * (WATCH_A2_EIC_CHANNEL % 8); + break; + case A3: + config_index = (WATCH_A3_EIC_CHANNEL > 7) ? 1 : 0; + sense_pos = 4 * (WATCH_A3_EIC_CHANNEL % 8); + break; + case A4: + config_index = (WATCH_A4_EIC_CHANNEL > 7) ? 1 : 0; + sense_pos = 4 * (WATCH_A4_EIC_CHANNEL % 8); + break; + case BTN_ALARM: + config_index = (WATCH_BTN_ALARM_EIC_CHANNEL > 7) ? 1 : 0; + sense_pos = 4 * (WATCH_BTN_ALARM_EIC_CHANNEL % 8); + break; + case BTN_LIGHT: + config_index = (WATCH_BTN_LIGHT_EIC_CHANNEL > 7) ? 1 : 0; + sense_pos = 4 * (WATCH_BTN_LIGHT_EIC_CHANNEL % 8); + break; + case BTN_MODE: + config_index = (WATCH_BTN_MODE_EIC_CHANNEL > 7) ? 1 : 0; + sense_pos = 4 * (WATCH_BTN_MODE_EIC_CHANNEL % 8); + break; + default: + return; + } + + gpio_set_pin_direction(pin, GPIO_DIRECTION_IN); + + // EIC configuration register is enable-protected, so we have to disable it first... + if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) { + hri_eic_clear_CTRLA_ENABLE_bit(EIC); + // ...and wait for it to synchronize. + hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE); + } + // now update the configuration... + hri_eic_config_reg_t config = EIC->CONFIG[config_index].reg; + config &= ~(7 << sense_pos); + config |= trigger << (sense_pos); + hri_eic_write_CONFIG_reg(EIC, config_index, config); + // ...set the pin mode... + gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_A); + if (pin == BTN_ALARM || pin == BTN_LIGHT || pin == BTN_MODE) gpio_set_pin_pull_mode(pin, GPIO_PULL_DOWN); + // ...and re-enable the EIC + hri_eic_set_CTRLA_ENABLE_bit(EIC); + + ext_irq_register(pin, callback); +} + +inline void watch_register_button_callback(const uint8_t pin, ext_irq_cb_t callback) { + watch_register_interrupt_callback(pin, callback, INTERRUPT_TRIGGER_RISING); +} + +inline void watch_enable_buttons(void) { + watch_enable_external_interrupts(); +} diff --git a/watch-library/hardware/watch/watch_gpio.c b/watch-library/hardware/watch/watch_gpio.c new file mode 100644 index 00000000..b37d009f --- /dev/null +++ b/watch-library/hardware/watch/watch_gpio.c @@ -0,0 +1,61 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_gpio.h" + + void watch_enable_digital_input(const uint8_t pin) { + gpio_set_pin_direction(pin, GPIO_DIRECTION_IN); + gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF); +} + +void watch_disable_digital_input(const uint8_t pin) { + gpio_set_pin_direction(pin, GPIO_DIRECTION_OFF); + gpio_set_pin_pull_mode(pin, GPIO_PULL_OFF); + gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF); +} + +void watch_enable_pull_up(const uint8_t pin) { + gpio_set_pin_pull_mode(pin, GPIO_PULL_UP); +} + +void watch_enable_pull_down(const uint8_t pin) { + gpio_set_pin_pull_mode(pin, GPIO_PULL_DOWN); +} + +bool watch_get_pin_level(const uint8_t pin) { + return gpio_get_pin_level(pin); +} + +void watch_enable_digital_output(const uint8_t pin) { + gpio_set_pin_direction(pin, GPIO_DIRECTION_OUT); + gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF); +} + +void watch_disable_digital_output(const uint8_t pin) { + gpio_set_pin_direction(pin, GPIO_DIRECTION_OFF); +} + +void watch_set_pin_level(const uint8_t pin, const bool level) { + gpio_set_pin_level(pin, level); +} diff --git a/watch-library/hardware/watch/watch_i2c.c b/watch-library/hardware/watch/watch_i2c.c new file mode 100644 index 00000000..ff20afc6 --- /dev/null +++ b/watch-library/hardware/watch/watch_i2c.c @@ -0,0 +1,93 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_i2c.h" + +struct io_descriptor *I2C_0_io; + +void watch_enable_i2c(void) { + I2C_0_init(); + i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); + i2c_m_sync_enable(&I2C_0); +} + +void watch_disable_i2c(void) { + i2c_m_sync_disable(&I2C_0); + hri_mclk_clear_APBCMASK_SERCOM1_bit(MCLK); +} + +void watch_i2c_send(int16_t addr, uint8_t *buf, uint16_t length) { + i2c_m_sync_set_periphaddr(&I2C_0, addr, I2C_M_SEVEN); + io_write(I2C_0_io, buf, length); +} + +void watch_i2c_receive(int16_t addr, uint8_t *buf, uint16_t length) { + i2c_m_sync_set_periphaddr(&I2C_0, addr, I2C_M_SEVEN); + io_read(I2C_0_io, buf, length); +} + +void watch_i2c_write8(int16_t addr, uint8_t reg, uint8_t data) { + uint8_t buf[2]; + buf[0] = reg; + buf[1] = data; + + watch_i2c_send(addr, (uint8_t *)&buf, 2); +} + +uint8_t watch_i2c_read8(int16_t addr, uint8_t reg) { + uint8_t data; + + watch_i2c_send(addr, (uint8_t *)®, 1); + watch_i2c_receive(addr, (uint8_t *)&data, 1); + + return data; +} + +uint16_t watch_i2c_read16(int16_t addr, uint8_t reg) { + uint16_t data; + + watch_i2c_send(addr, (uint8_t *)®, 1); + watch_i2c_receive(addr, (uint8_t *)&data, 2); + + return data; +} + +uint32_t watch_i2c_read24(int16_t addr, uint8_t reg) { + uint32_t data; + data = 0; + + watch_i2c_send(addr, (uint8_t *)®, 1); + watch_i2c_receive(addr, (uint8_t *)&data, 3); + + return data << 8; +} + +uint32_t watch_i2c_read32(int16_t addr, uint8_t reg) { + uint32_t data; + + watch_i2c_send(addr, (uint8_t *)®, 1); + watch_i2c_receive(addr, (uint8_t *)&data, 4); + + return data; +} diff --git a/watch-library/hardware/watch/watch_led.c b/watch-library/hardware/watch/watch_led.c new file mode 100644 index 00000000..52174b54 --- /dev/null +++ b/watch-library/hardware/watch/watch_led.c @@ -0,0 +1,69 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_led.h" + +void watch_enable_leds(void) { + if (!hri_tcc_get_CTRLA_reg(TCC0, TCC_CTRLA_ENABLE)) { + _watch_enable_tcc(); + } +} + +void watch_disable_leds(void) { + _watch_disable_tcc(); +} + +void watch_enable_led(bool unused) { + (void)unused; + watch_enable_leds(); +} + +void watch_disable_led(bool unused) { + (void)unused; + watch_disable_leds(); +} + +void watch_set_led_color(uint8_t red, uint8_t green) { + if (hri_tcc_get_CTRLA_reg(TCC0, TCC_CTRLA_ENABLE)) { + uint32_t period = hri_tcc_get_PER_reg(TCC0, TCC_PER_MASK); + hri_tcc_write_CCBUF_reg(TCC0, WATCH_RED_TCC_CHANNEL, ((period * red * 1000ull) / 255000ull)); + hri_tcc_write_CCBUF_reg(TCC0, WATCH_GREEN_TCC_CHANNEL, ((period * green * 1000ull) / 255000ull)); + } +} + +void watch_set_led_red(void) { + watch_set_led_color(255, 0); +} + +void watch_set_led_green(void) { + watch_set_led_color(0, 255); +} + +void watch_set_led_yellow(void) { + watch_set_led_color(255, 255); +} + +void watch_set_led_off(void) { + watch_set_led_color(0, 0); +} diff --git a/watch-library/hardware/watch/watch_private.c b/watch-library/hardware/watch/watch_private.c new file mode 100644 index 00000000..ae2589e7 --- /dev/null +++ b/watch-library/hardware/watch/watch_private.c @@ -0,0 +1,423 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_private.h" +#include "watch_utility.h" +#include "tusb.h" + +void _watch_init(void) { + // disable the LED pin (it may have been enabled by the bootloader) + watch_disable_digital_output(RED); + + // RAM should be back-biased in STANDBY + PM->STDBYCFG.bit.BBIASHS = 1; + + // Use switching regulator for lower power consumption. + SUPC->VREG.bit.SEL = 1; + while(!SUPC->STATUS.bit.VREGRDY); + + // set up the brownout detector (low battery warning) + NVIC_DisableIRQ(SYSTEM_IRQn); + NVIC_ClearPendingIRQ(SYSTEM_IRQn); + NVIC_EnableIRQ(SYSTEM_IRQn); + SUPC->BOD33.bit.ENABLE = 0; // BOD33 must be disabled to change its configuration + SUPC->BOD33.bit.VMON = 0; // Monitor VDD in active and standby mode + SUPC->BOD33.bit.ACTCFG = 1; // Enable sampling mode when active + SUPC->BOD33.bit.RUNSTDBY = 1; // Enable sampling mode in standby + SUPC->BOD33.bit.STDBYCFG = 1; // Run in standby + SUPC->BOD33.bit.RUNBKUP = 0; // Don't run in backup mode + SUPC->BOD33.bit.PSEL = 0xB; // Check battery level every 4 seconds + SUPC->BOD33.bit.LEVEL = 31; // Detect brownout at 2.5V (1.445V + level * 34mV) + SUPC->BOD33.bit.ACTION = 0x2; // Generate an interrupt when BOD33 is triggered + SUPC->BOD33.bit.HYST = 0; // Disable hysteresis + while(!SUPC->STATUS.bit.B33SRDY); + + // Enable interrupt on BOD33 detect + SUPC->INTENSET.bit.BOD33DET = 1; + SUPC->BOD33.bit.ENABLE = 1; + + // External wake depends on RTC; calendar is a required module. + _watch_rtc_init(); + + // set up state + btn_alarm_callback = NULL; + a2_callback = NULL; + a4_callback = NULL; +} + +static inline void _watch_wait_for_entropy() { + while (!hri_trng_get_INTFLAG_reg(TRNG, TRNG_INTFLAG_DATARDY)); +} + +// this function is called by arc4random to get entropy for random number generation. +// let's use the SAM L22's true random number generator to seed the PRNG! +int getentropy(void *buf, size_t buflen) { + hri_mclk_set_APBCMASK_TRNG_bit(MCLK); + hri_trng_set_CTRLA_ENABLE_bit(TRNG); + + size_t i = 0; + while(i < buflen / 4) { + _watch_wait_for_entropy(); + ((uint32_t *)buf)[i++] = hri_trng_read_DATA_reg(TRNG); + } + + // but what if they asked for an awkward number of bytes? + if (buflen % 4) { + // all good: let's fill in one, two or three bytes at the end of the buffer. + _watch_wait_for_entropy(); + uint32_t last_little_bit = hri_trng_read_DATA_reg(TRNG); + for(size_t j = 0; j <= (buflen % 4); j++) { + ((uint8_t *)buf)[i * 4 + j] = (last_little_bit >> (j * 8)) & 0xFF; + } + } + + hri_trng_clear_CTRLA_ENABLE_bit(TRNG); + hri_mclk_clear_APBCMASK_TRNG_bit(MCLK); + + return 0; +} + +int _gettimeofday(struct timeval *tv, void *tzvp) { + (void)tzvp; + watch_date_time date_time = watch_rtc_get_date_time(); + + // FIXME: this assumes the system time is UTC! Will break for any other time zone. + tv->tv_sec = watch_utility_date_time_to_unix_time(date_time, 0); + tv->tv_usec = 0; + + return 0; +} + +void _watch_enable_tcc(void) { + // clock TCC0 with the main clock (8 MHz) and enable the peripheral clock. + hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK0_Val | GCLK_PCHCTRL_CHEN); + hri_mclk_set_APBCMASK_TCC0_bit(MCLK); + // disable and reset TCC0. + hri_tcc_clear_CTRLA_ENABLE_bit(TCC0); + hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_ENABLE); + hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_SWRST); + hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_SWRST); + // divide the clock down to 1 MHz + if (hri_usbdevice_get_CTRLA_ENABLE_bit(USB)) { + // if USB is enabled, we are running an 8 MHz clock. + hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_PRESCALER_DIV8); + } else { + // otherwise it's 4 Mhz. + hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_PRESCALER_DIV4); + } + // We're going to use normal PWM mode, which means period is controlled by PER, and duty cycle is controlled by + // each compare channel's value: + // * Buzzer tones are set by setting PER to the desired period for a given frequency, and CC[1] to half of that + // period (i.e. a square wave with a 50% duty cycle). + // * LEDs on CC[2] and CC[3] can be set to any value from 0 (off) to PER (fully on). + hri_tcc_write_WAVE_reg(TCC0, TCC_WAVE_WAVEGEN_NPWM); + #ifdef WATCH_INVERT_LED_POLARITY + // This is here for the dev board, which uses a common anode LED (instead of common cathode like the actual watch). + hri_tcc_set_WAVE_reg(TCC0, (1 << (TCC_WAVE_POL0_Pos + WATCH_RED_TCC_CHANNEL)) | + (1 << (TCC_WAVE_POL0_Pos + WATCH_GREEN_TCC_CHANNEL))); + #endif + // The buzzer will set the period depending on the tone it wants to play, but we have to set some period here to + // get the LED working. Almost any period will do, tho it should be below 20000 (i.e. 50 Hz) to avoid flickering. + hri_tcc_write_PER_reg(TCC0, 4096); + // Set the duty cycle of all pins to 0: LED's off, buzzer not buzzing. + hri_tcc_write_CC_reg(TCC0, WATCH_BUZZER_TCC_CHANNEL, 0); + hri_tcc_write_CC_reg(TCC0, WATCH_RED_TCC_CHANNEL, 0); + hri_tcc_write_CC_reg(TCC0, WATCH_GREEN_TCC_CHANNEL, 0); + // Enable the TCC + hri_tcc_set_CTRLA_ENABLE_bit(TCC0); + hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_ENABLE); + + // enable LED PWM pins (the LED driver assumes if the TCC is on, the pins are enabled) + gpio_set_pin_direction(RED, GPIO_DIRECTION_OUT); + gpio_set_pin_function(RED, WATCH_RED_TCC_PINMUX); + gpio_set_pin_direction(GREEN, GPIO_DIRECTION_OUT); + gpio_set_pin_function(GREEN, WATCH_GREEN_TCC_PINMUX); +} + +void _watch_disable_tcc(void) { + // disable all PWM pins + gpio_set_pin_direction(BUZZER, GPIO_DIRECTION_OFF); + gpio_set_pin_function(BUZZER, GPIO_PIN_FUNCTION_OFF); + gpio_set_pin_direction(RED, GPIO_DIRECTION_OFF); + gpio_set_pin_function(RED, GPIO_PIN_FUNCTION_OFF); + gpio_set_pin_direction(GREEN, GPIO_DIRECTION_OFF); + gpio_set_pin_function(GREEN, GPIO_PIN_FUNCTION_OFF); + + // disable the TCC + hri_tcc_clear_CTRLA_ENABLE_bit(TCC0); + hri_mclk_clear_APBCMASK_TCC0_bit(MCLK); +} + +void _watch_enable_usb(void) { + // disable USB, just in case. + hri_usb_clear_CTRLA_ENABLE_bit(USB); + + // bump clock up to 8 MHz + hri_oscctrl_write_OSC16MCTRL_FSEL_bf(OSCCTRL, OSCCTRL_OSC16MCTRL_FSEL_8_Val); + + // reset flags and disable DFLL + OSCCTRL->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; + OSCCTRL->DFLLCTRL.reg = 0; + while (!(OSCCTRL->STATUS.reg & OSCCTRL_STATUS_DFLLRDY)); + + // set the coarse and fine values to speed up frequency lock. + uint32_t coarse =(*((uint32_t *)NVMCTRL_OTP5)) >> 26; + OSCCTRL->DFLLVAL.reg = OSCCTRL_DFLLVAL_COARSE(coarse) | + OSCCTRL_DFLLVAL_FINE(0x200); + // set coarse and fine steps, and multiplier (48 MHz = 32768 Hz * 1465) + OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_CSTEP( 1 ) | + OSCCTRL_DFLLMUL_FSTEP( 1 ) | + OSCCTRL_DFLLMUL_MUL( 1465 ); + // set closed loop mode, chill cycle disable and USB clock recovery mode, and enable the DFLL. + OSCCTRL->DFLLCTRL.reg = OSCCTRL_DFLLCTRL_MODE | OSCCTRL_DFLLCTRL_CCDIS | OSCCTRL_DFLLCTRL_ONDEMAND | OSCCTRL_DFLLCTRL_RUNSTDBY | OSCCTRL_DFLLCTRL_USBCRM | OSCCTRL_DFLLCTRL_ENABLE; + while (!(OSCCTRL->STATUS.reg & OSCCTRL_STATUS_DFLLRDY)); + + // assign DFLL to GCLK1 + GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL48M) | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;// | GCLK_GENCTRL_OE; + while (GCLK->SYNCBUSY.bit.GENCTRL1); + + // assign GCLK1 to USB + hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); + hri_mclk_set_AHBMASK_USB_bit(MCLK); + hri_mclk_set_APBBMASK_USB_bit(MCLK); + + // USB Pin Init + gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA24, false); + gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); + gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA25, false); + gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); + + gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); + gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); + + // before we init TinyUSB, we are going to need a periodic callback to handle TinyUSB tasks. + // TC2 and TC3 are reserved for devices on the 9-pin connector, so let's use TC0. + // clock TC0 with the 8 MHz clock on GCLK0. + hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK0_Val | GCLK_PCHCTRL_CHEN); + // and enable the peripheral clock. + hri_mclk_set_APBCMASK_TC0_bit(MCLK); + // disable and reset TC0. + hri_tc_clear_CTRLA_ENABLE_bit(TC0); + hri_tc_wait_for_sync(TC0, TC_SYNCBUSY_ENABLE); + hri_tc_write_CTRLA_reg(TC0, TC_CTRLA_SWRST); + hri_tc_wait_for_sync(TC0, TC_SYNCBUSY_SWRST); + // configure the TC to overflow 1,000 times per second + hri_tc_write_CTRLA_reg(TC0, TC_CTRLA_PRESCALER_DIV64 | // divide the 8 MHz clock by 64 to count at 125 KHz + TC_CTRLA_MODE_COUNT8 | // count in 8-bit mode + TC_CTRLA_RUNSTDBY); // run in standby, just in case we figure that out + hri_tccount8_write_PER_reg(TC0, 125); // 125000 Hz / 125 = 1,000 Hz + // set an interrupt on overflow; this will call TC0_Handler below. + hri_tc_set_INTEN_OVF_bit(TC0); + NVIC_ClearPendingIRQ(TC0_IRQn); + NVIC_EnableIRQ (TC0_IRQn); + + // now we can init TinyUSB + tusb_init(); + // and start the timer that handles USB device tasks. + hri_tc_set_CTRLA_ENABLE_bit(TC0); +} + +// this function ends up getting called by printf to log stuff to the USB console. +int _write(int file, char *ptr, int len) { + (void)file; + if (hri_usbdevice_get_CTRLA_ENABLE_bit(USB)) { + tud_cdc_n_write(0, (void const*)ptr, len); + tud_cdc_n_write_flush(0); + return len; + } + + return 0; +} + +// this method could be overridden to read stuff from the USB console? but no need rn. +int _read(void) { + return 0; +} + +// Alternate function that outputs to the debug UART. useful for debugging USB issues. +// int _write(int file, char *ptr, int len) { +// (void)file; +// int pos = 0; +// while(pos < len) watch_debug_putc(ptr[pos++]); + +// return 0; +// } + +void USB_Handler(void) { + tud_int_handler(0); +} + +void TC0_Handler(void) { + tud_task(); + TC0->COUNT8.INTFLAG.reg |= TC_INTFLAG_OVF; +} + + +// USB Descriptors and tinyUSB callbacks follow. + +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +//--------------------------------------------------------------------+ +// Device Descriptors +//--------------------------------------------------------------------+ +tusb_desc_device_t const desc_device = +{ + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0200, + + // Use Interface Association Descriptor (IAD) for CDC + // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + .idVendor = 0x1209, + .idProduct = 0x2151, + .bcdDevice = 0x0100, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01 +}; + +// Invoked when received GET DEVICE DESCRIPTOR +// Application return pointer to descriptor +uint8_t const * tud_descriptor_device_cb(void) { + return (uint8_t const *) &desc_device; +} + +//--------------------------------------------------------------------+ +// Configuration Descriptor +//--------------------------------------------------------------------+ + +enum { + ITF_NUM_CDC = 0, + ITF_NUM_CDC_DATA, + ITF_NUM_TOTAL +}; + +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN) + +#define EPNUM_CDC_NOTIF 0x81 +#define EPNUM_CDC_OUT 0x02 +#define EPNUM_CDC_IN 0x82 + + +uint8_t const desc_fs_configuration[] = { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + + // Interface number, string index, EP notification address and size, EP data address (out, in) and size. + TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64), +}; + +// Invoked when received GET CONFIGURATION DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const * tud_descriptor_configuration_cb(uint8_t index) { + (void) index; // for multiple configurations + return desc_fs_configuration; +} + +//--------------------------------------------------------------------+ +// String Descriptors +//--------------------------------------------------------------------+ + +// array of pointer to string descriptors +char const* string_desc_arr [] = +{ + (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + "123456", // 3: Serials, should use chip ID + "TinyUSB CDC", // 4: CDC Interface +}; + +static uint16_t _desc_str[32]; + +// Invoked when received GET STRING DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) +{ + (void) langid; + + uint8_t chr_count; + + if ( index == 0) { + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + } else { + // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. + // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors + + if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL; + + const char* str = string_desc_arr[index]; + + // Cap at max char + chr_count = strlen(str); + if ( chr_count > 31 ) chr_count = 31; + + // Convert ASCII string into UTF-16 + for(uint8_t i=0; iMODE2.CTRLA.bit.ENABLE; +} + +static void _sync_rtc(void) { + while (RTC->MODE2.SYNCBUSY.reg); +} + +void _watch_rtc_init(void) { + MCLK->APBAMASK.reg |= MCLK_APBAMASK_RTC; + + if (_watch_rtc_is_enabled()) return; // don't reset the RTC if it's already set up. + + RTC->MODE2.CTRLA.bit.ENABLE = 0; + _sync_rtc(); + + RTC->MODE2.CTRLA.bit.SWRST = 1; + _sync_rtc(); + + RTC->MODE2.CTRLA.bit.MODE = RTC_MODE2_CTRLA_MODE_CLOCK_Val; + RTC->MODE2.CTRLA.bit.PRESCALER = RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val; + RTC->MODE2.CTRLA.bit.CLOCKSYNC = 1; + RTC->MODE2.CTRLA.bit.ENABLE = 1; + _sync_rtc(); +} + +void watch_rtc_set_date_time(watch_date_time date_time) { + RTC->MODE2.CLOCK.reg = date_time.reg; + _sync_rtc(); +} + +watch_date_time watch_rtc_get_date_time(void) { + watch_date_time retval; + + _sync_rtc(); + retval.reg = RTC->MODE2.CLOCK.reg; + + return retval; +} + +void watch_rtc_register_tick_callback(ext_irq_cb_t callback) { + watch_rtc_register_periodic_callback(callback, 1); +} + +void watch_rtc_disable_tick_callback(void) { + watch_rtc_disable_periodic_callback(1); +} + +void watch_rtc_register_periodic_callback(ext_irq_cb_t callback, uint8_t frequency) { + // we told them, it has to be a power of 2. + if (__builtin_popcount(frequency) != 1) return; + + // this left-justifies the period in a 32-bit integer. + uint32_t tmp = frequency << 24; + // now we can count the leading zeroes to get the value we need. + // 0x01 (1 Hz) will have 7 leading zeros for PER7. 0xF0 (128 Hz) will have no leading zeroes for PER0. + uint8_t per_n = __builtin_clz(tmp); + + // this also maps nicely to an index for our list of tick callbacks. + tick_callbacks[per_n] = callback; + + NVIC_ClearPendingIRQ(RTC_IRQn); + NVIC_EnableIRQ(RTC_IRQn); + RTC->MODE2.INTENSET.reg = 1 << per_n; +} + +void watch_rtc_disable_periodic_callback(uint8_t frequency) { + if (__builtin_popcount(frequency) != 1) return; + uint8_t per_n = __builtin_clz(frequency << 24); + RTC->MODE2.INTENCLR.reg = 1 << per_n; +} + +void watch_rtc_disable_all_periodic_callbacks(void) { + RTC->MODE2.INTENCLR.reg = 0xFF; +} + +void watch_rtc_register_alarm_callback(ext_irq_cb_t callback, watch_date_time alarm_time, watch_rtc_alarm_match mask) { + RTC->MODE2.Mode2Alarm[0].ALARM.reg = alarm_time.reg; + RTC->MODE2.Mode2Alarm[0].MASK.reg = mask; + RTC->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + alarm_callback = callback; + NVIC_ClearPendingIRQ(RTC_IRQn); + NVIC_EnableIRQ(RTC_IRQn); + RTC->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +void watch_rtc_disable_alarm_callback(void) { + RTC->MODE2.INTENCLR.reg = RTC_MODE2_INTENCLR_ALARM0; +} + +void RTC_Handler(void) { + uint16_t interrupt_status = RTC->MODE2.INTFLAG.reg; + uint16_t interrupt_enabled = RTC->MODE2.INTENSET.reg; + + if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_PER_Msk) { + // handle the tick callback first, it's what we do the most. + // start from PER7, the 1 Hz tick. + for(int8_t i = 7; i >= 0; i--) { + if ((interrupt_status & interrupt_enabled) & (1 << i)) { + if (tick_callbacks[i] != NULL) { + tick_callbacks[i](); + } + RTC->MODE2.INTFLAG.reg = 1 << i; + break; + } + } + } else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) { + // handle the extwake interrupts next. + uint8_t reason = RTC->MODE2.TAMPID.reg; + if (reason & RTC_TAMPID_TAMPID2) { + if (btn_alarm_callback != NULL) btn_alarm_callback(); + } else if (reason & RTC_TAMPID_TAMPID1) { + if (a2_callback != NULL) a2_callback(); + } else if (reason & RTC_TAMPID_TAMPID0) { + if (a4_callback != NULL) a4_callback(); + } + RTC->MODE2.TAMPID.reg = reason; + RTC->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; + } else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_ALARM0) { + // finally handle the alarm. + if (alarm_callback != NULL) { + alarm_callback(); + } + RTC->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; + } +} + +/////////////////////// +// Deprecated functions + +void watch_set_date_time(struct calendar_date_time date_time) { + RTC_MODE2_CLOCK_Type val; + + val.bit.SECOND = date_time.time.sec; + val.bit.MINUTE = date_time.time.min; + val.bit.HOUR = date_time.time.hour; + val.bit.DAY = date_time.date.day; + val.bit.MONTH = date_time.date.month; + val.bit.YEAR = (uint8_t)(date_time.date.year - WATCH_RTC_REFERENCE_YEAR); + + RTC->MODE2.CLOCK.reg = val.reg; + + _sync_rtc(); +} + +void watch_get_date_time(struct calendar_date_time *date_time) { + _sync_rtc(); + RTC_MODE2_CLOCK_Type val = RTC->MODE2.CLOCK; + + date_time->time.sec = val.bit.SECOND; + date_time->time.min = val.bit.MINUTE; + date_time->time.hour = val.bit.HOUR; + date_time->date.day = val.bit.DAY; + date_time->date.month = val.bit.MONTH; + date_time->date.year = val.bit.YEAR + WATCH_RTC_REFERENCE_YEAR; +} + +void watch_register_tick_callback(ext_irq_cb_t callback) { + tick_callbacks[7] = callback; + NVIC_ClearPendingIRQ(RTC_IRQn); + NVIC_EnableIRQ(RTC_IRQn); + RTC->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; +} diff --git a/watch-library/hardware/watch/watch_slcd.c b/watch-library/hardware/watch/watch_slcd.c new file mode 100644 index 00000000..c3bacd0d --- /dev/null +++ b/watch-library/hardware/watch/watch_slcd.c @@ -0,0 +1,101 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_slcd.h" +#include "watch_private_display.h" +#include "hpl_slcd_config.h" + + ////////////////////////////////////////////////////////////////////////////////////////// +// Segmented Display + +static void _sync_slcd(void) { + while (SLCD->SYNCBUSY.reg); +} + +void watch_enable_display(void) { + SEGMENT_LCD_0_init(); + slcd_sync_enable(&SEGMENT_LCD_0); +} + +inline void watch_set_pixel(uint8_t com, uint8_t seg) { + slcd_sync_seg_on(&SEGMENT_LCD_0, SLCD_SEGID(com, seg)); +} + +inline void watch_clear_pixel(uint8_t com, uint8_t seg) { + slcd_sync_seg_off(&SEGMENT_LCD_0, SLCD_SEGID(com, seg)); +} + +void watch_clear_display(void) { + SLCD->SDATAL0.reg = 0; + SLCD->SDATAL1.reg = 0; + SLCD->SDATAL2.reg = 0; +} + +void watch_start_character_blink(char character, uint32_t duration) { + SLCD->CTRLD.bit.FC0EN = 0; + _sync_slcd(); + + if (duration <= SLCD_FC_BYPASS_MAX_MS) { + SLCD->FC0.reg = SLCD_FC0_PB | ((duration / (1000 / SLCD_FRAME_FREQUENCY)) - 1); + } else { + SLCD->FC0.reg = (((duration / (1000 / SLCD_FRAME_FREQUENCY)) / 8 - 1)); + } + SLCD->CTRLD.bit.FC0EN = 1; + + watch_display_character(character, 7); + watch_clear_pixel(2, 10); // clear segment B of position 7 since it can't blink + + SLCD->CTRLD.bit.BLINK = 0; + SLCD->CTRLA.bit.ENABLE = 0; + _sync_slcd(); + + SLCD->BCFG.bit.BSS0 = 0x07; + SLCD->BCFG.bit.BSS1 = 0x07; + + SLCD->CTRLD.bit.BLINK = 1; + _sync_slcd(); + SLCD->CTRLA.bit.ENABLE = 1; + _sync_slcd(); +} + +void watch_stop_blink(void) { + SLCD->CTRLD.bit.FC0EN = 0; + SLCD->CTRLD.bit.BLINK = 0; +} + +void watch_start_tick_animation(uint32_t duration) { + watch_display_character(' ', 8); + const uint32_t segs[] = { SLCD_SEGID(0, 2)}; + slcd_sync_start_animation(&SEGMENT_LCD_0, segs, 1, duration); +} + +bool watch_tick_animation_is_running(void) { + return hri_slcd_get_CTRLD_CSREN_bit(SLCD); +} + +void watch_stop_tick_animation(void) { + const uint32_t segs[] = { SLCD_SEGID(0, 2)}; + slcd_sync_stop_animation(&SEGMENT_LCD_0, segs, 1); + watch_display_character(' ', 8); +} diff --git a/watch-library/hardware/watch/watch_uart.c b/watch-library/hardware/watch/watch_uart.c new file mode 100644 index 00000000..64b63bee --- /dev/null +++ b/watch-library/hardware/watch/watch_uart.c @@ -0,0 +1,89 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* + * UART methods are Copyright (c) 2014-2017, Alex Taradov + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "watch_uart.h" +#include "peripheral_clk_config.h" + +void watch_enable_debug_uart(uint32_t baud) { + uint64_t br = (uint64_t)65536 * ((CONF_CPU_FREQUENCY * 4) - 16 * baud) / (CONF_CPU_FREQUENCY * 4); + + gpio_set_pin_direction(A2, GPIO_DIRECTION_OUT); + gpio_set_pin_function(A2, PINMUX_PB02C_SERCOM3_PAD0); + + MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3; + + GCLK->PCHCTRL[SERCOM3_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN(0) | GCLK_PCHCTRL_CHEN; + while (0 == (GCLK->PCHCTRL[SERCOM3_GCLK_ID_CORE].reg & GCLK_PCHCTRL_CHEN)); + + SERCOM3->USART.CTRLA.reg = + SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE(1/*USART_INT_CLK*/) | + SERCOM_USART_CTRLA_RXPO(1/*PAD1*/) | SERCOM_USART_CTRLA_TXPO(0/*PAD0*/); + + SERCOM3->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN | + SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/); + + SERCOM3->USART.BAUD.reg = (uint16_t)br; + + SERCOM3->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; +} + +void watch_debug_putc(char c) { + while (!(SERCOM3->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)); + SERCOM3->USART.DATA.reg = c; +} + +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wdeprecated-declarations" +void watch_debug_puts(char *s) { + while (*s) watch_debug_putc(*s++); +} +#pragma GCC diagnostic pop diff --git a/watch-library/hpl/core/hpl_core_m0plus_base.c b/watch-library/hpl/core/hpl_core_m0plus_base.c deleted file mode 100644 index cad2a662..00000000 --- a/watch-library/hpl/core/hpl_core_m0plus_base.c +++ /dev/null @@ -1,202 +0,0 @@ -/** - * \file - * - * \brief Core related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include -#include -#ifndef _UNIT_TEST_ -#include -#endif -#include -#include - -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 1000000 -#endif - -#if CONF_CPU_FREQUENCY < 1000 -#define CPU_FREQ_POWER 3 -#elif CONF_CPU_FREQUENCY < 10000 -#define CPU_FREQ_POWER 4 -#elif CONF_CPU_FREQUENCY < 100000 -#define CPU_FREQ_POWER 5 -#elif CONF_CPU_FREQUENCY < 1000000 -#define CPU_FREQ_POWER 6 -#elif CONF_CPU_FREQUENCY < 10000000 -#define CPU_FREQ_POWER 7 -#elif CONF_CPU_FREQUENCY < 100000000 -#define CPU_FREQ_POWER 8 -#endif - -/** - * \brief The array of interrupt handlers - */ -struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; - -/** - * \brief Reset MCU - */ -void _reset_mcu(void) -{ - NVIC_SystemReset(); -} - -/** - * \brief Put MCU to sleep - */ -void _go_to_sleep(void) -{ - __DSB(); - __WFI(); -} - -/** - * \brief Retrieve current IRQ number - */ -uint8_t _irq_get_current(void) -{ - return (uint8_t)__get_IPSR() - 16; -} - -/** - * \brief Disable the given IRQ - */ -void _irq_disable(uint8_t n) -{ - NVIC_DisableIRQ((IRQn_Type)n); -} - -/** - * \brief Set the given IRQ - */ -void _irq_set(uint8_t n) -{ - NVIC_SetPendingIRQ((IRQn_Type)n); -} - -/** - * \brief Clear the given IRQ - */ -void _irq_clear(uint8_t n) -{ - NVIC_ClearPendingIRQ((IRQn_Type)n); -} - -/** - * \brief Enable the given IRQ - */ -void _irq_enable(uint8_t n) -{ - NVIC_EnableIRQ((IRQn_Type)n); -} - -/** - * \brief Register IRQ handler - */ -void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) -{ - ASSERT(n < PERIPH_COUNT_IRQn); - - _irq_table[n] = irq; -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Default_Handler(void) -{ - while (1) { - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - */ -static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) -{ - switch (power) { - case 8: - return (us * (freq / 100000) - 1) / 10 + 1; - case 7: - return (us * (freq / 10000) - 1) / 100 + 1; - case 6: - return (us * (freq / 1000) - 1) / 1000 + 1; - case 5: - return (us * (freq / 100) - 1) / 10000 + 1; - case 4: - return (us * (freq / 10) - 1) / 100000 + 1; - default: - return (us * freq - 1) / 1000000 + 1; - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - */ -uint32_t _get_cycles_for_us(const uint16_t us) -{ - int32_t freq = hri_usbdevice_get_CTRLA_ENABLE_bit(USB) ? 8000000 : 4000000; - return _get_cycles_for_us_internal(us, freq, CPU_FREQ_POWER); -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - */ -static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) -{ - switch (power) { - case 8: - return (ms * (freq / 100000)) * 100; - case 7: - return (ms * (freq / 10000)) * 10; - case 6: - return (ms * (freq / 1000)); - case 5: - return (ms * (freq / 100) - 1) / 10 + 1; - case 4: - return (ms * (freq / 10) - 1) / 100 + 1; - default: - return (ms * freq - 1) / 1000 + 1; - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - */ -uint32_t _get_cycles_for_ms(const uint16_t ms) -{ - int32_t freq = hri_usbdevice_get_CTRLA_ENABLE_bit(USB) ? 8000000 : 4000000; - return _get_cycles_for_ms_internal(ms, freq, CPU_FREQ_POWER); -} diff --git a/watch-library/hpl/core/hpl_core_port.h b/watch-library/hpl/core/hpl_core_port.h deleted file mode 100644 index 33c18dd0..00000000 --- a/watch-library/hpl/core/hpl_core_port.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * \file - * - * \brief Core related functionality implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_CORE_PORT_H_INCLUDED -#define _HPL_CORE_PORT_H_INCLUDED - -#include - -/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR - * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), - * there will be assembling errors. - * So the following things are not included for assembling. - */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) - -#ifndef _UNIT_TEST_ -#include -#endif - -/** - * \brief Check if it's in ISR handling - * \return \c true if it's in ISR - */ -static inline bool _is_in_isr(void) -{ - return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); -} - -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -void Default_Handler(void); - -#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/watch-library/hpl/core/hpl_init.c b/watch-library/hpl/core/hpl_init.c deleted file mode 100644 index 900cf420..00000000 --- a/watch-library/hpl/core/hpl_init.c +++ /dev/null @@ -1,74 +0,0 @@ -/** - * \file - * - * \brief HPL initialization related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -#include -#include - -/* Referenced GCLKs (out of 0~4), should be initialized firstly - */ -#define _GCLK_INIT_1ST 0x00000000 -/* Not referenced GCLKs, initialized last */ -#define _GCLK_INIT_LAST 0x0000001F - -/** - * \brief Initialize the hardware abstraction layer - */ -void _init_chip(void) -{ - hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); - - _set_performance_level(2); - - _osc32kctrl_init_sources(); - _oscctrl_init_sources(); - _mclk_init(); -#if _GCLK_INIT_1ST - _gclk_init_generators_by_fref(_GCLK_INIT_1ST); -#endif - _oscctrl_init_referenced_generators(); - _gclk_init_generators_by_fref(_GCLK_INIT_LAST); - -#if CONF_DMAC_ENABLE - hri_mclk_set_AHBMASK_DMAC_bit(MCLK); - _dma_init(); -#endif - -#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) - _port_event_init(); -#endif -} diff --git a/watch-library/hpl/dmac/hpl_dmac.c b/watch-library/hpl/dmac/hpl_dmac.c deleted file mode 100644 index c12e0254..00000000 --- a/watch-library/hpl/dmac/hpl_dmac.c +++ /dev/null @@ -1,244 +0,0 @@ - -/** - * \file - * - * \brief Generic DMAC related functionality. - * - * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include -#include - -#if CONF_DMAC_ENABLE - -/* Section containing first descriptors for all DMAC channels */ -COMPILER_ALIGNED(16) -DmacDescriptor _descriptor_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; - -/* Section containing current descriptors for all DMAC channels */ -COMPILER_ALIGNED(16) -DmacDescriptor _write_back_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; - -/* Array containing callbacks for DMAC channels */ -static struct _dma_resource _resources[DMAC_CH_NUM]; - -/* This macro DMAC configuration */ -#define DMAC_CHANNEL_CFG(i, n) \ - {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | (CONF_DMAC_ENABLE_##n << DMAC_CHCTRLA_ENABLE_Pos), \ - DMAC_CHCTRLB_TRIGACT(CONF_DMAC_TRIGACT_##n) | DMAC_CHCTRLB_TRIGSRC(CONF_DMAC_TRIGSRC_##n) \ - | DMAC_CHCTRLB_LVL(CONF_DMAC_LVL_##n) | (CONF_DMAC_EVOE_##n << DMAC_CHCTRLB_EVOE_Pos) \ - | (CONF_DMAC_EVIE_##n << DMAC_CHCTRLB_EVIE_Pos) | DMAC_CHCTRLB_EVACT(CONF_DMAC_EVACT_##n), \ - DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ - | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ - | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ - | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, - -/* DMAC channel configuration */ -struct dmac_channel_cfg { - uint8_t ctrla; - uint32_t ctrlb; - uint16_t btctrl; -}; - -/* DMAC channel configurations */ -const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; - -/** - * \brief Initialize DMAC - */ -int32_t _dma_init(void) -{ - uint8_t i = 0; - - hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); - hri_dmac_clear_CTRL_CRCENABLE_bit(DMAC); - hri_dmac_set_CHCTRLA_SWRST_bit(DMAC); - - hri_dmac_write_CTRL_reg(DMAC, - (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) - | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) - | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); - hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); - - hri_dmac_write_QOSCTRL_reg(DMAC, - DMAC_QOSCTRL_WRBQOS(CONF_DMAC_WRBQOS) | DMAC_QOSCTRL_FQOS(CONF_DMAC_FQOS) - | DMAC_QOSCTRL_DQOS(CONF_DMAC_DQOS)); - - hri_dmac_write_PRICTRL0_reg( - DMAC, - DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) - | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) - | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) - | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); - hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); - hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); - - for (; i < DMAC_CH_NUM; i++) { - hri_dmac_write_CHID_reg(DMAC, i); - - hri_dmac_write_CHCTRLA_RUNSTDBY_bit(DMAC, _cfgs[i].ctrla & DMAC_CHCTRLA_RUNSTDBY); - - hri_dmac_write_CHCTRLB_reg(DMAC, _cfgs[i].ctrlb); - hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); - hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); - } - - NVIC_DisableIRQ(DMAC_IRQn); - NVIC_ClearPendingIRQ(DMAC_IRQn); - NVIC_EnableIRQ(DMAC_IRQn); - - hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); - - return ERR_NONE; -} - -/** - * \brief Enable/disable DMA interrupt - */ -void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) -{ - hri_dmac_write_CHID_reg(DMAC, channel); - - if (DMA_TRANSFER_COMPLETE_CB == type) { - hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, state); - } else if (DMA_TRANSFER_ERROR_CB == type) { - hri_dmac_write_CHINTEN_TERR_bit(DMAC, state); - } -} - -int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) -{ - hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); - - return ERR_NONE; -} - -int32_t _dma_set_source_address(const uint8_t channel, const void *const src) -{ - hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); - - return ERR_NONE; -} - -int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) -{ - hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], - (uint32_t)&_descriptor_section[next_channel]); - - return ERR_NONE; -} - -int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) -{ - hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); - - return ERR_NONE; -} - -int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) -{ - uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); - uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); - - if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { - hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); - } - - address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); - - if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { - hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); - } - - hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); - - return ERR_NONE; -} - -int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) -{ - hri_dmac_write_CHID_reg(DMAC, channel); - hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); - hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC); - if (software_trigger) { - hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); - } - - return ERR_NONE; -} - -int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) -{ - *resource = &_resources[channel]; - - return ERR_NONE; -} - -int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) -{ - hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); - - return ERR_NONE; -} - -/** - * \internal DMAC interrupt handler - */ -static inline void _dmac_handler(void) -{ - uint8_t channel = hri_dmac_read_INTPEND_ID_bf(DMAC); - uint8_t current_channel = hri_dmac_read_CHID_reg(DMAC); - uint8_t flag_status; - struct _dma_resource *tmp_resource = &_resources[channel]; - - hri_dmac_write_CHID_reg(DMAC, channel); - flag_status = hri_dmac_get_CHINTFLAG_reg(DMAC, DMAC_CHINTFLAG_MASK); - - if (flag_status & DMAC_CHINTFLAG_TERR) { - hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC); - tmp_resource->dma_cb.error(tmp_resource); - } else if (flag_status & DMAC_CHINTFLAG_TCMPL) { - hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC); - tmp_resource->dma_cb.transfer_done(tmp_resource); - } - hri_dmac_write_CHID_reg(DMAC, current_channel); -} - -/** - * \brief DMAC interrupt handler - */ -void DMAC_Handler(void) -{ - _dmac_handler(); -} - -#endif /* CONF_DMAC_ENABLE */ diff --git a/watch-library/hpl/eic/hpl_eic.c b/watch-library/hpl/eic/hpl_eic.c deleted file mode 100644 index 2bd31615..00000000 --- a/watch-library/hpl/eic/hpl_eic.c +++ /dev/null @@ -1,255 +0,0 @@ - -/** - * \file - * - * \brief EIC related functionality implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include -#include - -#ifdef __MINGW32__ -#define ffs __builtin_ffs -#endif -#if defined(__CC_ARM) || defined(__ICCARM__) -/* Find the first bit set */ -static int ffs(int v) -{ - int i, bit = 1; - for (i = 0; i < sizeof(int) * 8; i++) { - if (v & bit) { - return i + 1; - } - bit <<= 1; - } - return 0; -} -#endif - -/** - * \brief Invalid external interrupt and pin numbers - */ -#define INVALID_EXTINT_NUMBER 0xFF -#define INVALID_PIN_NUMBER 0xFFFFFFFF - -#ifndef CONFIG_EIC_EXTINT_MAP -/** Dummy mapping to pass compiling. */ -#define CONFIG_EIC_EXTINT_MAP \ - { \ - INVALID_EXTINT_NUMBER, INVALID_PIN_NUMBER \ - } -#endif - -#define EXT_IRQ_AMOUNT 6 - -/** - * \brief EXTINTx and pin number map - */ -struct _eic_map { - uint8_t extint; - uint32_t pin; -}; - -/** - * \brief PIN and EXTINT map for enabled external interrupts - */ -static const struct _eic_map _map[] = {CONFIG_EIC_EXTINT_MAP}; - -/** - * \brief The callback to upper layer's interrupt processing routine - */ -static void (*callback)(const uint32_t pin); - -static void _ext_irq_handler(void); - -/** - * \brief Initialize external interrupt module - */ -int32_t _ext_irq_init(void (*cb)(const uint32_t pin)) -{ - if (!hri_eic_is_syncing(EIC, EIC_SYNCBUSY_SWRST)) { - if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) { - hri_eic_clear_CTRLA_ENABLE_bit(EIC); - hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE); - } - hri_eic_write_CTRLA_reg(EIC, EIC_CTRLA_SWRST); - } - hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST); - - hri_eic_write_CTRLA_CKSEL_bit(EIC, CONF_EIC_CKSEL); - - hri_eic_write_NMICTRL_reg(EIC, - (CONF_EIC_NMIFILTEN << EIC_NMICTRL_NMIFILTEN_Pos) - | EIC_NMICTRL_NMISENSE(CONF_EIC_NMISENSE) | EIC_ASYNCH_ASYNCH(CONF_EIC_NMIASYNCH) - | 0); - - hri_eic_write_EVCTRL_reg(EIC, - (CONF_EIC_EXTINTEO0 << 0) | (CONF_EIC_EXTINTEO1 << 1) | (CONF_EIC_EXTINTEO2 << 2) - | (CONF_EIC_EXTINTEO3 << 3) | (CONF_EIC_EXTINTEO4 << 4) | (CONF_EIC_EXTINTEO5 << 5) - | (CONF_EIC_EXTINTEO6 << 6) | (CONF_EIC_EXTINTEO7 << 7) | (CONF_EIC_EXTINTEO8 << 8) - | (CONF_EIC_EXTINTEO9 << 9) | (CONF_EIC_EXTINTEO10 << 10) | (CONF_EIC_EXTINTEO11 << 11) - | (CONF_EIC_EXTINTEO12 << 12) | (CONF_EIC_EXTINTEO13 << 13) - | (CONF_EIC_EXTINTEO14 << 14) | (CONF_EIC_EXTINTEO15 << 15) | 0); - hri_eic_write_ASYNCH_reg(EIC, - (CONF_EIC_ASYNCH0 << 0) | (CONF_EIC_ASYNCH1 << 1) | (CONF_EIC_ASYNCH2 << 2) - | (CONF_EIC_ASYNCH3 << 3) | (CONF_EIC_ASYNCH4 << 4) | (CONF_EIC_ASYNCH5 << 5) - | (CONF_EIC_ASYNCH6 << 6) | (CONF_EIC_ASYNCH7 << 7) | (CONF_EIC_ASYNCH8 << 8) - | (CONF_EIC_ASYNCH9 << 9) | (CONF_EIC_ASYNCH10 << 10) | (CONF_EIC_ASYNCH11 << 11) - | (CONF_EIC_ASYNCH12 << 12) | (CONF_EIC_ASYNCH13 << 13) | (CONF_EIC_ASYNCH14 << 14) - | (CONF_EIC_ASYNCH15 << 15) | 0); - - hri_eic_write_CONFIG_reg(EIC, - 0, - (CONF_EIC_FILTEN0 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE0) - | (CONF_EIC_FILTEN1 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE1) - | (CONF_EIC_FILTEN2 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE2) - | (CONF_EIC_FILTEN3 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE3) - | (CONF_EIC_FILTEN4 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE4) - | (CONF_EIC_FILTEN5 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE5) - | (CONF_EIC_FILTEN6 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE6) - | (CONF_EIC_FILTEN7 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE7) - | 0); - - hri_eic_write_CONFIG_reg(EIC, - 1, - (CONF_EIC_FILTEN8 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE8) - | (CONF_EIC_FILTEN9 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE9) - | (CONF_EIC_FILTEN10 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE10) - | (CONF_EIC_FILTEN11 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE11) - | (CONF_EIC_FILTEN12 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE12) - | (CONF_EIC_FILTEN13 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE13) - | (CONF_EIC_FILTEN14 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE14) - | (CONF_EIC_FILTEN15 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE15) - | 0); - - hri_eic_set_CTRLA_ENABLE_bit(EIC); - NVIC_DisableIRQ(EIC_IRQn); - NVIC_ClearPendingIRQ(EIC_IRQn); - NVIC_EnableIRQ(EIC_IRQn); - - callback = cb; - - return ERR_NONE; -} - -/** - * \brief De-initialize external interrupt module - */ -int32_t _ext_irq_deinit(void) -{ - NVIC_DisableIRQ(EIC_IRQn); - callback = NULL; - - hri_eic_clear_CTRLA_ENABLE_bit(EIC); - hri_eic_set_CTRLA_SWRST_bit(EIC); - - return ERR_NONE; -} - -/** - * \brief Enable / disable external irq - */ -int32_t _ext_irq_enable(const uint32_t pin, const bool enable) -{ - uint8_t extint = INVALID_EXTINT_NUMBER; - uint8_t i = 0; - - for (; i < ARRAY_SIZE(_map); i++) { - if (_map[i].pin == pin) { - extint = _map[i].extint; - break; - } - } - if (INVALID_EXTINT_NUMBER == extint) { - return -1; - } - - if (enable) { - hri_eic_set_INTEN_reg(EIC, 1ul << extint); - } else { - hri_eic_clear_INTEN_reg(EIC, 1ul << extint); - hri_eic_clear_INTFLAG_reg(EIC, 1ul << extint); - } - - return ERR_NONE; -} - -/** - * \brief Inter EIC interrupt handler - */ -static void _ext_irq_handler(void) -{ - volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC); - int8_t pos; - uint32_t pin = INVALID_PIN_NUMBER; - - hri_eic_clear_INTFLAG_reg(EIC, flags); - - ASSERT(callback); - - while (flags) { - pos = ffs(flags) - 1; - while (-1 != pos) { - uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; - - while (upper >= lower) { - middle = (upper + lower) >> 1; - if (_map[middle].extint == pos) { - pin = _map[middle].pin; - break; - } - if (_map[middle].extint < pos) { - lower = middle + 1; - } else { - upper = middle - 1; - } - } - - if (INVALID_PIN_NUMBER != pin) { - callback(pin); - } - flags &= ~(1ul << pos); - pos = ffs(flags) - 1; - } - flags = hri_eic_read_INTFLAG_reg(EIC); - hri_eic_clear_INTFLAG_reg(EIC, flags); - } -} - -/** - * \brief EIC interrupt handler - */ -void EIC_Handler(void) -{ - _ext_irq_handler(); -} diff --git a/watch-library/hpl/gclk/hpl_gclk.c b/watch-library/hpl/gclk/hpl_gclk.c deleted file mode 100644 index be66ef77..00000000 --- a/watch-library/hpl/gclk/hpl_gclk.c +++ /dev/null @@ -1,164 +0,0 @@ - -/** - * \file - * - * \brief Generic Clock Controller related functionality. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -/* Compatible naming definition */ -#ifndef GCLK_GENCTRL_SRC_DPLL -#define GCLK_GENCTRL_SRC_DPLL GCLK_GENCTRL_SRC_FDPLL -#endif - -/** - * \brief Initializes generators - */ -void _gclk_init_generators(void) -{ - -#if CONF_GCLK_GENERATOR_0_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 0, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_1_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 1, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_2_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 2, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_3_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 3, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_4_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 4, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); -#endif -} - -void _gclk_init_generators_by_fref(uint32_t bm) -{ - -#if CONF_GCLK_GENERATOR_0_CONFIG == 1 - if (bm & (1ul << 0)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 0, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_1_CONFIG == 1 - if (bm & (1ul << 1)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 1, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_2_CONFIG == 1 - if (bm & (1ul << 2)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 2, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_3_CONFIG == 1 - if (bm & (1ul << 3)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 3, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_4_CONFIG == 1 - if (bm & (1ul << 4)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 4, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); - } -#endif -} diff --git a/watch-library/hpl/gclk/hpl_gclk_base.h b/watch-library/hpl/gclk/hpl_gclk_base.h deleted file mode 100644 index 3e7d2825..00000000 --- a/watch-library/hpl/gclk/hpl_gclk_base.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * \brief Generic Clock Controller. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_GCLK_H_INCLUDED -#define _HPL_GCLK_H_INCLUDED - -#include -#ifdef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup gclk_group GCLK Hardware Proxy Layer - * - * \section gclk_hpl_rev Revision History - * - v0.0.0.1 Initial Commit - * - *@{ - */ - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Enable clock on the given channel with the given clock source - * - * This function maps the given clock source to the given clock channel - * and enables channel. - * - * \param[in] channel The channel to enable clock for - * \param[in] source The clock source for the given channel - */ -static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) -{ - - hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); -} - -/** - * \brief Initialize GCLK generators by function references - * \param[in] bm Bit mapping for referenced generators, - * a bit 1 in position triggers generator initialization. - */ -void _gclk_init_generators_by_fref(uint32_t bm); - -//@} -/**@}*/ -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/watch-library/hpl/mclk/hpl_mclk.c b/watch-library/hpl/mclk/hpl_mclk.c deleted file mode 100644 index 46e7c853..00000000 --- a/watch-library/hpl/mclk/hpl_mclk.c +++ /dev/null @@ -1,46 +0,0 @@ -/** - * \file - * - * \brief SAM Main Clock. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Initialize master clock generator - */ -void _mclk_init(void) -{ - void *hw = (void *)MCLK; - hri_mclk_write_BUPDIV_reg(hw, MCLK_BUPDIV_BUPDIV(CONF_MCLK_BUPDIV)); - hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_CPUDIV(CONF_MCLK_CPUDIV)); -} diff --git a/watch-library/hpl/nvmctrl/hpl_nvmctrl.c b/watch-library/hpl/nvmctrl/hpl_nvmctrl.c deleted file mode 100755 index c1d42c5e..00000000 --- a/watch-library/hpl/nvmctrl/hpl_nvmctrl.c +++ /dev/null @@ -1,782 +0,0 @@ - -/** - * \file - * - * \brief Non-Volatile Memory Controller - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include -#include -#include - -#define NVM_MEMORY ((volatile uint16_t *)FLASH_ADDR) - -/** - * \brief NVM configuration type - */ -struct nvm_configuration { - hri_nvmctrl_ctrlb_reg_t ctrlb; /*!< Control B Register */ -}; - -/** - * \brief Array of NVM configurations - */ -static struct nvm_configuration _nvm - = {(CONF_NVM_CACHE << NVMCTRL_CTRLB_CACHEDIS_Pos) | (CONF_NVM_READ_MODE << NVMCTRL_CTRLB_READMODE_Pos) - | (CONF_NVM_SLEEPPRM << NVMCTRL_CTRLB_SLEEPPRM_Pos)}; - -/*!< Pointer to hpl device */ -static struct _flash_device *_nvm_dev = NULL; - -static void _flash_erase_row(void *const hw, const uint32_t dst_addr, uint32_t nvmctrl_cmd); -static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size, - uint32_t nvmctrl_cmd); - -/** - * \brief Initialize NVM - */ -int32_t _flash_init(struct _flash_device *const device, void *const hw) -{ - ASSERT(device && (hw == NVMCTRL)); - uint32_t ctrlb; - - device->hw = hw; - ctrlb = _nvm.ctrlb & ~(NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW); - ctrlb |= hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW); - hri_nvmctrl_write_CTRLB_reg(device->hw, ctrlb); - - _nvm_dev = device; - NVIC_DisableIRQ(NVMCTRL_IRQn); - NVIC_ClearPendingIRQ(NVMCTRL_IRQn); - NVIC_EnableIRQ(NVMCTRL_IRQn); - return ERR_NONE; -} - -/** - * \brief De-initialize NVM - */ -void _flash_deinit(struct _flash_device *const device) -{ - device->hw = NULL; - NVIC_DisableIRQ(NVMCTRL_IRQn); -} - -/** - * \brief Get the flash page size. - */ -uint32_t _flash_get_page_size(struct _flash_device *const device) -{ - (void)device; - return (uint32_t)NVMCTRL_PAGE_SIZE; -} - -/** - * \brief Get the numbers of flash page. - */ -uint32_t _flash_get_total_pages(struct _flash_device *const device) -{ - (void)device; - return (uint32_t)FLASH_NB_OF_PAGES; -} - -/** - * \brief Get the number of wait states for read and write operations. - */ -uint8_t _flash_get_wait_state(struct _flash_device *const device) -{ - return hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk); -} - -/** - * \brief Set the number of wait states for read and write operations. - */ -void _flash_set_wait_state(struct _flash_device *const device, uint8_t state) -{ - hri_nvmctrl_write_CTRLB_RWS_bf(device->hw, state); -} - -/** - * \brief Reads a number of bytes to a page in the internal Flash. - */ -void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length) -{ - uint32_t nvm_address = src_addr / 2; - uint32_t i; - uint16_t data; - - /* Check if the module is busy */ - while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { - /* Wait until this module isn't busy */ - } - - /* Clear flags */ - hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); - - /* Check whether byte address is word-aligned*/ - if (src_addr % 2) { - data = NVM_MEMORY[nvm_address++]; - buffer[0] = data >> 8; - i = 1; - } else { - i = 0; - } - - /* NVM _must_ be accessed as a series of 16-bit words, perform manual copy - * to ensure alignment */ - while (i < length) { - data = NVM_MEMORY[nvm_address++]; - buffer[i] = (data & 0xFF); - if (i < (length - 1)) { - buffer[i + 1] = (data >> 8); - } - i += 2; - } -} - -/** - * \brief Writes a number of bytes to a page in the internal Flash. - */ -void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) -{ - uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE]; - uint32_t row_start_addr, row_end_addr; - uint32_t i, j, k; - uint32_t wr_start_addr = dst_addr; - - do { - row_start_addr = wr_start_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); - row_end_addr = row_start_addr + NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE - 1; - - /* store the erase data into temp buffer before write */ - for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { - _flash_read(device, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); - } - - /* temp buffer update */ - j = (wr_start_addr - row_start_addr) / NVMCTRL_PAGE_SIZE; - k = wr_start_addr - row_start_addr - j * NVMCTRL_PAGE_SIZE; - while ((wr_start_addr <= row_end_addr) && (length > 0)) { - tmp_buffer[j][k] = *buffer; - k = (k + 1) % NVMCTRL_PAGE_SIZE; - if (0 == k) { - j++; - } - wr_start_addr++; - buffer++; - length--; - } - - /* erase row before write */ - _flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_ER); - - /* write buffer to flash */ - for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { - _flash_program(device->hw, - row_start_addr + i * NVMCTRL_PAGE_SIZE, - tmp_buffer[i], - NVMCTRL_PAGE_SIZE, - NVMCTRL_CTRLA_CMD_WP); - } - - } while (row_end_addr < (wr_start_addr + length - 1)); -} - -/** - * \brief Appends a number of bytes in the internal Flash. - */ -void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) -{ - uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1); - uint32_t size; - uint32_t offset = 0; - - if (dst_addr != page_start_addr) { - /* Need to write some data to the end of a page */ - size = min(length, NVMCTRL_PAGE_SIZE - (dst_addr - page_start_addr)); - _flash_program(device->hw, dst_addr, buffer, size, NVMCTRL_CTRLA_CMD_WP); - page_start_addr += NVMCTRL_PAGE_SIZE; - offset += size; - } - - while (offset < length) { - size = min(length - offset, NVMCTRL_PAGE_SIZE); - _flash_program(device->hw, page_start_addr, buffer + offset, size, NVMCTRL_CTRLA_CMD_WP); - page_start_addr += NVMCTRL_PAGE_SIZE; - offset += size; - } -} - -/** - * \brief Execute erase in the internal flash - */ -void _flash_erase(struct _flash_device *const device, uint32_t dst_addr, uint32_t page_nums) -{ - uint8_t tmp_buffer[NVMCTRL_PAGE_SIZE]; - uint32_t row_start_addr; - uint32_t i; - - row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); - - memset(tmp_buffer, 0xFF, NVMCTRL_PAGE_SIZE); - - /* when address is not aligned with row start address */ - if (dst_addr != row_start_addr) { - row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE; - for (i = 0; i < NVMCTRL_ROW_PAGES - 1; i++) { - _flash_write(device, dst_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); - if (--page_nums == 0) { - return; - } - dst_addr += NVMCTRL_PAGE_SIZE; - if (dst_addr == row_start_addr) { - break; - } - } - } - - while (page_nums >= NVMCTRL_ROW_PAGES) { - _flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_ER); - row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE; - page_nums -= NVMCTRL_ROW_PAGES; - } - - if (page_nums != 0) { - for (i = 0; i < page_nums; i++) { - _flash_write(device, row_start_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); - row_start_addr += NVMCTRL_PAGE_SIZE; - } - } -} - -/** - * \brief Execute lock in the internal flash - */ -int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) -{ - uint32_t region_pages; - uint32_t row_start_addr; - - region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); - row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); - - if ((page_nums != region_pages) || (dst_addr != row_start_addr)) { - return ERR_INVALID_ARG; - } - - while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { - /* Wait until this module isn't busy */ - } - - /* Clear flags */ - hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); - - hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2); - hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_LR | NVMCTRL_CTRLA_CMDEX_KEY); - - return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); -} - -/** - * \brief Execute unlock in the internal flash - */ -int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) -{ - uint32_t region_pages; - uint32_t row_start_addr; - - region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); - row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); - - if ((page_nums != region_pages) || (dst_addr != row_start_addr)) { - return ERR_INVALID_ARG; - } - - while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { - /* Wait until this module isn't busy */ - } - - /* Clear flags */ - hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); - - hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2); - hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_UR | NVMCTRL_CTRLA_CMDEX_KEY); - - return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); -} - -/** - * \brief check whether the region which is pointed by address - */ -bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr) -{ - uint16_t region_id; - - /* Get region for given page */ - region_id = dst_addr / (NVMCTRL_FLASH_SIZE / 16); - - return !(hri_nvmctrl_get_LOCK_reg(device->hw, 1 << region_id)); -} - -/** - * \brief Enable/disable Flash interrupt - */ -void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state) -{ - ASSERT(device); - - if (FLASH_DEVICE_CB_READY == type) { - hri_nvmctrl_write_INTEN_READY_bit(device->hw, state); - } else if (FLASH_DEVICE_CB_ERROR == type) { - hri_nvmctrl_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \internal erase a row in flash - * \param[in] hw The pointer to hardware instance - * \param[in] dst_addr Destination page address to erase - */ -static void _flash_erase_row(void *const hw, const uint32_t dst_addr, uint32_t nvmctrl_cmd) -{ - while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - /* Clear flags */ - hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); - - /* Set address and command */ - hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2); - hri_nvmctrl_write_CTRLA_reg(hw, nvmctrl_cmd | NVMCTRL_CTRLA_CMDEX_KEY); -} - -/** - * \internal write a page in flash - * \param[in] hw The pointer to hardware instance - * \param[in] dst_addr Destination page address to write - * \param[in] buffer Pointer to buffer where the data to - * write is stored - * \param[in] size The size of data to write to a page - */ -static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size, - uint32_t nvmctrl_cmd) -{ - ASSERT(!(dst_addr % 2)); - - uint32_t nvm_address = dst_addr / 2; - uint16_t i, data; - - while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY); - - while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - /* Clear flags */ - hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); - - for (i = 0; i < size; i += 2) { - data = buffer[i]; - if (i < NVMCTRL_PAGE_SIZE - 1) { - data |= (buffer[i + 1] << 8); - } - NVM_MEMORY[nvm_address++] = data; - } - - while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2); - hri_nvmctrl_write_CTRLA_reg(hw, nvmctrl_cmd | NVMCTRL_CTRLA_CMDEX_KEY); -} - -/** - * \internal NVM interrupt handler - */ -void NVMCTRL_Handler(void) -{ - void *const hw = _nvm_dev->hw; - - if (hri_nvmctrl_get_interrupt_READY_bit(hw)) { - if (NULL != _nvm_dev->flash_cb.ready_cb) { - _nvm_dev->flash_cb.ready_cb(_nvm_dev); - } - } else if (hri_nvmctrl_get_interrupt_ERROR_bit(hw)) { - hri_nvmctrl_clear_interrupt_ERROR_bit(hw); - if (NULL != _nvm_dev->flash_cb.error_cb) { - _nvm_dev->flash_cb.error_cb(_nvm_dev); - } - } -} - -/* -The NVM User Row contains calibration data that are automatically read at device -power on. -The NVM User Row can be read at address 0x804000. -*/ -#ifndef _NVM_USER_ROW_BASE -#define _NVM_USER_ROW_BASE 0x804000 -#endif -#define _NVM_USER_ROW_N_BITS 64 -#define _NVM_USER_ROW_N_BYTES (_NVM_USER_ROW_N_BITS / 8) -#define _NVM_USER_ROW_END (((uint8_t *)_NVM_USER_ROW_BASE) + _NVM_USER_ROW_N_BYTES - 1) -#define _IS_NVM_USER_ROW(b) \ - (((uint8_t *)(b) >= (uint8_t *)(_NVM_USER_ROW_BASE)) && ((uint8_t *)(b) <= (uint8_t *)(_NVM_USER_ROW_END))) -#define _IN_NVM_USER_ROW(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_USER_ROW_END)) - -/* -The NVM Software Calibration Area can be read at address 0x806020. -The NVM Software Calibration Area can not be written. -*/ -#ifndef _NVM_SW_CALIB_AREA_BASE -#define _NVM_SW_CALIB_AREA_BASE 0x806020 -#endif -#define _NVM_SW_CALIB_AREA_N_BITS 128 -#define _NVM_SW_CALIB_AREA_N_BYTES (_NVM_SW_CALIB_AREA_N_BITS / 8) -#define _NVM_SW_CALIB_AREA_END (((uint8_t *)_NVM_SW_CALIB_AREA_BASE) + _NVM_SW_CALIB_AREA_N_BYTES - 1) -#define _IS_NVM_SW_CALIB_AREA(b) \ - (((uint8_t *)(b) >= (uint8_t *)_NVM_SW_CALIB_AREA_BASE) && ((uint8_t *)(b) <= (uint8_t *)_NVM_SW_CALIB_AREA_END)) -#define _IN_NVM_SW_CALIB_AREA(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_SW_CALIB_AREA_END)) - -/** - * \internal Read left aligned data bits - * \param[in] base Base address for the data - * \param[in] bit_offset Offset for the bitfield start - * \param[in] n_bits Number of bits in the bitfield - */ -static inline uint32_t _user_area_read_l32_bits(const volatile uint32_t *base, const uint32_t bit_offset, - const uint8_t n_bits) -{ - return base[bit_offset >> 5] & ((1 << n_bits) - 1); -} - -/** - * \internal Read right aligned data bits - * \param[in] base Base address for the data - * \param[in] bit_offset Offset for the bitfield start - * \param[in] n_bits Number of bits in the bitfield - */ -static inline uint32_t _user_area_read_r32_bits(const volatile uint32_t *base, const uint32_t bit_offset, - const uint8_t n_bits) -{ - return (base[bit_offset >> 5] >> (bit_offset & 0x1F)) & ((1 << n_bits) - 1); -} - -int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, uint32_t size) -{ - ASSERT(buf); - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - if (!_IN_NVM_USER_ROW(base, offset)) { - return ERR_BAD_ADDRESS; - } - /* Cut off if request too many bytes */ - if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { - return ERR_INVALID_ARG; - } - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - if (!_IN_NVM_SW_CALIB_AREA(base, offset)) { - return ERR_BAD_ADDRESS; - } - /* Cut off if request too many bytes */ - if (!_IN_NVM_SW_CALIB_AREA(base, offset + size - 1)) { - return ERR_INVALID_ARG; - } - } else { - return ERR_UNSUPPORTED_OP; - } - - /* Copy data */ - memcpy(buf, ((uint8_t *)base) + offset, size); - return ERR_NONE; -} - -uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits) -{ - volatile uint32_t *mem_base = (volatile uint32_t *)base; - uint32_t l_off, l_bits; - uint32_t r_off, r_bits; - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - ASSERT(_IN_NVM_USER_ROW(base, bit_offset >> 3) && _IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)); - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - ASSERT(_IN_NVM_SW_CALIB_AREA(base, bit_offset >> 3) - && _IN_NVM_SW_CALIB_AREA(base, (bit_offset + n_bits - 1) >> 3)); - } else { - ASSERT(false); - } - - /* Since the bitfield can cross 32-bits boundaries, - * left and right bits are read from 32-bit aligned address - * and then combined together. */ - l_off = bit_offset & (~(32 - 1)); - r_off = l_off + 32; - l_bits = 32 - (bit_offset & (32 - 1)); - if (n_bits > l_bits) { - r_bits = n_bits - l_bits; - } else { - l_bits = n_bits; - r_bits = 0; - } - return _user_area_read_r32_bits(mem_base, bit_offset, l_bits) - + (_user_area_read_l32_bits(mem_base, r_off, r_bits) << l_bits); -} - -/** \internal Write 64-bit user row - * \param[in] _row Pointer to 64-bit user row data. - */ -static int32_t _user_row_write_exec(const uint32_t *_row) -{ - Nvmctrl *hw = NVMCTRL; - uint32_t ctrlb = hri_nvmctrl_read_CTRLB_reg(NVMCTRL); - - /* Denie if Security Bit is set */ - if (hri_nvmctrl_get_STATUS_reg(hw, NVMCTRL_STATUS_SB)) { - return ERR_DENIED; - } - - /* Do Save */ - - /* - Prepare. */ - while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { - /* Wait until this module isn't busy */ - } - hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); - hri_nvmctrl_set_CTRLB_MANW_bit(hw); - - /* - Erase AUX row. */ - hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)(_NVM_USER_ROW_BASE / 2)); - hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_EAR | NVMCTRL_CTRLA_CMDEX_KEY); - while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { - /* Wait until this module isn't busy */ - } - - /* - Page buffer clear & write. */ - hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY); - while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { - /* Wait until this module isn't busy */ - } - *((uint32_t *)NVMCTRL_AUX0_ADDRESS) = _row[0]; - *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1) = _row[1]; - - /* - Write AUX row. */ - hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)(_NVM_USER_ROW_BASE / 2)); - hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_WAP | NVMCTRL_CTRLA_CMDEX_KEY); - while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { - /* Wait until this module isn't busy */ - } - - /* Restore CTRLB */ - hri_nvmctrl_write_CTRLB_reg(NVMCTRL, ctrlb); - - return ERR_NONE; -} - -int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size) -{ - uint32_t _row[2]; /* Copy of user row. */ - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - if (!_IN_NVM_USER_ROW(base, offset)) { - return ERR_BAD_ADDRESS; - } else if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { - return ERR_INVALID_ARG; - } - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - return ERR_DENIED; - } else { - return ERR_UNSUPPORTED_OP; - } - - memcpy(_row, base, 8); /* Store previous data. */ - memcpy((uint8_t *)_row + offset, buf, size); /* Modify with buf data. */ - - return _user_row_write_exec(_row); -} - -int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits) -{ - uint32_t _row[2]; /* Copy of user row. */ - uint32_t l_off, l_bits; - uint32_t r_off, r_bits; - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - if (!_IN_NVM_USER_ROW(base, bit_offset >> 3)) { - return ERR_BAD_ADDRESS; - } else if (!_IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)) { - return ERR_INVALID_ARG; - } - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - return ERR_DENIED; - } else { - return ERR_UNSUPPORTED_OP; - } - - /* Since the bitfield can cross 32-bits boundaries, - * left and right bits are splitted for 32-bit aligned address - * and then saved. */ - l_off = bit_offset & (~(32 - 1)); - r_off = l_off + 32; - l_bits = 32 - (bit_offset & (32 - 1)); - if (n_bits > l_bits) { - r_bits = n_bits - l_bits; - } else { - l_bits = n_bits; - r_bits = 0; - } - - memcpy(_row, base, 8); /* Store previous data. */ - if (l_bits) { - uint32_t l_mask = ((1 << l_bits) - 1) << (bit_offset & (32 - 1)); - _row[bit_offset >> 5] &= ~l_mask; - _row[bit_offset >> 5] |= (bits << (bit_offset & (32 - 1))) & l_mask; - } - if (r_bits) { - uint32_t r_mask = (1 << r_bits) - 1; - _row[r_off >> 5] &= ~r_mask; - _row[r_off >> 5] |= bits >> l_bits; - } - return _user_row_write_exec(_row); -} - -/** - * \brief Return if given address is in Flash RWWEE array range. - */ -static bool _is_valid_rww_flash_address(uint32_t addr) -{ -#define RWWEE_ADDR_START NVMCTRL_RWW_EEPROM_ADDR -#define RWWEE_ADDR_END (NVMCTRL_RWW_EEPROM_ADDR + NVMCTRL_PAGE_SIZE * NVMCTRL_RWWEE_PAGES) - - if ((addr < NVMCTRL_RWW_EEPROM_ADDR) - || (addr > (NVMCTRL_RWW_EEPROM_ADDR + NVMCTRL_PAGE_SIZE * NVMCTRL_RWWEE_PAGES))) { - return false; - } - return true; -} - -/** - * \brief Get the RWWEE flash page size. - */ -uint32_t _rww_flash_get_page_size(struct _flash_device *const device) -{ - (void)device; - return (uint32_t)NVMCTRL_PAGE_SIZE; -} - -/** - * \brief Get the total page numbers of RWWEE flash. - */ -uint32_t _rww_flash_get_total_pages(struct _flash_device *const device) -{ - (void)device; - return (uint32_t)NVMCTRL_RWWEE_PAGES; -} - -/** - * \brief Reads a number of bytes in the internal RWWEE Flash. - */ -int32_t _rww_flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length) -{ - /* Check if the address is valid */ - if (!_is_valid_rww_flash_address(src_addr) || !_is_valid_rww_flash_address(src_addr + length)) { - return ERR_BAD_ADDRESS; - } - - _flash_read(device, src_addr, buffer, length); - - return ERR_NONE; -} - -/** - * \brief Writes a number of bytes in the internal RWWEE Flash. - */ -int32_t _rww_flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) -{ - uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE]; - uint32_t row_start_addr, row_end_addr; - uint32_t i, j, k; - uint32_t wr_start_addr = dst_addr; - - /* Check if the address is valid */ - if (!_is_valid_rww_flash_address(dst_addr) || !_is_valid_rww_flash_address(dst_addr + length)) { - return ERR_BAD_ADDRESS; - } - - do { - row_start_addr = wr_start_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); - row_end_addr = row_start_addr + NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE - 1; - - /* store the erase data into temp buffer before write */ - for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { - _rww_flash_read(device, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); - } - - /* temp buffer update */ - j = (wr_start_addr - row_start_addr) / NVMCTRL_PAGE_SIZE; - k = wr_start_addr - row_start_addr - j * NVMCTRL_PAGE_SIZE; - while ((wr_start_addr <= row_end_addr) && (length > 0)) { - tmp_buffer[j][k] = *buffer; - k = (k + 1) % NVMCTRL_PAGE_SIZE; - if (0 == k) { - j++; - } - wr_start_addr++; - buffer++; - length--; - } - - /* erase row before write */ - _flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_RWWEEER); - - /* write buffer to flash */ - for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { - _flash_program(device->hw, - row_start_addr + i * NVMCTRL_PAGE_SIZE, - tmp_buffer[i], - NVMCTRL_PAGE_SIZE, - NVMCTRL_CTRLA_CMD_RWWEEWP); - } - - } while (row_end_addr < (wr_start_addr + length - 1)); - - return ERR_NONE; -} diff --git a/watch-library/hpl/osc32kctrl/hpl_osc32kctrl.c b/watch-library/hpl/osc32kctrl/hpl_osc32kctrl.c deleted file mode 100644 index b6c624cc..00000000 --- a/watch-library/hpl/osc32kctrl/hpl_osc32kctrl.c +++ /dev/null @@ -1,86 +0,0 @@ -/** - * \file - * - * \brief SAM 32k Oscillators Controller. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include - -/** - * \brief Initialize 32 kHz clock sources - */ -void _osc32kctrl_init_sources(void) -{ - void * hw = (void *)OSC32KCTRL; - uint16_t calib = 0; - -#if CONF_XOSC32K_CONFIG == 1 - hri_osc32kctrl_write_XOSC32K_reg( - hw, - OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) - | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) - | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) - | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) - | (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); - - hri_osc32kctrl_write_CFDCTRL_reg(hw, - (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos) - | (CONF_XOSC32K_SWBEN << OSC32KCTRL_CFDCTRL_SWBACK_Pos)); - - hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); -#endif - -#if CONF_OSCULP32K_CONFIG == 1 - calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); - hri_osc32kctrl_write_OSCULP32K_reg(hw, -#if CONF_OSC32K_CALIB_ENABLE == 1 - OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB) -#else - OSC32KCTRL_OSCULP32K_CALIB(calib) -#endif - ); -#endif - -#if CONF_XOSC32K_CONFIG -#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 - while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) - ; -#endif -#if CONF_OSCULP32K_ULP32KSW == 1 - hri_osc32kctrl_set_OSCULP32K_reg(hw, OSC32KCTRL_OSCULP32K_ULP32KSW); - while (!hri_osc32kctrl_get_STATUS_ULP32KSW_bit(hw)) - ; -#endif -#endif - - hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); - (void)calib; -} diff --git a/watch-library/hpl/oscctrl/hpl_oscctrl.c b/watch-library/hpl/oscctrl/hpl_oscctrl.c deleted file mode 100644 index e11d70d8..00000000 --- a/watch-library/hpl/oscctrl/hpl_oscctrl.c +++ /dev/null @@ -1,179 +0,0 @@ - -/** - * \file - * - * \brief SAM Oscillators Controller. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include - -/** - * \brief Initialize clock sources - */ -void _oscctrl_init_sources(void) -{ - void *hw = (void *)OSCCTRL; - -#if CONF_XOSC_CONFIG == 1 - hri_oscctrl_write_XOSCCTRL_reg( - hw, - OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC_STARTUP) | (0 << OSCCTRL_XOSCCTRL_AMPGC_Pos) - | OSCCTRL_XOSCCTRL_GAIN(CONF_XOSC_GAIN) | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) - | (CONF_XOSC_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) | (CONF_XOSC_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) - | (CONF_XOSC_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) | (CONF_XOSC_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) - | (CONF_XOSC_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); - - hri_oscctrl_write_EVCTRL_reg(hw, (CONF_XOSC_CFDEO << OSCCTRL_EVCTRL_CFDEO_Pos)); -#endif - -#if CONF_OSC16M_CONFIG == 1 - hri_oscctrl_write_OSC16MCTRL_reg(hw, - (CONF_OSC16M_ONDEMAND << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos) - | (CONF_OSC16M_RUNSTDBY << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos) - | (CONF_OSC16M_ENABLE << OSCCTRL_OSC16MCTRL_ENABLE_Pos) - | OSCCTRL_OSC16MCTRL_FSEL(CONF_OSC16M_FSEL)); -#endif - -#if CONF_XOSC_CONFIG == 1 -#if CONF_XOSC_ENABLE == 1 - while (!hri_oscctrl_get_STATUS_XOSCRDY_bit(hw)) - ; -#endif -#if CONF_XOSC_AMPGC == 1 - hri_oscctrl_set_XOSCCTRL_AMPGC_bit(hw); -#endif -#if CONF_XOSC_ONDEMAND == 1 - hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw); -#endif -#endif - -#if CONF_OSC16M_CONFIG == 1 -#if CONF_OSC16M_ENABLE == 1 - while (!hri_oscctrl_get_STATUS_OSC16MRDY_bit(hw)) - ; -#endif -#if CONF_OSC16M_ONDEMAND == 1 - hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(hw); -#endif -#endif - (void)hw; -} - -void _oscctrl_init_referenced_generators(void) -{ - void * hw = (void *)OSCCTRL; - hri_oscctrl_dfllctrl_reg_t tmp = 0; - -#if CONF_DFLL_CONFIG == 1 -#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 -#define NVM_DFLL_COARSE_POS 26 -#define NVM_DFLL_COARSE_SIZE 6 - uint32_t coarse; - coarse = *((uint32_t *)(NVMCTRL_OTP5)) >> NVM_DFLL_COARSE_POS; -#endif -#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 - hri_gclk_write_PCHCTRL_reg(GCLK, 0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); -#endif - hri_oscctrl_write_DFLLCTRL_reg(hw, OSCCTRL_DFLLCTRL_ENABLE); - while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) - ; - hri_oscctrl_write_DFLLMUL_reg(hw, - OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) - | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); - while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) - ; - -#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 - /* FINE is set to fixed value, which defined by DFLL48M Characteristics */ - hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(coarse) | OSCCTRL_DFLLVAL_FINE(512)); -#else - hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); -#endif - - tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRL_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRL_BPLCKC_Pos) - | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRL_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRL_CCDIS_Pos) - | (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos) | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRL_USBCRM_Pos) - | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRL_LLAW_Pos) | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRL_STABLE_Pos) - | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRL_MODE_Pos) | (CONF_DFLL_ENABLE << OSCCTRL_DFLLCTRL_ENABLE_Pos); - hri_oscctrl_write_DFLLCTRL_reg(hw, tmp); - -#endif - -#if CONF_DPLL_CONFIG == 1 -#if CONF_DPLL_REFCLK == 2 - hri_gclk_write_PCHCTRL_reg(GCLK, 1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DPLL_GCLK)); -#endif - hri_oscctrl_write_DPLLRATIO_reg( - hw, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_DPLL_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_DPLL_LDR)); - hri_oscctrl_write_DPLLCTRLB_reg( - hw, - OSCCTRL_DPLLCTRLB_DIV(CONF_DPLL_DIV) | (CONF_DPLL_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) - | OSCCTRL_DPLLCTRLB_LTIME(CONF_DPLL_LTIME) | OSCCTRL_DPLLCTRLB_REFCLK(CONF_DPLL_REFCLK) - | (CONF_DPLL_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) | (CONF_DPLL_LPEN << OSCCTRL_DPLLCTRLB_LPEN_Pos) - | OSCCTRL_DPLLCTRLB_FILTER(CONF_DPLL_FILTER)); - hri_oscctrl_write_DPLLPRESC_reg(hw, OSCCTRL_DPLLPRESC_PRESC(CONF_DPLL_PRESC)); - hri_oscctrl_write_DPLLCTRLA_reg(hw, - (0 << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) - | (CONF_DPLL_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) - | (CONF_DPLL_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); -#endif - -#if CONF_DFLL_CONFIG == 1 - if (hri_oscctrl_get_DFLLCTRL_MODE_bit(hw)) { - hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; - - while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) - ; - } else { - while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) - ; - } -#if CONF_DFLL_ONDEMAND == 1 - hri_oscctrl_set_DFLLCTRL_ONDEMAND_bit(hw); -#endif -#endif - -#if CONF_DPLL_CONFIG == 1 -#if CONF_DPLL_ENABLE == 1 - while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw))) - ; -#endif -#if CONF_DPLL_ONDEMAND == 1 - hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw); -#endif -#endif - -#if CONF_DFLL_CONFIG == 1 - while (hri_gclk_read_SYNCBUSY_reg(GCLK)) - ; -#endif - (void)hw, (void)tmp; -} diff --git a/watch-library/hpl/pm/hpl_pm.c b/watch-library/hpl/pm/hpl_pm.c deleted file mode 100644 index d6439f1d..00000000 --- a/watch-library/hpl/pm/hpl_pm.c +++ /dev/null @@ -1,77 +0,0 @@ - -/** - * \file - * - * \brief SAM Power manager - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Retrieve the reset reason - */ -enum reset_reason _get_reset_reason(void) -{ - return (enum reset_reason)hri_rstc_read_RCAUSE_reg(RSTC); -} - -/** - * \brief Set the sleep mode for the device - */ -int32_t _set_sleep_mode(const uint8_t mode) -{ - switch (mode) { - case 2: /* IDLE */ - case 4: /* STANDBY */ - case 5: /* BACKUP */ - case 6: /* OFF */ - hri_pm_write_SLEEPCFG_SLEEPMODE_bf(PM, mode); - break; - default: - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Set performance level - */ -void _set_performance_level(const uint8_t level) -{ - if (hri_pm_get_PLCFG_PLSEL_bf(PM, PM_PLCFG_PLSEL_Msk) != level) { - hri_pm_clear_INTFLAG_reg(PM, 0xFF); - hri_pm_write_PLCFG_PLSEL_bf(PM, level); - while (!hri_pm_read_INTFLAG_reg(PM)) - ; - } -} diff --git a/watch-library/hpl/pm/hpl_pm_base.h b/watch-library/hpl/pm/hpl_pm_base.h deleted file mode 100644 index 5a50a914..00000000 --- a/watch-library/hpl/pm/hpl_pm_base.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * \file - * - * \brief SAM Power manager - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - */ - -#ifndef _HPL_PM_BASE_H_INCLUDED -#define _HPL_PM_BASE_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/watch-library/hpl/port/hpl_gpio_base.h b/watch-library/hpl/port/hpl_gpio_base.h deleted file mode 100644 index 3cc1981f..00000000 --- a/watch-library/hpl/port/hpl_gpio_base.h +++ /dev/null @@ -1,170 +0,0 @@ - -/** - * \file - * - * \brief SAM PORT. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include - -/** - * \brief Set direction on port with mask - */ -static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction) -{ - switch (direction) { - case GPIO_DIRECTION_OFF: - hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg( - PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); - break; - - case GPIO_DIRECTION_IN: - hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg(PORT, - port, - PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN - | ((mask & 0xffff0000) >> 16)); - break; - - case GPIO_DIRECTION_OUT: - hri_port_set_DIR_reg(PORT_IOBUS, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg( - PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); - break; - - default: - ASSERT(false); - } -} - -/** - * \brief Set output level on port with mask - */ -static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) -{ - if (level) { - hri_port_set_OUT_reg(PORT_IOBUS, port, mask); - } else { - hri_port_clear_OUT_reg(PORT_IOBUS, port, mask); - } -} - -/** - * \brief Change output level to the opposite with mask - */ -static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) -{ - hri_port_toggle_OUT_reg(PORT_IOBUS, port, mask); -} - -/** - * \brief Get input levels on all port pins - */ -static inline uint32_t _gpio_get_level(const enum gpio_port port) -{ - uint32_t tmp; - - CRITICAL_SECTION_ENTER(); - - uint32_t dir_tmp = hri_port_read_DIR_reg(PORT_IOBUS, port); - - tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; - tmp |= hri_port_read_OUT_reg(PORT_IOBUS, port) & dir_tmp; - - CRITICAL_SECTION_LEAVE(); - - return tmp; -} - -/** - * \brief Set pin pull mode - */ -static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, - const enum gpio_pull_mode pull_mode) -{ - switch (pull_mode) { - case GPIO_PULL_OFF: - hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); - break; - - case GPIO_PULL_UP: - hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); - hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); - hri_port_set_OUT_reg(PORT_IOBUS, port, 1U << pin); - break; - - case GPIO_PULL_DOWN: - hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); - hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); - hri_port_clear_OUT_reg(PORT_IOBUS, port, 1U << pin); - break; - - default: - ASSERT(false); - break; - } -} - -/** - * \brief Set gpio pin function - */ -static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) -{ - uint8_t port = GPIO_PORT(gpio); - uint8_t pin = GPIO_PIN(gpio); - - if (function == GPIO_PIN_FUNCTION_OFF) { - hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); - - } else { - hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); - - if (pin & 1) { - // Odd numbered pin - hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); - } else { - // Even numbered pin - hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); - } - } -} - -static inline void _port_event_init() -{ - hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); - hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); -} diff --git a/watch-library/hpl/sercom/hpl_sercom.c b/watch-library/hpl/sercom/hpl_sercom.c deleted file mode 100644 index f01476dc..00000000 --- a/watch-library/hpl/sercom/hpl_sercom.c +++ /dev/null @@ -1,2932 +0,0 @@ - -/** - * \file - * - * \brief SAM Serial Communication Interface - * - * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONF_SERCOM_0_USART_ENABLE -#define CONF_SERCOM_0_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_USART_ENABLE -#define CONF_SERCOM_1_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_USART_ENABLE -#define CONF_SERCOM_2_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_USART_ENABLE -#define CONF_SERCOM_3_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_USART_ENABLE -#define CONF_SERCOM_4_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_USART_ENABLE -#define CONF_SERCOM_5_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_USART_ENABLE -#define CONF_SERCOM_6_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_USART_ENABLE -#define CONF_SERCOM_7_USART_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as USART. */ -#define SERCOM_USART_AMOUNT \ - (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ - + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ - + CONF_SERCOM_7_USART_ENABLE) - -/** - * \brief Macro is used to fill usart configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define SERCOM_CONFIGURATION(n) \ - { \ - n, \ - SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ - | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ - | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ - | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ - | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ - | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ - | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ - | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ - | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ - | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ - SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ - | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ - | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ - | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ - | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ - | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ - (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ - CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ - } - -/** - * \brief SERCOM USART configuration type - */ -struct usart_configuration { - uint8_t number; - hri_sercomusart_ctrla_reg_t ctrl_a; - hri_sercomusart_ctrlb_reg_t ctrl_b; - hri_sercomusart_baud_reg_t baud; - uint8_t fractional; - hri_sercomusart_rxpl_reg_t rxpl; - hri_sercomusart_dbgctrl_reg_t debug_ctrl; -}; - -#if SERCOM_USART_AMOUNT < 1 -/** Dummy array to pass compiling. */ -static struct usart_configuration _usarts[1] = {{0}}; -#else -/** - * \brief Array of SERCOM USART configurations - */ -static struct usart_configuration _usarts[] = { -#if CONF_SERCOM_0_USART_ENABLE == 1 - SERCOM_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_USART_ENABLE == 1 - SERCOM_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_USART_ENABLE == 1 - SERCOM_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_USART_ENABLE == 1 - SERCOM_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_USART_ENABLE == 1 - SERCOM_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_USART_ENABLE == 1 - SERCOM_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_USART_ENABLE == 1 - SERCOM_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_USART_ENABLE == 1 - SERCOM_CONFIGURATION(7), -#endif -}; -#endif - -static uint8_t _get_sercom_index(const void *const hw); -static uint8_t _sercom_get_irq_num(const void *const hw); -static void _sercom_init_irq_param(const void *const hw, void *dev); -static uint8_t _sercom_get_hardware_index(const void *const hw); - -static int32_t _usart_init(void *const hw); -static inline void _usart_deinit(void *const hw); -static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); -static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); -static void _usart_set_data_order(void *const hw, const enum usart_data_order order); -static void _usart_set_mode(void *const hw, const enum usart_mode mode); -static void _usart_set_parity(void *const hw, const enum usart_parity parity); -static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); -static void _usart_set_character_size(void *const hw, const enum usart_character_size size); - -/** - * \brief Initialize synchronous SERCOM USART - */ -int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) -{ - ASSERT(device); - - device->hw = hw; - - return _usart_init(hw); -} - -/** - * \brief Initialize asynchronous SERCOM USART - */ -int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _usart_init(hw); - if (init_status) { - return init_status; - } - device->hw = hw; - _sercom_init_irq_param(hw, (void *)device); - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - return ERR_NONE; -} - -/** - * \brief De-initialize SERCOM USART - */ -void _usart_sync_deinit(struct _usart_sync_device *const device) -{ - _usart_deinit(device->hw); -} - -/** - * \brief De-initialize SERCOM USART - */ -void _usart_async_deinit(struct _usart_async_device *const device) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); - _usart_deinit(device->hw); -} - -/** - * \brief Calculate baud rate register value - */ -uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); -} - -/** - * \brief Calculate baud rate register value - */ -uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); -} - -/** - * \brief Enable SERCOM module - */ -void _usart_sync_enable(struct _usart_sync_device *const device) -{ - hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Enable SERCOM module - */ -void _usart_async_enable(struct _usart_async_device *const device) -{ - hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable SERCOM module - */ -void _usart_sync_disable(struct _usart_sync_device *const device) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable SERCOM module - */ -void _usart_async_disable(struct _usart_async_device *const device) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Set baud rate - */ -void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) -{ - _usart_set_baud_rate(device->hw, baud_rate); -} - -/** - * \brief Set baud rate - */ -void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) -{ - _usart_set_baud_rate(device->hw, baud_rate); -} - -/** - * \brief Set data order - */ -void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) -{ - _usart_set_data_order(device->hw, order); -} - -/** - * \brief Set data order - */ -void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) -{ - _usart_set_data_order(device->hw, order); -} - -/** - * \brief Set mode - */ -void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) -{ - _usart_set_mode(device->hw, mode); -} - -/** - * \brief Set mode - */ -void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) -{ - _usart_set_mode(device->hw, mode); -} - -/** - * \brief Set parity - */ -void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) -{ - _usart_set_parity(device->hw, parity); -} - -/** - * \brief Set parity - */ -void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) -{ - _usart_set_parity(device->hw, parity); -} - -/** - * \brief Set stop bits mode - */ -void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) -{ - _usart_set_stop_bits(device->hw, stop_bits); -} - -/** - * \brief Set stop bits mode - */ -void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) -{ - _usart_set_stop_bits(device->hw, stop_bits); -} - -/** - * \brief Set character size - */ -void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) -{ - _usart_set_character_size(device->hw, size); -} - -/** - * \brief Set character size - */ -void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) -{ - _usart_set_character_size(device->hw, size); -} - -/** - * \brief Retrieve SERCOM usart status - */ -uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_read_STATUS_reg(device->hw); -} - -/** - * \brief Retrieve SERCOM usart status - */ -uint32_t _usart_async_get_status(const struct _usart_async_device *const device) -{ - return hri_sercomusart_read_STATUS_reg(device->hw); -} - -/** - * \brief Write a byte to the given SERCOM USART instance - */ -void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) -{ - hri_sercomusart_write_DATA_reg(device->hw, data); -} - -/** - * \brief Write a byte to the given SERCOM USART instance - */ -void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) -{ - hri_sercomusart_write_DATA_reg(device->hw, data); -} - -/** - * \brief Read a byte from the given SERCOM USART instance - */ -uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_read_DATA_reg(device->hw); -} - -/** - * \brief Check if USART is ready to send next byte - */ -bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_DRE_bit(device->hw); -} - -/** - * \brief Check if USART transmission complete - */ -bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_TXC_bit(device->hw); -} - -/** - * \brief Check if USART is ready to send next byte - */ -bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) -{ - return hri_sercomusart_get_interrupt_DRE_bit(device->hw); -} - -/** - * \brief Check if there is data received by USART - */ -bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_RXC_bit(device->hw); -} - -/** - * \brief Set the state of flow control pins - */ -void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, - const union usart_flow_control_state state) -{ - (void)device; - (void)state; -} - -/** - * \brief Set the state of flow control pins - */ -void _usart_async_set_flow_control_state(struct _usart_async_device *const device, - const union usart_flow_control_state state) -{ - (void)device; - (void)state; -} - -/** - * \brief Retrieve the state of flow control pins - */ -union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) -{ - (void)device; - union usart_flow_control_state state; - - state.value = 0; - state.bit.unavailable = 1; - return state; -} - -/** - * \brief Retrieve the state of flow control pins - */ -union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) -{ - (void)device; - union usart_flow_control_state state; - - state.value = 0; - state.bit.unavailable = 1; - return state; -} - -/** - * \brief Enable data register empty interrupt - */ -void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) -{ - hri_sercomusart_set_INTEN_DRE_bit(device->hw); -} - -/** - * \brief Enable transmission complete interrupt - */ -void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) -{ - hri_sercomusart_set_INTEN_TXC_bit(device->hw); -} - -/** - * \brief Retrieve ordinal number of the given sercom hardware instance - */ -static uint8_t _sercom_get_hardware_index(const void *const hw) -{ -#ifdef _UNIT_TEST_ - return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom); -#endif - - return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10; -} - -/** - * \brief Retrieve ordinal number of the given SERCOM USART hardware instance - */ -uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) -{ - return _sercom_get_hardware_index(device->hw); -} - -/** - * \brief Retrieve ordinal number of the given SERCOM USART hardware instance - */ -uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) -{ - return _sercom_get_hardware_index(device->hw); -} - -/** - * \brief Enable/disable USART interrupt - */ -void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, - const bool state) -{ - ASSERT(device); - - if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { - hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); - hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); - } else if (USART_ASYNC_RX_DONE == type) { - hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); - } else if (USART_ASYNC_ERROR == type) { - hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - - * \return The ordinal number of the given sercom hardware instance - */ -static uint8_t _get_sercom_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_usarts); i++) { - if (_usarts[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return 0; -} - -/** - * \brief Init irq param with the given sercom hardware instance - */ -static void _sercom_init_irq_param(const void *const hw, void *dev) -{ - (void)hw; - (void)dev; -} - -/** - * \internal Initialize SERCOM USART - * - * \param[in] hw The pointer to hardware instance - * - * \return The status of initialization - */ -static int32_t _usart_init(void *const hw) -{ - uint8_t i = _get_sercom_index(hw); - - if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { - uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; - if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - } - hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); - } - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - - hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); - hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); - if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { - ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; - ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; - } else { - hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); - } - - hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); - hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); - - return ERR_NONE; -} - -/** - * \internal De-initialize SERCOM USART - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _usart_deinit(void *const hw) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - hri_sercomusart_set_CTRLA_SWRST_bit(hw); -} - -/** - * \internal Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate SERCOM clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { - return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; - } - - if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { - return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); - } - - if (USART_BAUDRATE_SYNCH == mode) { - return clock_rate / baud / 2 - 1; - } - - return 0; -} - -/** - * \internal Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_BAUD_reg(hw, baud_rate); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -static void _usart_set_data_order(void *const hw, const enum usart_data_order order) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLA_DORD_bit(hw, order); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -static void _usart_set_mode(void *const hw, const enum usart_mode mode) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -static void _usart_set_parity(void *const hw, const enum usart_parity parity) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - - if (USART_PARITY_NONE != parity) { - hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); - } else { - hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); - } - - hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -static void _usart_set_character_size(void *const hw, const enum usart_character_size size) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); - CRITICAL_SECTION_LEAVE() - - if (enabled) { - hri_sercomusart_set_CTRLA_ENABLE_bit(hw); - } -} - - /* Sercom I2C implementation */ - -#ifndef CONF_SERCOM_0_I2CM_ENABLE -#define CONF_SERCOM_0_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_I2CM_ENABLE -#define CONF_SERCOM_1_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_I2CM_ENABLE -#define CONF_SERCOM_2_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_I2CM_ENABLE -#define CONF_SERCOM_3_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_I2CM_ENABLE -#define CONF_SERCOM_4_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_I2CM_ENABLE -#define CONF_SERCOM_5_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_I2CM_ENABLE -#define CONF_SERCOM_6_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_I2CM_ENABLE -#define CONF_SERCOM_7_I2CM_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as I2C Master. */ -#define SERCOM_I2CM_AMOUNT \ - (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ - + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) - -/** - * \brief Macro is used to fill i2cm configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define I2CM_CONFIGURATION(n) \ - { \ - (n), \ - (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ - | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ - | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ - SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ - CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ - } - -#define ERROR_FLAG (1 << 7) -#define SB_FLAG (1 << 1) -#define MB_FLAG (1 << 0) - -#define CMD_STOP 0x3 -#define I2C_IDLE 0x1 -#define I2C_SM 0x0 -#define I2C_FM 0x1 -#define I2C_HS 0x2 -#define TEN_ADDR_FRAME 0x78 -#define TEN_ADDR_MASK 0x3ff -#define SEVEN_ADDR_MASK 0x7f - -/** - * \brief SERCOM I2CM configuration type - */ -struct i2cm_configuration { - uint8_t number; - hri_sercomi2cm_ctrla_reg_t ctrl_a; - hri_sercomi2cm_ctrlb_reg_t ctrl_b; - hri_sercomi2cm_baud_reg_t baud; - hri_sercomi2cm_dbgctrl_reg_t dbgctrl; - uint16_t trise; - uint32_t clk; /* SERCOM peripheral clock frequency */ -}; - -static inline int32_t _i2c_m_enable_implementation(void *hw); -static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); - -#if SERCOM_I2CM_AMOUNT < 1 -/** Dummy array to pass compiling. */ -static struct i2cm_configuration _i2cms[1] = {{0}}; -#else -/** - * \brief Array of SERCOM I2CM configurations - */ -static struct i2cm_configuration _i2cms[] = { -#if CONF_SERCOM_0_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(7), -#endif -}; -#endif - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - - * \return The ordinal number of the given sercom hardware instance - */ -static int8_t _get_i2cm_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { - if (_i2cms[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return -1; -} - -static inline void _sercom_i2c_send_stop(void *const hw) -{ - hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); -} - -/** - * \brief SERCOM I2CM analyze hardware status and transfer next byte - */ -static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) -{ - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); - - if (flags & MB_FLAG) { - /* tx error */ - if (status & SERCOM_I2CM_STATUS_ARBLOST) { - hri_sercomi2cm_clear_interrupt_MB_bit(hw); - msg->flags |= I2C_M_FAIL; - msg->flags &= ~I2C_M_BUSY; - - if (status & SERCOM_I2CM_STATUS_BUSERR) { - return I2C_ERR_BUS; - } - - return I2C_ERR_BAD_ADDRESS; - } else { - if (status & SERCOM_I2CM_STATUS_RXNACK) { - - /* Slave rejects to receive more data */ - if (msg->len > 0) { - msg->flags |= I2C_M_FAIL; - } - - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - - return I2C_NACK; - } - - if (msg->flags & I2C_M_TEN) { - hri_sercomi2cm_write_ADDR_reg(hw, - ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - msg->flags &= ~I2C_M_TEN; - - return I2C_OK; - } - - if (msg->len == 0) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - } else { - hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); - msg->buffer++; - msg->len--; - } - - return I2C_OK; - } - } else if (flags & SB_FLAG) { - if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { - msg->len--; - - /* last byte, send nack */ - if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } - - if (msg->len == 0) { - if (msg->flags & I2C_M_STOP) { - hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - } - - /* Accessing DATA.DATA auto-triggers I2C bus operations. - * The operation performed depends on the state of - * CTRLB.ACKACT, CTRLB.SMEN - **/ - *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); - } else { - hri_sercomi2cm_clear_interrupt_SB_bit(hw); - return I2C_NACK; - } - - hri_sercomi2cm_clear_interrupt_SB_bit(hw); - } - - return I2C_OK; -} - -/** - * \brief Enable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - return _i2c_m_enable_implementation(i2c_dev->hw); -} - -/** - * \brief Disable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** - * \brief Set baudrate of master - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] clkrate The clock rate of i2c master, in KHz - * \param[in] baudrate The baud rate desired for i2c master, in KHz - */ -int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) -{ - uint32_t tmp; - void * hw = i2c_dev->hw; - - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - - tmp = _get_i2cm_index(hw); - clkrate = _i2cms[tmp].clk / 1000; - - if (i2c_dev->service.mode == I2C_STANDARD_MODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_FASTMODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { - tmp = (clkrate - 2 * baudrate) / (2 * baudrate); - hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); - } else { - /* error baudrate */ - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Retrieve IRQ number for the given hardware instance - */ -static uint8_t _sercom_get_irq_num(const void *const hw) -{ - return SERCOM0_IRQn + _sercom_get_hardware_index(hw); -} - -/** - * \brief Initialize sercom i2c module to use in async mode - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) -{ - int32_t init_status; - - ASSERT(i2c_dev); - - i2c_dev->hw = hw; - - init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); - if (init_status) { - return init_status; - } - - _sercom_init_irq_param(hw, (void *)i2c_dev); - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - return ERR_NONE; -} - -/** - * \brief Deinitialize sercom i2c module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); - hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Transfer the slave address to bus, which will start the transfer - * - * \param[in] i2c_dev The pointer to i2c device - */ -static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) -{ - void * hw = i2c_dev->hw; - struct _i2c_m_msg *msg = &i2c_dev->service.msg; - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - - ASSERT(i2c_dev); - - if (msg->len == 1 && sclsm) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } else { - hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); - } - - /* ten bit address */ - if (msg->addr & I2C_M_TEN) { - if (msg->flags & I2C_M_RD) { - msg->flags |= I2C_M_TEN; - } - - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } else { - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } - - return ERR_NONE; -} - -/** - * \brief Transfer data specified by msg - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] msg The pointer to i2c message - * - * \return Transfer status. - * \retval 0 Transfer success - * \retval <0 Transfer fail, return the error code - */ -int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) -{ - int ret; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - ASSERT(msg); - - if (msg->len == 0) { - return ERR_NONE; - } - - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return ERR_BUSY; - } - - msg->flags |= I2C_M_BUSY; - i2c_dev->service.msg = *msg; - hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); - - ret = _sercom_i2c_send_address(i2c_dev); - - if (ret) { - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Set callback to be called in interrupt handler - * - * \param[in] i2c_dev The pointer to master i2c device - * \param[in] type The callback type - * \param[in] func The callback function pointer - */ -int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, - FUNC_PTR func) -{ - switch (type) { - case I2C_M_ASYNC_DEVICE_ERROR: - i2c_dev->cb.error = (_i2c_error_cb_t)func; - break; - case I2C_M_ASYNC_DEVICE_TX_COMPLETE: - i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; - break; - case I2C_M_ASYNC_DEVICE_RX_COMPLETE: - i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; - break; - default: - /* error */ - break; - } - - return ERR_NONE; -} - -/** - * \brief Set stop condition on I2C - * - * \param i2c_dev Pointer to master i2c device - * - * \return Operation status - * \retval I2C_OK Operation was successfull - */ -int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - _sercom_i2c_send_stop(hw); - - return I2C_OK; -} - -/** - * \brief Get number of bytes left in transfer buffer - * - * \param i2c_dev Pointer to i2c master device - * - * \return Bytes left in buffer - * \retval =>0 Bytes left in buffer - */ -int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) -{ - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return i2c_dev->service.msg.len; - } - - return 0; -} - -/** - * \brief Initialize sercom i2c module to use in sync mode - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) -{ - ASSERT(i2c_dev); - - i2c_dev->hw = hw; - - return _i2c_m_sync_init_impl(&i2c_dev->service, hw); -} - -/** - * \brief Deinitialize sercom i2c module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); - hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Enable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - return _i2c_m_enable_implementation(i2c_dev->hw); -} - -/** - * \brief Disable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** - * \brief Set baudrate of master - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] clkrate The clock rate of i2c master, in KHz - * \param[in] baudrate The baud rate desired for i2c master, in KHz - */ -int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) -{ - uint32_t tmp; - void * hw = i2c_dev->hw; - - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - - tmp = _get_i2cm_index(hw); - clkrate = _i2cms[tmp].clk / 1000; - - if (i2c_dev->service.mode == I2C_STANDARD_MODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_FASTMODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { - tmp = (clkrate - 2 * baudrate) / (2 * baudrate); - hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); - } else { - /* error baudrate */ - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Enable/disable I2C master interrupt - */ -void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, - const bool state) -{ - if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { - hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); - hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); - } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { - hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \brief Wait for bus response - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] flags Store the hardware response - * - * \return Bus response status. - * \retval 0 Bus response status OK - * \retval <0 Bus response fail - */ -inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) -{ - uint32_t timeout = 65535; - void * hw = i2c_dev->hw; - - do { - *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); - - if (timeout-- == 0) { - return I2C_ERR_BUS; - } - } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); - - return I2C_OK; -} - -/** - * \brief Send the slave address to bus, which will start the transfer - * - * \param[in] i2c_dev The pointer to i2c device - */ -static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) -{ - void * hw = i2c_dev->hw; - struct _i2c_m_msg *msg = &i2c_dev->service.msg; - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - uint32_t flags; - - ASSERT(i2c_dev); - - if (msg->len == 1 && sclsm) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } else { - hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); - } - - /* ten bit address */ - if (msg->addr & I2C_M_TEN) { - if (msg->flags & I2C_M_RD) { - msg->flags |= I2C_M_TEN; - } - - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } else { - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } - - _sercom_i2c_sync_wait_bus(i2c_dev, &flags); - return _sercom_i2c_sync_analyse_flags(hw, flags, msg); -} - -/** - * \brief Transfer data specified by msg - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] msg The pointer to i2c message - * - * \return Transfer status. - * \retval 0 Transfer success - * \retval <0 Transfer fail or partial fail, return the error code - */ -int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) -{ - uint32_t flags; - int ret; - void * hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - ASSERT(msg); - - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return I2C_ERR_BUSY; - } - - msg->flags |= I2C_M_BUSY; - i2c_dev->service.msg = *msg; - hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); - - ret = _sercom_i2c_sync_send_address(i2c_dev); - - if (ret) { - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - while (i2c_dev->service.msg.flags & I2C_M_BUSY) { - ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); - - if (ret) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); - } - - return ret; -} - -int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - _sercom_i2c_send_stop(hw); - - return I2C_OK; -} - -static inline int32_t _i2c_m_enable_implementation(void *const hw) -{ - int timeout = 65535; - int timeout_attempt = 4; - - ASSERT(hw); - - /* Enable interrupts */ - hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); - - while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { - timeout--; - - if (timeout <= 0) { - if (--timeout_attempt) - timeout = 65535; - else - return I2C_ERR_BUSY; - hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); - } - } - return ERR_NONE; -} - -static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) -{ - uint8_t i = _get_i2cm_index(hw); - - if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { - uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; - if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); - } - hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); - } - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - - hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); - hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); - hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); - - service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); - - service->trise = _i2cms[i].trise; - - return ERR_NONE; -} - - /* SERCOM I2C slave */ - -#ifndef CONF_SERCOM_0_I2CS_ENABLE -#define CONF_SERCOM_0_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_I2CS_ENABLE -#define CONF_SERCOM_1_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_I2CS_ENABLE -#define CONF_SERCOM_2_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_I2CS_ENABLE -#define CONF_SERCOM_3_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_I2CS_ENABLE -#define CONF_SERCOM_4_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_I2CS_ENABLE -#define CONF_SERCOM_5_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_I2CS_ENABLE -#define CONF_SERCOM_6_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_I2CS_ENABLE -#define CONF_SERCOM_7_I2CS_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as I2C Slave. */ -#define SERCOM_I2CS_AMOUNT \ - (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ - + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) - -/** - * \brief Macro is used to fill I2C slave configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define I2CS_CONFIGURATION(n) \ - { \ - n, \ - SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ - | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ - | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ - | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ - | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ - SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ - (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ - | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ - | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ - | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ - } - -/** - * \brief Macro to check 10-bit addressing - */ -#define I2CS_7BIT_ADDRESSING_MASK 0x7F - -static int32_t _i2c_s_init(void *const hw); -static int8_t _get_i2c_s_index(const void *const hw); -static inline void _i2c_s_deinit(void *const hw); -static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); - -/** - * \brief SERCOM I2C slave configuration type - */ -struct i2cs_configuration { - uint8_t number; - hri_sercomi2cs_ctrla_reg_t ctrl_a; - hri_sercomi2cs_ctrlb_reg_t ctrl_b; - hri_sercomi2cs_addr_reg_t address; -}; - -#if SERCOM_I2CS_AMOUNT < 1 -/** Dummy array for compiling. */ -static struct i2cs_configuration _i2css[1] = {{0}}; -#else -/** - * \brief Array of SERCOM I2C slave configurations - */ -static struct i2cs_configuration _i2css[] = { -#if CONF_SERCOM_0_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(7), -#endif -}; -#endif - -/** - * \brief Initialize synchronous I2C slave - */ -int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) -{ - int32_t status; - - ASSERT(device); - - status = _i2c_s_init(hw); - if (status) { - return status; - } - device->hw = hw; - - return ERR_NONE; -} - -/** - * \brief Initialize asynchronous I2C slave - */ -int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _i2c_s_init(hw); - if (init_status) { - return init_status; - } - - device->hw = hw; - _sercom_init_irq_param(hw, (void *)device); - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - // Enable Address Match and PREC interrupt by default. - hri_sercomi2cs_set_INTEN_AMATCH_bit(hw); - hri_sercomi2cs_set_INTEN_PREC_bit(hw); - - return ERR_NONE; -} - -/** - * \brief Deinitialize synchronous I2C - */ -int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) -{ - _i2c_s_deinit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Deinitialize asynchronous I2C - */ -int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); - _i2c_s_deinit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable I2C module - */ -int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable I2C module - */ -int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Disable I2C module - */ -int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Disable I2C module - */ -int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Check if 10-bit addressing mode is on - */ -int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); -} - -/** - * \brief Check if 10-bit addressing mode is on - */ -int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) -{ - return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); -} - -/** - * \brief Set I2C slave address - */ -int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) -{ - return _i2c_s_set_address(device->hw, address); -} - -/** - * \brief Set I2C slave address - */ -int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) -{ - return _i2c_s_set_address(device->hw, address); -} - -/** - * \brief Write a byte to the given I2C instance - */ -void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) -{ - hri_sercomi2cs_write_DATA_reg(device->hw, data); -} - -/** - * \brief Write a byte to the given I2C instance - */ -void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) -{ - hri_sercomi2cs_write_DATA_reg(device->hw, data); -} - -/** - * \brief Read a byte from the given I2C instance - */ -uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_read_DATA_reg(device->hw); -} - -/** - * \brief Check if I2C is ready to send next byt - */ -bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); -} - -/** - * \brief Check if there is data received by I2C - */ -bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); -} - -/** - * \brief Retrieve I2C slave status - */ -i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_read_STATUS_reg(device->hw); -} - -/** - * \brief Clear the Data Ready interrupt flag - */ -int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Retrieve I2C slave status - */ -i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) -{ - return hri_sercomi2cs_read_STATUS_reg(device->hw); -} - -/** - * \brief Abort data transmission - */ -int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable/disable I2C slave interrupt - */ -int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, - const bool state) -{ - ASSERT(device); - - if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { - hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); - } else if (I2C_S_DEVICE_ERROR == type) { - hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); - } - - return ERR_NONE; -} - -/** - * \internal Initalize i2c slave hardware - * - * \param[in] p The pointer to hardware instance - * - *\ return status of initialization - */ -static int32_t _i2c_s_init(void *const hw) -{ - int8_t i = _get_i2c_s_index(hw); - if (i == -1) { - return ERR_INVALID_ARG; - } - - if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { - uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; - if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); - } - hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); - } - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - - hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); - hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); - hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); - - return ERR_NONE; -} - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - * - * \return The ordinal number of the given sercom hardware instance - */ -static int8_t _get_i2c_s_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_i2css); i++) { - if (_i2css[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return -1; -} - -/** - * \internal De-initialize i2c slave - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _i2c_s_deinit(void *const hw) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); -} - -/** - * \internal De-initialize i2c slave - * - * \param[in] hw The pointer to hardware instance - * \param[in] address Address to set - */ -static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) -{ - bool enabled; - - enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); - CRITICAL_SECTION_LEAVE() - - if (enabled) { - hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); - } - - return ERR_NONE; -} - - /* Sercom SPI implementation */ - -#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE -#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) -#endif - -#define SPI_DEV_IRQ_MODE 0x8000 - -#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) -#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) - -COMPILER_PACK_SET(1) -/** Initialization configuration of registers. */ -struct sercomspi_regs_cfg { - uint32_t ctrla; - uint32_t ctrlb; - uint32_t addr; - uint8_t baud; - uint8_t dbgctrl; - uint16_t dummy_byte; - uint8_t n; -}; -COMPILER_PACK_RESET() - -/** Build configuration from header macros. */ -#define SERCOMSPI_REGS(n) \ - { \ - (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ - | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ - | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ - | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ - | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ - | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ - | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ - | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ - ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ - | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ - | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ - | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ - | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ - | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ - (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ - | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ - ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ - (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ - CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ - n /* sercom number */ \ - } - -#ifndef CONF_SERCOM_0_SPI_ENABLE -#define CONF_SERCOM_0_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_SPI_ENABLE -#define CONF_SERCOM_1_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_SPI_ENABLE -#define CONF_SERCOM_2_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_SPI_ENABLE -#define CONF_SERCOM_3_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_SPI_ENABLE -#define CONF_SERCOM_4_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_SPI_ENABLE -#define CONF_SERCOM_5_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_SPI_ENABLE -#define CONF_SERCOM_6_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_SPI_ENABLE -#define CONF_SERCOM_7_SPI_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as SPI */ -#define SERCOM_SPI_AMOUNT \ - (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ - + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) - -#if SERCOM_SPI_AMOUNT < 1 -/** Dummy array for compiling. */ -static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; -#else -/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ -static const struct sercomspi_regs_cfg sercomspi_regs[] = { -#if CONF_SERCOM_0_SPI_ENABLE - SERCOMSPI_REGS(0), -#endif -#if CONF_SERCOM_1_SPI_ENABLE - SERCOMSPI_REGS(1), -#endif -#if CONF_SERCOM_2_SPI_ENABLE - SERCOMSPI_REGS(2), -#endif -#if CONF_SERCOM_3_SPI_ENABLE - SERCOMSPI_REGS(3), -#endif -#if CONF_SERCOM_4_SPI_ENABLE - SERCOMSPI_REGS(4), -#endif -#if CONF_SERCOM_5_SPI_ENABLE - SERCOMSPI_REGS(5), -#endif -#if CONF_SERCOM_6_SPI_ENABLE - SERCOMSPI_REGS(6), -#endif -#if CONF_SERCOM_7_SPI_ENABLE - SERCOMSPI_REGS(7), -#endif -}; -#endif - -/** \internal De-initialize SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return De-initialization status - */ -static int32_t _spi_deinit(void *const hw) -{ - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - hri_sercomspi_set_CTRLA_SWRST_bit(hw); - - return ERR_NONE; -} - -/** \internal Enable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Enabling status - */ -static int32_t _spi_sync_enable(void *const hw) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - hri_sercomspi_set_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** \internal Enable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Enabling status - */ -static int32_t _spi_async_enable(void *const hw) -{ - _spi_sync_enable(hw); - NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - return ERR_NONE; -} - -/** \internal Disable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Disabling status - */ -static int32_t _spi_sync_disable(void *const hw) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** \internal Disable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Disabling status - */ -static int32_t _spi_async_disable(void *const hw) -{ - _spi_sync_disable(hw); - hri_sercomspi_clear_INTEN_reg( - hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI mode - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] mode The mode to set - * - * \return Setting mode status - */ -static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) -{ - uint32_t ctrla; - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { - return ERR_BUSY; - } - - ctrla = hri_sercomspi_read_CTRLA_reg(hw); - ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); - ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; - hri_sercomspi_write_CTRLA_reg(hw, ctrla); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI baudrate - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * - * \return Setting baudrate status - */ -static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - hri_sercomspi_write_BAUD_reg(hw, baud_val); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI char size - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * \param[out] size Stored char size - * - * \return Setting char size status - */ -static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) -{ - /* Only 8-bit or 9-bit accepted */ - if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { - return ERR_INVALID_ARG; - } - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { - return ERR_BUSY; - } - - hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); - *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI data order - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * - * \return Setting data order status - */ -static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) -{ - uint32_t ctrla; - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - ctrla = hri_sercomspi_read_CTRLA_reg(hw); - - if (dord == SPI_DATA_ORDER_LSB_1ST) { - ctrla |= SERCOM_SPI_CTRLA_DORD; - } else { - ctrla &= ~SERCOM_SPI_CTRLA_DORD; - } - hri_sercomspi_write_CTRLA_reg(hw, ctrla); - - return ERR_NONE; -} - -/** \brief Load SERCOM registers to init for SPI master mode - * The settings will be applied with default master mode, unsupported things - * are ignored. - * \param[in, out] hw Pointer to the hardware register base. - * \param[in] regs Pointer to register configuration values. - */ -static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) -{ - ASSERT(hw && regs); - hri_sercomspi_write_CTRLA_reg( - hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); - hri_sercomspi_write_CTRLB_reg( - hw, - (regs->ctrlb - & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) - | (SERCOM_SPI_CTRLB_RXEN)); - hri_sercomspi_write_BAUD_reg(hw, regs->baud); - hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); -} - -/** \brief Load SERCOM registers to init for SPI slave mode - * The settings will be applied with default slave mode, unsupported things - * are ignored. - * \param[in, out] hw Pointer to the hardware register base. - * \param[in] regs Pointer to register configuration values. - */ -static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) -{ - ASSERT(hw && regs); - hri_sercomspi_write_CTRLA_reg( - hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); - hri_sercomspi_write_CTRLB_reg(hw, - (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) - | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); - hri_sercomspi_write_ADDR_reg(hw, regs->addr); - hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); - while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) - ; -} - -/** \brief Return the pointer to register settings of specific SERCOM - * \param[in] hw_addr The hardware register base address. - * \return Pointer to register settings of specific SERCOM. - */ -static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) -{ - uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); - uint8_t i; - - for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { - if (sercomspi_regs[i].n == n) { - return &sercomspi_regs[i]; - } - } - - return NULL; -} - -int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) -{ - const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); - - ASSERT(dev && hw); - - if (regs == NULL) { - return ERR_INVALID_ARG; - } - - if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; - if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); - } - hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); - } - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - - dev->prvt = hw; - - if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { - _spi_load_regs_slave(hw, regs); - } else { - _spi_load_regs_master(hw, regs); - } - - /* Load character size from default hardware configuration */ - dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; - - dev->dummy_byte = regs->dummy_byte; - - return ERR_NONE; -} - -int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) -{ - return _spi_m_sync_init(dev, hw); -} - -int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) -{ - struct _spi_async_dev *spid = dev; - /* Do hardware initialize. */ - int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); - - if (rc < 0) { - return rc; - } - - _sercom_init_irq_param(hw, (void *)dev); - /* Initialize callbacks: must use them */ - spid->callbacks.complete = NULL; - spid->callbacks.rx = NULL; - spid->callbacks.tx = NULL; - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - return ERR_NONE; -} - -int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) -{ - return _spi_m_async_init(dev, hw); -} - -int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - - return _spi_deinit(dev->prvt); -} - -int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - - return _spi_deinit(dev->prvt); -} - -int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) -{ - return _spi_deinit(dev->prvt); -} - -int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) -{ - return _spi_deinit(dev->prvt); -} - -int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_enable(dev->prvt); -} - -int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_enable(dev->prvt); -} - -int32_t _spi_m_async_enable(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_enable(dev->prvt); -} - -int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_enable(dev->prvt); -} - -int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_disable(dev->prvt); -} - -int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_disable(dev->prvt); -} - -int32_t _spi_m_async_disable(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_disable(dev->prvt); -} - -int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_disable(dev->prvt); -} - -int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) -{ - int32_t rc; - ASSERT(dev); - (void)dev; - - /* Not accept 0es */ - if (clk == 0 || baud == 0) { - return ERR_INVALID_ARG; - } - - /* Check baudrate range of current assigned clock */ - if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { - return ERR_INVALID_ARG; - } - - rc = ((clk >> 1) / baud) - 1; - return rc; -} - -int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_baudrate(dev->prvt, baud_val); -} - -int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_baudrate(dev->prvt, baud_val); -} - -int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -/** Wait until SPI bus idle. */ -static inline void _spi_wait_bus_idle(void *const hw) -{ - while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { - ; - } - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); -} - -/** Holds run time information for message sync transaction. */ -struct _spi_trans_ctrl { - /** Pointer to transmitting data buffer. */ - uint8_t *txbuf; - /** Pointer to receiving data buffer. */ - uint8_t *rxbuf; - /** Count number of data transmitted. */ - uint32_t txcnt; - /** Count number of data received. */ - uint32_t rxcnt; - /** Data character size. */ - uint8_t char_size; -}; - -/** Check interrupt flag of RXC and update transaction runtime information. */ -static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) -{ - uint32_t data; - - if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { - return false; - } - - data = hri_sercomspi_read_DATA_reg(hw); - - if (ctrl->rxbuf) { - *ctrl->rxbuf++ = (uint8_t)data; - - if (ctrl->char_size > 1) { - *ctrl->rxbuf++ = (uint8_t)(data >> 8); - } - } - - ctrl->rxcnt++; - - return true; -} - -/** Check interrupt flag of DRE and update transaction runtime information. */ -static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, - uint16_t dummy) -{ - uint32_t data; - - if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { - return; - } - - if (ctrl->txbuf) { - data = *ctrl->txbuf++; - - if (ctrl->char_size > 1) { - data |= (*ctrl->txbuf) << 8; - ctrl->txbuf++; - } - } else { - data = dummy; - } - - ctrl->txcnt++; - hri_sercomspi_write_DATA_reg(hw, data); -} - -/** Check interrupt flag of ERROR and update transaction runtime information. */ -static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) -{ - if (SERCOM_SPI_INTFLAG_ERROR & iflag) { - hri_sercomspi_clear_STATUS_reg(hw, ~0); - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); - return ERR_OVERFLOW; - } - - return ERR_NONE; -} - -int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) -{ - void * hw = dev->prvt; - int32_t rc = 0; - struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; - - ASSERT(dev && hw); - - /* If settings are not applied (pending), we can not go on */ - if (hri_sercomspi_is_syncing( - hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { - return ERR_BUSY; - } - - /* SPI must be enabled to start synchronous transfer */ - if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { - return ERR_NOT_INITIALIZED; - } - - for (;;) { - uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); - - if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { - /* In master mode, do not start next byte before previous byte received - * to make better output waveform */ - if (ctrl.rxcnt >= ctrl.txcnt) { - _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); - } - } - - rc = _spi_err_check(iflag, hw); - - if (rc < 0) { - break; - } - if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { - rc = ctrl.txcnt; - break; - } - } - /* Wait until SPI bus idle */ - _spi_wait_bus_idle(hw); - - return rc; -} - -int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (state) { - hri_sercomspi_set_INTEN_DRE_bit(hw); - } else { - hri_sercomspi_clear_INTEN_DRE_bit(hw); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_tx(dev, state); -} - -int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) -{ - void *hw = dev->prvt; - - ASSERT(dev); - ASSERT(hw); - - if (state) { - hri_sercomspi_set_INTEN_RXC_bit(hw); - } else { - hri_sercomspi_clear_INTEN_RXC_bit(hw); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_rx(dev, state); -} - -int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) -{ - ASSERT(dev && dev->prvt); - - if (state) { - hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); - } else { - hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_tx_complete(dev, state); -} - -int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, - const FUNC_PTR func) -{ - typedef void (*func_t)(void); - struct _spi_async_dev *spid = dev; - - ASSERT(dev && (cb_type < SPI_DEV_CB_N)); - - func_t *p_ls = (func_t *)&spid->callbacks; - p_ls[cb_type] = (func_t)func; - - return ERR_NONE; -} - -int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, - const FUNC_PTR func) -{ - return _spi_m_async_register_callback(dev, cb_type, func); -} - -bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); -} - -bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); -} - -bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); - return true; - } - return false; -} - -bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { - hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); - return true; - } - return false; -} - -/** - * \brief Enable/disable SPI master interrupt - * - * param[in] device The pointer to SPI master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, - const bool state) -{ - ASSERT(device); - - if (SPI_DEV_CB_ERROR == type) { - hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); - } -} - -/** - * \brief Enable/disable SPI slave interrupt - * - * param[in] device The pointer to SPI slave device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, - const bool state) -{ - _spi_m_async_set_irq_state(device, type, state); -} diff --git a/watch-library/hpl/slcd/hpl_slcd.c b/watch-library/hpl/slcd/hpl_slcd.c deleted file mode 100644 index 0f58b1f5..00000000 --- a/watch-library/hpl/slcd/hpl_slcd.c +++ /dev/null @@ -1,289 +0,0 @@ -/** - * \file - * - * \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality - * Implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -static int32_t _slcd_sync_set_segment(struct _slcd_sync_device *dev, const uint32_t com, const uint32_t seg, - const bool on); - -/** - * \brief SLCD configuration type - */ -struct slcd_configuration { - hri_slcd_ctrla_reg_t ctrla; /*!< Control A Register */ - hri_slcd_ctrlb_reg_t ctrlb; /*!< Control B Register */ - hri_slcd_ctrlc_reg_t ctrlc; /*!< Control C Register */ - hri_slcd_ctrld_reg_t ctrld; /*!< Control D Register */ -}; - -/** - * \brief Array of AC configurations - */ -static struct slcd_configuration _slcd - = {SLCD_CTRLA_DUTY(CONF_SLCD_COM_NUM) | CONF_SLCD_WMOD << SLCD_CTRLA_WMOD_Pos - | CONF_SLCD_RUNSTDBY << SLCD_CTRLA_RUNSTDBY_Pos | SLCD_CTRLA_PRESC(CONF_SLCD_PRESC) - | SLCD_CTRLA_CKDIV(CONF_SLCD_CKDIV) | SLCD_CTRLA_BIAS(CONF_SLCD_BIAS) - | CONF_SLCD_XVLCD << SLCD_CTRLA_XVLCD_Pos | SLCD_CTRLA_PRF(CONF_SLCD_PRF) | SLCD_CTRLA_RRF(CONF_SLCD_RRF), - CONF_SLCD_BBEN << SLCD_CTRLB_BBEN_Pos | SLCD_CTRLB_BBD(CONF_SLCD_BBD - 1), - SLCD_CTRLC_CTST(CONF_SLCD_CONTRAST_ADJUST), - SLCD_CTRLD_DISPEN}; -/** - * \brief Initialize SLCD Device Descriptor - */ -int32_t _slcd_sync_init(struct _slcd_sync_device *dev, void *const hw) -{ - if (!hri_slcd_is_syncing(hw, SLCD_SYNCBUSY_SWRST)) { - if (hri_slcd_get_CTRLA_ENABLE_bit(hw)) { - hri_slcd_clear_CTRLA_ENABLE_bit(hw); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_ENABLE); - } - hri_slcd_write_CTRLA_reg(hw, SLCD_CTRLA_SWRST); - } - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST); - - dev->hw = hw; - hri_slcd_write_CTRLA_reg(hw, _slcd.ctrla); - hri_slcd_write_CTRLB_reg(hw, _slcd.ctrlb); - hri_slcd_write_CTRLC_reg(hw, _slcd.ctrlc); - hri_slcd_write_CTRLD_reg(hw, _slcd.ctrld); - hri_slcd_write_LPENL_reg(hw, CONF_SLCD_LPENL); - hri_slcd_write_LPENH_reg(hw, CONF_SLCD_LPENH); - hri_slcd_write_SDATAL0_reg(hw, 0); - hri_slcd_write_SDATAH0_reg(hw, 0); - hri_slcd_write_SDATAL1_reg(hw, 0); - hri_slcd_write_SDATAH1_reg(hw, 0); - hri_slcd_write_SDATAL2_reg(hw, 0); - hri_slcd_write_SDATAH2_reg(hw, 0); - hri_slcd_write_SDATAL3_reg(hw, 0); - hri_slcd_write_SDATAH3_reg(hw, 0); - hri_slcd_write_SDATAL4_reg(hw, 0); - hri_slcd_write_SDATAH4_reg(hw, 0); - hri_slcd_write_SDATAL5_reg(hw, 0); - hri_slcd_write_SDATAH5_reg(hw, 0); - hri_slcd_write_SDATAL6_reg(hw, 0); - hri_slcd_write_SDATAH6_reg(hw, 0); - hri_slcd_write_SDATAL7_reg(hw, 0); - hri_slcd_write_SDATAH7_reg(hw, 0); - hri_slcd_set_BCFG_MODE_bit(dev->hw); - return ERR_NONE; -} - -/** - * \brief DeInitialize SLCD Device Descriptor - */ -int32_t _slcd_sync_deinit(struct _slcd_sync_device *dev) -{ - hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw); - hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE); - hri_slcd_set_CTRLA_SWRST_bit(dev->hw); - dev->hw = NULL; - - return ERR_NONE; -} - -/** - * \brief Enable SLCD driver - * - * \param[in] dev SLCD device descriptor to be enabled - */ -int32_t _slcd_sync_enable(struct _slcd_sync_device *dev) -{ - hri_slcd_set_CTRLA_ENABLE_bit(dev->hw); - return ERR_NONE; -} - -/** - * \brief Disable SLCD driver - */ -int32_t _slcd_sync_disable(struct _slcd_sync_device *dev) -{ - hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw); - return ERR_NONE; -} - -/** - * \brief Turn on a Segment - */ -int32_t _slcd_sync_seg_on(struct _slcd_sync_device *dev, uint32_t seg) -{ - return _slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), true); -} - -/** - * \brief Turn off a Segment - */ -int32_t _slcd_sync_seg_off(struct _slcd_sync_device *dev, uint32_t seg) -{ - return _slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), false); -} - -/** - * \brief Blink a Segment - */ -int32_t _slcd_sync_seg_blink(struct _slcd_sync_device *dev, uint32_t seg, const uint32_t period) -{ - if ((SLCD_COMNUM(seg) >= CONF_SLCD_COM_NUM) || (SLCD_SEGNUM(seg) >= CONF_SLCD_SEG_NUM)) { - return ERR_INVALID_ARG; - } - /* COM[0..7], Seg[0,1] support blink */ - if (SLCD_SEGNUM(seg) >= 2) { - return ERR_INVALID_ARG; - } - /* Verify period */ - if (period > SLCD_FC_MAX_MS || period < SLCD_FC_MIN_MS) { - return ERR_INVALID_ARG; - } - /* Set Period, use Frame Counter 0 for blink */ - hri_slcd_clear_CTRLD_FC0EN_bit(dev->hw); - hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD); - if (period <= SLCD_FC_BYPASS_MAX_MS) { - hri_slcd_set_FC0_reg(dev->hw, SLCD_FC0_PB | ((period / (1000 / SLCD_FRAME_FREQUENCY)) - 1)); - } else { - hri_slcd_set_FC0_reg(dev->hw, (((period / (1000 / SLCD_FRAME_FREQUENCY)) / 8 - 1))); - } - hri_slcd_set_CTRLD_FC0EN_bit(dev->hw); - - /* Set Blink Segments */ - _slcd_sync_set_segment(dev, SLCD_COMNUM(seg), SLCD_SEGNUM(seg), true); - hri_slcd_clear_CTRLD_BLINK_bit(dev->hw); - - hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw); - hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE); - - /* Update BCFG */ - if (SLCD_SEGNUM(seg) == 0) { - hri_slcd_set_BCFG_BSS0_bf(dev->hw, 1 << SLCD_COMNUM(seg)); - } else { - hri_slcd_set_BCFG_BSS1_bf(dev->hw, 1 << SLCD_COMNUM(seg)); - } - hri_slcd_set_CTRLA_ENABLE_bit(dev->hw); - hri_slcd_set_CTRLD_BLINK_bit(dev->hw); - - return ERR_NONE; -} - -/** - * \brief Start animation play by a segment array - */ -int32_t _slcd_sync_start_animation(struct _slcd_sync_device *dev, const uint32_t segs[], uint32_t len, - const uint32_t period) -{ - uint32_t i; - uint32_t csrlen = 0; - if (len > 16) { - return ERR_INVALID_ARG; - } - /* COM[0..7], Seg[2,3] support animation */ - for (i = 0; i < len; i++) { - if ((SLCD_SEGNUM(segs[i]) != 2 && SLCD_SEGNUM(segs[i]) != 3)) { - return ERR_INVALID_ARG; - } - } - /* Verify period */ - if (period > SLCD_FC_MAX_MS || period < SLCD_FC_MIN_MS) { - return ERR_INVALID_ARG; - } - /* Set Period */ - _slcd_sync_set_animation_period(dev, period); - - /* Set animation segments */ - hri_slcd_clear_CTRLA_ENABLE_bit(dev->hw); - hri_slcd_clear_CTRLD_CSREN_bit(dev->hw); - - hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_ENABLE | SLCD_SYNCBUSY_CTRLD); - hri_slcd_set_CSRCFG_FCS_bf(dev->hw, 1); - hri_slcd_write_CSRCFG_DATA_bf(dev->hw, 0); - for (i = 0; i < len; i++) { - hri_slcd_set_CSRCFG_DATA_bf(dev->hw, (1 << ((SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2)))); - if (((SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2)) > csrlen) { - csrlen = (SLCD_COMNUM(segs[i]) * 2) + (SLCD_SEGNUM(segs[i]) - 2); - } - } - hri_slcd_set_CSRCFG_SIZE_bf(dev->hw, csrlen + 1); - hri_slcd_set_BCFG_MODE_bit(dev->hw); - hri_slcd_set_CTRLD_CSREN_bit(dev->hw); - hri_slcd_set_CTRLA_ENABLE_bit(dev->hw); - - return ERR_NONE; -} - -/** - * \brief Stop animation play by a segment array - */ -int32_t _slcd_sync_stop_animation(struct _slcd_sync_device *dev, const uint32_t segs[], uint32_t len) -{ - /* Not used because of the current version is not supported, Reserved */ - (void)segs; - (void)len; - hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD); - hri_slcd_clear_CTRLD_CSREN_bit(dev->hw); - return ERR_NONE; -} - -/** - * \brief Set animation Frequency - */ -int32_t _slcd_sync_set_animation_period(struct _slcd_sync_device *dev, const uint32_t period) -{ - hri_slcd_clear_CTRLD_FC1EN_bit(dev->hw); - hri_slcd_wait_for_sync(dev->hw, SLCD_SYNCBUSY_CTRLD); - /* Use Frame Counter 1 for blink */ - if (period <= SLCD_FC_BYPASS_MAX_MS) { - hri_slcd_set_FC1_reg(dev->hw, SLCD_FC1_PB | ((period / (1000 / SLCD_FRAME_FREQUENCY)) - 1)); - } else { - hri_slcd_set_FC1_reg(dev->hw, (((period / (1000 / SLCD_FRAME_FREQUENCY)) / 8 - 1))); - } - hri_slcd_set_CTRLD_FC1EN_bit(dev->hw); - return ERR_NONE; -} - -static int32_t _slcd_sync_set_segment(struct _slcd_sync_device *dev, const uint32_t com, const uint32_t seg, - const bool on) -{ - if ((SLCD_COMNUM(seg) >= CONF_SLCD_COM_NUM) || (SLCD_SEGNUM(seg) >= CONF_SLCD_SEG_NUM)) { - return ERR_INVALID_ARG; - } - /* Use register instead hri interface to optimization code */ - if (on) { - ((uint32_t *)&(((Slcd *)dev->hw)->SDATAL0))[(com * 2) + (seg >> 5)] - |= (seg < 32) ? (1 << seg) : (1 << (seg >> 5)); - } else { - ((uint32_t *)&(((Slcd *)dev->hw)->SDATAL0))[(com * 2) + (seg >> 5)] - &= ~((seg < 32) ? (1 << seg) : (1 << (seg >> 5))); - } - - return ERR_NONE; -} diff --git a/watch-library/hpl/slcd/hpl_slcd_cm.h b/watch-library/hpl/slcd/hpl_slcd_cm.h deleted file mode 100644 index 66dbde93..00000000 --- a/watch-library/hpl/slcd/hpl_slcd_cm.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * \file - * - * \brief SLCD Character Mapping declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef HPL_SLCD_CM_H_INCLUDED -#define HPL_SLCD_CM_H_INCLUDED - -#include - -/* Character Mapping Struct */ -struct slcd_char_mapping { - uint32_t character : 8; /*!< ASCII character */ - uint32_t mapping : 24; /*!< Mapping value */ -}; - -/* SLCD Character settting Struct */ -struct slcd_char_setting { - uint8_t com_index; /*!< Common terminal index, start from 0 */ - uint8_t seg_index; /*!< Segment terminal index, start from 0 */ - uint8_t nseg; /*!< Number of Segment, this field is used to - indentify which segments line will be - used. For example, if char mapping from - COM1/SEG2 and nseg=2,size=7, then - COM1/SEG2, COM1/SEG3, COM2/SEG2, - COM2/SEG3, COM3/SEG2, COM3/SEG3, - COM4/SEG2 will be used for mapping - */ - uint8_t size; /*!< char size, typical is 7/14/16 */ -}; -#endif /* HPL_SLCD_CM_H_INCLUDED */ diff --git a/watch-library/hpl/systick/hpl_systick.c b/watch-library/hpl/systick/hpl_systick.c deleted file mode 100644 index c2f3b29e..00000000 --- a/watch-library/hpl/systick/hpl_systick.c +++ /dev/null @@ -1,104 +0,0 @@ - -/** - * \file - * - * \brief SysTick related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Initialize system time module - */ -void _system_time_init(void *const hw) -{ - (void)hw; - SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos); - SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos) - | (1 << SysTick_CTRL_CLKSOURCE_Pos); -} -/** - * \brief Initialize delay functionality - */ -void _delay_init(void *const hw) -{ - _system_time_init(hw); -} - -/** - * \brief De-initialize system time module - */ -void _system_time_deinit(void *const hw) -{ - (void)hw; - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; -} - -/** - * \brief Get system time - */ -system_time_t _system_time_get(const void *const hw) -{ - (void)hw; - return (system_time_t)SysTick->VAL; -} - -/** - * \brief Get maximum possible system time - */ -system_time_t _system_time_get_max_time_value(const void *const hw) -{ - (void)hw; - return 0xFFFFFF; -} -/** - * \brief Delay loop to delay n number of cycles - */ -void _delay_cycles(void *const hw, uint32_t cycles) -{ - (void)hw; - uint8_t n = cycles >> 24; - uint32_t buf = cycles; - - while (n--) { - SysTick->LOAD = 0xFFFFFF; - SysTick->VAL = 0xFFFFFF; - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) - ; - buf -= 0xFFFFFF; - } - - SysTick->LOAD = buf; - SysTick->VAL = buf; - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) - ; -} diff --git a/watch-library/hpl/trng/hpl_trng.c b/watch-library/hpl/trng/hpl_trng.c deleted file mode 100755 index 43ede044..00000000 --- a/watch-library/hpl/trng/hpl_trng.c +++ /dev/null @@ -1,110 +0,0 @@ -/** - * \file - * - * \brief True Random Number Generator - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -static inline int32_t _trng_init(void *hw) -{ - if (hri_trng_get_CTRLA_reg(hw, TRNG_CTRLA_ENABLE)) { - return ERR_DENIED; - } - if (CONF_TRNG_RUNSTDBY) { - hri_trng_set_CTRLA_RUNSTDBY_bit(hw); - } else { - hri_trng_clear_CTRLA_RUNSTDBY_bit(hw); - } - if (CONF_TRNG_DATARDYEO) { - hri_trng_set_EVCTRL_DATARDYEO_bit(hw); - } else { - hri_trng_clear_EVCTRL_DATARDYEO_bit(hw); - } - return ERR_NONE; -} - -int32_t _rand_sync_init(struct _rand_sync_dev *const dev, void *const hw) -{ - int32_t rc; - - ASSERT(dev && hw); - - rc = _trng_init(hw); - if (rc == ERR_NONE) { - dev->prvt = hw; - dev->n_bits = 32; - } - return rc; -} - -void _rand_sync_deinit(struct _rand_sync_dev *const dev) -{ - _rand_sync_disable(dev); -} - -int32_t _rand_sync_enable(struct _rand_sync_dev *const dev) -{ - ASSERT(dev); - ASSERT(dev->prvt); - - hri_trng_set_CTRLA_ENABLE_bit(dev->prvt); - return ERR_NONE; -} - -void _rand_sync_disable(struct _rand_sync_dev *const dev) -{ - ASSERT(dev); - ASSERT(dev->prvt); - - hri_trng_clear_CTRLA_ENABLE_bit(dev->prvt); -} - -int32_t _rand_sync_set_seed(struct _rand_sync_dev *const dev, const uint32_t seed) -{ - (void)dev; - (void)seed; - return ERR_UNSUPPORTED_OP; -} - -uint32_t _rand_sync_read_one(const struct _rand_sync_dev *const dev) -{ - ASSERT(dev); - ASSERT(dev->prvt); - ASSERT(hri_trng_get_CTRLA_reg(dev->prvt, TRNG_CTRLA_ENABLE)); - - while (!hri_trng_get_INTFLAG_reg(dev->prvt, TRNG_INTFLAG_DATARDY)) { - /* Wait until data ready. */ - } - return hri_trng_read_DATA_reg(dev->prvt); -} diff --git a/watch-library/hri/hri_ac_l22.h b/watch-library/hri/hri_ac_l22.h deleted file mode 100644 index f1e17cef..00000000 --- a/watch-library/hri/hri_ac_l22.h +++ /dev/null @@ -1,1746 +0,0 @@ -/** - * \file - * - * \brief SAM AC - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_AC_COMPONENT_ -#ifndef _HRI_AC_L22_H_INCLUDED_ -#define _HRI_AC_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_AC_CRITICAL_SECTIONS) -#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define AC_CRITICAL_SECTION_ENTER() -#define AC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_ac_evctrl_reg_t; -typedef uint32_t hri_ac_compctrl_reg_t; -typedef uint32_t hri_ac_syncbusy_reg_t; -typedef uint8_t hri_ac_ctrla_reg_t; -typedef uint8_t hri_ac_ctrlb_reg_t; -typedef uint8_t hri_ac_dbgctrl_reg_t; -typedef uint8_t hri_ac_intenset_reg_t; -typedef uint8_t hri_ac_intflag_reg_t; -typedef uint8_t hri_ac_scaler_reg_t; -typedef uint8_t hri_ac_statusa_reg_t; -typedef uint8_t hri_ac_statusb_reg_t; -typedef uint8_t hri_ac_winctrl_reg_t; - -static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) -{ - while (((Ac *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) -{ - return ((Ac *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; -} - -static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; -} - -static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; -} - -static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; -} - -static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; -} - -static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; -} - -static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; -} - -static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; -} - -static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; -} - -static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; -} - -static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; -} - -static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; -} - -static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) -{ - return ((Ac *)hw)->INTFLAG.reg; -} - -static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) -{ - ((Ac *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; -} - -static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; -} - -static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; - } -} - -static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; -} - -static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; -} - -static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; -} - -static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; - } -} - -static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; -} - -static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; -} - -static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; -} - -static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; - } -} - -static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; -} - -static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - ((Ac *)hw)->INTENSET.reg = mask; -} - -static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) -{ - return ((Ac *)hw)->INTENSET.reg; -} - -static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) -{ - ((Ac *)hw)->INTENSET.reg = data; - ((Ac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - ((Ac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; -} - -static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) -{ - return ((Ac *)hw)->STATUSA.reg; -} - -static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; -} - -static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; -} - -static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) -{ - return ((Ac *)hw)->STATUSB.reg; -} - -static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; -} - -static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Ac *)hw)->SYNCBUSY.reg; -} - -static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= ~AC_CTRLA_ENABLE; - tmp |= value << AC_CTRLA_ENABLE_Pos; - ((Ac *)hw)->CTRLA.reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg |= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg = data; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg &= ~mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg ^= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) -{ - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - return ((Ac *)hw)->CTRLA.reg; -} - -static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEO0; - tmp |= value << AC_EVCTRL_COMPEO0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEO1; - tmp |= value << AC_EVCTRL_COMPEO1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_WINEO0; - tmp |= value << AC_EVCTRL_WINEO0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEI0; - tmp |= value << AC_EVCTRL_COMPEI0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEI1; - tmp |= value << AC_EVCTRL_COMPEI1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_INVEI0; - tmp |= value << AC_EVCTRL_INVEI0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_INVEI1; - tmp |= value << AC_EVCTRL_INVEI1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) -{ - return ((Ac *)hw)->EVCTRL.reg; -} - -static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp &= ~AC_DBGCTRL_DBGRUN; - tmp |= value << AC_DBGCTRL_DBGRUN_Pos; - ((Ac *)hw)->DBGCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Ac *)hw)->DBGCTRL.reg; -} - -static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= ~AC_WINCTRL_WEN0; - tmp |= value << AC_WINCTRL_WEN0_Pos; - ((Ac *)hw)->WINCTRL.reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; - return tmp; -} - -static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= ~AC_WINCTRL_WINTSEL0_Msk; - tmp |= AC_WINCTRL_WINTSEL0(data); - ((Ac *)hw)->WINCTRL.reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; - return tmp; -} - -static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg |= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg = data; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg &= ~mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg ^= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) -{ - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - return ((Ac *)hw)->WINCTRL.reg; -} - -static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, - hri_ac_scaler_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; - return tmp; -} - -static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp &= ~AC_SCALER_VALUE_Msk; - tmp |= AC_SCALER_VALUE(data); - ((Ac *)hw)->SCALER[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; - return tmp; -} - -static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) -{ - return ((Ac *)hw)->SCALER[index].reg; -} - -static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_ENABLE; - tmp |= value << AC_COMPCTRL_ENABLE_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SINGLE; - tmp |= value << AC_COMPCTRL_SINGLE_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_RUNSTDBY; - tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SWAP; - tmp |= value << AC_COMPCTRL_SWAP_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_HYSTEN; - tmp |= value << AC_COMPCTRL_HYSTEN_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_INTSEL_Msk; - tmp |= AC_COMPCTRL_INTSEL(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_MUXNEG_Msk; - tmp |= AC_COMPCTRL_MUXNEG(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_MUXPOS_Msk; - tmp |= AC_COMPCTRL_MUXPOS(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SPEED_Msk; - tmp |= AC_COMPCTRL_SPEED(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_HYST_Msk; - tmp |= AC_COMPCTRL_HYST(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_FLEN_Msk; - tmp |= AC_COMPCTRL_FLEN(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_OUT_Msk; - tmp |= AC_COMPCTRL_OUT(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg = data; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) -{ - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - return ((Ac *)hw)->COMPCTRL[index].reg; -} - -static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLB.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_AC_L22_H_INCLUDED */ -#endif /* _SAML22_AC_COMPONENT_ */ diff --git a/watch-library/hri/hri_adc_l22.h b/watch-library/hri/hri_adc_l22.h deleted file mode 100644 index 53ba6af8..00000000 --- a/watch-library/hri/hri_adc_l22.h +++ /dev/null @@ -1,2803 +0,0 @@ -/** - * \file - * - * \brief SAM ADC - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_ADC_COMPONENT_ -#ifndef _HRI_ADC_L22_H_INCLUDED_ -#define _HRI_ADC_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_ADC_CRITICAL_SECTIONS) -#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define ADC_CRITICAL_SECTION_ENTER() -#define ADC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_adc_calib_reg_t; -typedef uint16_t hri_adc_ctrlc_reg_t; -typedef uint16_t hri_adc_gaincorr_reg_t; -typedef uint16_t hri_adc_inputctrl_reg_t; -typedef uint16_t hri_adc_offsetcorr_reg_t; -typedef uint16_t hri_adc_result_reg_t; -typedef uint16_t hri_adc_syncbusy_reg_t; -typedef uint16_t hri_adc_winlt_reg_t; -typedef uint16_t hri_adc_winut_reg_t; -typedef uint32_t hri_adc_seqctrl_reg_t; -typedef uint8_t hri_adc_avgctrl_reg_t; -typedef uint8_t hri_adc_ctrla_reg_t; -typedef uint8_t hri_adc_ctrlb_reg_t; -typedef uint8_t hri_adc_dbgctrl_reg_t; -typedef uint8_t hri_adc_evctrl_reg_t; -typedef uint8_t hri_adc_intenset_reg_t; -typedef uint8_t hri_adc_intflag_reg_t; -typedef uint8_t hri_adc_refctrl_reg_t; -typedef uint8_t hri_adc_sampctrl_reg_t; -typedef uint8_t hri_adc_seqstatus_reg_t; -typedef uint8_t hri_adc_swtrig_reg_t; - -static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) -{ - while (((Adc *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) -{ - return ((Adc *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; -} - -static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; -} - -static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; -} - -static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; -} - -static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; -} - -static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; -} - -static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; -} - -static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; -} - -static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; -} - -static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; -} - -static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; -} - -static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; -} - -static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) -{ - return ((Adc *)hw)->INTFLAG.reg; -} - -static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) -{ - ((Adc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; -} - -static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; -} - -static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; - } -} - -static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; -} - -static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; -} - -static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; -} - -static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; - } -} - -static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; -} - -static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; -} - -static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; -} - -static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; - } -} - -static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; -} - -static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - ((Adc *)hw)->INTENSET.reg = mask; -} - -static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) -{ - return ((Adc *)hw)->INTENSET.reg; -} - -static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) -{ - ((Adc *)hw)->INTENSET.reg = data; - ((Adc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - ((Adc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_adc_get_SEQSTATUS_SEQBUSY_bit(const void *const hw) -{ - return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY) >> ADC_SEQSTATUS_SEQBUSY_Pos; -} - -static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_SEQSTATE_bf(const void *const hw, - hri_adc_seqstatus_reg_t mask) -{ - return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE(mask)) >> ADC_SEQSTATUS_SEQSTATE_Pos; -} - -static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_SEQSTATE_bf(const void *const hw) -{ - return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE_Msk) >> ADC_SEQSTATUS_SEQSTATE_Pos; -} - -static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_reg(const void *const hw, hri_adc_seqstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SEQSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_reg(const void *const hw) -{ - return ((Adc *)hw)->SEQSTATUS.reg; -} - -static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_CTRLC_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLC) >> ADC_SYNCBUSY_CTRLC_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; -} - -static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Adc *)hw)->SYNCBUSY.reg; -} - -static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) -{ - return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; -} - -static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) -{ - return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; -} - -static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->RESULT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) -{ - return ((Adc *)hw)->RESULT.reg; -} - -static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_ENABLE; - tmp |= value << ADC_CTRLA_ENABLE_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_RUNSTDBY; - tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_ONDEMAND; - tmp |= value << ADC_CTRLA_ONDEMAND_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - return ((Adc *)hw)->CTRLA.reg; -} - -static inline void hri_adc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_PRESCALER(mask)) >> ADC_CTRLB_PRESCALER_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_PRESCALER_Msk; - tmp |= ADC_CTRLB_PRESCALER(data); - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_PRESCALER_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_PRESCALER_Msk) >> ADC_CTRLB_PRESCALER_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) -{ - return ((Adc *)hw)->CTRLB.reg; -} - -static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= ~ADC_REFCTRL_REFCOMP; - tmp |= value << ADC_REFCTRL_REFCOMP_Pos; - ((Adc *)hw)->REFCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= ~ADC_REFCTRL_REFSEL_Msk; - tmp |= ADC_REFCTRL_REFSEL(data); - ((Adc *)hw)->REFCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->REFCTRL.reg; -} - -static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_FLUSHEI; - tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_STARTEI; - tmp |= value << ADC_EVCTRL_STARTEI_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_FLUSHINV; - tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_STARTINV; - tmp |= value << ADC_EVCTRL_STARTINV_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_RESRDYEO; - tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_WINMONEO; - tmp |= value << ADC_EVCTRL_WINMONEO_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->EVCTRL.reg; -} - -static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; - tmp |= ADC_INPUTCTRL_MUXPOS(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; - tmp |= ADC_INPUTCTRL_MUXNEG(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->INPUTCTRL.reg; -} - -static inline void hri_adc_set_CTRLC_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DIFFMODE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLC_DIFFMODE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLC.reg; - tmp = (tmp & ADC_CTRLC_DIFFMODE) >> ADC_CTRLC_DIFFMODE_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLC_DIFFMODE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLC.reg; - tmp &= ~ADC_CTRLC_DIFFMODE; - tmp |= value << ADC_CTRLC_DIFFMODE_Pos; - ((Adc *)hw)->CTRLC.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLC_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DIFFMODE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLC_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DIFFMODE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLC_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_LEFTADJ; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLC_LEFTADJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLC.reg; - tmp = (tmp & ADC_CTRLC_LEFTADJ) >> ADC_CTRLC_LEFTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLC_LEFTADJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLC.reg; - tmp &= ~ADC_CTRLC_LEFTADJ; - tmp |= value << ADC_CTRLC_LEFTADJ_Pos; - ((Adc *)hw)->CTRLC.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLC_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_LEFTADJ; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLC_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_LEFTADJ; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLC_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_FREERUN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLC_FREERUN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLC.reg; - tmp = (tmp & ADC_CTRLC_FREERUN) >> ADC_CTRLC_FREERUN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLC_FREERUN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLC.reg; - tmp &= ~ADC_CTRLC_FREERUN; - tmp |= value << ADC_CTRLC_FREERUN_Pos; - ((Adc *)hw)->CTRLC.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLC_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_FREERUN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLC_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_FREERUN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLC_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_CORREN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLC_CORREN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLC.reg; - tmp = (tmp & ADC_CTRLC_CORREN) >> ADC_CTRLC_CORREN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLC_CORREN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLC.reg; - tmp &= ~ADC_CTRLC_CORREN; - tmp |= value << ADC_CTRLC_CORREN_Pos; - ((Adc *)hw)->CTRLC.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLC_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_CORREN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLC_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_CORREN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLC_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_R2R; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLC_R2R_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLC.reg; - tmp = (tmp & ADC_CTRLC_R2R) >> ADC_CTRLC_R2R_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLC_R2R_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLC.reg; - tmp &= ~ADC_CTRLC_R2R; - tmp |= value << ADC_CTRLC_R2R_Pos; - ((Adc *)hw)->CTRLC.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLC_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_R2R; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLC_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_R2R; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_RESSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLC.reg; - tmp = (tmp & ADC_CTRLC_RESSEL(mask)) >> ADC_CTRLC_RESSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLC.reg; - tmp &= ~ADC_CTRLC_RESSEL_Msk; - tmp |= ADC_CTRLC_RESSEL(data); - ((Adc *)hw)->CTRLC.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_RESSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_RESSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_RESSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLC.reg; - tmp = (tmp & ADC_CTRLC_RESSEL_Msk) >> ADC_CTRLC_RESSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_WINMODE(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLC.reg; - tmp = (tmp & ADC_CTRLC_WINMODE(mask)) >> ADC_CTRLC_WINMODE_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLC.reg; - tmp &= ~ADC_CTRLC_WINMODE_Msk; - tmp |= ADC_CTRLC_WINMODE(data); - ((Adc *)hw)->CTRLC.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_WINMODE(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_WINMODE(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_WINMODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLC.reg; - tmp = (tmp & ADC_CTRLC_WINMODE_Msk) >> ADC_CTRLC_WINMODE_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DUALSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLC.reg; - tmp = (tmp & ADC_CTRLC_DUALSEL(mask)) >> ADC_CTRLC_DUALSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLC.reg; - tmp &= ~ADC_CTRLC_DUALSEL_Msk; - tmp |= ADC_CTRLC_DUALSEL(data); - ((Adc *)hw)->CTRLC.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DUALSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DUALSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_DUALSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLC.reg; - tmp = (tmp & ADC_CTRLC_DUALSEL_Msk) >> ADC_CTRLC_DUALSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLC.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->CTRLC.reg; -} - -static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; - tmp |= ADC_AVGCTRL_SAMPLENUM(data); - ((Adc *)hw)->AVGCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; - return tmp; -} - -static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= ~ADC_AVGCTRL_ADJRES_Msk; - tmp |= ADC_AVGCTRL_ADJRES(data); - ((Adc *)hw)->AVGCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; - return tmp; -} - -static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->AVGCTRL.reg; -} - -static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= ~ADC_SAMPCTRL_OFFCOMP; - tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; - ((Adc *)hw)->SAMPCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; - return tmp; -} - -static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; - tmp |= ADC_SAMPCTRL_SAMPLEN(data); - ((Adc *)hw)->SAMPCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; - return tmp; -} - -static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->SAMPCTRL.reg; -} - -static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; - return tmp; -} - -static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->WINLT.reg; - tmp &= ~ADC_WINLT_WINLT_Msk; - tmp |= ADC_WINLT_WINLT(data); - ((Adc *)hw)->WINLT.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; - return tmp; -} - -static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - return ((Adc *)hw)->WINLT.reg; -} - -static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; - return tmp; -} - -static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->WINUT.reg; - tmp &= ~ADC_WINUT_WINUT_Msk; - tmp |= ADC_WINUT_WINUT(data); - ((Adc *)hw)->WINUT.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; - return tmp; -} - -static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - return ((Adc *)hw)->WINUT.reg; -} - -static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; - return tmp; -} - -static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp &= ~ADC_GAINCORR_GAINCORR_Msk; - tmp |= ADC_GAINCORR_GAINCORR(data); - ((Adc *)hw)->GAINCORR.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; - return tmp; -} - -static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - return ((Adc *)hw)->GAINCORR.reg; -} - -static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, - hri_adc_offsetcorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; - return tmp; -} - -static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; - tmp |= ADC_OFFSETCORR_OFFSETCORR(data); - ((Adc *)hw)->OFFSETCORR.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; - return tmp; -} - -static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - return ((Adc *)hw)->OFFSETCORR.reg; -} - -static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= ~ADC_SWTRIG_FLUSH; - tmp |= value << ADC_SWTRIG_FLUSH_Pos; - ((Adc *)hw)->SWTRIG.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= ~ADC_SWTRIG_START; - tmp |= value << ADC_SWTRIG_START_Pos; - ((Adc *)hw)->SWTRIG.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->SWTRIG.reg; -} - -static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp &= ~ADC_DBGCTRL_DBGRUN; - tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; - ((Adc *)hw)->DBGCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->DBGCTRL.reg; -} - -static inline void hri_adc_set_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SEQCTRL.reg |= ADC_SEQCTRL_SEQEN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->SEQCTRL.reg; - tmp = (tmp & ADC_SEQCTRL_SEQEN(mask)) >> ADC_SEQCTRL_SEQEN_Pos; - return tmp; -} - -static inline void hri_adc_write_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t data) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SEQCTRL.reg; - tmp &= ~ADC_SEQCTRL_SEQEN_Msk; - tmp |= ADC_SEQCTRL_SEQEN(data); - ((Adc *)hw)->SEQCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SEQCTRL.reg &= ~ADC_SEQCTRL_SEQEN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SEQCTRL.reg ^= ADC_SEQCTRL_SEQEN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_SEQEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->SEQCTRL.reg; - tmp = (tmp & ADC_SEQCTRL_SEQEN_Msk) >> ADC_SEQCTRL_SEQEN_Pos; - return tmp; -} - -static inline void hri_adc_set_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SEQCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->SEQCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SEQCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SEQCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SEQCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->SEQCTRL.reg; -} - -static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIASCOMP_Msk; - tmp |= ADC_CALIB_BIASCOMP(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIASREFBUF_Msk; - tmp |= ADC_CALIB_BIASREFBUF(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) -{ - return ((Adc *)hw)->CALIB.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_ADC_L22_H_INCLUDED */ -#endif /* _SAML22_ADC_COMPONENT_ */ diff --git a/watch-library/hri/hri_aes_l22.h b/watch-library/hri/hri_aes_l22.h deleted file mode 100644 index f88f081e..00000000 --- a/watch-library/hri/hri_aes_l22.h +++ /dev/null @@ -1,1213 +0,0 @@ -/** - * \file - * - * \brief SAM AES - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_AES_COMPONENT_ -#ifndef _HRI_AES_L22_H_INCLUDED_ -#define _HRI_AES_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_AES_CRITICAL_SECTIONS) -#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define AES_CRITICAL_SECTION_ENTER() -#define AES_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_aes_ciplen_reg_t; -typedef uint32_t hri_aes_ctrla_reg_t; -typedef uint32_t hri_aes_ghash_reg_t; -typedef uint32_t hri_aes_hashkey_reg_t; -typedef uint32_t hri_aes_indata_reg_t; -typedef uint32_t hri_aes_intvectv_reg_t; -typedef uint32_t hri_aes_keyword_reg_t; -typedef uint32_t hri_aes_randseed_reg_t; -typedef uint8_t hri_aes_ctrlb_reg_t; -typedef uint8_t hri_aes_databufptr_reg_t; -typedef uint8_t hri_aes_dbgctrl_reg_t; -typedef uint8_t hri_aes_intenset_reg_t; -typedef uint8_t hri_aes_intflag_reg_t; - -static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; -} - -static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; -} - -static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; -} - -static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; -} - -static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; -} - -static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; -} - -static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; -} - -static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; -} - -static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) -{ - return ((Aes *)hw)->INTFLAG.reg; -} - -static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) -{ - ((Aes *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; -} - -static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; -} - -static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; - } else { - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; - } -} - -static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; -} - -static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; -} - -static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; -} - -static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; - } else { - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; - } -} - -static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; -} - -static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - ((Aes *)hw)->INTENSET.reg = mask; -} - -static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) -{ - return ((Aes *)hw)->INTENSET.reg; -} - -static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) -{ - ((Aes *)hw)->INTENSET.reg = data; - ((Aes *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - ((Aes *)hw)->INTENCLR.reg = mask; -} - -static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_ENABLE; - tmp |= value << AES_CTRLA_ENABLE_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CIPHER; - tmp |= value << AES_CTRLA_CIPHER_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_STARTMODE; - tmp |= value << AES_CTRLA_STARTMODE_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_LOD; - tmp |= value << AES_CTRLA_LOD_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_KEYGEN; - tmp |= value << AES_CTRLA_KEYGEN_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_XORKEY; - tmp |= value << AES_CTRLA_XORKEY_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_AESMODE_Msk; - tmp |= AES_CTRLA_AESMODE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CFBS_Msk; - tmp |= AES_CTRLA_CFBS(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_KEYSIZE_Msk; - tmp |= AES_CTRLA_KEYSIZE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CTYPE_Msk; - tmp |= AES_CTRLA_CTYPE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) -{ - return ((Aes *)hw)->CTRLA.reg; -} - -static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_START; - tmp |= value << AES_CTRLB_START_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_NEWMSG; - tmp |= value << AES_CTRLB_NEWMSG_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_EOM; - tmp |= value << AES_CTRLB_EOM_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_GFMUL; - tmp |= value << AES_CTRLB_GFMUL_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) -{ - return ((Aes *)hw)->CTRLB.reg; -} - -static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, - hri_aes_databufptr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; - return tmp; -} - -static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; - tmp |= AES_DATABUFPTR_INDATAPTR(data); - ((Aes *)hw)->DATABUFPTR.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; - return tmp; -} - -static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) -{ - return ((Aes *)hw)->DATABUFPTR.reg; -} - -static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->INDATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) -{ - return ((Aes *)hw)->INDATA.reg; -} - -static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, - hri_aes_hashkey_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->HASHKEY[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) -{ - return ((Aes *)hw)->HASHKEY[index].reg; -} - -static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->GHASH[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) -{ - return ((Aes *)hw)->GHASH[index].reg; -} - -static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CIPLEN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) -{ - return ((Aes *)hw)->CIPLEN.reg; -} - -static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->RANDSEED.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) -{ - return ((Aes *)hw)->RANDSEED.reg; -} - -static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->KEYWORD[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INTVECTV[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_AES_L22_H_INCLUDED */ -#endif /* _SAML22_AES_COMPONENT_ */ diff --git a/watch-library/hri/hri_ccl_l22.h b/watch-library/hri/hri_ccl_l22.h deleted file mode 100644 index b510c86a..00000000 --- a/watch-library/hri/hri_ccl_l22.h +++ /dev/null @@ -1,776 +0,0 @@ -/** - * \file - * - * \brief SAM CCL - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_CCL_COMPONENT_ -#ifndef _HRI_CCL_L22_H_INCLUDED_ -#define _HRI_CCL_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_CCL_CRITICAL_SECTIONS) -#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define CCL_CRITICAL_SECTION_ENTER() -#define CCL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_ccl_lutctrl_reg_t; -typedef uint8_t hri_ccl_ctrl_reg_t; -typedef uint8_t hri_ccl_seqctrl_reg_t; - -static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= ~CCL_CTRL_ENABLE; - tmp |= value << CCL_CTRL_ENABLE_Pos; - ((Ccl *)hw)->CTRL.reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= ~CCL_CTRL_RUNSTDBY; - tmp |= value << CCL_CTRL_RUNSTDBY_Pos; - ((Ccl *)hw)->CTRL.reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) -{ - return ((Ccl *)hw)->CTRL.reg; -} - -static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, - hri_ccl_seqctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; - return tmp; -} - -static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; - tmp |= CCL_SEQCTRL_SEQSEL(data); - ((Ccl *)hw)->SEQCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; - return tmp; -} - -static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, - hri_ccl_seqctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Ccl *)hw)->SEQCTRL[index].reg; -} - -static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_ENABLE; - tmp |= value << CCL_LUTCTRL_ENABLE_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_EDGESEL; - tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INVEI; - tmp |= value << CCL_LUTCTRL_INVEI_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_LUTEI; - tmp |= value << CCL_LUTCTRL_LUTEI_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_LUTEO; - tmp |= value << CCL_LUTCTRL_LUTEO_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; - tmp |= CCL_LUTCTRL_FILTSEL(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL0_Msk; - tmp |= CCL_LUTCTRL_INSEL0(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL1_Msk; - tmp |= CCL_LUTCTRL_INSEL1(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL2_Msk; - tmp |= CCL_LUTCTRL_INSEL2(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_TRUTH_Msk; - tmp |= CCL_LUTCTRL_TRUTH(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Ccl *)hw)->LUTCTRL[index].reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_CCL_L22_H_INCLUDED */ -#endif /* _SAML22_CCL_COMPONENT_ */ diff --git a/watch-library/hri/hri_dmac_l22.h b/watch-library/hri/hri_dmac_l22.h deleted file mode 100644 index a20e28ee..00000000 --- a/watch-library/hri/hri_dmac_l22.h +++ /dev/null @@ -1,4559 +0,0 @@ -/** - * \file - * - * \brief SAM DMAC - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_DMAC_COMPONENT_ -#ifndef _HRI_DMAC_L22_H_INCLUDED_ -#define _HRI_DMAC_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) -#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DMAC_CRITICAL_SECTION_ENTER() -#define DMAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_dmac_crcctrl_reg_t; -typedef uint16_t hri_dmac_ctrl_reg_t; -typedef uint16_t hri_dmac_intpend_reg_t; -typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; -typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; -typedef uint32_t hri_dmac_active_reg_t; -typedef uint32_t hri_dmac_baseaddr_reg_t; -typedef uint32_t hri_dmac_busych_reg_t; -typedef uint32_t hri_dmac_chctrlb_reg_t; -typedef uint32_t hri_dmac_crcchksum_reg_t; -typedef uint32_t hri_dmac_crcdatain_reg_t; -typedef uint32_t hri_dmac_intstatus_reg_t; -typedef uint32_t hri_dmac_pendch_reg_t; -typedef uint32_t hri_dmac_prictrl0_reg_t; -typedef uint32_t hri_dmac_swtrigctrl_reg_t; -typedef uint32_t hri_dmac_wrbaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; -typedef uint8_t hri_dmac_chctrla_reg_t; -typedef uint8_t hri_dmac_chid_reg_t; -typedef uint8_t hri_dmac_chintenset_reg_t; -typedef uint8_t hri_dmac_chintflag_reg_t; -typedef uint8_t hri_dmac_chstatus_reg_t; -typedef uint8_t hri_dmac_crcstatus_reg_t; -typedef uint8_t hri_dmac_dbgctrl_reg_t; -typedef uint8_t hri_dmac_qosctrl_reg_t; - -static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHINTFLAG.reg; -} - -static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) -{ - ((Dmac *)hw)->CHINTFLAG.reg = mask; -} - -static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; -} - -static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; -} - -static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; - } else { - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; - } -} - -static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; -} - -static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; -} - -static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; - } else { - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; - } -} - -static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; -} - -static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; -} - -static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; - } else { - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; - } -} - -static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; -} - -static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - ((Dmac *)hw)->CHINTENSET.reg = mask; -} - -static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHINTENSET.reg; -} - -static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) -{ - ((Dmac *)hw)->CHINTENSET.reg = data; - ((Dmac *)hw)->CHINTENCLR.reg = ~data; -} - -static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - ((Dmac *)hw)->CHINTENCLR.reg = mask; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; -} - -static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->INTSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->INTSTATUS.reg; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; -} - -static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BUSYCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) -{ - return ((Dmac *)hw)->BUSYCH.reg; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; -} - -static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PENDCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) -{ - return ((Dmac *)hw)->PENDCH.reg; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->ACTIVE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) -{ - return ((Dmac *)hw)->ACTIVE.reg; -} - -static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; -} - -static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; -} - -static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; -} - -static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHSTATUS.reg; -} - -static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_DMAENABLE; - tmp |= value << DMAC_CTRL_DMAENABLE_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_CRCENABLE; - tmp |= value << DMAC_CTRL_CRCENABLE_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN0; - tmp |= value << DMAC_CTRL_LVLEN0_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN1; - tmp |= value << DMAC_CTRL_LVLEN1_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN2; - tmp |= value << DMAC_CTRL_LVLEN2_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN3; - tmp |= value << DMAC_CTRL_LVLEN3_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->CTRL.reg; -} - -static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, - hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; - tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; - tmp |= DMAC_CRCCTRL_CRCPOLY(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; - tmp |= DMAC_CRCCTRL_CRCSRC(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCCTRL.reg; -} - -static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, - hri_dmac_crcdatain_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; - tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); - ((Dmac *)hw)->CRCDATAIN.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCDATAIN.reg; -} - -static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, - hri_dmac_crcchksum_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; - tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); - ((Dmac *)hw)->CRCCHKSUM.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCCHKSUM.reg; -} - -static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp &= ~DMAC_DBGCTRL_DBGRUN; - tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; - ((Dmac *)hw)->DBGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->DBGCTRL.reg; -} - -static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos; - return tmp; -} - -static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk; - tmp |= DMAC_QOSCTRL_WRBQOS(data); - ((Dmac *)hw)->QOSCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos; - return tmp; -} - -static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos; - return tmp; -} - -static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp &= ~DMAC_QOSCTRL_FQOS_Msk; - tmp |= DMAC_QOSCTRL_FQOS(data); - ((Dmac *)hw)->QOSCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos; - return tmp; -} - -static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp &= ~DMAC_QOSCTRL_DQOS_Msk; - tmp |= DMAC_QOSCTRL_DQOS(data); - ((Dmac *)hw)->QOSCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->QOSCTRL.reg; -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, - hri_dmac_swtrigctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->SWTRIGCTRL.reg; -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN0; - tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN1; - tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN2; - tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN3; - tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI0(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI1(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI2(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI3(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) -{ - return ((Dmac *)hw)->PRICTRL0.reg; -} - -static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_TERR; - tmp |= value << DMAC_INTPEND_TERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_TCMPL; - tmp |= value << DMAC_INTPEND_TCMPL_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_SUSP; - tmp |= value << DMAC_INTPEND_SUSP_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_FERR; - tmp |= value << DMAC_INTPEND_FERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_BUSY; - tmp |= value << DMAC_INTPEND_BUSY_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_PEND; - tmp |= value << DMAC_INTPEND_PEND_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_ID_Msk; - tmp |= DMAC_INTPEND_ID(data); - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) -{ - return ((Dmac *)hw)->INTPEND.reg; -} - -static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, - hri_dmac_baseaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; - return tmp; -} - -static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; - tmp |= DMAC_BASEADDR_BASEADDR(data); - ((Dmac *)hw)->BASEADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; - return tmp; -} - -static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) -{ - return ((Dmac *)hw)->BASEADDR.reg; -} - -static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; - return tmp; -} - -static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; - tmp |= DMAC_WRBADDR_WRBADDR(data); - ((Dmac *)hw)->WRBADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; - return tmp; -} - -static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) -{ - return ((Dmac *)hw)->WRBADDR.reg; -} - -static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHID.reg; - tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHID.reg; - tmp &= ~DMAC_CHID_ID_Msk; - tmp |= DMAC_CHID_ID(data); - ((Dmac *)hw)->CHID.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHID.reg; - tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHID.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHID.reg; -} - -static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_ENABLE; - tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; - ((Dmac *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_RUNSTDBY; - tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; - ((Dmac *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHCTRLA.reg; -} - -static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_EVIE; - tmp |= value << DMAC_CHCTRLB_EVIE_Pos; - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_EVOE; - tmp |= value << DMAC_CHCTRLB_EVOE_Pos; - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_EVACT_Msk; - tmp |= DMAC_CHCTRLB_EVACT(data); - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_LVL_Msk; - tmp |= DMAC_CHCTRLB_LVL(data); - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk; - tmp |= DMAC_CHCTRLB_TRIGSRC(data); - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk; - tmp |= DMAC_CHCTRLB_TRIGACT(data); - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_CMD_Msk; - tmp |= DMAC_CHCTRLB_CMD(data); - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHCTRLB.reg; -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CRCSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCSTATUS.reg; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_VALID; - tmp |= value << DMAC_BTCTRL_VALID_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_SRCINC; - tmp |= value << DMAC_BTCTRL_SRCINC_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_DSTINC; - tmp |= value << DMAC_BTCTRL_DSTINC_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_STEPSEL; - tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; - tmp |= DMAC_BTCTRL_EVOSEL(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; - tmp |= DMAC_BTCTRL_BLOCKACT(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; - tmp |= DMAC_BTCTRL_BEATSIZE(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; - tmp |= DMAC_BTCTRL_STEPSIZE(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->BTCTRL.reg; -} - -static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, - hri_dmacdescriptor_btcnt_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp &= ~DMAC_BTCNT_BTCNT_Msk; - tmp |= DMAC_BTCNT_BTCNT(data); - ((DmacDescriptor *)hw)->BTCNT.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, - hri_dmacdescriptor_btcnt_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->BTCNT.reg; -} - -static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t -hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; - tmp |= DMAC_SRCADDR_SRCADDR(data); - ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->SRCADDR.reg; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t -hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; - tmp |= DMAC_DSTADDR_DSTADDR(data); - ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->DSTADDR.reg; -} - -static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t -hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; - tmp |= DMAC_DESCADDR_DESCADDR(data); - ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t -hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->DESCADDR.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DMAC_L22_H_INCLUDED */ -#endif /* _SAML22_DMAC_COMPONENT_ */ diff --git a/watch-library/hri/hri_dsu_l22.h b/watch-library/hri/hri_dsu_l22.h deleted file mode 100644 index 2e8bbe8b..00000000 --- a/watch-library/hri/hri_dsu_l22.h +++ /dev/null @@ -1,1163 +0,0 @@ -/** - * \file - * - * \brief SAM DSU - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_DSU_COMPONENT_ -#ifndef _HRI_DSU_L22_H_INCLUDED_ -#define _HRI_DSU_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DSU_CRITICAL_SECTIONS) -#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DSU_CRITICAL_SECTION_ENTER() -#define DSU_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_dsu_addr_reg_t; -typedef uint32_t hri_dsu_cid0_reg_t; -typedef uint32_t hri_dsu_cid1_reg_t; -typedef uint32_t hri_dsu_cid2_reg_t; -typedef uint32_t hri_dsu_cid3_reg_t; -typedef uint32_t hri_dsu_data_reg_t; -typedef uint32_t hri_dsu_dcc_reg_t; -typedef uint32_t hri_dsu_dcfg_reg_t; -typedef uint32_t hri_dsu_did_reg_t; -typedef uint32_t hri_dsu_end_reg_t; -typedef uint32_t hri_dsu_entry0_reg_t; -typedef uint32_t hri_dsu_entry1_reg_t; -typedef uint32_t hri_dsu_length_reg_t; -typedef uint32_t hri_dsu_memtype_reg_t; -typedef uint32_t hri_dsu_pid0_reg_t; -typedef uint32_t hri_dsu_pid1_reg_t; -typedef uint32_t hri_dsu_pid2_reg_t; -typedef uint32_t hri_dsu_pid3_reg_t; -typedef uint32_t hri_dsu_pid4_reg_t; -typedef uint32_t hri_dsu_pid5_reg_t; -typedef uint32_t hri_dsu_pid6_reg_t; -typedef uint32_t hri_dsu_pid7_reg_t; -typedef uint8_t hri_dsu_ctrl_reg_t; -typedef uint8_t hri_dsu_statusa_reg_t; -typedef uint8_t hri_dsu_statusb_reg_t; - -static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; -} - -static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; -} - -static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dsu *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) -{ - return ((Dsu *)hw)->STATUSB.reg; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DID.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) -{ - return ((Dsu *)hw)->DID.reg; -} - -static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; -} - -static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ENTRY0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) -{ - return ((Dsu *)hw)->ENTRY0.reg; -} - -static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ENTRY1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) -{ - return ((Dsu *)hw)->ENTRY1.reg; -} - -static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) -{ - return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; -} - -static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) -{ - return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; -} - -static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->END.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) -{ - return ((Dsu *)hw)->END.reg; -} - -static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) -{ - return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; -} - -static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MEMTYPE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) -{ - return ((Dsu *)hw)->MEMTYPE.reg; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID4.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID4.reg; -} - -static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID5.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID5.reg; -} - -static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID6.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID6.reg; -} - -static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID7.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID7.reg; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) -{ - return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID0.reg; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID1.reg; -} - -static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID2.reg; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID3.reg; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) -{ - return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID0.reg; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID1.reg; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) -{ - return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID2.reg; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) -{ - return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID3.reg; -} - -static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; - return tmp; -} - -static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= ~DSU_ADDR_AMOD_Msk; - tmp |= DSU_ADDR_AMOD(data); - ((Dsu *)hw)->ADDR.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; - return tmp; -} - -static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= ~DSU_ADDR_ADDR_Msk; - tmp |= DSU_ADDR_ADDR(data); - ((Dsu *)hw)->ADDR.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) -{ - return ((Dsu *)hw)->ADDR.reg; -} - -static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; - return tmp; -} - -static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp &= ~DSU_LENGTH_LENGTH_Msk; - tmp |= DSU_LENGTH_LENGTH(data); - ((Dsu *)hw)->LENGTH.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; - return tmp; -} - -static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) -{ - return ((Dsu *)hw)->LENGTH.reg; -} - -static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DATA.reg; - tmp &= ~DSU_DATA_DATA_Msk; - tmp |= DSU_DATA_DATA(data); - ((Dsu *)hw)->DATA.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) -{ - return ((Dsu *)hw)->DATA.reg; -} - -static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp &= ~DSU_DCC_DATA_Msk; - tmp |= DSU_DCC_DATA(data); - ((Dsu *)hw)->DCC[index].reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) -{ - return ((Dsu *)hw)->DCC[index].reg; -} - -static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos; - return tmp; -} - -static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp &= ~DSU_DCFG_DCFG_Msk; - tmp |= DSU_DCFG_DCFG(data); - ((Dsu *)hw)->DCFG[index].reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos; - return tmp; -} - -static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index) -{ - return ((Dsu *)hw)->DCFG[index].reg; -} - -static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; -} - -static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; -} - -static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; -} - -static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; -} - -static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; -} - -static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dsu *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) -{ - return ((Dsu *)hw)->STATUSA.reg; -} - -static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CTRL.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DSU_L22_H_INCLUDED */ -#endif /* _SAML22_DSU_COMPONENT_ */ diff --git a/watch-library/hri/hri_eic_l22.h b/watch-library/hri/hri_eic_l22.h deleted file mode 100644 index 058012bf..00000000 --- a/watch-library/hri/hri_eic_l22.h +++ /dev/null @@ -1,1463 +0,0 @@ -/** - * \file - * - * \brief SAM EIC - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_EIC_COMPONENT_ -#ifndef _HRI_EIC_L22_H_INCLUDED_ -#define _HRI_EIC_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_EIC_CRITICAL_SECTIONS) -#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define EIC_CRITICAL_SECTION_ENTER() -#define EIC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_eic_nmiflag_reg_t; -typedef uint32_t hri_eic_asynch_reg_t; -typedef uint32_t hri_eic_config_reg_t; -typedef uint32_t hri_eic_evctrl_reg_t; -typedef uint32_t hri_eic_intenset_reg_t; -typedef uint32_t hri_eic_intflag_reg_t; -typedef uint32_t hri_eic_syncbusy_reg_t; -typedef uint8_t hri_eic_ctrla_reg_t; -typedef uint8_t hri_eic_nmictrl_reg_t; - -static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) -{ - while (((Eic *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) -{ - return ((Eic *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) -{ - return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; -} - -static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) -{ - ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; -} - -static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Eic *)hw)->NMIFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) -{ - return ((Eic *)hw)->NMIFLAG.reg; -} - -static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) -{ - ((Eic *)hw)->NMIFLAG.reg = mask; -} - -static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) -{ - return ((Eic *)hw)->INTFLAG.reg; -} - -static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) -{ - ((Eic *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); -} - -static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; - return tmp; -} - -static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; - return tmp; -} - -static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); - ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); -} - -static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); -} - -static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENSET.reg = mask; -} - -static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) -{ - return ((Eic *)hw)->INTENSET.reg; -} - -static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) -{ - ((Eic *)hw)->INTENSET.reg = data; - ((Eic *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Eic *)hw)->SYNCBUSY.reg; -} - -static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= ~EIC_CTRLA_ENABLE; - tmp |= value << EIC_CTRLA_ENABLE_Pos; - ((Eic *)hw)->CTRLA.reg = tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= ~EIC_CTRLA_CKSEL; - tmp |= value << EIC_CTRLA_CKSEL_Pos; - ((Eic *)hw)->CTRLA.reg = tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= mask; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg = data; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg &= ~mask; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg ^= mask; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) -{ - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - return ((Eic *)hw)->CTRLA.reg; -} - -static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMIFILTEN; - tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMIASYNCH; - tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; - return tmp; -} - -static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMISENSE_Msk; - tmp |= EIC_NMICTRL_NMISENSE(data); - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; - return tmp; -} - -static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) -{ - return ((Eic *)hw)->NMICTRL.reg; -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; - return tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; - tmp |= EIC_EVCTRL_EXTINTEO(data); - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; - return tmp; -} - -static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) -{ - return ((Eic *)hw)->EVCTRL.reg; -} - -static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; - return tmp; -} - -static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp &= ~EIC_ASYNCH_ASYNCH_Msk; - tmp |= EIC_ASYNCH_ASYNCH(data); - ((Eic *)hw)->ASYNCH.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; - return tmp; -} - -static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) -{ - return ((Eic *)hw)->ASYNCH.reg; -} - -static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN0; - tmp |= value << EIC_CONFIG_FILTEN0_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN1; - tmp |= value << EIC_CONFIG_FILTEN1_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN2; - tmp |= value << EIC_CONFIG_FILTEN2_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN3; - tmp |= value << EIC_CONFIG_FILTEN3_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN4; - tmp |= value << EIC_CONFIG_FILTEN4_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN5; - tmp |= value << EIC_CONFIG_FILTEN5_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN6; - tmp |= value << EIC_CONFIG_FILTEN6_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN7; - tmp |= value << EIC_CONFIG_FILTEN7_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE0_Msk; - tmp |= EIC_CONFIG_SENSE0(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE1_Msk; - tmp |= EIC_CONFIG_SENSE1(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE2_Msk; - tmp |= EIC_CONFIG_SENSE2(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE3_Msk; - tmp |= EIC_CONFIG_SENSE3(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE4_Msk; - tmp |= EIC_CONFIG_SENSE4(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE5_Msk; - tmp |= EIC_CONFIG_SENSE5(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE6_Msk; - tmp |= EIC_CONFIG_SENSE6(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE7_Msk; - tmp |= EIC_CONFIG_SENSE7(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) -{ - return ((Eic *)hw)->CONFIG[index].reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_EIC_L22_H_INCLUDED */ -#endif /* _SAML22_EIC_COMPONENT_ */ diff --git a/watch-library/hri/hri_evsys_l22.h b/watch-library/hri/hri_evsys_l22.h deleted file mode 100644 index a2964f94..00000000 --- a/watch-library/hri/hri_evsys_l22.h +++ /dev/null @@ -1,1333 +0,0 @@ -/** - * \file - * - * \brief SAM EVSYS - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_EVSYS_COMPONENT_ -#ifndef _HRI_EVSYS_L22_H_INCLUDED_ -#define _HRI_EVSYS_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) -#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define EVSYS_CRITICAL_SECTION_ENTER() -#define EVSYS_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_evsys_channel_reg_t; -typedef uint32_t hri_evsys_chstatus_reg_t; -typedef uint32_t hri_evsys_intenset_reg_t; -typedef uint32_t hri_evsys_intflag_reg_t; -typedef uint32_t hri_evsys_swevt_reg_t; -typedef uint32_t hri_evsys_user_reg_t; -typedef uint8_t hri_evsys_ctrla_reg_t; - -static inline bool hri_evsys_get_INTFLAG_OVR0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; -} - -static inline bool hri_evsys_get_INTFLAG_OVR1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; -} - -static inline bool hri_evsys_get_INTFLAG_OVR2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; -} - -static inline bool hri_evsys_get_INTFLAG_OVR3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; -} - -static inline bool hri_evsys_get_INTFLAG_OVR4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; -} - -static inline bool hri_evsys_get_INTFLAG_OVR5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; -} - -static inline bool hri_evsys_get_INTFLAG_OVR6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; -} - -static inline bool hri_evsys_get_INTFLAG_OVR7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; -} - -static inline bool hri_evsys_get_INTFLAG_EVD0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; -} - -static inline bool hri_evsys_get_INTFLAG_EVD1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; -} - -static inline bool hri_evsys_get_INTFLAG_EVD2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; -} - -static inline bool hri_evsys_get_INTFLAG_EVD3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; -} - -static inline bool hri_evsys_get_INTFLAG_EVD4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; -} - -static inline bool hri_evsys_get_INTFLAG_EVD5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; -} - -static inline bool hri_evsys_get_INTFLAG_EVD6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; -} - -static inline bool hri_evsys_get_INTFLAG_EVD7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; -} - -static inline bool hri_evsys_get_interrupt_OVR0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; -} - -static inline bool hri_evsys_get_interrupt_OVR1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; -} - -static inline bool hri_evsys_get_interrupt_OVR2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; -} - -static inline bool hri_evsys_get_interrupt_OVR3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; -} - -static inline bool hri_evsys_get_interrupt_OVR4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; -} - -static inline bool hri_evsys_get_interrupt_OVR5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; -} - -static inline bool hri_evsys_get_interrupt_OVR6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; -} - -static inline bool hri_evsys_get_interrupt_OVR7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; -} - -static inline bool hri_evsys_get_interrupt_EVD0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; -} - -static inline bool hri_evsys_get_interrupt_EVD1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; -} - -static inline bool hri_evsys_get_interrupt_EVD2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; -} - -static inline bool hri_evsys_get_interrupt_EVD3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; -} - -static inline bool hri_evsys_get_interrupt_EVD4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; -} - -static inline bool hri_evsys_get_interrupt_EVD5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; -} - -static inline bool hri_evsys_get_interrupt_EVD6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; -} - -static inline bool hri_evsys_get_interrupt_EVD7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; -} - -static inline hri_evsys_intflag_reg_t hri_evsys_get_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_intflag_reg_t hri_evsys_read_INTFLAG_reg(const void *const hw) -{ - return ((Evsys *)hw)->INTFLAG.reg; -} - -static inline void hri_evsys_clear_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) -{ - ((Evsys *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; -} - -static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; - } -} - -static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; -} - -static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; -} - -static inline bool hri_evsys_get_INTEN_OVR1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; - } -} - -static inline void hri_evsys_clear_INTEN_OVR1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; -} - -static inline void hri_evsys_set_INTEN_OVR2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; -} - -static inline bool hri_evsys_get_INTEN_OVR2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; - } -} - -static inline void hri_evsys_clear_INTEN_OVR2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; -} - -static inline void hri_evsys_set_INTEN_OVR3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; -} - -static inline bool hri_evsys_get_INTEN_OVR3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR3) >> EVSYS_INTENSET_OVR3_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; - } -} - -static inline void hri_evsys_clear_INTEN_OVR3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; -} - -static inline void hri_evsys_set_INTEN_OVR4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; -} - -static inline bool hri_evsys_get_INTEN_OVR4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR4) >> EVSYS_INTENSET_OVR4_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; - } -} - -static inline void hri_evsys_clear_INTEN_OVR4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; -} - -static inline void hri_evsys_set_INTEN_OVR5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; -} - -static inline bool hri_evsys_get_INTEN_OVR5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR5) >> EVSYS_INTENSET_OVR5_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; - } -} - -static inline void hri_evsys_clear_INTEN_OVR5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; -} - -static inline void hri_evsys_set_INTEN_OVR6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; -} - -static inline bool hri_evsys_get_INTEN_OVR6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR6) >> EVSYS_INTENSET_OVR6_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; - } -} - -static inline void hri_evsys_clear_INTEN_OVR6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; -} - -static inline void hri_evsys_set_INTEN_OVR7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; -} - -static inline bool hri_evsys_get_INTEN_OVR7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR7) >> EVSYS_INTENSET_OVR7_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; - } -} - -static inline void hri_evsys_clear_INTEN_OVR7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; -} - -static inline void hri_evsys_set_INTEN_EVD0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; -} - -static inline bool hri_evsys_get_INTEN_EVD0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD0) >> EVSYS_INTENSET_EVD0_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; - } -} - -static inline void hri_evsys_clear_INTEN_EVD0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; -} - -static inline void hri_evsys_set_INTEN_EVD1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; -} - -static inline bool hri_evsys_get_INTEN_EVD1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD1) >> EVSYS_INTENSET_EVD1_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; - } -} - -static inline void hri_evsys_clear_INTEN_EVD1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; -} - -static inline void hri_evsys_set_INTEN_EVD2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; -} - -static inline bool hri_evsys_get_INTEN_EVD2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD2) >> EVSYS_INTENSET_EVD2_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; - } -} - -static inline void hri_evsys_clear_INTEN_EVD2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; -} - -static inline void hri_evsys_set_INTEN_EVD3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; -} - -static inline bool hri_evsys_get_INTEN_EVD3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD3) >> EVSYS_INTENSET_EVD3_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; - } -} - -static inline void hri_evsys_clear_INTEN_EVD3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; -} - -static inline void hri_evsys_set_INTEN_EVD4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; -} - -static inline bool hri_evsys_get_INTEN_EVD4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD4) >> EVSYS_INTENSET_EVD4_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; - } -} - -static inline void hri_evsys_clear_INTEN_EVD4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; -} - -static inline void hri_evsys_set_INTEN_EVD5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; -} - -static inline bool hri_evsys_get_INTEN_EVD5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD5) >> EVSYS_INTENSET_EVD5_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; - } -} - -static inline void hri_evsys_clear_INTEN_EVD5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; -} - -static inline void hri_evsys_set_INTEN_EVD6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; -} - -static inline bool hri_evsys_get_INTEN_EVD6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD6) >> EVSYS_INTENSET_EVD6_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; - } -} - -static inline void hri_evsys_clear_INTEN_EVD6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; -} - -static inline void hri_evsys_set_INTEN_EVD7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; -} - -static inline bool hri_evsys_get_INTEN_EVD7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD7) >> EVSYS_INTENSET_EVD7_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; - } -} - -static inline void hri_evsys_clear_INTEN_EVD7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; -} - -static inline void hri_evsys_set_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) -{ - ((Evsys *)hw)->INTENSET.reg = mask; -} - -static inline hri_evsys_intenset_reg_t hri_evsys_get_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_intenset_reg_t hri_evsys_read_INTEN_reg(const void *const hw) -{ - return ((Evsys *)hw)->INTENSET.reg; -} - -static inline void hri_evsys_write_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t data) -{ - ((Evsys *)hw)->INTENSET.reg = data; - ((Evsys *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_evsys_clear_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) -{ - ((Evsys *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY0_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY0) >> EVSYS_CHSTATUS_USRRDY0_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY1_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY1) >> EVSYS_CHSTATUS_USRRDY1_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY2_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY2) >> EVSYS_CHSTATUS_USRRDY2_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY3_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY3) >> EVSYS_CHSTATUS_USRRDY3_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY4_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY4) >> EVSYS_CHSTATUS_USRRDY4_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY5_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY5) >> EVSYS_CHSTATUS_USRRDY5_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY6_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY6) >> EVSYS_CHSTATUS_USRRDY6_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY7_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY7) >> EVSYS_CHSTATUS_USRRDY7_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY0_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY0) >> EVSYS_CHSTATUS_CHBUSY0_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY1_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY1) >> EVSYS_CHSTATUS_CHBUSY1_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY2_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY2) >> EVSYS_CHSTATUS_CHBUSY2_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY3_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY3) >> EVSYS_CHSTATUS_CHBUSY3_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY4_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY4) >> EVSYS_CHSTATUS_CHBUSY4_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY5_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY5) >> EVSYS_CHSTATUS_CHBUSY5_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY6_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY6) >> EVSYS_CHSTATUS_CHBUSY6_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY7_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY7) >> EVSYS_CHSTATUS_CHBUSY7_Pos; -} - -static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, hri_evsys_chstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw) -{ - return ((Evsys *)hw)->CHSTATUS.reg; -} - -static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->CTRLA.reg; - tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) -{ - return ((Evsys *)hw)->CTRLA.reg; -} - -static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp &= ~EVSYS_CHANNEL_RUNSTDBY; - tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; - ((Evsys *)hw)->CHANNEL[index].reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp &= ~EVSYS_CHANNEL_ONDEMAND; - tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; - ((Evsys *)hw)->CHANNEL[index].reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; - tmp |= EVSYS_CHANNEL_EVGEN(data); - ((Evsys *)hw)->CHANNEL[index].reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp &= ~EVSYS_CHANNEL_PATH_Msk; - tmp |= EVSYS_CHANNEL_PATH(data); - ((Evsys *)hw)->CHANNEL[index].reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; - tmp |= EVSYS_CHANNEL_EDGSEL(data); - ((Evsys *)hw)->CHANNEL[index].reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL[index].reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t index) -{ - return ((Evsys *)hw)->CHANNEL[index].reg; -} - -static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, - hri_evsys_user_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->USER[index].reg; - tmp &= ~EVSYS_USER_CHANNEL_Msk; - tmp |= EVSYS_USER_CHANNEL(data); - ((Evsys *)hw)->USER[index].reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, - hri_evsys_user_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) -{ - return ((Evsys *)hw)->USER[index].reg; -} - -static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->SWEVT.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_EVSYS_L22_H_INCLUDED */ -#endif /* _SAML22_EVSYS_COMPONENT_ */ diff --git a/watch-library/hri/hri_freqm_l22.h b/watch-library/hri/hri_freqm_l22.h deleted file mode 100644 index e221bbfd..00000000 --- a/watch-library/hri/hri_freqm_l22.h +++ /dev/null @@ -1,464 +0,0 @@ -/** - * \file - * - * \brief SAM FREQM - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_FREQM_COMPONENT_ -#ifndef _HRI_FREQM_L22_H_INCLUDED_ -#define _HRI_FREQM_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) -#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define FREQM_CRITICAL_SECTION_ENTER() -#define FREQM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_freqm_cfga_reg_t; -typedef uint32_t hri_freqm_syncbusy_reg_t; -typedef uint32_t hri_freqm_value_reg_t; -typedef uint8_t hri_freqm_ctrla_reg_t; -typedef uint8_t hri_freqm_ctrlb_reg_t; -typedef uint8_t hri_freqm_intenset_reg_t; -typedef uint8_t hri_freqm_intflag_reg_t; -typedef uint8_t hri_freqm_status_reg_t; - -static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) -{ - while (((Freqm *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) -{ - return ((Freqm *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; -} - -static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; -} - -static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; -} - -static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; -} - -static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) -{ - return ((Freqm *)hw)->INTFLAG.reg; -} - -static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) -{ - ((Freqm *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; -} - -static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; -} - -static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; - } else { - ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; - } -} - -static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; -} - -static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - ((Freqm *)hw)->INTENSET.reg = mask; -} - -static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) -{ - return ((Freqm *)hw)->INTENSET.reg; -} - -static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) -{ - ((Freqm *)hw)->INTENSET.reg = data; - ((Freqm *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - ((Freqm *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Freqm *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Freqm *)hw)->SYNCBUSY.reg; -} - -static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) -{ - return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; -} - -static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) -{ - return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; -} - -static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) -{ - uint32_t tmp; - tmp = ((Freqm *)hw)->VALUE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) -{ - return ((Freqm *)hw)->VALUE.reg; -} - -static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - FREQM_CRITICAL_SECTION_ENTER(); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp &= ~FREQM_CTRLA_ENABLE; - tmp |= value << FREQM_CTRLA_ENABLE_Pos; - ((Freqm *)hw)->CTRLA.reg = tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg |= mask; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg = data; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg &= ~mask; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg ^= mask; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) -{ - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - return ((Freqm *)hw)->CTRLA.reg; -} - -static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; - return tmp; -} - -static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) -{ - uint16_t tmp; - FREQM_CRITICAL_SECTION_ENTER(); - tmp = ((Freqm *)hw)->CFGA.reg; - tmp &= ~FREQM_CFGA_REFNUM_Msk; - tmp |= FREQM_CFGA_REFNUM(data); - ((Freqm *)hw)->CFGA.reg = tmp; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; - return tmp; -} - -static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg |= mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg = data; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg &= ~mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg ^= mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) -{ - return ((Freqm *)hw)->CFGA.reg; -} - -static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) -{ - return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; -} - -static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) -{ - return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; -} - -static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) -{ - return ((Freqm *)hw)->STATUS.reg; -} - -static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLB.reg = data; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_FREQM_L22_H_INCLUDED */ -#endif /* _SAML22_FREQM_COMPONENT_ */ diff --git a/watch-library/hri/hri_gclk_l22.h b/watch-library/hri/hri_gclk_l22.h deleted file mode 100644 index 2ae6d491..00000000 --- a/watch-library/hri/hri_gclk_l22.h +++ /dev/null @@ -1,770 +0,0 @@ -/** - * \file - * - * \brief SAM GCLK - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_GCLK_COMPONENT_ -#ifndef _HRI_GCLK_L22_H_INCLUDED_ -#define _HRI_GCLK_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) -#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define GCLK_CRITICAL_SECTION_ENTER() -#define GCLK_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_gclk_genctrl_reg_t; -typedef uint32_t hri_gclk_pchctrl_reg_t; -typedef uint32_t hri_gclk_syncbusy_reg_t; -typedef uint8_t hri_gclk_ctrla_reg_t; - -static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) -{ - while (((Gclk *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) -{ - return ((Gclk *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; -} - -static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Gclk *)hw)->SYNCBUSY.reg; -} - -static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - tmp = ((Gclk *)hw)->CTRLA.reg; - tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg |= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - tmp = ((Gclk *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg = data; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg &= ~mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg ^= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) -{ - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - return ((Gclk *)hw)->CTRLA.reg; -} - -static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_GENEN; - tmp |= value << GCLK_GENCTRL_GENEN_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_IDC; - tmp |= value << GCLK_GENCTRL_IDC_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_OOV; - tmp |= value << GCLK_GENCTRL_OOV_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_OE; - tmp |= value << GCLK_GENCTRL_OE_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_DIVSEL; - tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_RUNSTDBY; - tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_SRC_Msk; - tmp |= GCLK_GENCTRL_SRC(data); - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_DIV_Msk; - tmp |= GCLK_GENCTRL_DIV(data); - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg = data; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) -{ - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - return ((Gclk *)hw)->GENCTRL[index].reg; -} - -static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_CHEN; - tmp |= value << GCLK_PCHCTRL_CHEN_Pos; - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_WRTLOCK; - tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, - hri_gclk_pchctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; - return tmp; -} - -static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_GEN_Msk; - tmp |= GCLK_PCHCTRL_GEN(data); - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; - return tmp; -} - -static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, - hri_gclk_pchctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg = data; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Gclk *)hw)->PCHCTRL[index].reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_GCLK_L22_H_INCLUDED */ -#endif /* _SAML22_GCLK_COMPONENT_ */ diff --git a/watch-library/hri/hri_l22.h b/watch-library/hri/hri_l22.h deleted file mode 100644 index d99268c1..00000000 --- a/watch-library/hri/hri_l22.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * \file - * - * \brief SAM L22 HRI top-level header file - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HRI_L22_H_INCLUDED_ -#define _HRI_L22_H_INCLUDED_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#endif /* _HRI_L22_H_INCLUDED_ */ diff --git a/watch-library/hri/hri_mclk_l22.h b/watch-library/hri/hri_mclk_l22.h deleted file mode 100644 index b03c0064..00000000 --- a/watch-library/hri/hri_mclk_l22.h +++ /dev/null @@ -1,2300 +0,0 @@ -/** - * \file - * - * \brief SAM MCLK - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_MCLK_COMPONENT_ -#ifndef _HRI_MCLK_L22_H_INCLUDED_ -#define _HRI_MCLK_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) -#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define MCLK_CRITICAL_SECTION_ENTER() -#define MCLK_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_mclk_ahbmask_reg_t; -typedef uint32_t hri_mclk_apbamask_reg_t; -typedef uint32_t hri_mclk_apbbmask_reg_t; -typedef uint32_t hri_mclk_apbcmask_reg_t; -typedef uint8_t hri_mclk_bupdiv_reg_t; -typedef uint8_t hri_mclk_cpudiv_reg_t; -typedef uint8_t hri_mclk_intenset_reg_t; -typedef uint8_t hri_mclk_intflag_reg_t; - -static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; -} - -static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; -} - -static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; -} - -static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; -} - -static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) -{ - return ((Mclk *)hw)->INTFLAG.reg; -} - -static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) -{ - ((Mclk *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; -} - -static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; -} - -static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; - } else { - ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; - } -} - -static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; -} - -static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - ((Mclk *)hw)->INTENSET.reg = mask; -} - -static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) -{ - return ((Mclk *)hw)->INTENSET.reg; -} - -static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) -{ - ((Mclk *)hw)->INTENSET.reg = data; - ((Mclk *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - ((Mclk *)hw)->INTENCLR.reg = mask; -} - -static inline void hri_mclk_set_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp = (tmp & MCLK_CPUDIV_CPUDIV(mask)) >> MCLK_CPUDIV_CPUDIV_Pos; - return tmp; -} - -static inline void hri_mclk_write_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) -{ - uint8_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp &= ~MCLK_CPUDIV_CPUDIV_Msk; - tmp |= MCLK_CPUDIV_CPUDIV(data); - ((Mclk *)hw)->CPUDIV.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_CPUDIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_CPUDIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_CPUDIV_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp = (tmp & MCLK_CPUDIV_CPUDIV_Msk) >> MCLK_CPUDIV_CPUDIV_Pos; - return tmp; -} - -static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) -{ - return ((Mclk *)hw)->CPUDIV.reg; -} - -static inline void hri_mclk_set_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->BUPDIV.reg |= MCLK_BUPDIV_BUPDIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->BUPDIV.reg; - tmp = (tmp & MCLK_BUPDIV_BUPDIV(mask)) >> MCLK_BUPDIV_BUPDIV_Pos; - return tmp; -} - -static inline void hri_mclk_write_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t data) -{ - uint8_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->BUPDIV.reg; - tmp &= ~MCLK_BUPDIV_BUPDIV_Msk; - tmp |= MCLK_BUPDIV_BUPDIV(data); - ((Mclk *)hw)->BUPDIV.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->BUPDIV.reg &= ~MCLK_BUPDIV_BUPDIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->BUPDIV.reg ^= MCLK_BUPDIV_BUPDIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_BUPDIV_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->BUPDIV.reg; - tmp = (tmp & MCLK_BUPDIV_BUPDIV_Msk) >> MCLK_BUPDIV_BUPDIV_Pos; - return tmp; -} - -static inline void hri_mclk_set_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->BUPDIV.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->BUPDIV.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->BUPDIV.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->BUPDIV.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->BUPDIV.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_reg(const void *const hw) -{ - return ((Mclk *)hw)->BUPDIV.reg; -} - -static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB0; - tmp |= value << MCLK_AHBMASK_HPB0_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB1; - tmp |= value << MCLK_AHBMASK_HPB1_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB2; - tmp |= value << MCLK_AHBMASK_HPB2_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_DMAC; - tmp |= value << MCLK_AHBMASK_DMAC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_USB; - tmp |= value << MCLK_AHBMASK_USB_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_DSU; - tmp |= value << MCLK_AHBMASK_DSU_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_PAC; - tmp |= value << MCLK_AHBMASK_PAC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_NVMCTRL; - tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HSRAM; - tmp |= value << MCLK_AHBMASK_HSRAM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_PICACHU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_NVMCTRL_PICACHU) >> MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; - tmp |= value << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_PICACHU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->AHBMASK.reg; -} - -static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_PAC; - tmp |= value << MCLK_APBAMASK_PAC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_PM; - tmp |= value << MCLK_APBAMASK_PM_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_MCLK; - tmp |= value << MCLK_APBAMASK_MCLK_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_RSTC; - tmp |= value << MCLK_APBAMASK_RSTC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_OSCCTRL; - tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_OSC32KCTRL; - tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_SUPC; - tmp |= value << MCLK_APBAMASK_SUPC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_GCLK; - tmp |= value << MCLK_APBAMASK_GCLK_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_WDT; - tmp |= value << MCLK_APBAMASK_WDT_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_RTC; - tmp |= value << MCLK_APBAMASK_RTC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_EIC; - tmp |= value << MCLK_APBAMASK_EIC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_FREQM; - tmp |= value << MCLK_APBAMASK_FREQM_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBAMASK.reg; -} - -static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_USB; - tmp |= value << MCLK_APBBMASK_USB_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_DSU; - tmp |= value << MCLK_APBBMASK_DSU_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_NVMCTRL; - tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_PORT; - tmp |= value << MCLK_APBBMASK_PORT_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBBMASK.reg; -} - -static inline void hri_mclk_set_APBCMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_EVSYS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_EVSYS) >> MCLK_APBCMASK_EVSYS_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_EVSYS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_EVSYS; - tmp |= value << MCLK_APBCMASK_EVSYS_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_SERCOM0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_SERCOM0) >> MCLK_APBCMASK_SERCOM0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_SERCOM0; - tmp |= value << MCLK_APBCMASK_SERCOM0_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_SERCOM1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_SERCOM1) >> MCLK_APBCMASK_SERCOM1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_SERCOM1; - tmp |= value << MCLK_APBCMASK_SERCOM1_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_SERCOM2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_SERCOM2) >> MCLK_APBCMASK_SERCOM2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_SERCOM2; - tmp |= value << MCLK_APBCMASK_SERCOM2_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_SERCOM3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_SERCOM3) >> MCLK_APBCMASK_SERCOM3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_SERCOM3; - tmp |= value << MCLK_APBCMASK_SERCOM3_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_SERCOM4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_SERCOM4) >> MCLK_APBCMASK_SERCOM4_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_SERCOM4; - tmp |= value << MCLK_APBCMASK_SERCOM4_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_SERCOM5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_SERCOM5) >> MCLK_APBCMASK_SERCOM5_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_SERCOM5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_SERCOM5; - tmp |= value << MCLK_APBCMASK_SERCOM5_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TCC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TCC0) >> MCLK_APBCMASK_TCC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TCC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TCC0; - tmp |= value << MCLK_APBCMASK_TCC0_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TC0) >> MCLK_APBCMASK_TC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TC0; - tmp |= value << MCLK_APBCMASK_TC0_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TC1) >> MCLK_APBCMASK_TC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TC1; - tmp |= value << MCLK_APBCMASK_TC1_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TC2) >> MCLK_APBCMASK_TC2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TC2; - tmp |= value << MCLK_APBCMASK_TC2_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TC3) >> MCLK_APBCMASK_TC3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TC3; - tmp |= value << MCLK_APBCMASK_TC3_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_ADC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ADC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_ADC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_ADC) >> MCLK_APBCMASK_ADC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_ADC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_ADC; - tmp |= value << MCLK_APBCMASK_ADC_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_ADC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ADC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_ADC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ADC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_AC; - tmp |= value << MCLK_APBCMASK_AC_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_PTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_PTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_PTC) >> MCLK_APBCMASK_PTC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_PTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_PTC; - tmp |= value << MCLK_APBCMASK_PTC_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_PTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_PTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_SLCD_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SLCD; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_SLCD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_SLCD) >> MCLK_APBCMASK_SLCD_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_SLCD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_SLCD; - tmp |= value << MCLK_APBCMASK_SLCD_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_SLCD_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SLCD; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_SLCD_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SLCD; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_AES; - tmp |= value << MCLK_APBCMASK_AES_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TRNG; - tmp |= value << MCLK_APBCMASK_TRNG_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_CCL; - tmp |= value << MCLK_APBCMASK_CCL_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBCMASK.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_MCLK_L22_H_INCLUDED */ -#endif /* _SAML22_MCLK_COMPONENT_ */ diff --git a/watch-library/hri/hri_mtb_l22.h b/watch-library/hri/hri_mtb_l22.h deleted file mode 100644 index f8cb66d5..00000000 --- a/watch-library/hri/hri_mtb_l22.h +++ /dev/null @@ -1,551 +0,0 @@ -/** - * \file - * - * \brief SAM MTB - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_MTB_COMPONENT_ -#ifndef _HRI_MTB_L22_H_INCLUDED_ -#define _HRI_MTB_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_MTB_CRITICAL_SECTIONS) -#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define MTB_CRITICAL_SECTION_ENTER() -#define MTB_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_mtb_authstatus_reg_t; -typedef uint32_t hri_mtb_base_reg_t; -typedef uint32_t hri_mtb_cid0_reg_t; -typedef uint32_t hri_mtb_cid1_reg_t; -typedef uint32_t hri_mtb_cid2_reg_t; -typedef uint32_t hri_mtb_cid3_reg_t; -typedef uint32_t hri_mtb_claimset_reg_t; -typedef uint32_t hri_mtb_devarch_reg_t; -typedef uint32_t hri_mtb_devid_reg_t; -typedef uint32_t hri_mtb_devtype_reg_t; -typedef uint32_t hri_mtb_flow_reg_t; -typedef uint32_t hri_mtb_itctrl_reg_t; -typedef uint32_t hri_mtb_lockaccess_reg_t; -typedef uint32_t hri_mtb_lockstatus_reg_t; -typedef uint32_t hri_mtb_master_reg_t; -typedef uint32_t hri_mtb_pid0_reg_t; -typedef uint32_t hri_mtb_pid1_reg_t; -typedef uint32_t hri_mtb_pid2_reg_t; -typedef uint32_t hri_mtb_pid3_reg_t; -typedef uint32_t hri_mtb_pid4_reg_t; -typedef uint32_t hri_mtb_pid5_reg_t; -typedef uint32_t hri_mtb_pid6_reg_t; -typedef uint32_t hri_mtb_pid7_reg_t; -typedef uint32_t hri_mtb_position_reg_t; - -static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) -{ - ((Mtb *)hw)->CLAIMSET.reg = mask; -} - -static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->CLAIMSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw) -{ - return ((Mtb *)hw)->CLAIMSET.reg; -} - -static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data) -{ - ((Mtb *)hw)->CLAIMSET.reg = data; - ((Mtb *)hw)->CLAIMCLR.reg = ~data; -} - -static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) -{ - ((Mtb *)hw)->CLAIMCLR.reg = mask; -} - -static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->BASE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw) -{ - return ((Mtb *)hw)->BASE.reg; -} - -static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->LOCKSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw) -{ - return ((Mtb *)hw)->LOCKSTATUS.reg; -} - -static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->AUTHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw) -{ - return ((Mtb *)hw)->AUTHSTATUS.reg; -} - -static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->DEVARCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw) -{ - return ((Mtb *)hw)->DEVARCH.reg; -} - -static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->DEVID.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw) -{ - return ((Mtb *)hw)->DEVID.reg; -} - -static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->DEVTYPE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw) -{ - return ((Mtb *)hw)->DEVTYPE.reg; -} - -static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID4.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID4.reg; -} - -static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID5.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID5.reg; -} - -static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID6.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID6.reg; -} - -static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID7.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID7.reg; -} - -static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID0.reg; -} - -static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID1.reg; -} - -static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID2.reg; -} - -static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID3.reg; -} - -static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->CID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw) -{ - return ((Mtb *)hw)->CID0.reg; -} - -static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->CID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw) -{ - return ((Mtb *)hw)->CID1.reg; -} - -static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->CID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw) -{ - return ((Mtb *)hw)->CID2.reg; -} - -static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->CID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw) -{ - return ((Mtb *)hw)->CID3.reg; -} - -static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->POSITION.reg |= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->POSITION.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->POSITION.reg = data; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->POSITION.reg &= ~mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->POSITION.reg ^= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw) -{ - return ((Mtb *)hw)->POSITION.reg; -} - -static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->MASTER.reg |= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->MASTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->MASTER.reg = data; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->MASTER.reg &= ~mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->MASTER.reg ^= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw) -{ - return ((Mtb *)hw)->MASTER.reg; -} - -static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->FLOW.reg |= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->FLOW.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->FLOW.reg = data; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->FLOW.reg &= ~mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->FLOW.reg ^= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw) -{ - return ((Mtb *)hw)->FLOW.reg; -} - -static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->ITCTRL.reg |= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->ITCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->ITCTRL.reg = data; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->ITCTRL.reg &= ~mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->ITCTRL.reg ^= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw) -{ - return ((Mtb *)hw)->ITCTRL.reg; -} - -static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->LOCKACCESS.reg |= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->LOCKACCESS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->LOCKACCESS.reg = data; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->LOCKACCESS.reg &= ~mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->LOCKACCESS.reg ^= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw) -{ - return ((Mtb *)hw)->LOCKACCESS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_MTB_L22_H_INCLUDED */ -#endif /* _SAML22_MTB_COMPONENT_ */ diff --git a/watch-library/hri/hri_nvic_l22.h b/watch-library/hri/hri_nvic_l22.h deleted file mode 100644 index 5596c99a..00000000 --- a/watch-library/hri/hri_nvic_l22.h +++ /dev/null @@ -1,269 +0,0 @@ -/** - * \file - * - * \brief SAM NVIC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_NVIC_COMPONENT_ -#ifndef _HRI_NVIC_L22_H_INCLUDED_ -#define _HRI_NVIC_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_NVIC_CRITICAL_SECTIONS) -#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define NVIC_CRITICAL_SECTION_ENTER() -#define NVIC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_nvic_icer_reg_t; -typedef uint32_t hri_nvic_icpr_reg_t; -typedef uint32_t hri_nvic_ipr_reg_t; -typedef uint32_t hri_nvic_iser_reg_t; -typedef uint32_t hri_nvic_ispr_reg_t; - -static inline void hri_nvic_set_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ISER.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->ISER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_ISER_reg(const void *const hw, hri_nvic_iser_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ISER.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ISER.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ISER.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw) -{ - return ((Nvic *)hw)->ISER.reg; -} - -static inline void hri_nvic_set_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ICER.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->ICER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_ICER_reg(const void *const hw, hri_nvic_icer_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ICER.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ICER.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ICER.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw) -{ - return ((Nvic *)hw)->ICER.reg; -} - -static inline void hri_nvic_set_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ISPR.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->ISPR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ISPR.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ISPR.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ISPR.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw) -{ - return ((Nvic *)hw)->ISPR.reg; -} - -static inline void hri_nvic_set_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ICPR.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->ICPR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ICPR.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ICPR.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->ICPR.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw) -{ - return ((Nvic *)hw)->ICPR.reg; -} - -static inline void hri_nvic_set_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->IPR[index].reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_ipr_reg_t hri_nvic_get_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->IPR[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->IPR[index].reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->IPR[index].reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->IPR[index].reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_ipr_reg_t hri_nvic_read_IPR_reg(const void *const hw, uint8_t index) -{ - return ((Nvic *)hw)->IPR[index].reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_NVIC_L22_H_INCLUDED */ -#endif /* _SAML22_NVIC_COMPONENT_ */ diff --git a/watch-library/hri/hri_nvmctrl_l22.h b/watch-library/hri/hri_nvmctrl_l22.h deleted file mode 100644 index 07629fba..00000000 --- a/watch-library/hri/hri_nvmctrl_l22.h +++ /dev/null @@ -1,1104 +0,0 @@ -/** - * \file - * - * \brief SAM NVMCTRL - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_NVMCTRL_COMPONENT_ -#ifndef _HRI_NVMCTRL_L22_H_INCLUDED_ -#define _HRI_NVMCTRL_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) -#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define NVMCTRL_CRITICAL_SECTION_ENTER() -#define NVMCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_nvmctrl_ctrla_reg_t; -typedef uint16_t hri_nvmctrl_lock_reg_t; -typedef uint16_t hri_nvmctrl_status_reg_t; -typedef uint32_t hri_nvmctrl_addr_reg_t; -typedef uint32_t hri_nvmctrl_ctrlb_reg_t; -typedef uint32_t hri_nvmctrl_param_reg_t; -typedef uint8_t hri_nvmctrl_intenset_reg_t; -typedef uint8_t hri_nvmctrl_intflag_reg_t; - -static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; -} - -static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; -} - -static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; -} - -static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; -} - -static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, - hri_nvmctrl_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; -} - -static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; - } -} - -static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; -} - -static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; -} - -static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; - } -} - -static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; -} - -static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) -{ - ((Nvmctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, - hri_nvmctrl_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->INTENSET.reg; -} - -static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) -{ - ((Nvmctrl *)hw)->INTENSET.reg = data; - ((Nvmctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = mask; -} - -static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_CMD_Msk; - tmp |= NVMCTRL_CTRLA_CMD(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk; - tmp |= NVMCTRL_CTRLA_CMDEX(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->CTRLA.reg; -} - -static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= ~NVMCTRL_CTRLB_MANW; - tmp |= value << NVMCTRL_CTRLB_MANW_Pos; - ((Nvmctrl *)hw)->CTRLB.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLB_FWUP_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_FWUP; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLB_FWUP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_FWUP) >> NVMCTRL_CTRLB_FWUP_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_FWUP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= ~NVMCTRL_CTRLB_FWUP; - tmp |= value << NVMCTRL_CTRLB_FWUP_Pos; - ((Nvmctrl *)hw)->CTRLB.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_FWUP_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_FWUP; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_FWUP_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_FWUP; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLB_CACHEDIS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS) >> NVMCTRL_CTRLB_CACHEDIS_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= ~NVMCTRL_CTRLB_CACHEDIS; - tmp |= value << NVMCTRL_CTRLB_CACHEDIS_Pos; - ((Nvmctrl *)hw)->CTRLB.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= ~NVMCTRL_CTRLB_RWS_Msk; - tmp |= NVMCTRL_CTRLB_RWS(data); - ((Nvmctrl *)hw)->CTRLB.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const hw, - hri_nvmctrl_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk; - tmp |= NVMCTRL_CTRLB_SLEEPPRM(data); - ((Nvmctrl *)hw)->CTRLB.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const hw, - hri_nvmctrl_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= ~NVMCTRL_CTRLB_READMODE_Msk; - tmp |= NVMCTRL_CTRLB_READMODE(data); - ((Nvmctrl *)hw)->CTRLB.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->CTRLB.reg; -} - -static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp &= ~NVMCTRL_PARAM_NVMP_Msk; - tmp |= NVMCTRL_PARAM_NVMP(data); - ((Nvmctrl *)hw)->PARAM.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp &= ~NVMCTRL_PARAM_PSZ_Msk; - tmp |= NVMCTRL_PARAM_PSZ(data); - ((Nvmctrl *)hw)->PARAM.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_RWWEEP(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_RWWEEP_bf(const void *const hw, - hri_nvmctrl_param_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp = (tmp & NVMCTRL_PARAM_RWWEEP(mask)) >> NVMCTRL_PARAM_RWWEEP_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp &= ~NVMCTRL_PARAM_RWWEEP_Msk; - tmp |= NVMCTRL_PARAM_RWWEEP(data); - ((Nvmctrl *)hw)->PARAM.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_RWWEEP(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_RWWEEP(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_RWWEEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp = (tmp & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->PARAM.reg; -} - -static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp &= ~NVMCTRL_ADDR_ADDR_Msk; - tmp |= NVMCTRL_ADDR_ADDR(data); - ((Nvmctrl *)hw)->ADDR.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->ADDR.reg; -} - -static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->LOCK.reg; - tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->LOCK.reg; - tmp &= ~NVMCTRL_LOCK_LOCK_Msk; - tmp |= NVMCTRL_LOCK_LOCK(data); - ((Nvmctrl *)hw)->LOCK.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->LOCK.reg; - tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->LOCK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->LOCK.reg; -} - -static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_NVMCTRL_L22_H_INCLUDED */ -#endif /* _SAML22_NVMCTRL_COMPONENT_ */ diff --git a/watch-library/hri/hri_osc32kctrl_l22.h b/watch-library/hri/hri_osc32kctrl_l22.h deleted file mode 100644 index 44bb32ba..00000000 --- a/watch-library/hri/hri_osc32kctrl_l22.h +++ /dev/null @@ -1,1233 +0,0 @@ -/** - * \file - * - * \brief SAM OSC32KCTRL - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_OSC32KCTRL_COMPONENT_ -#ifndef _HRI_OSC32KCTRL_L22_H_INCLUDED_ -#define _HRI_OSC32KCTRL_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) -#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define OSC32KCTRL_CRITICAL_SECTION_ENTER() -#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; -typedef uint32_t hri_osc32kctrl_intenset_reg_t; -typedef uint32_t hri_osc32kctrl_intflag_reg_t; -typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; -typedef uint32_t hri_osc32kctrl_status_reg_t; -typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; -typedef uint8_t hri_osc32kctrl_evctrl_reg_t; -typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t; -typedef uint8_t hri_osc32kctrl_slcdctrl_reg_t; - -static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_INTFLAG_CLKFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_CLKFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL; -} - -static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_interrupt_CLKFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos; -} - -static inline void hri_osc32kctrl_clear_interrupt_CLKFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL; -} - -static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, - hri_osc32kctrl_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; - } else { - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; - } -} - -static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; -} - -static inline void hri_osc32kctrl_set_INTEN_CLKFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL; -} - -static inline bool hri_osc32kctrl_get_INTEN_CLKFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_CLKFAIL) >> OSC32KCTRL_INTENSET_CLKFAIL_Pos; -} - -static inline void hri_osc32kctrl_write_INTEN_CLKFAIL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL; - } else { - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL; - } -} - -static inline void hri_osc32kctrl_clear_INTEN_CLKFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL; -} - -static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, - hri_osc32kctrl_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->INTENSET.reg; -} - -static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = data; - ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; -} - -static inline bool hri_osc32kctrl_get_STATUS_CLKFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKFAIL) >> OSC32KCTRL_STATUS_CLKFAIL_Pos; -} - -static inline bool hri_osc32kctrl_get_STATUS_CLKSW_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKSW) >> OSC32KCTRL_STATUS_CLKSW_Pos; -} - -static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, - hri_osc32kctrl_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->STATUS.reg; -} - -static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, - hri_osc32kctrl_rtcctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; - tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); - ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, - hri_osc32kctrl_rtcctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->RTCCTRL.reg; -} - -static inline void hri_osc32kctrl_set_SLCDCTRL_SLCDSEL_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->SLCDCTRL.reg |= OSC32KCTRL_SLCDCTRL_SLCDSEL; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_SLCDCTRL_SLCDSEL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg; - tmp = (tmp & OSC32KCTRL_SLCDCTRL_SLCDSEL) >> OSC32KCTRL_SLCDCTRL_SLCDSEL_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_SLCDCTRL_SLCDSEL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg; - tmp &= ~OSC32KCTRL_SLCDCTRL_SLCDSEL; - tmp |= value << OSC32KCTRL_SLCDCTRL_SLCDSEL_Pos; - ((Osc32kctrl *)hw)->SLCDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_SLCDCTRL_SLCDSEL_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->SLCDCTRL.reg &= ~OSC32KCTRL_SLCDCTRL_SLCDSEL; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_SLCDCTRL_SLCDSEL_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->SLCDCTRL.reg ^= OSC32KCTRL_SLCDCTRL_SLCDSEL; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->SLCDCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_slcdctrl_reg_t hri_osc32kctrl_get_SLCDCTRL_reg(const void *const hw, - hri_osc32kctrl_slcdctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->SLCDCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->SLCDCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->SLCDCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_slcdctrl_reg_t hri_osc32kctrl_read_SLCDCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->SLCDCTRL.reg; -} - -static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; - tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; - tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_EN32K; - tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_EN1K; - tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; - tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; - tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; - tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, - hri_osc32kctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; - tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, - hri_osc32kctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->XOSC32K.reg; -} - -static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; - tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; - tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; - tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, - hri_osc32kctrl_cfdctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->CFDCTRL.reg; -} - -static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; - tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; - ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, - hri_osc32kctrl_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->EVCTRL.reg; -} - -static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_EN32K; - tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_EN1K; - tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; - tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, - hri_osc32kctrl_osculp32k_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; - tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, - hri_osc32kctrl_osculp32k_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->OSCULP32K.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_OSC32KCTRL_L22_H_INCLUDED */ -#endif /* _SAML22_OSC32KCTRL_COMPONENT_ */ diff --git a/watch-library/hri/hri_oscctrl_l22.h b/watch-library/hri/hri_oscctrl_l22.h deleted file mode 100644 index d1bc4b60..00000000 --- a/watch-library/hri/hri_oscctrl_l22.h +++ /dev/null @@ -1,3451 +0,0 @@ -/** - * \file - * - * \brief SAM OSCCTRL - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_OSCCTRL_COMPONENT_ -#ifndef _HRI_OSCCTRL_L22_H_INCLUDED_ -#define _HRI_OSCCTRL_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) -#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define OSCCTRL_CRITICAL_SECTION_ENTER() -#define OSCCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_oscctrl_dfllctrl_reg_t; -typedef uint16_t hri_oscctrl_xoscctrl_reg_t; -typedef uint32_t hri_oscctrl_dfllmul_reg_t; -typedef uint32_t hri_oscctrl_dfllval_reg_t; -typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; -typedef uint32_t hri_oscctrl_dpllratio_reg_t; -typedef uint32_t hri_oscctrl_intenset_reg_t; -typedef uint32_t hri_oscctrl_intflag_reg_t; -typedef uint32_t hri_oscctrl_status_reg_t; -typedef uint8_t hri_oscctrl_cfdpresc_reg_t; -typedef uint8_t hri_oscctrl_dfllsync_reg_t; -typedef uint8_t hri_oscctrl_dpllctrla_reg_t; -typedef uint8_t hri_oscctrl_dpllpresc_reg_t; -typedef uint8_t hri_oscctrl_dpllstatus_reg_t; -typedef uint8_t hri_oscctrl_dpllsyncbusy_reg_t; -typedef uint8_t hri_oscctrl_evctrl_reg_t; -typedef uint8_t hri_oscctrl_osc16mctrl_reg_t; - -static inline void hri_oscctrl_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) -{ - while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_oscctrl_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) -{ - return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL; -} - -static inline bool hri_oscctrl_get_INTFLAG_OSC16MRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_OSC16MRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLLLTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLLLTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLLLDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLLLDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCFAIL_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCFAIL_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL; -} - -static inline bool hri_oscctrl_get_interrupt_OSC16MRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_OSC16MRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; -} - -static inline bool hri_oscctrl_get_interrupt_DPLLLCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLLLCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; -} - -static inline bool hri_oscctrl_get_interrupt_DPLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; -} - -static inline bool hri_oscctrl_get_interrupt_DPLLLTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLLLTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; -} - -static inline bool hri_oscctrl_get_interrupt_DPLLLDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLLLDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; -} - -static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, - hri_oscctrl_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) -{ - ((Oscctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_oscctrl_set_INTEN_XOSCRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY) >> OSCCTRL_INTENSET_XOSCRDY_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; -} - -static inline void hri_oscctrl_set_INTEN_XOSCFAIL_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCFAIL_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL) >> OSCCTRL_INTENSET_XOSCFAIL_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCFAIL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCFAIL_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL; -} - -static inline void hri_oscctrl_set_INTEN_OSC16MRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; -} - -static inline bool hri_oscctrl_get_INTEN_OSC16MRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_OSC16MRDY) >> OSCCTRL_INTENSET_OSC16MRDY_Pos; -} - -static inline void hri_oscctrl_write_INTEN_OSC16MRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; - } -} - -static inline void hri_oscctrl_clear_INTEN_OSC16MRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; -} - -static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; -} - -static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; -} - -static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; -} - -static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; -} - -static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; -} - -static inline void hri_oscctrl_set_INTEN_DPLLLCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; -} - -static inline bool hri_oscctrl_get_INTEN_DPLLLCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKR) >> OSCCTRL_INTENSET_DPLLLCKR_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLLLCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; -} - -static inline void hri_oscctrl_set_INTEN_DPLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; -} - -static inline bool hri_oscctrl_get_INTEN_DPLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKF) >> OSCCTRL_INTENSET_DPLLLCKF_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; -} - -static inline void hri_oscctrl_set_INTEN_DPLLLTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLLLTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLTO) >> OSCCTRL_INTENSET_DPLLLTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLLLTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; -} - -static inline void hri_oscctrl_set_INTEN_DPLLLDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLLLDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLDRTO) >> OSCCTRL_INTENSET_DPLLLDRTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLLLDRTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLLLDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; -} - -static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) -{ - ((Oscctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, - hri_oscctrl_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->INTENSET.reg; -} - -static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) -{ - ((Oscctrl *)hw)->INTENSET.reg = data; - ((Oscctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) -{ - ((Oscctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY) >> OSCCTRL_STATUS_XOSCRDY_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCFAIL_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL) >> OSCCTRL_STATUS_XOSCFAIL_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCCKSW_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW) >> OSCCTRL_STATUS_XOSCCKSW_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_OSC16MRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_OSC16MRDY) >> OSCCTRL_STATUS_OSC16MRDY_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLLLCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKR) >> OSCCTRL_STATUS_DPLLLCKR_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKF) >> OSCCTRL_STATUS_DPLLLCKF_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLLTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLTO) >> OSCCTRL_STATUS_DPLLTO_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLLLDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLDRTO) >> OSCCTRL_STATUS_DPLLLDRTO_Pos; -} - -static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->STATUS.reg; -} - -static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; -} - -static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLPRESC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) >> OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, - hri_oscctrl_dpllsyncbusy_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; -} - -static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; -} - -static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, - hri_oscctrl_dpllstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DPLLSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DPLLSTATUS.reg; -} - -static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; - tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; - ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_XTALEN; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; - tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_XTALEN; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_XTALEN; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_CFDEN; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; - tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_CFDEN; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_CFDEN; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_SWBEN; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; - tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_SWBEN; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_SWBEN; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; - tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; - ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; - tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; - ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_AMPGC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_AMPGC; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_AMPGC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_AMPGC) >> OSCCTRL_XOSCCTRL_AMPGC_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_AMPGC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp &= ~OSCCTRL_XOSCCTRL_AMPGC; - tmp |= value << OSCCTRL_XOSCCTRL_AMPGC_Pos; - ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_AMPGC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_AMPGC; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_AMPGC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_AMPGC; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_GAIN(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_GAIN_bf(const void *const hw, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN(mask)) >> OSCCTRL_XOSCCTRL_GAIN_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp &= ~OSCCTRL_XOSCCTRL_GAIN_Msk; - tmp |= OSCCTRL_XOSCCTRL_GAIN(data); - ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_GAIN(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_GAIN(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_GAIN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN_Msk) >> OSCCTRL_XOSCCTRL_GAIN_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; - tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); - ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg |= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint16_t tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg = data; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg &= ~mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL.reg ^= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw) -{ - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - return ((Oscctrl *)hw)->XOSCCTRL.reg; -} - -static inline void hri_oscctrl_set_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->CFDPRESC.reg |= OSCCTRL_CFDPRESC_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_CFDPRESC_bf(const void *const hw, - hri_oscctrl_cfdpresc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->CFDPRESC.reg; - tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC(mask)) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t data) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->CFDPRESC.reg; - tmp &= ~OSCCTRL_CFDPRESC_CFDPRESC_Msk; - tmp |= OSCCTRL_CFDPRESC_CFDPRESC(data); - ((Oscctrl *)hw)->CFDPRESC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->CFDPRESC.reg &= ~OSCCTRL_CFDPRESC_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->CFDPRESC.reg ^= OSCCTRL_CFDPRESC_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_CFDPRESC_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->CFDPRESC.reg; - tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC_Msk) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->CFDPRESC.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_reg(const void *const hw, - hri_oscctrl_cfdpresc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->CFDPRESC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->CFDPRESC.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->CFDPRESC.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->CFDPRESC.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->CFDPRESC.reg; -} - -static inline void hri_oscctrl_set_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_EVCTRL_CFDEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp = (tmp & OSCCTRL_EVCTRL_CFDEO) >> OSCCTRL_EVCTRL_CFDEO_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp &= ~OSCCTRL_EVCTRL_CFDEO; - tmp |= value << OSCCTRL_EVCTRL_CFDEO_Pos; - ((Oscctrl *)hw)->EVCTRL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->EVCTRL.reg; -} - -static inline void hri_oscctrl_set_OSC16MCTRL_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_OSC16MCTRL_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; - tmp = (tmp & OSCCTRL_OSC16MCTRL_ENABLE) >> OSCCTRL_OSC16MCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_OSC16MCTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; - tmp &= ~OSCCTRL_OSC16MCTRL_ENABLE; - tmp |= value << OSCCTRL_OSC16MCTRL_ENABLE_Pos; - ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_OSC16MCTRL_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_OSC16MCTRL_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; - tmp = (tmp & OSCCTRL_OSC16MCTRL_RUNSTDBY) >> OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_OSC16MCTRL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; - tmp &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY; - tmp |= value << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos; - ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_OSC16MCTRL_ONDEMAND_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; - tmp = (tmp & OSCCTRL_OSC16MCTRL_ONDEMAND) >> OSCCTRL_OSC16MCTRL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_OSC16MCTRL_ONDEMAND_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; - tmp &= ~OSCCTRL_OSC16MCTRL_ONDEMAND; - tmp |= value << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos; - ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_OSC16MCTRL_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_OSC16MCTRL_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_FSEL(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_FSEL_bf(const void *const hw, - hri_oscctrl_osc16mctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; - tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL(mask)) >> OSCCTRL_OSC16MCTRL_FSEL_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; - tmp &= ~OSCCTRL_OSC16MCTRL_FSEL_Msk; - tmp |= OSCCTRL_OSC16MCTRL_FSEL(data); - ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_FSEL(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_FSEL(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_FSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; - tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL_Msk) >> OSCCTRL_OSC16MCTRL_FSEL_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg |= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_reg(const void *const hw, - hri_oscctrl_osc16mctrl_reg_t mask) -{ - uint8_t tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg = data; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->OSC16MCTRL.reg ^= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_reg(const void *const hw) -{ - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - return ((Oscctrl *)hw)->OSC16MCTRL.reg; -} - -static inline void hri_oscctrl_set_DFLLCTRL_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRL_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & OSCCTRL_DFLLCTRL_ENABLE) >> OSCCTRL_DFLLCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= ~OSCCTRL_DFLLCTRL_ENABLE; - tmp |= value << OSCCTRL_DFLLCTRL_ENABLE_Pos; - ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRL_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_MODE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRL_MODE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & OSCCTRL_DFLLCTRL_MODE) >> OSCCTRL_DFLLCTRL_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_MODE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= ~OSCCTRL_DFLLCTRL_MODE; - tmp |= value << OSCCTRL_DFLLCTRL_MODE_Pos; - ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_MODE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_MODE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRL_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_STABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRL_STABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & OSCCTRL_DFLLCTRL_STABLE) >> OSCCTRL_DFLLCTRL_STABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_STABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= ~OSCCTRL_DFLLCTRL_STABLE; - tmp |= value << OSCCTRL_DFLLCTRL_STABLE_Pos; - ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_STABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_STABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRL_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_LLAW; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRL_LLAW_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & OSCCTRL_DFLLCTRL_LLAW) >> OSCCTRL_DFLLCTRL_LLAW_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_LLAW_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= ~OSCCTRL_DFLLCTRL_LLAW; - tmp |= value << OSCCTRL_DFLLCTRL_LLAW_Pos; - ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_LLAW; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_LLAW; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRL_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_USBCRM; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRL_USBCRM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & OSCCTRL_DFLLCTRL_USBCRM) >> OSCCTRL_DFLLCTRL_USBCRM_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_USBCRM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= ~OSCCTRL_DFLLCTRL_USBCRM; - tmp |= value << OSCCTRL_DFLLCTRL_USBCRM_Pos; - ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_USBCRM; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_USBCRM; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRL_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRL_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & OSCCTRL_DFLLCTRL_RUNSTDBY) >> OSCCTRL_DFLLCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= ~OSCCTRL_DFLLCTRL_RUNSTDBY; - tmp |= value << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos; - ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRL_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRL_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & OSCCTRL_DFLLCTRL_ONDEMAND) >> OSCCTRL_DFLLCTRL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= ~OSCCTRL_DFLLCTRL_ONDEMAND; - tmp |= value << OSCCTRL_DFLLCTRL_ONDEMAND_Pos; - ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRL_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_CCDIS; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRL_CCDIS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & OSCCTRL_DFLLCTRL_CCDIS) >> OSCCTRL_DFLLCTRL_CCDIS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_CCDIS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= ~OSCCTRL_DFLLCTRL_CCDIS; - tmp |= value << OSCCTRL_DFLLCTRL_CCDIS_Pos; - ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_CCDIS; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_CCDIS; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRL_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_QLDIS; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRL_QLDIS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & OSCCTRL_DFLLCTRL_QLDIS) >> OSCCTRL_DFLLCTRL_QLDIS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_QLDIS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= ~OSCCTRL_DFLLCTRL_QLDIS; - tmp |= value << OSCCTRL_DFLLCTRL_QLDIS_Pos; - ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_QLDIS; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_QLDIS; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRL_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_BPLCKC; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRL_BPLCKC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & OSCCTRL_DFLLCTRL_BPLCKC) >> OSCCTRL_DFLLCTRL_BPLCKC_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_BPLCKC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= ~OSCCTRL_DFLLCTRL_BPLCKC; - tmp |= value << OSCCTRL_DFLLCTRL_BPLCKC_Pos; - ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_BPLCKC; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_BPLCKC; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRL_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_WAITLOCK; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRL_WAITLOCK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & OSCCTRL_DFLLCTRL_WAITLOCK) >> OSCCTRL_DFLLCTRL_WAITLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_WAITLOCK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= ~OSCCTRL_DFLLCTRL_WAITLOCK; - tmp |= value << OSCCTRL_DFLLCTRL_WAITLOCK_Pos; - ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_WAITLOCK; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_WAITLOCK; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg |= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_get_DFLLCTRL_reg(const void *const hw, - hri_oscctrl_dfllctrl_reg_t mask) -{ - uint16_t tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg = data; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg &= ~mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRL.reg ^= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_read_DFLLCTRL_reg(const void *const hw) -{ - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - return ((Oscctrl *)hw)->DFLLCTRL.reg; -} - -static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; - tmp |= OSCCTRL_DFLLVAL_FINE(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; - tmp |= OSCCTRL_DFLLVAL_COARSE(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; - tmp |= OSCCTRL_DFLLVAL_DIFF(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLVAL.reg; -} - -static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; - tmp |= OSCCTRL_DFLLMUL_MUL(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; - tmp |= OSCCTRL_DFLLMUL_FSTEP(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; - tmp |= OSCCTRL_DFLLMUL_CSTEP(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLMUL.reg; -} - -static inline void hri_oscctrl_set_DFLLSYNC_READREQ_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_READREQ; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_READREQ_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_READREQ) >> OSCCTRL_DFLLSYNC_READREQ_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_READREQ_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_READREQ; - tmp |= value << OSCCTRL_DFLLSYNC_READREQ_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_READREQ_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_READREQ; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_READREQ_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_READREQ; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, - hri_oscctrl_dfllsync_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLSYNC.reg; -} - -static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; - tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; - ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg |= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, - hri_oscctrl_dpllctrla_reg_t mask) -{ - uint8_t tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg = data; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLA.reg ^= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw) -{ - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - return ((Oscctrl *)hw)->DPLLCTRLA.reg; -} - -static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDR(data); - ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); - ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLRATIO.reg |= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLRATIO.reg = data; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLRATIO.reg &= ~mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLRATIO.reg ^= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw) -{ - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - return ((Oscctrl *)hw)->DPLLRATIO.reg; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_LPEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LPEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_LPEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LPEN) >> OSCCTRL_DPLLCTRLB_LPEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_LPEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LPEN; - tmp |= value << OSCCTRL_DPLLCTRLB_LPEN_Pos; - ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_LPEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LPEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_LPEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LPEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_WUF; - tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; - ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); - ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; - tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); - ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; - tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); - ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DIV(data); - ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLCTRLB.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DPLLCTRLB.reg; -} - -static inline void hri_oscctrl_set_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLPRESC.reg |= OSCCTRL_DPLLPRESC_PRESC(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_PRESC_bf(const void *const hw, - hri_oscctrl_dpllpresc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; - tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC(mask)) >> OSCCTRL_DPLLPRESC_PRESC_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; - tmp &= ~OSCCTRL_DPLLPRESC_PRESC_Msk; - tmp |= OSCCTRL_DPLLPRESC_PRESC(data); - ((Oscctrl *)hw)->DPLLPRESC.reg = tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLPRESC.reg &= ~OSCCTRL_DPLLPRESC_PRESC(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLPRESC.reg ^= OSCCTRL_DPLLPRESC_PRESC(mask); - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_PRESC_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; - tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC_Msk) >> OSCCTRL_DPLLPRESC_PRESC_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLPRESC.reg |= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_reg(const void *const hw, - hri_oscctrl_dpllpresc_reg_t mask) -{ - uint8_t tmp; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLPRESC.reg = data; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLPRESC.reg &= ~mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DPLLPRESC.reg ^= mask; - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_reg(const void *const hw) -{ - hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - return ((Oscctrl *)hw)->DPLLPRESC.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_OSCCTRL_L22_H_INCLUDED */ -#endif /* _SAML22_OSCCTRL_COMPONENT_ */ diff --git a/watch-library/hri/hri_pac_l22.h b/watch-library/hri/hri_pac_l22.h deleted file mode 100644 index 488c7079..00000000 --- a/watch-library/hri/hri_pac_l22.h +++ /dev/null @@ -1,1076 +0,0 @@ -/** - * \file - * - * \brief SAM PAC - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_PAC_COMPONENT_ -#ifndef _HRI_PAC_L22_H_INCLUDED_ -#define _HRI_PAC_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PAC_CRITICAL_SECTIONS) -#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PAC_CRITICAL_SECTION_ENTER() -#define PAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_pac_intflaga_reg_t; -typedef uint32_t hri_pac_intflagahb_reg_t; -typedef uint32_t hri_pac_intflagb_reg_t; -typedef uint32_t hri_pac_intflagc_reg_t; -typedef uint32_t hri_pac_statusa_reg_t; -typedef uint32_t hri_pac_statusb_reg_t; -typedef uint32_t hri_pac_statusc_reg_t; -typedef uint32_t hri_pac_wrctrl_reg_t; -typedef uint8_t hri_pac_evctrl_reg_t; -typedef uint8_t hri_pac_intenset_reg_t; - -static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; -} - -static inline bool hri_pac_get_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMCM0P) >> PAC_INTFLAGAHB_HSRAMCM0P_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMCM0P; -} - -static inline bool hri_pac_get_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDSU) >> PAC_INTFLAGAHB_HSRAMDSU_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDSU; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; -} - -static inline bool hri_pac_get_INTFLAGAHB_HSRAMDMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDMAC) >> PAC_INTFLAGAHB_HSRAMDMAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HSRAMDMAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDMAC; -} - -static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGAHB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGAHB.reg; -} - -static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) -{ - ((Pac *)hw)->INTFLAGAHB.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; -} - -static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; -} - -static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; -} - -static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; -} - -static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; -} - -static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; -} - -static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; -} - -static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; -} - -static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; -} - -static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; -} - -static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; -} - -static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; -} - -static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGA.reg; -} - -static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) -{ - ((Pac *)hw)->INTFLAGA.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; -} - -static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; -} - -static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; -} - -static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; -} - -static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; -} - -static inline bool hri_pac_get_INTFLAGB_MTB_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_MTB) >> PAC_INTFLAGB_MTB_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_MTB_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_MTB; -} - -static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGB.reg; -} - -static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) -{ - ((Pac *)hw)->INTFLAGB.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGC_EVSYS_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_EVSYS) >> PAC_INTFLAGC_EVSYS_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_EVSYS_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_EVSYS; -} - -static inline bool hri_pac_get_INTFLAGC_SERCOM0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM0) >> PAC_INTFLAGC_SERCOM0_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_SERCOM0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM0; -} - -static inline bool hri_pac_get_INTFLAGC_SERCOM1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM1) >> PAC_INTFLAGC_SERCOM1_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_SERCOM1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM1; -} - -static inline bool hri_pac_get_INTFLAGC_SERCOM2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM2) >> PAC_INTFLAGC_SERCOM2_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_SERCOM2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM2; -} - -static inline bool hri_pac_get_INTFLAGC_SERCOM3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM3) >> PAC_INTFLAGC_SERCOM3_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_SERCOM3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM3; -} - -static inline bool hri_pac_get_INTFLAGC_SERCOM4_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM4) >> PAC_INTFLAGC_SERCOM4_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_SERCOM4_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM4; -} - -static inline bool hri_pac_get_INTFLAGC_SERCOM5_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM5) >> PAC_INTFLAGC_SERCOM5_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_SERCOM5_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM5; -} - -static inline bool hri_pac_get_INTFLAGC_TCC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC0) >> PAC_INTFLAGC_TCC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TCC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC0; -} - -static inline bool hri_pac_get_INTFLAGC_TC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC0) >> PAC_INTFLAGC_TC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC0; -} - -static inline bool hri_pac_get_INTFLAGC_TC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC1) >> PAC_INTFLAGC_TC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC1; -} - -static inline bool hri_pac_get_INTFLAGC_TC2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC2) >> PAC_INTFLAGC_TC2_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TC2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC2; -} - -static inline bool hri_pac_get_INTFLAGC_TC3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC3) >> PAC_INTFLAGC_TC3_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TC3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC3; -} - -static inline bool hri_pac_get_INTFLAGC_ADC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ADC) >> PAC_INTFLAGC_ADC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_ADC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ADC; -} - -static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; -} - -static inline bool hri_pac_get_INTFLAGC_PTC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PTC) >> PAC_INTFLAGC_PTC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_PTC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PTC; -} - -static inline bool hri_pac_get_INTFLAGC_SLCD_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SLCD) >> PAC_INTFLAGC_SLCD_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_SLCD_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SLCD; -} - -static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; -} - -static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; -} - -static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; -} - -static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGC.reg; -} - -static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) -{ - ((Pac *)hw)->INTFLAGC.reg = mask; -} - -static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) -{ - ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; -} - -static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; -} - -static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; - } else { - ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; - } -} - -static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; -} - -static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - ((Pac *)hw)->INTENSET.reg = mask; -} - -static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) -{ - return ((Pac *)hw)->INTENSET.reg; -} - -static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) -{ - ((Pac *)hw)->INTENSET.reg = data; - ((Pac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - ((Pac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; -} - -static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; -} - -static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; -} - -static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; -} - -static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; -} - -static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; -} - -static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; -} - -static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; -} - -static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; -} - -static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; -} - -static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSA.reg; -} - -static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; -} - -static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; -} - -static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; -} - -static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; -} - -static inline bool hri_pac_get_STATUSB_MTB_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_MTB) >> PAC_STATUSB_MTB_Pos; -} - -static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSB.reg; -} - -static inline bool hri_pac_get_STATUSC_EVSYS_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_EVSYS) >> PAC_STATUSC_EVSYS_Pos; -} - -static inline bool hri_pac_get_STATUSC_SERCOM0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM0) >> PAC_STATUSC_SERCOM0_Pos; -} - -static inline bool hri_pac_get_STATUSC_SERCOM1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM1) >> PAC_STATUSC_SERCOM1_Pos; -} - -static inline bool hri_pac_get_STATUSC_SERCOM2_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM2) >> PAC_STATUSC_SERCOM2_Pos; -} - -static inline bool hri_pac_get_STATUSC_SERCOM3_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM3) >> PAC_STATUSC_SERCOM3_Pos; -} - -static inline bool hri_pac_get_STATUSC_SERCOM4_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM4) >> PAC_STATUSC_SERCOM4_Pos; -} - -static inline bool hri_pac_get_STATUSC_SERCOM5_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM5) >> PAC_STATUSC_SERCOM5_Pos; -} - -static inline bool hri_pac_get_STATUSC_TCC0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC0) >> PAC_STATUSC_TCC0_Pos; -} - -static inline bool hri_pac_get_STATUSC_TC0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC0) >> PAC_STATUSC_TC0_Pos; -} - -static inline bool hri_pac_get_STATUSC_TC1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC1) >> PAC_STATUSC_TC1_Pos; -} - -static inline bool hri_pac_get_STATUSC_TC2_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC2) >> PAC_STATUSC_TC2_Pos; -} - -static inline bool hri_pac_get_STATUSC_TC3_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC3) >> PAC_STATUSC_TC3_Pos; -} - -static inline bool hri_pac_get_STATUSC_ADC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ADC) >> PAC_STATUSC_ADC_Pos; -} - -static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; -} - -static inline bool hri_pac_get_STATUSC_PTC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PTC) >> PAC_STATUSC_PTC_Pos; -} - -static inline bool hri_pac_get_STATUSC_SLCD_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SLCD) >> PAC_STATUSC_SLCD_Pos; -} - -static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; -} - -static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; -} - -static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; -} - -static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSC.reg; -} - -static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - uint32_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= ~PAC_WRCTRL_PERID_Msk; - tmp |= PAC_WRCTRL_PERID(data); - ((Pac *)hw)->WRCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; - return tmp; -} - -static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - uint32_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= ~PAC_WRCTRL_KEY_Msk; - tmp |= PAC_WRCTRL_KEY(data); - ((Pac *)hw)->WRCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; - return tmp; -} - -static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg = data; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) -{ - return ((Pac *)hw)->WRCTRL.reg; -} - -static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; - return (bool)tmp; -} - -static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp &= ~PAC_EVCTRL_ERREO; - tmp |= value << PAC_EVCTRL_ERREO_Pos; - ((Pac *)hw)->EVCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg |= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg = data; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg &= ~mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg ^= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) -{ - return ((Pac *)hw)->EVCTRL.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PAC_L22_H_INCLUDED */ -#endif /* _SAML22_PAC_COMPONENT_ */ diff --git a/watch-library/hri/hri_pm_l22.h b/watch-library/hri/hri_pm_l22.h deleted file mode 100644 index d56d3cf7..00000000 --- a/watch-library/hri/hri_pm_l22.h +++ /dev/null @@ -1,592 +0,0 @@ -/** - * \file - * - * \brief SAM PM - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_PM_COMPONENT_ -#ifndef _HRI_PM_L22_H_INCLUDED_ -#define _HRI_PM_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PM_CRITICAL_SECTIONS) -#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PM_CRITICAL_SECTION_ENTER() -#define PM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_pm_stdbycfg_reg_t; -typedef uint8_t hri_pm_ctrla_reg_t; -typedef uint8_t hri_pm_intenset_reg_t; -typedef uint8_t hri_pm_intflag_reg_t; -typedef uint8_t hri_pm_plcfg_reg_t; -typedef uint8_t hri_pm_sleepcfg_reg_t; - -static inline bool hri_pm_get_INTFLAG_PLRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos; -} - -static inline void hri_pm_clear_INTFLAG_PLRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY; -} - -static inline bool hri_pm_get_interrupt_PLRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos; -} - -static inline void hri_pm_clear_interrupt_PLRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY; -} - -static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) -{ - return ((Pm *)hw)->INTFLAG.reg; -} - -static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) -{ - ((Pm *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_pm_set_INTEN_PLRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; -} - -static inline bool hri_pm_get_INTEN_PLRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_PLRDY) >> PM_INTENSET_PLRDY_Pos; -} - -static inline void hri_pm_write_INTEN_PLRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; - } else { - ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; - } -} - -static inline void hri_pm_clear_INTEN_PLRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; -} - -static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - ((Pm *)hw)->INTENSET.reg = mask; -} - -static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) -{ - return ((Pm *)hw)->INTENSET.reg; -} - -static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) -{ - ((Pm *)hw)->INTENSET.reg = data; - ((Pm *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - ((Pm *)hw)->INTENCLR.reg = mask; -} - -static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CTRLA.reg; - tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->CTRLA.reg; - tmp &= ~PM_CTRLA_IORET; - tmp |= value << PM_CTRLA_IORET_Pos; - ((Pm *)hw)->CTRLA.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) -{ - return ((Pm *)hw)->CTRLA.reg; -} - -static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; - return tmp; -} - -static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; - tmp |= PM_SLEEPCFG_SLEEPMODE(data); - ((Pm *)hw)->SLEEPCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; - return tmp; -} - -static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->SLEEPCFG.reg; -} - -static inline void hri_pm_set_PLCFG_PLDIS_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLDIS; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_PLCFG_PLDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PLCFG.reg; - tmp = (tmp & PM_PLCFG_PLDIS) >> PM_PLCFG_PLDIS_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_PLCFG_PLDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->PLCFG.reg; - tmp &= ~PM_PLCFG_PLDIS; - tmp |= value << PM_PLCFG_PLDIS_Pos; - ((Pm *)hw)->PLCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PLCFG_PLDIS_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLDIS; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PLCFG_PLDIS_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLDIS; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLSEL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PLCFG.reg; - tmp = (tmp & PM_PLCFG_PLSEL(mask)) >> PM_PLCFG_PLSEL_Pos; - return tmp; -} - -static inline void hri_pm_write_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->PLCFG.reg; - tmp &= ~PM_PLCFG_PLSEL_Msk; - tmp |= PM_PLCFG_PLSEL(data); - ((Pm *)hw)->PLCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLSEL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLSEL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_PLSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PLCFG.reg; - tmp = (tmp & PM_PLCFG_PLSEL_Msk) >> PM_PLCFG_PLSEL_Pos; - return tmp; -} - -static inline void hri_pm_set_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PLCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PLCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PLCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PLCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PLCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->PLCFG.reg; -} - -static inline void hri_pm_set_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_VREGSMOD(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_VREGSMOD(mask)) >> PM_STDBYCFG_VREGSMOD_Pos; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - uint16_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= ~PM_STDBYCFG_VREGSMOD_Msk; - tmp |= PM_STDBYCFG_VREGSMOD(data); - ((Pm *)hw)->STDBYCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_VREGSMOD(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_VREGSMOD(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_VREGSMOD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_VREGSMOD_Msk) >> PM_STDBYCFG_VREGSMOD_Pos; - return tmp; -} - -static inline void hri_pm_set_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASHS(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_BBIASHS(mask)) >> PM_STDBYCFG_BBIASHS_Pos; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - uint16_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= ~PM_STDBYCFG_BBIASHS_Msk; - tmp |= PM_STDBYCFG_BBIASHS(data); - ((Pm *)hw)->STDBYCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASHS(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASHS(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASHS_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_BBIASHS_Msk) >> PM_STDBYCFG_BBIASHS_Pos; - return tmp; -} - -static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->STDBYCFG.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PM_L22_H_INCLUDED */ -#endif /* _SAML22_PM_COMPONENT_ */ diff --git a/watch-library/hri/hri_port_l22.h b/watch-library/hri/hri_port_l22.h deleted file mode 100644 index ee99c2e8..00000000 --- a/watch-library/hri/hri_port_l22.h +++ /dev/null @@ -1,2357 +0,0 @@ -/** - * \file - * - * \brief SAM PORT - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_PORT_COMPONENT_ -#ifndef _HRI_PORT_L22_H_INCLUDED_ -#define _HRI_PORT_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PORT_CRITICAL_SECTIONS) -#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PORT_CRITICAL_SECTION_ENTER() -#define PORT_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_port_ctrl_reg_t; -typedef uint32_t hri_port_dir_reg_t; -typedef uint32_t hri_port_evctrl_reg_t; -typedef uint32_t hri_port_in_reg_t; -typedef uint32_t hri_port_out_reg_t; -typedef uint32_t hri_port_wrconfig_reg_t; -typedef uint32_t hri_portgroup_ctrl_reg_t; -typedef uint32_t hri_portgroup_dir_reg_t; -typedef uint32_t hri_portgroup_evctrl_reg_t; -typedef uint32_t hri_portgroup_in_reg_t; -typedef uint32_t hri_portgroup_out_reg_t; -typedef uint32_t hri_portgroup_wrconfig_reg_t; -typedef uint8_t hri_port_pincfg_reg_t; -typedef uint8_t hri_port_pmux_reg_t; -typedef uint8_t hri_portgroup_pincfg_reg_t; -typedef uint8_t hri_portgroup_pmux_reg_t; - -static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRSET.reg = mask; -} - -static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) -{ - return ((PortGroup *)hw)->DIR.reg; -} - -static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) -{ - ((PortGroup *)hw)->DIRSET.reg = data; - ((PortGroup *)hw)->DIRCLR.reg = ~data; -} - -static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRCLR.reg = mask; -} - -static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRTGL.reg = mask; -} - -static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTSET.reg = mask; -} - -static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) -{ - return ((PortGroup *)hw)->OUT.reg; -} - -static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) -{ - ((PortGroup *)hw)->OUTSET.reg = data; - ((PortGroup *)hw)->OUTCLR.reg = ~data; -} - -static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTCLR.reg = mask; -} - -static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTTGL.reg = mask; -} - -static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->IN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) -{ - return ((PortGroup *)hw)->IN.reg; -} - -static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp &= ~PORT_CTRL_SAMPLING_Msk; - tmp |= PORT_CTRL_SAMPLING(data); - ((PortGroup *)hw)->CTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) -{ - return ((PortGroup *)hw)->CTRL.reg; -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI0; - tmp |= value << PORT_EVCTRL_PORTEI0_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI1; - tmp |= value << PORT_EVCTRL_PORTEI1_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI2; - tmp |= value << PORT_EVCTRL_PORTEI2_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI3; - tmp |= value << PORT_EVCTRL_PORTEI3_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID0_Msk; - tmp |= PORT_EVCTRL_PID0(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT0_Msk; - tmp |= PORT_EVCTRL_EVACT0(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID1_Msk; - tmp |= PORT_EVCTRL_PID1(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT1_Msk; - tmp |= PORT_EVCTRL_EVACT1(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID2_Msk; - tmp |= PORT_EVCTRL_PID2(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT2_Msk; - tmp |= PORT_EVCTRL_EVACT2(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID3_Msk; - tmp |= PORT_EVCTRL_PID3(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT3_Msk; - tmp |= PORT_EVCTRL_EVACT3(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) -{ - return ((PortGroup *)hw)->EVCTRL.reg; -} - -static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXE_Msk; - tmp |= PORT_PMUX_PMUXE(data); - ((PortGroup *)hw)->PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXO_Msk; - tmp |= PORT_PMUX_PMUXO(data); - ((PortGroup *)hw)->PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) -{ - return ((PortGroup *)hw)->PMUX[index].reg; -} - -static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PMUXEN; - tmp |= value << PORT_PINCFG_PMUXEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_INEN; - tmp |= value << PORT_PINCFG_INEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PULLEN; - tmp |= value << PORT_PINCFG_PULLEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_DRVSTR; - tmp |= value << PORT_PINCFG_DRVSTR_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) -{ - return ((PortGroup *)hw)->PINCFG[index].reg; -} - -static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->WRCONFIG.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; -} - -static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, - hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].DIR.reg; -} - -static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; -} - -static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; -} - -static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; -} - -static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; -} - -static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, - hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].OUT.reg; -} - -static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; -} - -static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; -} - -static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; -} - -static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, - hri_port_in_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].IN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].IN.reg; -} - -static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp &= ~PORT_CTRL_SAMPLING_Msk; - tmp |= PORT_CTRL_SAMPLING(data); - ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].CTRL.reg; -} - -static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI0; - tmp |= value << PORT_EVCTRL_PORTEI0_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI1; - tmp |= value << PORT_EVCTRL_PORTEI1_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI2; - tmp |= value << PORT_EVCTRL_PORTEI2_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI3; - tmp |= value << PORT_EVCTRL_PORTEI3_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID0_Msk; - tmp |= PORT_EVCTRL_PID0(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT0_Msk; - tmp |= PORT_EVCTRL_EVACT0(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID1_Msk; - tmp |= PORT_EVCTRL_PID1(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT1_Msk; - tmp |= PORT_EVCTRL_EVACT1(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID2_Msk; - tmp |= PORT_EVCTRL_PID2(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT2_Msk; - tmp |= PORT_EVCTRL_EVACT2(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID3_Msk; - tmp |= PORT_EVCTRL_PID3(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT3_Msk; - tmp |= PORT_EVCTRL_EVACT3(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; -} - -static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXE_Msk; - tmp |= PORT_PMUX_PMUXE(data); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXO_Msk; - tmp |= PORT_PMUX_PMUXO(data); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; -} - -static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PMUXEN; - tmp |= value << PORT_PINCFG_PMUXEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_INEN; - tmp |= value << PORT_PINCFG_INEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PULLEN; - tmp |= value << PORT_PINCFG_PULLEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_DRVSTR; - tmp |= value << PORT_PINCFG_DRVSTR_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pincfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; -} - -static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, - hri_port_wrconfig_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PORT_L22_H_INCLUDED */ -#endif /* _SAML22_PORT_COMPONENT_ */ diff --git a/watch-library/hri/hri_rstc_l22.h b/watch-library/hri/hri_rstc_l22.h deleted file mode 100644 index 853744e2..00000000 --- a/watch-library/hri/hri_rstc_l22.h +++ /dev/null @@ -1,132 +0,0 @@ -/** - * \file - * - * \brief SAM RSTC - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_RSTC_COMPONENT_ -#ifndef _HRI_RSTC_L22_H_INCLUDED_ -#define _HRI_RSTC_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) -#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RSTC_CRITICAL_SECTION_ENTER() -#define RSTC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint8_t hri_rstc_bkupexit_reg_t; -typedef uint8_t hri_rstc_rcause_reg_t; - -static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; -} - -static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rstc *)hw)->RCAUSE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) -{ - return ((Rstc *)hw)->RCAUSE.reg; -} - -static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) -{ - return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; -} - -static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) -{ - return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; -} - -static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rstc *)hw)->BKUPEXIT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) -{ - return ((Rstc *)hw)->BKUPEXIT.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RSTC_L22_H_INCLUDED */ -#endif /* _SAML22_RSTC_COMPONENT_ */ diff --git a/watch-library/hri/hri_rtc_l22.h b/watch-library/hri/hri_rtc_l22.h deleted file mode 100644 index 0b46f010..00000000 --- a/watch-library/hri/hri_rtc_l22.h +++ /dev/null @@ -1,9084 +0,0 @@ -/** - * \file - * - * \brief SAM RTC - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_RTC_COMPONENT_ -#ifndef _HRI_RTC_L22_H_INCLUDED_ -#define _HRI_RTC_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RTC_CRITICAL_SECTIONS) -#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RTC_CRITICAL_SECTION_ENTER() -#define RTC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_rtcmode0_ctrla_reg_t; -typedef uint16_t hri_rtcmode0_ctrlb_reg_t; -typedef uint16_t hri_rtcmode0_intenset_reg_t; -typedef uint16_t hri_rtcmode0_intflag_reg_t; -typedef uint16_t hri_rtcmode1_comp_reg_t; -typedef uint16_t hri_rtcmode1_count_reg_t; -typedef uint16_t hri_rtcmode1_ctrla_reg_t; -typedef uint16_t hri_rtcmode1_ctrlb_reg_t; -typedef uint16_t hri_rtcmode1_intenset_reg_t; -typedef uint16_t hri_rtcmode1_intflag_reg_t; -typedef uint16_t hri_rtcmode1_per_reg_t; -typedef uint16_t hri_rtcmode2_ctrla_reg_t; -typedef uint16_t hri_rtcmode2_ctrlb_reg_t; -typedef uint16_t hri_rtcmode2_intenset_reg_t; -typedef uint16_t hri_rtcmode2_intflag_reg_t; -typedef uint32_t hri_rtc_bkup_reg_t; -typedef uint32_t hri_rtc_gp_reg_t; -typedef uint32_t hri_rtc_tampctrl_reg_t; -typedef uint32_t hri_rtc_tampid_reg_t; -typedef uint32_t hri_rtcalarm_alarm_reg_t; -typedef uint32_t hri_rtcmode0_comp_reg_t; -typedef uint32_t hri_rtcmode0_count_reg_t; -typedef uint32_t hri_rtcmode0_evctrl_reg_t; -typedef uint32_t hri_rtcmode0_syncbusy_reg_t; -typedef uint32_t hri_rtcmode0_timestamp_reg_t; -typedef uint32_t hri_rtcmode1_evctrl_reg_t; -typedef uint32_t hri_rtcmode1_syncbusy_reg_t; -typedef uint32_t hri_rtcmode1_timestamp_reg_t; -typedef uint32_t hri_rtcmode2_alarm_reg_t; -typedef uint32_t hri_rtcmode2_clock_reg_t; -typedef uint32_t hri_rtcmode2_evctrl_reg_t; -typedef uint32_t hri_rtcmode2_syncbusy_reg_t; -typedef uint32_t hri_rtcmode2_timestamp_reg_t; -typedef uint8_t hri_rtc_dbgctrl_reg_t; -typedef uint8_t hri_rtc_freqcorr_reg_t; -typedef uint8_t hri_rtcalarm_mask_reg_t; -typedef uint8_t hri_rtcmode2_mask_reg_t; - -static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; - tmp |= RTC_MODE2_ALARM_SECOND(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; - tmp |= RTC_MODE2_ALARM_MINUTE(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; - tmp |= RTC_MODE2_ALARM_HOUR(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_DAY_Msk; - tmp |= RTC_MODE2_ALARM_DAY(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; - tmp |= RTC_MODE2_ALARM_MONTH(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; - tmp |= RTC_MODE2_ALARM_YEAR(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) -{ - return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; -} - -static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp &= ~RTC_MODE2_MASK_SEL_Msk; - tmp |= RTC_MODE2_MASK_SEL(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; -} - -static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; - tmp |= RTC_MODE2_ALARM_SECOND(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; - tmp |= RTC_MODE2_ALARM_MINUTE(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; - tmp |= RTC_MODE2_ALARM_HOUR(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_DAY_Msk; - tmp |= RTC_MODE2_ALARM_DAY(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; - tmp |= RTC_MODE2_ALARM_MONTH(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; - tmp |= RTC_MODE2_ALARM_YEAR(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; -} - -static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp &= ~RTC_MODE2_MASK_SEL_Msk; - tmp |= RTC_MODE2_MASK_SEL(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; -} - -static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; -} - -static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; -} - -static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; -} - -static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; -} - -static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; -} - -static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; -} - -static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; -} - -static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; -} - -static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; -} - -static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; -} - -static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, - hri_rtcmode0_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.INTFLAG.reg; -} - -static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; -} - -static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; -} - -static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; -} - -static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; -} - -static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; -} - -static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; -} - -static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; -} - -static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; -} - -static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; -} - -static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, - hri_rtcmode1_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.INTFLAG.reg; -} - -static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; -} - -static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; -} - -static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; -} - -static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; -} - -static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; -} - -static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; -} - -static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; -} - -static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; -} - -static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; -} - -static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; -} - -static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; -} - -static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; -} - -static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; -} - -static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, - hri_rtcmode2_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.INTFLAG.reg; -} - -static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; -} - -static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; -} - -static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; -} - -static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; -} - -static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; -} - -static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; -} - -static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; -} - -static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; -} - -static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; -} - -static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; -} - -static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; -} - -static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; -} - -static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; -} - -static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; -} - -static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; -} - -static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; -} - -static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; -} - -static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; -} - -static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; - } -} - -static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; -} - -static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; -} - -static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; -} - -static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; - } -} - -static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; -} - -static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = mask; -} - -static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, - hri_rtcmode0_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.INTENSET.reg; -} - -static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = data; - ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; -} - -static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; -} - -static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; -} - -static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; -} - -static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; -} - -static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; -} - -static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; -} - -static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; -} - -static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; -} - -static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; -} - -static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; -} - -static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; -} - -static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; -} - -static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; -} - -static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; -} - -static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; -} - -static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; -} - -static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; -} - -static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; -} - -static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; -} - -static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; -} - -static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; - } -} - -static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; -} - -static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = mask; -} - -static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, - hri_rtcmode1_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.INTENSET.reg; -} - -static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = data; - ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; -} - -static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; -} - -static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; -} - -static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; -} - -static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; -} - -static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; -} - -static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; -} - -static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; -} - -static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; -} - -static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; -} - -static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; -} - -static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; -} - -static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; -} - -static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; -} - -static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; -} - -static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; -} - -static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; -} - -static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; -} - -static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; - } -} - -static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; -} - -static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; -} - -static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; -} - -static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; - } -} - -static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; -} - -static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = mask; -} - -static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, - hri_rtcmode2_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.INTENSET.reg; -} - -static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = data; - ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos; -} - -static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode0_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos; -} - -static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode1_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos; -} - -static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode2_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const hw, - hri_rtcmode0_timestamp_reg_t mask) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode0_timestamp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE0.TIMESTAMP.reg; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const hw, - hri_rtcmode1_timestamp_reg_t mask) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode1_timestamp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE1.TIMESTAMP.reg; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return ((Rtc *)hw)->MODE2.TIMESTAMP.reg; -} - -static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_ENABLE; - tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; - tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_BKTRST; - tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_GPTRST; - tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; - tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; - tmp |= RTC_MODE0_CTRLA_MODE(data); - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE0_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - return ((Rtc *)hw)->MODE0.CTRLA.reg; -} - -static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_ENABLE; - tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_BKTRST; - tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_GPTRST; - tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; - tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; - tmp |= RTC_MODE1_CTRLA_MODE(data); - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE1_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg = data; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - return ((Rtc *)hw)->MODE1.CTRLA.reg; -} - -static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_ENABLE; - tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_CLKREP; - tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; - tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_BKTRST; - tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_GPTRST; - tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; - tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; - tmp |= RTC_MODE2_CTRLA_MODE(data); - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE2_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg = data; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - return ((Rtc *)hw)->MODE2.CTRLA.reg; -} - -static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_GP0EN; - tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_RTCOUT; - tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DMAEN; - tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk; - tmp |= RTC_MODE0_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk; - tmp |= RTC_MODE0_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.CTRLB.reg; -} - -static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_GP0EN; - tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_RTCOUT; - tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DMAEN; - tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk; - tmp |= RTC_MODE1_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk; - tmp |= RTC_MODE1_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.CTRLB.reg; -} - -static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_GP0EN; - tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_RTCOUT; - tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DMAEN; - tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk; - tmp |= RTC_MODE2_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk; - tmp |= RTC_MODE2_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.CTRLB.reg; -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO0; - tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO1; - tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO2; - tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO3; - tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO4; - tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO5; - tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO6; - tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO7; - tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; - tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_OVFEO; - tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, - hri_rtcmode0_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.EVCTRL.reg; -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO0; - tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO1; - tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO2; - tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO3; - tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO4; - tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO5; - tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO6; - tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO7; - tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_OVFEO; - tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, - hri_rtcmode1_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.EVCTRL.reg; -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO0; - tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO1; - tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO2; - tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO3; - tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO4; - tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO5; - tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO6; - tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO7; - tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; - tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_OVFEO; - tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, - hri_rtcmode2_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.EVCTRL.reg; -} - -static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp &= ~RTC_DBGCTRL_DBGRUN; - tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; - ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.DBGCTRL.reg; -} - -static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_SIGN; - tmp |= value << RTC_FREQCORR_SIGN_Pos; - ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_VALUE_Msk; - tmp |= RTC_FREQCORR_VALUE(data); - ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - uint8_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - return ((Rtc *)hw)->MODE0.FREQCORR.reg; -} - -static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, - hri_rtcmode0_count_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; - tmp |= RTC_MODE0_COUNT_COUNT(data); - ((Rtc *)hw)->MODE0.COUNT.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE0.COUNT.reg; -} - -static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, - hri_rtcmode1_count_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; - tmp |= RTC_MODE1_COUNT_COUNT(data); - ((Rtc *)hw)->MODE1.COUNT.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg |= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg = data; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE1.COUNT.reg; -} - -static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; - tmp |= RTC_MODE2_CLOCK_SECOND(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; - tmp |= RTC_MODE2_CLOCK_MINUTE(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; - tmp |= RTC_MODE2_CLOCK_HOUR(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; - tmp |= RTC_MODE2_CLOCK_DAY(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; - tmp |= RTC_MODE2_CLOCK_MONTH(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; - tmp |= RTC_MODE2_CLOCK_YEAR(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg = data; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return ((Rtc *)hw)->MODE2.CLOCK.reg; -} - -static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp &= ~RTC_MODE1_PER_PER_Msk; - tmp |= RTC_MODE1_PER_PER(data); - ((Rtc *)hw)->MODE1.PER.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg |= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg = data; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg &= ~mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg ^= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - return ((Rtc *)hw)->MODE1.PER.reg; -} - -static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, - hri_rtcmode0_comp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp &= ~RTC_MODE0_COMP_COMP_Msk; - tmp |= RTC_MODE0_COMP_COMP(data); - ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, - hri_rtcmode0_comp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); - return ((Rtc *)hw)->MODE0.COMP[index].reg; -} - -static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, - hri_rtcmode1_comp_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp &= ~RTC_MODE1_COMP_COMP_Msk; - tmp |= RTC_MODE1_COMP_COMP(data); - ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, - hri_rtcmode1_comp_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg = data; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); - return ((Rtc *)hw)->MODE1.COMP[index].reg; -} - -static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp &= ~RTC_GP_GP_Msk; - tmp |= RTC_GP_GP(data); - ((Rtc *)hw)->MODE0.GP[index].reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1); - return ((Rtc *)hw)->MODE0.GP[index].reg; -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL0; - tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL1; - tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL2; - tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL3; - tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL4; - tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC0; - tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC1; - tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC2; - tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC3; - tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC4; - tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; - tmp |= RTC_TAMPCTRL_IN0ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; - tmp |= RTC_TAMPCTRL_IN1ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; - tmp |= RTC_TAMPCTRL_IN2ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; - tmp |= RTC_TAMPCTRL_IN3ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; - tmp |= RTC_TAMPCTRL_IN4ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.TAMPCTRL.reg; -} - -static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID0; - tmp |= value << RTC_TAMPID_TAMPID0_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID1; - tmp |= value << RTC_TAMPID_TAMPID1_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID2; - tmp |= value << RTC_TAMPID_TAMPID2_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID3; - tmp |= value << RTC_TAMPID_TAMPID3_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID4; - tmp |= value << RTC_TAMPID_TAMPID4_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPEVT; - tmp |= value << RTC_TAMPID_TAMPEVT_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.TAMPID.reg; -} - -static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp &= ~RTC_BKUP_BKUP_Msk; - tmp |= RTC_BKUP_BKUP(data); - ((Rtc *)hw)->MODE0.BKUP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE0.BKUP[index].reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RTC_L22_H_INCLUDED */ -#endif /* _SAML22_RTC_COMPONENT_ */ diff --git a/watch-library/hri/hri_sercom_l22.h b/watch-library/hri/hri_sercom_l22.h deleted file mode 100644 index 6d97ca8a..00000000 --- a/watch-library/hri/hri_sercom_l22.h +++ /dev/null @@ -1,7827 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_SERCOM_COMPONENT_ -#ifndef _HRI_SERCOM_L22_H_INCLUDED_ -#define _HRI_SERCOM_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) -#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SERCOM_CRITICAL_SECTION_ENTER() -#define SERCOM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_sercomi2cm_status_reg_t; -typedef uint16_t hri_sercomi2cs_status_reg_t; -typedef uint16_t hri_sercomspi_status_reg_t; -typedef uint16_t hri_sercomusart_baud_reg_t; -typedef uint16_t hri_sercomusart_data_reg_t; -typedef uint16_t hri_sercomusart_status_reg_t; -typedef uint32_t hri_sercomi2cm_addr_reg_t; -typedef uint32_t hri_sercomi2cm_baud_reg_t; -typedef uint32_t hri_sercomi2cm_ctrla_reg_t; -typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; -typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; -typedef uint32_t hri_sercomi2cs_addr_reg_t; -typedef uint32_t hri_sercomi2cs_ctrla_reg_t; -typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; -typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; -typedef uint32_t hri_sercomspi_addr_reg_t; -typedef uint32_t hri_sercomspi_ctrla_reg_t; -typedef uint32_t hri_sercomspi_ctrlb_reg_t; -typedef uint32_t hri_sercomspi_data_reg_t; -typedef uint32_t hri_sercomspi_syncbusy_reg_t; -typedef uint32_t hri_sercomusart_ctrla_reg_t; -typedef uint32_t hri_sercomusart_ctrlb_reg_t; -typedef uint32_t hri_sercomusart_ctrlc_reg_t; -typedef uint32_t hri_sercomusart_syncbusy_reg_t; -typedef uint8_t hri_sercomi2cm_data_reg_t; -typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; -typedef uint8_t hri_sercomi2cm_intenset_reg_t; -typedef uint8_t hri_sercomi2cm_intflag_reg_t; -typedef uint8_t hri_sercomi2cs_data_reg_t; -typedef uint8_t hri_sercomi2cs_intenset_reg_t; -typedef uint8_t hri_sercomi2cs_intflag_reg_t; -typedef uint8_t hri_sercomspi_baud_reg_t; -typedef uint8_t hri_sercomspi_dbgctrl_reg_t; -typedef uint8_t hri_sercomspi_intenset_reg_t; -typedef uint8_t hri_sercomspi_intflag_reg_t; -typedef uint8_t hri_sercomusart_dbgctrl_reg_t; -typedef uint8_t hri_sercomusart_intenset_reg_t; -typedef uint8_t hri_sercomusart_intflag_reg_t; -typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; -typedef uint8_t hri_sercomusart_rxpl_reg_t; - -static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; -} - -static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; -} - -static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; -} - -static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; -} - -static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, - hri_sercomi2cm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.INTFLAG.reg; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; -} - -static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; -} - -static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -} - -static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; -} - -static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; -} - -static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, - hri_sercomi2cs_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.INTFLAG.reg; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; -} - -static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; -} - -static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; -} - -static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; -} - -static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; -} - -static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; -} - -static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; -} - -static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; -} - -static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; -} - -static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; -} - -static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; -} - -static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, - hri_sercomspi_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.INTFLAG.reg; -} - -static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = mask; -} - -static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; -} - -static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; -} - -static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; -} - -static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; -} - -static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; -} - -static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; -} - -static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; -} - -static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; -} - -static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; -} - -static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; -} - -static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; -} - -static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, - hri_sercomusart_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.INTFLAG.reg; -} - -static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = mask; -} - -static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; -} - -static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; -} - -static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; -} - -static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; -} - -static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; -} - -static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; -} - -static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = mask; -} - -static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, - hri_sercomi2cm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.INTENSET.reg; -} - -static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = data; - ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; -} - -static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; -} - -static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; -} - -static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; -} - -static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; -} - -static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; -} - -static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; -} - -static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; -} - -static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; -} - -static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; -} - -static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = mask; -} - -static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, - hri_sercomi2cs_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.INTENSET.reg; -} - -static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = data; - ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; -} - -static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; -} - -static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; -} - -static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; -} - -static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; - } -} - -static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; -} - -static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; -} - -static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; -} - -static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; - } -} - -static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; -} - -static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; -} - -static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; -} - -static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; - } -} - -static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; -} - -static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; -} - -static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; -} - -static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; - } -} - -static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; -} - -static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; -} - -static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; - } -} - -static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; -} - -static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = mask; -} - -static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, - hri_sercomspi_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.INTENSET.reg; -} - -static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = data; - ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; -} - -static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = mask; -} - -static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; -} - -static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; -} - -static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; - } -} - -static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; -} - -static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; -} - -static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; - } -} - -static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; -} - -static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; -} - -static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; -} - -static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; -} - -static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; -} - -static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; -} - -static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; - } -} - -static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; -} - -static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; -} - -static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; -} - -static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; -} - -static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; - } -} - -static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; -} - -static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) -{ - ((Sercom *)hw)->USART.INTENSET.reg = mask; -} - -static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, - hri_sercomusart_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.INTENSET.reg; -} - -static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) -{ - ((Sercom *)hw)->USART.INTENSET.reg = data; - ((Sercom *)hw)->USART.INTENCLR.reg = ~data; -} - -static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = mask; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; -} - -static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, - hri_sercomi2cm_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, - hri_sercomi2cs_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; -} - -static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, - hri_sercomspi_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.SYNCBUSY.reg; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; -} - -static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, - hri_sercomusart_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.SYNCBUSY.reg; -} - -static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const hw, - hri_sercomusart_rxerrcnt_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXERRCNT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.RXERRCNT.reg; -} - -static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; - tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; - tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; - tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; - tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; - tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; - tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; - tmp |= SERCOM_I2CM_CTRLA_MODE(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; - tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; - tmp |= SERCOM_I2CM_CTRLA_SPEED(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; - tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - return ((Sercom *)hw)->I2CM.CTRLA.reg; -} - -static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; - tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; - tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; - tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; - tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; - tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; - tmp |= SERCOM_I2CS_CTRLA_MODE(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; - tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; - tmp |= SERCOM_I2CS_CTRLA_SPEED(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg = data; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) -{ - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - return ((Sercom *)hw)->I2CS.CTRLA.reg; -} - -static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_ENABLE; - tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_IBON; - tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_CPHA; - tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_CPOL; - tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DORD; - tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; - tmp |= SERCOM_SPI_CTRLA_MODE(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; - tmp |= SERCOM_SPI_CTRLA_DOPO(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; - tmp |= SERCOM_SPI_CTRLA_DIPO(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; - tmp |= SERCOM_SPI_CTRLA_FORM(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg = data; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) -{ - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - return ((Sercom *)hw)->SPI.CTRLA.reg; -} - -static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_ENABLE; - tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_IBON; - tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_TXINV; - tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RXINV; - tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_CMODE; - tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_CPOL; - tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_DORD; - tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; - tmp |= SERCOM_USART_CTRLA_MODE(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; - tmp |= SERCOM_USART_CTRLA_SAMPR(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; - tmp |= SERCOM_USART_CTRLA_TXPO(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; - tmp |= SERCOM_USART_CTRLA_RXPO(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; - tmp |= SERCOM_USART_CTRLA_SAMPA(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; - tmp |= SERCOM_USART_CTRLA_FORM(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg = data; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) -{ - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - return ((Sercom *)hw)->USART.CTRLA.reg; -} - -static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_SMEN; - tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_QCEN; - tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; - tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, - hri_sercomi2cm_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; - tmp |= SERCOM_I2CM_CTRLB_CMD(data); - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, - hri_sercomi2cm_ctrlb_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.CTRLB.reg; -} - -static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_SMEN; - tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_GCMD; - tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; - tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; - tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; - tmp |= SERCOM_I2CS_CTRLB_AMODE(data); - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; - tmp |= SERCOM_I2CS_CTRLB_CMD(data); - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.CTRLB.reg; -} - -static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; - tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_SSDE; - tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_MSSEN; - tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_RXEN; - tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; - tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; - tmp |= SERCOM_SPI_CTRLB_AMODE(data); - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg = data; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) -{ - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - return ((Sercom *)hw)->SPI.CTRLB.reg; -} - -static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_SBMODE; - tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_COLDEN; - tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_SFDE; - tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_ENC; - tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_PMODE; - tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_TXEN; - tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_RXEN; - tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; - tmp |= SERCOM_USART_CTRLB_CHSIZE(data); - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg = data; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) -{ - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - return ((Sercom *)hw)->USART.CTRLB.reg; -} - -static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_INACK; - tmp |= value << SERCOM_USART_CTRLC_INACK_Pos; - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_DSNACK; - tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos; - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; - tmp |= SERCOM_USART_CTRLC_GTIME(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk; - tmp |= SERCOM_USART_CTRLC_MAXITER(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.CTRLC.reg; -} - -static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; - tmp |= SERCOM_I2CM_BAUD_BAUD(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; - tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; - tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; - tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.BAUD.reg; -} - -static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomspi_baud_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; - tmp |= SERCOM_SPI_BAUD_BAUD(data); - ((Sercom *)hw)->SPI.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.BAUD.reg; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; - tmp |= SERCOM_USART_BAUD_FRAC_FP(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; - tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.BAUD.reg; -} - -static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, - hri_sercomusart_rxpl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; - tmp |= SERCOM_USART_RXPL_RXPL(data); - ((Sercom *)hw)->USART.RXPL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, - hri_sercomusart_rxpl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.RXPL.reg; -} - -static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_LENEN; - tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_HS; - tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; - tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; - tmp |= SERCOM_I2CM_ADDR_ADDR(data); - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; - tmp |= SERCOM_I2CM_ADDR_LEN(data); - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.ADDR.reg; -} - -static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_GENCEN; - tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; - tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; - tmp |= SERCOM_I2CS_ADDR_ADDR(data); - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; - tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.ADDR.reg; -} - -static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; - tmp |= SERCOM_SPI_ADDR_ADDR(data); - ((Sercom *)hw)->SPI.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, - hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; - tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); - ((Sercom *)hw)->SPI.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.ADDR.reg; -} - -static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, - hri_sercomi2cm_data_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; - tmp |= SERCOM_I2CM_DATA_DATA(data); - ((Sercom *)hw)->I2CM.DATA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, - hri_sercomi2cm_data_reg_t mask) -{ - uint8_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.DATA.reg; -} - -static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, - hri_sercomi2cs_data_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; - tmp |= SERCOM_I2CS_DATA_DATA(data); - ((Sercom *)hw)->I2CS.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, - hri_sercomi2cs_data_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.DATA.reg; -} - -static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, - hri_sercomspi_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp &= ~SERCOM_SPI_DATA_DATA_Msk; - tmp |= SERCOM_SPI_DATA_DATA(data); - ((Sercom *)hw)->SPI.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.DATA.reg; -} - -static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, - hri_sercomusart_data_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp &= ~SERCOM_USART_DATA_DATA_Msk; - tmp |= SERCOM_USART_DATA_DATA(data); - ((Sercom *)hw)->USART.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, - hri_sercomusart_data_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.DATA.reg; -} - -static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, - hri_sercomi2cm_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.DBGCTRL.reg; -} - -static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, - hri_sercomspi_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.DBGCTRL.reg; -} - -static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, - hri_sercomusart_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.DBGCTRL.reg; -} - -static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, - hri_sercomi2cs_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.STATUS.reg; -} - -static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; -} - -static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, - hri_sercomspi_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.STATUS.reg; -} - -static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, - hri_sercomusart_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.STATUS.reg; -} - -static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_BUSERR; - tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; - tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_RXNACK; - tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; - tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; - tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; - tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; - tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_LENERR; - tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, - hri_sercomi2cm_status_reg_t mask) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; -} - -static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; - tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, - hri_sercomi2cm_status_reg_t mask) -{ - uint16_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - ((Sercom *)hw)->I2CM.STATUS.reg |= mask; -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.STATUS.reg; -} - -static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) -{ - ((Sercom *)hw)->I2CM.STATUS.reg = data; -} - -static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; -} - -static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SERCOM_L22_H_INCLUDED */ -#endif /* _SAML22_SERCOM_COMPONENT_ */ diff --git a/watch-library/hri/hri_slcd_l22.h b/watch-library/hri/hri_slcd_l22.h deleted file mode 100644 index 89fde269..00000000 --- a/watch-library/hri/hri_slcd_l22.h +++ /dev/null @@ -1,5440 +0,0 @@ -/** - * \file - * - * \brief SAM SLCD - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_SLCD_COMPONENT_ -#ifndef _HRI_SLCD_L22_H_INCLUDED_ -#define _HRI_SLCD_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SLCD_CRITICAL_SECTIONS) -#define SLCD_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SLCD_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SLCD_CRITICAL_SECTION_ENTER() -#define SLCD_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_slcd_cmindex_reg_t; -typedef uint16_t hri_slcd_ctrlb_reg_t; -typedef uint16_t hri_slcd_ctrlc_reg_t; -typedef uint32_t hri_slcd_acmcfg_reg_t; -typedef uint32_t hri_slcd_bcfg_reg_t; -typedef uint32_t hri_slcd_cmdata_reg_t; -typedef uint32_t hri_slcd_cmdmask_reg_t; -typedef uint32_t hri_slcd_csrcfg_reg_t; -typedef uint32_t hri_slcd_ctrla_reg_t; -typedef uint32_t hri_slcd_isdata_reg_t; -typedef uint32_t hri_slcd_lpenh_reg_t; -typedef uint32_t hri_slcd_lpenl_reg_t; -typedef uint32_t hri_slcd_sdatah0_reg_t; -typedef uint32_t hri_slcd_sdatah1_reg_t; -typedef uint32_t hri_slcd_sdatah2_reg_t; -typedef uint32_t hri_slcd_sdatah3_reg_t; -typedef uint32_t hri_slcd_sdatah4_reg_t; -typedef uint32_t hri_slcd_sdatah5_reg_t; -typedef uint32_t hri_slcd_sdatah6_reg_t; -typedef uint32_t hri_slcd_sdatah7_reg_t; -typedef uint32_t hri_slcd_sdatal0_reg_t; -typedef uint32_t hri_slcd_sdatal1_reg_t; -typedef uint32_t hri_slcd_sdatal2_reg_t; -typedef uint32_t hri_slcd_sdatal3_reg_t; -typedef uint32_t hri_slcd_sdatal4_reg_t; -typedef uint32_t hri_slcd_sdatal5_reg_t; -typedef uint32_t hri_slcd_sdatal6_reg_t; -typedef uint32_t hri_slcd_sdatal7_reg_t; -typedef uint32_t hri_slcd_syncbusy_reg_t; -typedef uint8_t hri_slcd_abmcfg_reg_t; -typedef uint8_t hri_slcd_cmcfg_reg_t; -typedef uint8_t hri_slcd_ctrld_reg_t; -typedef uint8_t hri_slcd_evctrl_reg_t; -typedef uint8_t hri_slcd_fc0_reg_t; -typedef uint8_t hri_slcd_fc1_reg_t; -typedef uint8_t hri_slcd_fc2_reg_t; -typedef uint8_t hri_slcd_intenset_reg_t; -typedef uint8_t hri_slcd_intflag_reg_t; -typedef uint8_t hri_slcd_status_reg_t; - -static inline void hri_slcd_wait_for_sync(const void *const hw, hri_slcd_syncbusy_reg_t reg) -{ - while (((Slcd *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_slcd_is_syncing(const void *const hw, hri_slcd_syncbusy_reg_t reg) -{ - return ((Slcd *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_slcd_get_INTFLAG_FC0O_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC0O) >> SLCD_INTFLAG_FC0O_Pos; -} - -static inline void hri_slcd_clear_INTFLAG_FC0O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC0O; -} - -static inline bool hri_slcd_get_INTFLAG_FC1O_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC1O) >> SLCD_INTFLAG_FC1O_Pos; -} - -static inline void hri_slcd_clear_INTFLAG_FC1O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC1O; -} - -static inline bool hri_slcd_get_INTFLAG_FC2O_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC2O) >> SLCD_INTFLAG_FC2O_Pos; -} - -static inline void hri_slcd_clear_INTFLAG_FC2O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC2O; -} - -static inline bool hri_slcd_get_INTFLAG_VLCDRT_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDRT) >> SLCD_INTFLAG_VLCDRT_Pos; -} - -static inline void hri_slcd_clear_INTFLAG_VLCDRT_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDRT; -} - -static inline bool hri_slcd_get_INTFLAG_VLCDST_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDST) >> SLCD_INTFLAG_VLCDST_Pos; -} - -static inline void hri_slcd_clear_INTFLAG_VLCDST_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDST; -} - -static inline bool hri_slcd_get_INTFLAG_PRST_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_PRST) >> SLCD_INTFLAG_PRST_Pos; -} - -static inline void hri_slcd_clear_INTFLAG_PRST_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_PRST; -} - -static inline bool hri_slcd_get_interrupt_FC0O_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC0O) >> SLCD_INTFLAG_FC0O_Pos; -} - -static inline void hri_slcd_clear_interrupt_FC0O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC0O; -} - -static inline bool hri_slcd_get_interrupt_FC1O_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC1O) >> SLCD_INTFLAG_FC1O_Pos; -} - -static inline void hri_slcd_clear_interrupt_FC1O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC1O; -} - -static inline bool hri_slcd_get_interrupt_FC2O_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC2O) >> SLCD_INTFLAG_FC2O_Pos; -} - -static inline void hri_slcd_clear_interrupt_FC2O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC2O; -} - -static inline bool hri_slcd_get_interrupt_VLCDRT_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDRT) >> SLCD_INTFLAG_VLCDRT_Pos; -} - -static inline void hri_slcd_clear_interrupt_VLCDRT_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDRT; -} - -static inline bool hri_slcd_get_interrupt_VLCDST_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDST) >> SLCD_INTFLAG_VLCDST_Pos; -} - -static inline void hri_slcd_clear_interrupt_VLCDST_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDST; -} - -static inline bool hri_slcd_get_interrupt_PRST_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_PRST) >> SLCD_INTFLAG_PRST_Pos; -} - -static inline void hri_slcd_clear_interrupt_PRST_bit(const void *const hw) -{ - ((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_PRST; -} - -static inline hri_slcd_intflag_reg_t hri_slcd_get_INTFLAG_reg(const void *const hw, hri_slcd_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_slcd_intflag_reg_t hri_slcd_read_INTFLAG_reg(const void *const hw) -{ - return ((Slcd *)hw)->INTFLAG.reg; -} - -static inline void hri_slcd_clear_INTFLAG_reg(const void *const hw, hri_slcd_intflag_reg_t mask) -{ - ((Slcd *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_slcd_set_INTEN_FC0O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC0O; -} - -static inline bool hri_slcd_get_INTEN_FC0O_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC0O) >> SLCD_INTENSET_FC0O_Pos; -} - -static inline void hri_slcd_write_INTEN_FC0O_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC0O; - } else { - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC0O; - } -} - -static inline void hri_slcd_clear_INTEN_FC0O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC0O; -} - -static inline void hri_slcd_set_INTEN_FC1O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC1O; -} - -static inline bool hri_slcd_get_INTEN_FC1O_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC1O) >> SLCD_INTENSET_FC1O_Pos; -} - -static inline void hri_slcd_write_INTEN_FC1O_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC1O; - } else { - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC1O; - } -} - -static inline void hri_slcd_clear_INTEN_FC1O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC1O; -} - -static inline void hri_slcd_set_INTEN_FC2O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC2O; -} - -static inline bool hri_slcd_get_INTEN_FC2O_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC2O) >> SLCD_INTENSET_FC2O_Pos; -} - -static inline void hri_slcd_write_INTEN_FC2O_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC2O; - } else { - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC2O; - } -} - -static inline void hri_slcd_clear_INTEN_FC2O_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC2O; -} - -static inline void hri_slcd_set_INTEN_VLCDRT_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDRT; -} - -static inline bool hri_slcd_get_INTEN_VLCDRT_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_VLCDRT) >> SLCD_INTENSET_VLCDRT_Pos; -} - -static inline void hri_slcd_write_INTEN_VLCDRT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDRT; - } else { - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDRT; - } -} - -static inline void hri_slcd_clear_INTEN_VLCDRT_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDRT; -} - -static inline void hri_slcd_set_INTEN_VLCDST_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDST; -} - -static inline bool hri_slcd_get_INTEN_VLCDST_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_VLCDST) >> SLCD_INTENSET_VLCDST_Pos; -} - -static inline void hri_slcd_write_INTEN_VLCDST_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDST; - } else { - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDST; - } -} - -static inline void hri_slcd_clear_INTEN_VLCDST_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDST; -} - -static inline void hri_slcd_set_INTEN_PRST_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_PRST; -} - -static inline bool hri_slcd_get_INTEN_PRST_bit(const void *const hw) -{ - return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_PRST) >> SLCD_INTENSET_PRST_Pos; -} - -static inline void hri_slcd_write_INTEN_PRST_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_PRST; - } else { - ((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_PRST; - } -} - -static inline void hri_slcd_clear_INTEN_PRST_bit(const void *const hw) -{ - ((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_PRST; -} - -static inline void hri_slcd_set_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask) -{ - ((Slcd *)hw)->INTENSET.reg = mask; -} - -static inline hri_slcd_intenset_reg_t hri_slcd_get_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_slcd_intenset_reg_t hri_slcd_read_INTEN_reg(const void *const hw) -{ - return ((Slcd *)hw)->INTENSET.reg; -} - -static inline void hri_slcd_write_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t data) -{ - ((Slcd *)hw)->INTENSET.reg = data; - ((Slcd *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_slcd_clear_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask) -{ - ((Slcd *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_slcd_get_STATUS_VLCDR_bit(const void *const hw) -{ - return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_VLCDR) >> SLCD_STATUS_VLCDR_Pos; -} - -static inline bool hri_slcd_get_STATUS_PRUN_bit(const void *const hw) -{ - return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_PRUN) >> SLCD_STATUS_PRUN_Pos; -} - -static inline bool hri_slcd_get_STATUS_VLCDS_bit(const void *const hw) -{ - return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_VLCDS) >> SLCD_STATUS_VLCDS_Pos; -} - -static inline bool hri_slcd_get_STATUS_CMWRBUSY_bit(const void *const hw) -{ - return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_CMWRBUSY) >> SLCD_STATUS_CMWRBUSY_Pos; -} - -static inline bool hri_slcd_get_STATUS_ACMBUSY_bit(const void *const hw) -{ - return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_ACMBUSY) >> SLCD_STATUS_ACMBUSY_Pos; -} - -static inline bool hri_slcd_get_STATUS_ABMBUSY_bit(const void *const hw) -{ - return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_ABMBUSY) >> SLCD_STATUS_ABMBUSY_Pos; -} - -static inline hri_slcd_status_reg_t hri_slcd_get_STATUS_reg(const void *const hw, hri_slcd_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_slcd_status_reg_t hri_slcd_read_STATUS_reg(const void *const hw) -{ - return ((Slcd *)hw)->STATUS.reg; -} - -static inline bool hri_slcd_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_SWRST) >> SLCD_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_slcd_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_ENABLE) >> SLCD_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_slcd_get_SYNCBUSY_CTRLD_bit(const void *const hw) -{ - return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_CTRLD) >> SLCD_SYNCBUSY_CTRLD_Pos; -} - -static inline hri_slcd_syncbusy_reg_t hri_slcd_get_SYNCBUSY_reg(const void *const hw, hri_slcd_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_slcd_syncbusy_reg_t hri_slcd_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Slcd *)hw)->SYNCBUSY.reg; -} - -static inline void hri_slcd_set_CTRLA_SWRST_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_SWRST; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_SWRST) >> SLCD_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_ENABLE; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_ENABLE) >> SLCD_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= ~SLCD_CTRLA_ENABLE; - tmp |= value << SLCD_CTRLA_ENABLE_Pos; - ((Slcd *)hw)->CTRLA.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_ENABLE; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_ENABLE; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLA_WMOD_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_WMOD; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLA_WMOD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_WMOD) >> SLCD_CTRLA_WMOD_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLA_WMOD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= ~SLCD_CTRLA_WMOD; - tmp |= value << SLCD_CTRLA_WMOD_Pos; - ((Slcd *)hw)->CTRLA.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_WMOD_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_WMOD; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_WMOD_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_WMOD; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_RUNSTDBY; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_RUNSTDBY) >> SLCD_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= ~SLCD_CTRLA_RUNSTDBY; - tmp |= value << SLCD_CTRLA_RUNSTDBY_Pos; - ((Slcd *)hw)->CTRLA.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_RUNSTDBY; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_RUNSTDBY; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLA_XVLCD_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_XVLCD; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLA_XVLCD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_XVLCD) >> SLCD_CTRLA_XVLCD_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLA_XVLCD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= ~SLCD_CTRLA_XVLCD; - tmp |= value << SLCD_CTRLA_XVLCD_Pos; - ((Slcd *)hw)->CTRLA.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_XVLCD_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_XVLCD; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_XVLCD_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_XVLCD; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_DUTY(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_DUTY(mask)) >> SLCD_CTRLA_DUTY_Pos; - return tmp; -} - -static inline void hri_slcd_write_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= ~SLCD_CTRLA_DUTY_Msk; - tmp |= SLCD_CTRLA_DUTY(data); - ((Slcd *)hw)->CTRLA.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_DUTY(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_DUTY(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_DUTY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_DUTY_Msk) >> SLCD_CTRLA_DUTY_Pos; - return tmp; -} - -static inline void hri_slcd_set_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_PRESC(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_PRESC(mask)) >> SLCD_CTRLA_PRESC_Pos; - return tmp; -} - -static inline void hri_slcd_write_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= ~SLCD_CTRLA_PRESC_Msk; - tmp |= SLCD_CTRLA_PRESC(data); - ((Slcd *)hw)->CTRLA.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_PRESC(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_PRESC(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_PRESC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_PRESC_Msk) >> SLCD_CTRLA_PRESC_Pos; - return tmp; -} - -static inline void hri_slcd_set_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_CKDIV(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_CKDIV(mask)) >> SLCD_CTRLA_CKDIV_Pos; - return tmp; -} - -static inline void hri_slcd_write_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= ~SLCD_CTRLA_CKDIV_Msk; - tmp |= SLCD_CTRLA_CKDIV(data); - ((Slcd *)hw)->CTRLA.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_CKDIV(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_CKDIV(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_CKDIV_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_CKDIV_Msk) >> SLCD_CTRLA_CKDIV_Pos; - return tmp; -} - -static inline void hri_slcd_set_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_BIAS(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_BIAS(mask)) >> SLCD_CTRLA_BIAS_Pos; - return tmp; -} - -static inline void hri_slcd_write_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= ~SLCD_CTRLA_BIAS_Msk; - tmp |= SLCD_CTRLA_BIAS(data); - ((Slcd *)hw)->CTRLA.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_BIAS(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_BIAS(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_BIAS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_BIAS_Msk) >> SLCD_CTRLA_BIAS_Pos; - return tmp; -} - -static inline void hri_slcd_set_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_PRF(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_PRF(mask)) >> SLCD_CTRLA_PRF_Pos; - return tmp; -} - -static inline void hri_slcd_write_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= ~SLCD_CTRLA_PRF_Msk; - tmp |= SLCD_CTRLA_PRF(data); - ((Slcd *)hw)->CTRLA.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_PRF(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_PRF(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_PRF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_PRF_Msk) >> SLCD_CTRLA_PRF_Pos; - return tmp; -} - -static inline void hri_slcd_set_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_DMFCS(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_DMFCS(mask)) >> SLCD_CTRLA_DMFCS_Pos; - return tmp; -} - -static inline void hri_slcd_write_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= ~SLCD_CTRLA_DMFCS_Msk; - tmp |= SLCD_CTRLA_DMFCS(data); - ((Slcd *)hw)->CTRLA.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_DMFCS(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_DMFCS(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_DMFCS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_DMFCS_Msk) >> SLCD_CTRLA_DMFCS_Pos; - return tmp; -} - -static inline void hri_slcd_set_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_RRF(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_RRF(mask)) >> SLCD_CTRLA_RRF_Pos; - return tmp; -} - -static inline void hri_slcd_write_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= ~SLCD_CTRLA_RRF_Msk; - tmp |= SLCD_CTRLA_RRF(data); - ((Slcd *)hw)->CTRLA.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_RRF(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_RRF(mask); - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_RRF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp = (tmp & SLCD_CTRLA_RRF_Msk) >> SLCD_CTRLA_RRF_Pos; - return tmp; -} - -static inline void hri_slcd_set_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg |= mask; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); - tmp = ((Slcd *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg = data; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg &= ~mask; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLA.reg ^= mask; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_reg(const void *const hw) -{ - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE); - return ((Slcd *)hw)->CTRLA.reg; -} - -static inline void hri_slcd_set_CTRLB_BBEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_BBEN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLB_BBEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLB.reg; - tmp = (tmp & SLCD_CTRLB_BBEN) >> SLCD_CTRLB_BBEN_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLB_BBEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLB.reg; - tmp &= ~SLCD_CTRLB_BBEN; - tmp |= value << SLCD_CTRLB_BBEN_Pos; - ((Slcd *)hw)->CTRLB.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLB_BBEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_BBEN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLB_BBEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_BBEN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLB_LREN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_LREN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLB_LREN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLB.reg; - tmp = (tmp & SLCD_CTRLB_LREN) >> SLCD_CTRLB_LREN_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLB_LREN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLB.reg; - tmp &= ~SLCD_CTRLB_LREN; - tmp |= value << SLCD_CTRLB_LREN_Pos; - ((Slcd *)hw)->CTRLB.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLB_LREN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_LREN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLB_LREN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_LREN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_BBD(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLB.reg; - tmp = (tmp & SLCD_CTRLB_BBD(mask)) >> SLCD_CTRLB_BBD_Pos; - return tmp; -} - -static inline void hri_slcd_write_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t data) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLB.reg; - tmp &= ~SLCD_CTRLB_BBD_Msk; - tmp |= SLCD_CTRLB_BBD(data); - ((Slcd *)hw)->CTRLB.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_BBD(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_BBD(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_BBD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLB.reg; - tmp = (tmp & SLCD_CTRLB_BBD_Msk) >> SLCD_CTRLB_BBD_Pos; - return tmp; -} - -static inline void hri_slcd_set_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_LRD(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLB.reg; - tmp = (tmp & SLCD_CTRLB_LRD(mask)) >> SLCD_CTRLB_LRD_Pos; - return tmp; -} - -static inline void hri_slcd_write_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t data) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLB.reg; - tmp &= ~SLCD_CTRLB_LRD_Msk; - tmp |= SLCD_CTRLB_LRD(data); - ((Slcd *)hw)->CTRLB.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_LRD(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_LRD(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_LRD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLB.reg; - tmp = (tmp & SLCD_CTRLB_LRD_Msk) >> SLCD_CTRLB_LRD_Pos; - return tmp; -} - -static inline void hri_slcd_set_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLB.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_reg(const void *const hw) -{ - return ((Slcd *)hw)->CTRLB.reg; -} - -static inline void hri_slcd_set_CTRLC_CLEAR_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_CLEAR; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLC_CLEAR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp = (tmp & SLCD_CTRLC_CLEAR) >> SLCD_CTRLC_CLEAR_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLC_CLEAR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp &= ~SLCD_CTRLC_CLEAR; - tmp |= value << SLCD_CTRLC_CLEAR_Pos; - ((Slcd *)hw)->CTRLC.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLC_CLEAR_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_CLEAR; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLC_CLEAR_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_CLEAR; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLC_LOCK_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_LOCK; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLC_LOCK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp = (tmp & SLCD_CTRLC_LOCK) >> SLCD_CTRLC_LOCK_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLC_LOCK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp &= ~SLCD_CTRLC_LOCK; - tmp |= value << SLCD_CTRLC_LOCK_Pos; - ((Slcd *)hw)->CTRLC.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLC_LOCK_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_LOCK; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLC_LOCK_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_LOCK; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLC_ABMEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_ABMEN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLC_ABMEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp = (tmp & SLCD_CTRLC_ABMEN) >> SLCD_CTRLC_ABMEN_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLC_ABMEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp &= ~SLCD_CTRLC_ABMEN; - tmp |= value << SLCD_CTRLC_ABMEN_Pos; - ((Slcd *)hw)->CTRLC.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLC_ABMEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_ABMEN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLC_ABMEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_ABMEN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLC_ACMEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_ACMEN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLC_ACMEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp = (tmp & SLCD_CTRLC_ACMEN) >> SLCD_CTRLC_ACMEN_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLC_ACMEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp &= ~SLCD_CTRLC_ACMEN; - tmp |= value << SLCD_CTRLC_ACMEN_Pos; - ((Slcd *)hw)->CTRLC.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLC_ACMEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_ACMEN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLC_ACMEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_ACMEN; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_CTST(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp = (tmp & SLCD_CTRLC_CTST(mask)) >> SLCD_CTRLC_CTST_Pos; - return tmp; -} - -static inline void hri_slcd_write_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t data) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp &= ~SLCD_CTRLC_CTST_Msk; - tmp |= SLCD_CTRLC_CTST(data); - ((Slcd *)hw)->CTRLC.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_CTST(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_CTST(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_CTST_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp = (tmp & SLCD_CTRLC_CTST_Msk) >> SLCD_CTRLC_CTST_Pos; - return tmp; -} - -static inline void hri_slcd_set_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_LPPM(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp = (tmp & SLCD_CTRLC_LPPM(mask)) >> SLCD_CTRLC_LPPM_Pos; - return tmp; -} - -static inline void hri_slcd_write_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t data) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp &= ~SLCD_CTRLC_LPPM_Msk; - tmp |= SLCD_CTRLC_LPPM(data); - ((Slcd *)hw)->CTRLC.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_LPPM(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_LPPM(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_LPPM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp = (tmp & SLCD_CTRLC_LPPM_Msk) >> SLCD_CTRLC_LPPM_Pos; - return tmp; -} - -static inline void hri_slcd_set_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLC.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_reg(const void *const hw) -{ - return ((Slcd *)hw)->CTRLC.reg; -} - -static inline void hri_slcd_set_CTRLD_BLANK_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_BLANK; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLD_BLANK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp = (tmp & SLCD_CTRLD_BLANK) >> SLCD_CTRLD_BLANK_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLD_BLANK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp &= ~SLCD_CTRLD_BLANK; - tmp |= value << SLCD_CTRLD_BLANK_Pos; - ((Slcd *)hw)->CTRLD.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLD_BLANK_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_BLANK; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLD_BLANK_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_BLANK; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLD_BLINK_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_BLINK; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLD_BLINK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp = (tmp & SLCD_CTRLD_BLINK) >> SLCD_CTRLD_BLINK_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLD_BLINK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp &= ~SLCD_CTRLD_BLINK; - tmp |= value << SLCD_CTRLD_BLINK_Pos; - ((Slcd *)hw)->CTRLD.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLD_BLINK_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_BLINK; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLD_BLINK_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_BLINK; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLD_CSREN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_CSREN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLD_CSREN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp = (tmp & SLCD_CTRLD_CSREN) >> SLCD_CTRLD_CSREN_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLD_CSREN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp &= ~SLCD_CTRLD_CSREN; - tmp |= value << SLCD_CTRLD_CSREN_Pos; - ((Slcd *)hw)->CTRLD.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLD_CSREN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_CSREN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLD_CSREN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_CSREN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLD_FC0EN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC0EN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLD_FC0EN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp = (tmp & SLCD_CTRLD_FC0EN) >> SLCD_CTRLD_FC0EN_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLD_FC0EN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp &= ~SLCD_CTRLD_FC0EN; - tmp |= value << SLCD_CTRLD_FC0EN_Pos; - ((Slcd *)hw)->CTRLD.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLD_FC0EN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC0EN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLD_FC0EN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC0EN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLD_FC1EN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC1EN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLD_FC1EN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp = (tmp & SLCD_CTRLD_FC1EN) >> SLCD_CTRLD_FC1EN_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLD_FC1EN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp &= ~SLCD_CTRLD_FC1EN; - tmp |= value << SLCD_CTRLD_FC1EN_Pos; - ((Slcd *)hw)->CTRLD.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLD_FC1EN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC1EN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLD_FC1EN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC1EN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLD_FC2EN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC2EN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLD_FC2EN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp = (tmp & SLCD_CTRLD_FC2EN) >> SLCD_CTRLD_FC2EN_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLD_FC2EN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp &= ~SLCD_CTRLD_FC2EN; - tmp |= value << SLCD_CTRLD_FC2EN_Pos; - ((Slcd *)hw)->CTRLD.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLD_FC2EN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC2EN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLD_FC2EN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC2EN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLD_DISPEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_DISPEN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CTRLD_DISPEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp = (tmp & SLCD_CTRLD_DISPEN) >> SLCD_CTRLD_DISPEN_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CTRLD_DISPEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp &= ~SLCD_CTRLD_DISPEN; - tmp |= value << SLCD_CTRLD_DISPEN_Pos; - ((Slcd *)hw)->CTRLD.reg = tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLD_DISPEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_DISPEN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLD_DISPEN_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_DISPEN; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg |= mask; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrld_reg_t hri_slcd_get_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask) -{ - uint8_t tmp; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - tmp = ((Slcd *)hw)->CTRLD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg = data; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg &= ~mask; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CTRLD.reg ^= mask; - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_ctrld_reg_t hri_slcd_read_CTRLD_reg(const void *const hw) -{ - hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK); - return ((Slcd *)hw)->CTRLD.reg; -} - -static inline void hri_slcd_set_EVCTRL_FC0OEO_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC0OEO; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_EVCTRL_FC0OEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->EVCTRL.reg; - tmp = (tmp & SLCD_EVCTRL_FC0OEO) >> SLCD_EVCTRL_FC0OEO_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_EVCTRL_FC0OEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->EVCTRL.reg; - tmp &= ~SLCD_EVCTRL_FC0OEO; - tmp |= value << SLCD_EVCTRL_FC0OEO_Pos; - ((Slcd *)hw)->EVCTRL.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_EVCTRL_FC0OEO_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC0OEO; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_EVCTRL_FC0OEO_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC0OEO; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_EVCTRL_FC1OEO_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC1OEO; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_EVCTRL_FC1OEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->EVCTRL.reg; - tmp = (tmp & SLCD_EVCTRL_FC1OEO) >> SLCD_EVCTRL_FC1OEO_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_EVCTRL_FC1OEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->EVCTRL.reg; - tmp &= ~SLCD_EVCTRL_FC1OEO; - tmp |= value << SLCD_EVCTRL_FC1OEO_Pos; - ((Slcd *)hw)->EVCTRL.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_EVCTRL_FC1OEO_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC1OEO; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_EVCTRL_FC1OEO_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC1OEO; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_EVCTRL_FC2OEO_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC2OEO; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_EVCTRL_FC2OEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->EVCTRL.reg; - tmp = (tmp & SLCD_EVCTRL_FC2OEO) >> SLCD_EVCTRL_FC2OEO_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_EVCTRL_FC2OEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->EVCTRL.reg; - tmp &= ~SLCD_EVCTRL_FC2OEO; - tmp |= value << SLCD_EVCTRL_FC2OEO_Pos; - ((Slcd *)hw)->EVCTRL.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_EVCTRL_FC2OEO_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC2OEO; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_EVCTRL_FC2OEO_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC2OEO; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_evctrl_reg_t hri_slcd_get_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->EVCTRL.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_evctrl_reg_t hri_slcd_read_EVCTRL_reg(const void *const hw) -{ - return ((Slcd *)hw)->EVCTRL.reg; -} - -static inline void hri_slcd_set_FC0_PB_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC0.reg |= SLCD_FC0_PB; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_FC0_PB_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC0.reg; - tmp = (tmp & SLCD_FC0_PB) >> SLCD_FC0_PB_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_FC0_PB_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->FC0.reg; - tmp &= ~SLCD_FC0_PB; - tmp |= value << SLCD_FC0_PB_Pos; - ((Slcd *)hw)->FC0.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_FC0_PB_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC0.reg &= ~SLCD_FC0_PB; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_FC0_PB_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC0.reg ^= SLCD_FC0_PB; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC0.reg |= SLCD_FC0_OVF(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc0_reg_t hri_slcd_get_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC0.reg; - tmp = (tmp & SLCD_FC0_OVF(mask)) >> SLCD_FC0_OVF_Pos; - return tmp; -} - -static inline void hri_slcd_write_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t data) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->FC0.reg; - tmp &= ~SLCD_FC0_OVF_Msk; - tmp |= SLCD_FC0_OVF(data); - ((Slcd *)hw)->FC0.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC0.reg &= ~SLCD_FC0_OVF(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC0.reg ^= SLCD_FC0_OVF(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc0_reg_t hri_slcd_read_FC0_OVF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC0.reg; - tmp = (tmp & SLCD_FC0_OVF_Msk) >> SLCD_FC0_OVF_Pos; - return tmp; -} - -static inline void hri_slcd_set_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC0.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc0_reg_t hri_slcd_get_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC0.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC0.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC0.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc0_reg_t hri_slcd_read_FC0_reg(const void *const hw) -{ - return ((Slcd *)hw)->FC0.reg; -} - -static inline void hri_slcd_set_FC1_PB_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC1.reg |= SLCD_FC1_PB; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_FC1_PB_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC1.reg; - tmp = (tmp & SLCD_FC1_PB) >> SLCD_FC1_PB_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_FC1_PB_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->FC1.reg; - tmp &= ~SLCD_FC1_PB; - tmp |= value << SLCD_FC1_PB_Pos; - ((Slcd *)hw)->FC1.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_FC1_PB_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC1.reg &= ~SLCD_FC1_PB; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_FC1_PB_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC1.reg ^= SLCD_FC1_PB; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC1.reg |= SLCD_FC1_OVF(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc1_reg_t hri_slcd_get_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC1.reg; - tmp = (tmp & SLCD_FC1_OVF(mask)) >> SLCD_FC1_OVF_Pos; - return tmp; -} - -static inline void hri_slcd_write_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t data) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->FC1.reg; - tmp &= ~SLCD_FC1_OVF_Msk; - tmp |= SLCD_FC1_OVF(data); - ((Slcd *)hw)->FC1.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC1.reg &= ~SLCD_FC1_OVF(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC1.reg ^= SLCD_FC1_OVF(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc1_reg_t hri_slcd_read_FC1_OVF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC1.reg; - tmp = (tmp & SLCD_FC1_OVF_Msk) >> SLCD_FC1_OVF_Pos; - return tmp; -} - -static inline void hri_slcd_set_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC1.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc1_reg_t hri_slcd_get_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC1.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC1.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC1.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc1_reg_t hri_slcd_read_FC1_reg(const void *const hw) -{ - return ((Slcd *)hw)->FC1.reg; -} - -static inline void hri_slcd_set_FC2_PB_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC2.reg |= SLCD_FC2_PB; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_FC2_PB_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC2.reg; - tmp = (tmp & SLCD_FC2_PB) >> SLCD_FC2_PB_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_FC2_PB_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->FC2.reg; - tmp &= ~SLCD_FC2_PB; - tmp |= value << SLCD_FC2_PB_Pos; - ((Slcd *)hw)->FC2.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_FC2_PB_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC2.reg &= ~SLCD_FC2_PB; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_FC2_PB_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC2.reg ^= SLCD_FC2_PB; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC2.reg |= SLCD_FC2_OVF(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc2_reg_t hri_slcd_get_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC2.reg; - tmp = (tmp & SLCD_FC2_OVF(mask)) >> SLCD_FC2_OVF_Pos; - return tmp; -} - -static inline void hri_slcd_write_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t data) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->FC2.reg; - tmp &= ~SLCD_FC2_OVF_Msk; - tmp |= SLCD_FC2_OVF(data); - ((Slcd *)hw)->FC2.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC2.reg &= ~SLCD_FC2_OVF(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC2.reg ^= SLCD_FC2_OVF(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc2_reg_t hri_slcd_read_FC2_OVF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC2.reg; - tmp = (tmp & SLCD_FC2_OVF_Msk) >> SLCD_FC2_OVF_Pos; - return tmp; -} - -static inline void hri_slcd_set_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC2.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc2_reg_t hri_slcd_get_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->FC2.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC2.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC2.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->FC2.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_fc2_reg_t hri_slcd_read_FC2_reg(const void *const hw) -{ - return ((Slcd *)hw)->FC2.reg; -} - -static inline void hri_slcd_set_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENL.reg |= SLCD_LPENL_LPEN(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_lpenl_reg_t hri_slcd_get_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->LPENL.reg; - tmp = (tmp & SLCD_LPENL_LPEN(mask)) >> SLCD_LPENL_LPEN_Pos; - return tmp; -} - -static inline void hri_slcd_write_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->LPENL.reg; - tmp &= ~SLCD_LPENL_LPEN_Msk; - tmp |= SLCD_LPENL_LPEN(data); - ((Slcd *)hw)->LPENL.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENL.reg &= ~SLCD_LPENL_LPEN(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENL.reg ^= SLCD_LPENL_LPEN(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_lpenl_reg_t hri_slcd_read_LPENL_LPEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->LPENL.reg; - tmp = (tmp & SLCD_LPENL_LPEN_Msk) >> SLCD_LPENL_LPEN_Pos; - return tmp; -} - -static inline void hri_slcd_set_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENL.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_lpenl_reg_t hri_slcd_get_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->LPENL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENL.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENL.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENL.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_lpenl_reg_t hri_slcd_read_LPENL_reg(const void *const hw) -{ - return ((Slcd *)hw)->LPENL.reg; -} - -static inline void hri_slcd_set_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENH.reg |= SLCD_LPENH_LPEN(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_lpenh_reg_t hri_slcd_get_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->LPENH.reg; - tmp = (tmp & SLCD_LPENH_LPEN(mask)) >> SLCD_LPENH_LPEN_Pos; - return tmp; -} - -static inline void hri_slcd_write_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->LPENH.reg; - tmp &= ~SLCD_LPENH_LPEN_Msk; - tmp |= SLCD_LPENH_LPEN(data); - ((Slcd *)hw)->LPENH.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENH.reg &= ~SLCD_LPENH_LPEN(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENH.reg ^= SLCD_LPENH_LPEN(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_lpenh_reg_t hri_slcd_read_LPENH_LPEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->LPENH.reg; - tmp = (tmp & SLCD_LPENH_LPEN_Msk) >> SLCD_LPENH_LPEN_Pos; - return tmp; -} - -static inline void hri_slcd_set_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENH.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_lpenh_reg_t hri_slcd_get_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->LPENH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENH.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENH.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->LPENH.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_lpenh_reg_t hri_slcd_read_LPENH_reg(const void *const hw) -{ - return ((Slcd *)hw)->LPENH.reg; -} - -static inline void hri_slcd_set_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL0.reg |= SLCD_SDATAL0_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal0_reg_t hri_slcd_get_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL0.reg; - tmp = (tmp & SLCD_SDATAL0_SDATA(mask)) >> SLCD_SDATAL0_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAL0.reg; - tmp &= ~SLCD_SDATAL0_SDATA_Msk; - tmp |= SLCD_SDATAL0_SDATA(data); - ((Slcd *)hw)->SDATAL0.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL0.reg &= ~SLCD_SDATAL0_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL0.reg ^= SLCD_SDATAL0_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal0_reg_t hri_slcd_read_SDATAL0_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL0.reg; - tmp = (tmp & SLCD_SDATAL0_SDATA_Msk) >> SLCD_SDATAL0_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL0.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal0_reg_t hri_slcd_get_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL0.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL0.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL0.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal0_reg_t hri_slcd_read_SDATAL0_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAL0.reg; -} - -static inline void hri_slcd_set_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH0.reg |= SLCD_SDATAH0_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah0_reg_t hri_slcd_get_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH0.reg; - tmp = (tmp & SLCD_SDATAH0_SDATA(mask)) >> SLCD_SDATAH0_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAH0.reg; - tmp &= ~SLCD_SDATAH0_SDATA_Msk; - tmp |= SLCD_SDATAH0_SDATA(data); - ((Slcd *)hw)->SDATAH0.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH0.reg &= ~SLCD_SDATAH0_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH0.reg ^= SLCD_SDATAH0_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah0_reg_t hri_slcd_read_SDATAH0_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH0.reg; - tmp = (tmp & SLCD_SDATAH0_SDATA_Msk) >> SLCD_SDATAH0_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH0.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah0_reg_t hri_slcd_get_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH0.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH0.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH0.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah0_reg_t hri_slcd_read_SDATAH0_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAH0.reg; -} - -static inline void hri_slcd_set_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL1.reg |= SLCD_SDATAL1_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal1_reg_t hri_slcd_get_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL1.reg; - tmp = (tmp & SLCD_SDATAL1_SDATA(mask)) >> SLCD_SDATAL1_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAL1.reg; - tmp &= ~SLCD_SDATAL1_SDATA_Msk; - tmp |= SLCD_SDATAL1_SDATA(data); - ((Slcd *)hw)->SDATAL1.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL1.reg &= ~SLCD_SDATAL1_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL1.reg ^= SLCD_SDATAL1_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal1_reg_t hri_slcd_read_SDATAL1_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL1.reg; - tmp = (tmp & SLCD_SDATAL1_SDATA_Msk) >> SLCD_SDATAL1_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL1.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal1_reg_t hri_slcd_get_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL1.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL1.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL1.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal1_reg_t hri_slcd_read_SDATAL1_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAL1.reg; -} - -static inline void hri_slcd_set_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH1.reg |= SLCD_SDATAH1_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah1_reg_t hri_slcd_get_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH1.reg; - tmp = (tmp & SLCD_SDATAH1_SDATA(mask)) >> SLCD_SDATAH1_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAH1.reg; - tmp &= ~SLCD_SDATAH1_SDATA_Msk; - tmp |= SLCD_SDATAH1_SDATA(data); - ((Slcd *)hw)->SDATAH1.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH1.reg &= ~SLCD_SDATAH1_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH1.reg ^= SLCD_SDATAH1_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah1_reg_t hri_slcd_read_SDATAH1_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH1.reg; - tmp = (tmp & SLCD_SDATAH1_SDATA_Msk) >> SLCD_SDATAH1_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH1.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah1_reg_t hri_slcd_get_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH1.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH1.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH1.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah1_reg_t hri_slcd_read_SDATAH1_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAH1.reg; -} - -static inline void hri_slcd_set_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL2.reg |= SLCD_SDATAL2_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal2_reg_t hri_slcd_get_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL2.reg; - tmp = (tmp & SLCD_SDATAL2_SDATA(mask)) >> SLCD_SDATAL2_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAL2.reg; - tmp &= ~SLCD_SDATAL2_SDATA_Msk; - tmp |= SLCD_SDATAL2_SDATA(data); - ((Slcd *)hw)->SDATAL2.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL2.reg &= ~SLCD_SDATAL2_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL2.reg ^= SLCD_SDATAL2_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal2_reg_t hri_slcd_read_SDATAL2_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL2.reg; - tmp = (tmp & SLCD_SDATAL2_SDATA_Msk) >> SLCD_SDATAL2_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL2.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal2_reg_t hri_slcd_get_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL2.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL2.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL2.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL2.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal2_reg_t hri_slcd_read_SDATAL2_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAL2.reg; -} - -static inline void hri_slcd_set_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH2.reg |= SLCD_SDATAH2_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah2_reg_t hri_slcd_get_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH2.reg; - tmp = (tmp & SLCD_SDATAH2_SDATA(mask)) >> SLCD_SDATAH2_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAH2.reg; - tmp &= ~SLCD_SDATAH2_SDATA_Msk; - tmp |= SLCD_SDATAH2_SDATA(data); - ((Slcd *)hw)->SDATAH2.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH2.reg &= ~SLCD_SDATAH2_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH2.reg ^= SLCD_SDATAH2_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah2_reg_t hri_slcd_read_SDATAH2_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH2.reg; - tmp = (tmp & SLCD_SDATAH2_SDATA_Msk) >> SLCD_SDATAH2_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH2.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah2_reg_t hri_slcd_get_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH2.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH2.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH2.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH2.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah2_reg_t hri_slcd_read_SDATAH2_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAH2.reg; -} - -static inline void hri_slcd_set_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL3.reg |= SLCD_SDATAL3_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal3_reg_t hri_slcd_get_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL3.reg; - tmp = (tmp & SLCD_SDATAL3_SDATA(mask)) >> SLCD_SDATAL3_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAL3.reg; - tmp &= ~SLCD_SDATAL3_SDATA_Msk; - tmp |= SLCD_SDATAL3_SDATA(data); - ((Slcd *)hw)->SDATAL3.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL3.reg &= ~SLCD_SDATAL3_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL3.reg ^= SLCD_SDATAL3_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal3_reg_t hri_slcd_read_SDATAL3_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL3.reg; - tmp = (tmp & SLCD_SDATAL3_SDATA_Msk) >> SLCD_SDATAL3_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL3.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal3_reg_t hri_slcd_get_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL3.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL3.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL3.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL3.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal3_reg_t hri_slcd_read_SDATAL3_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAL3.reg; -} - -static inline void hri_slcd_set_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH3.reg |= SLCD_SDATAH3_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah3_reg_t hri_slcd_get_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH3.reg; - tmp = (tmp & SLCD_SDATAH3_SDATA(mask)) >> SLCD_SDATAH3_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAH3.reg; - tmp &= ~SLCD_SDATAH3_SDATA_Msk; - tmp |= SLCD_SDATAH3_SDATA(data); - ((Slcd *)hw)->SDATAH3.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH3.reg &= ~SLCD_SDATAH3_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH3.reg ^= SLCD_SDATAH3_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah3_reg_t hri_slcd_read_SDATAH3_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH3.reg; - tmp = (tmp & SLCD_SDATAH3_SDATA_Msk) >> SLCD_SDATAH3_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH3.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah3_reg_t hri_slcd_get_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH3.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH3.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH3.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH3.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah3_reg_t hri_slcd_read_SDATAH3_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAH3.reg; -} - -static inline void hri_slcd_set_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL4.reg |= SLCD_SDATAL4_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal4_reg_t hri_slcd_get_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL4.reg; - tmp = (tmp & SLCD_SDATAL4_SDATA(mask)) >> SLCD_SDATAL4_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAL4.reg; - tmp &= ~SLCD_SDATAL4_SDATA_Msk; - tmp |= SLCD_SDATAL4_SDATA(data); - ((Slcd *)hw)->SDATAL4.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL4.reg &= ~SLCD_SDATAL4_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL4.reg ^= SLCD_SDATAL4_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal4_reg_t hri_slcd_read_SDATAL4_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL4.reg; - tmp = (tmp & SLCD_SDATAL4_SDATA_Msk) >> SLCD_SDATAL4_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL4.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal4_reg_t hri_slcd_get_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL4.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL4.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL4.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL4.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal4_reg_t hri_slcd_read_SDATAL4_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAL4.reg; -} - -static inline void hri_slcd_set_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH4.reg |= SLCD_SDATAH4_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah4_reg_t hri_slcd_get_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH4.reg; - tmp = (tmp & SLCD_SDATAH4_SDATA(mask)) >> SLCD_SDATAH4_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAH4.reg; - tmp &= ~SLCD_SDATAH4_SDATA_Msk; - tmp |= SLCD_SDATAH4_SDATA(data); - ((Slcd *)hw)->SDATAH4.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH4.reg &= ~SLCD_SDATAH4_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH4.reg ^= SLCD_SDATAH4_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah4_reg_t hri_slcd_read_SDATAH4_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH4.reg; - tmp = (tmp & SLCD_SDATAH4_SDATA_Msk) >> SLCD_SDATAH4_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH4.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah4_reg_t hri_slcd_get_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH4.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH4.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH4.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH4.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah4_reg_t hri_slcd_read_SDATAH4_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAH4.reg; -} - -static inline void hri_slcd_set_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL5.reg |= SLCD_SDATAL5_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal5_reg_t hri_slcd_get_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL5.reg; - tmp = (tmp & SLCD_SDATAL5_SDATA(mask)) >> SLCD_SDATAL5_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAL5.reg; - tmp &= ~SLCD_SDATAL5_SDATA_Msk; - tmp |= SLCD_SDATAL5_SDATA(data); - ((Slcd *)hw)->SDATAL5.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL5.reg &= ~SLCD_SDATAL5_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL5.reg ^= SLCD_SDATAL5_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal5_reg_t hri_slcd_read_SDATAL5_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL5.reg; - tmp = (tmp & SLCD_SDATAL5_SDATA_Msk) >> SLCD_SDATAL5_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL5.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal5_reg_t hri_slcd_get_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL5.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL5.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL5.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL5.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal5_reg_t hri_slcd_read_SDATAL5_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAL5.reg; -} - -static inline void hri_slcd_set_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH5.reg |= SLCD_SDATAH5_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah5_reg_t hri_slcd_get_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH5.reg; - tmp = (tmp & SLCD_SDATAH5_SDATA(mask)) >> SLCD_SDATAH5_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAH5.reg; - tmp &= ~SLCD_SDATAH5_SDATA_Msk; - tmp |= SLCD_SDATAH5_SDATA(data); - ((Slcd *)hw)->SDATAH5.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH5.reg &= ~SLCD_SDATAH5_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH5.reg ^= SLCD_SDATAH5_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah5_reg_t hri_slcd_read_SDATAH5_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH5.reg; - tmp = (tmp & SLCD_SDATAH5_SDATA_Msk) >> SLCD_SDATAH5_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH5.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah5_reg_t hri_slcd_get_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH5.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH5.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH5.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH5.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah5_reg_t hri_slcd_read_SDATAH5_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAH5.reg; -} - -static inline void hri_slcd_set_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL6.reg |= SLCD_SDATAL6_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal6_reg_t hri_slcd_get_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL6.reg; - tmp = (tmp & SLCD_SDATAL6_SDATA(mask)) >> SLCD_SDATAL6_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAL6.reg; - tmp &= ~SLCD_SDATAL6_SDATA_Msk; - tmp |= SLCD_SDATAL6_SDATA(data); - ((Slcd *)hw)->SDATAL6.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL6.reg &= ~SLCD_SDATAL6_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL6.reg ^= SLCD_SDATAL6_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal6_reg_t hri_slcd_read_SDATAL6_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL6.reg; - tmp = (tmp & SLCD_SDATAL6_SDATA_Msk) >> SLCD_SDATAL6_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL6.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal6_reg_t hri_slcd_get_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL6.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL6.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL6.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL6.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal6_reg_t hri_slcd_read_SDATAL6_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAL6.reg; -} - -static inline void hri_slcd_set_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH6.reg |= SLCD_SDATAH6_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah6_reg_t hri_slcd_get_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH6.reg; - tmp = (tmp & SLCD_SDATAH6_SDATA(mask)) >> SLCD_SDATAH6_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAH6.reg; - tmp &= ~SLCD_SDATAH6_SDATA_Msk; - tmp |= SLCD_SDATAH6_SDATA(data); - ((Slcd *)hw)->SDATAH6.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH6.reg &= ~SLCD_SDATAH6_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH6.reg ^= SLCD_SDATAH6_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah6_reg_t hri_slcd_read_SDATAH6_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH6.reg; - tmp = (tmp & SLCD_SDATAH6_SDATA_Msk) >> SLCD_SDATAH6_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH6.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah6_reg_t hri_slcd_get_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH6.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH6.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH6.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH6.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah6_reg_t hri_slcd_read_SDATAH6_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAH6.reg; -} - -static inline void hri_slcd_set_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL7.reg |= SLCD_SDATAL7_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal7_reg_t hri_slcd_get_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL7.reg; - tmp = (tmp & SLCD_SDATAL7_SDATA(mask)) >> SLCD_SDATAL7_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAL7.reg; - tmp &= ~SLCD_SDATAL7_SDATA_Msk; - tmp |= SLCD_SDATAL7_SDATA(data); - ((Slcd *)hw)->SDATAL7.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL7.reg &= ~SLCD_SDATAL7_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL7.reg ^= SLCD_SDATAL7_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal7_reg_t hri_slcd_read_SDATAL7_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL7.reg; - tmp = (tmp & SLCD_SDATAL7_SDATA_Msk) >> SLCD_SDATAL7_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL7.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal7_reg_t hri_slcd_get_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAL7.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL7.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL7.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAL7.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatal7_reg_t hri_slcd_read_SDATAL7_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAL7.reg; -} - -static inline void hri_slcd_set_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH7.reg |= SLCD_SDATAH7_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah7_reg_t hri_slcd_get_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH7.reg; - tmp = (tmp & SLCD_SDATAH7_SDATA(mask)) >> SLCD_SDATAH7_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->SDATAH7.reg; - tmp &= ~SLCD_SDATAH7_SDATA_Msk; - tmp |= SLCD_SDATAH7_SDATA(data); - ((Slcd *)hw)->SDATAH7.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH7.reg &= ~SLCD_SDATAH7_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH7.reg ^= SLCD_SDATAH7_SDATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah7_reg_t hri_slcd_read_SDATAH7_SDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH7.reg; - tmp = (tmp & SLCD_SDATAH7_SDATA_Msk) >> SLCD_SDATAH7_SDATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH7.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah7_reg_t hri_slcd_get_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->SDATAH7.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH7.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH7.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->SDATAH7.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_sdatah7_reg_t hri_slcd_read_SDATAH7_reg(const void *const hw) -{ - return ((Slcd *)hw)->SDATAH7.reg; -} - -static inline void hri_slcd_set_BCFG_MODE_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_MODE; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_BCFG_MODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->BCFG.reg; - tmp = (tmp & SLCD_BCFG_MODE) >> SLCD_BCFG_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_BCFG_MODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->BCFG.reg; - tmp &= ~SLCD_BCFG_MODE; - tmp |= value << SLCD_BCFG_MODE_Pos; - ((Slcd *)hw)->BCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_BCFG_MODE_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_MODE; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_BCFG_MODE_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_MODE; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->BCFG.reg; - tmp = (tmp & SLCD_BCFG_FCS(mask)) >> SLCD_BCFG_FCS_Pos; - return tmp; -} - -static inline void hri_slcd_write_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->BCFG.reg; - tmp &= ~SLCD_BCFG_FCS_Msk; - tmp |= SLCD_BCFG_FCS(data); - ((Slcd *)hw)->BCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_FCS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->BCFG.reg; - tmp = (tmp & SLCD_BCFG_FCS_Msk) >> SLCD_BCFG_FCS_Pos; - return tmp; -} - -static inline void hri_slcd_set_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_BSS0(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->BCFG.reg; - tmp = (tmp & SLCD_BCFG_BSS0(mask)) >> SLCD_BCFG_BSS0_Pos; - return tmp; -} - -static inline void hri_slcd_write_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->BCFG.reg; - tmp &= ~SLCD_BCFG_BSS0_Msk; - tmp |= SLCD_BCFG_BSS0(data); - ((Slcd *)hw)->BCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_BSS0(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_BSS0(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_BSS0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->BCFG.reg; - tmp = (tmp & SLCD_BCFG_BSS0_Msk) >> SLCD_BCFG_BSS0_Pos; - return tmp; -} - -static inline void hri_slcd_set_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_BSS1(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->BCFG.reg; - tmp = (tmp & SLCD_BCFG_BSS1(mask)) >> SLCD_BCFG_BSS1_Pos; - return tmp; -} - -static inline void hri_slcd_write_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->BCFG.reg; - tmp &= ~SLCD_BCFG_BSS1_Msk; - tmp |= SLCD_BCFG_BSS1(data); - ((Slcd *)hw)->BCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_BSS1(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_BSS1(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_BSS1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->BCFG.reg; - tmp = (tmp & SLCD_BCFG_BSS1_Msk) >> SLCD_BCFG_BSS1_Pos; - return tmp; -} - -static inline void hri_slcd_set_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->BCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->BCFG.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_reg(const void *const hw) -{ - return ((Slcd *)hw)->BCFG.reg; -} - -static inline void hri_slcd_set_CSRCFG_DIR_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_DIR; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CSRCFG_DIR_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp = (tmp & SLCD_CSRCFG_DIR) >> SLCD_CSRCFG_DIR_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CSRCFG_DIR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp &= ~SLCD_CSRCFG_DIR; - tmp |= value << SLCD_CSRCFG_DIR_Pos; - ((Slcd *)hw)->CSRCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CSRCFG_DIR_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_DIR; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CSRCFG_DIR_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_DIR; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp = (tmp & SLCD_CSRCFG_FCS(mask)) >> SLCD_CSRCFG_FCS_Pos; - return tmp; -} - -static inline void hri_slcd_write_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp &= ~SLCD_CSRCFG_FCS_Msk; - tmp |= SLCD_CSRCFG_FCS(data); - ((Slcd *)hw)->CSRCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_FCS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp = (tmp & SLCD_CSRCFG_FCS_Msk) >> SLCD_CSRCFG_FCS_Pos; - return tmp; -} - -static inline void hri_slcd_set_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_SIZE(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp = (tmp & SLCD_CSRCFG_SIZE(mask)) >> SLCD_CSRCFG_SIZE_Pos; - return tmp; -} - -static inline void hri_slcd_write_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp &= ~SLCD_CSRCFG_SIZE_Msk; - tmp |= SLCD_CSRCFG_SIZE(data); - ((Slcd *)hw)->CSRCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_SIZE(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_SIZE(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp = (tmp & SLCD_CSRCFG_SIZE_Msk) >> SLCD_CSRCFG_SIZE_Pos; - return tmp; -} - -static inline void hri_slcd_set_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_DATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp = (tmp & SLCD_CSRCFG_DATA(mask)) >> SLCD_CSRCFG_DATA_Pos; - return tmp; -} - -static inline void hri_slcd_write_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp &= ~SLCD_CSRCFG_DATA_Msk; - tmp |= SLCD_CSRCFG_DATA(data); - ((Slcd *)hw)->CSRCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_DATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_DATA(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp = (tmp & SLCD_CSRCFG_DATA_Msk) >> SLCD_CSRCFG_DATA_Pos; - return tmp; -} - -static inline void hri_slcd_set_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CSRCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CSRCFG.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_reg(const void *const hw) -{ - return ((Slcd *)hw)->CSRCFG.reg; -} - -static inline void hri_slcd_set_CMCFG_DEC_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMCFG.reg |= SLCD_CMCFG_DEC; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_CMCFG_DEC_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->CMCFG.reg; - tmp = (tmp & SLCD_CMCFG_DEC) >> SLCD_CMCFG_DEC_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_CMCFG_DEC_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CMCFG.reg; - tmp &= ~SLCD_CMCFG_DEC; - tmp |= value << SLCD_CMCFG_DEC_Pos; - ((Slcd *)hw)->CMCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CMCFG_DEC_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMCFG.reg &= ~SLCD_CMCFG_DEC; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CMCFG_DEC_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMCFG.reg ^= SLCD_CMCFG_DEC; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMCFG.reg |= SLCD_CMCFG_NSEG(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmcfg_reg_t hri_slcd_get_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->CMCFG.reg; - tmp = (tmp & SLCD_CMCFG_NSEG(mask)) >> SLCD_CMCFG_NSEG_Pos; - return tmp; -} - -static inline void hri_slcd_write_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t data) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CMCFG.reg; - tmp &= ~SLCD_CMCFG_NSEG_Msk; - tmp |= SLCD_CMCFG_NSEG(data); - ((Slcd *)hw)->CMCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMCFG.reg &= ~SLCD_CMCFG_NSEG(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMCFG.reg ^= SLCD_CMCFG_NSEG(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmcfg_reg_t hri_slcd_read_CMCFG_NSEG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->CMCFG.reg; - tmp = (tmp & SLCD_CMCFG_NSEG_Msk) >> SLCD_CMCFG_NSEG_Pos; - return tmp; -} - -static inline void hri_slcd_set_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMCFG.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmcfg_reg_t hri_slcd_get_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->CMCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMCFG.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMCFG.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMCFG.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmcfg_reg_t hri_slcd_read_CMCFG_reg(const void *const hw) -{ - return ((Slcd *)hw)->CMCFG.reg; -} - -static inline void hri_slcd_set_ACMCFG_MODE_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_MODE; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_slcd_get_ACMCFG_MODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_MODE) >> SLCD_ACMCFG_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_slcd_write_ACMCFG_MODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp &= ~SLCD_ACMCFG_MODE; - tmp |= value << SLCD_ACMCFG_MODE_Pos; - ((Slcd *)hw)->ACMCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_ACMCFG_MODE_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_MODE; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_ACMCFG_MODE_bit(const void *const hw) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_MODE; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_set_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NCOM(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_NCOM(mask)) >> SLCD_ACMCFG_NCOM_Pos; - return tmp; -} - -static inline void hri_slcd_write_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp &= ~SLCD_ACMCFG_NCOM_Msk; - tmp |= SLCD_ACMCFG_NCOM(data); - ((Slcd *)hw)->ACMCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NCOM(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NCOM(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NCOM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_NCOM_Msk) >> SLCD_ACMCFG_NCOM_Pos; - return tmp; -} - -static inline void hri_slcd_set_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NDIG(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_NDIG(mask)) >> SLCD_ACMCFG_NDIG_Pos; - return tmp; -} - -static inline void hri_slcd_write_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp &= ~SLCD_ACMCFG_NDIG_Msk; - tmp |= SLCD_ACMCFG_NDIG(data); - ((Slcd *)hw)->ACMCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NDIG(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NDIG(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NDIG_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_NDIG_Msk) >> SLCD_ACMCFG_NDIG_Pos; - return tmp; -} - -static inline void hri_slcd_set_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_STEPS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_STEPS(mask)) >> SLCD_ACMCFG_STEPS_Pos; - return tmp; -} - -static inline void hri_slcd_write_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp &= ~SLCD_ACMCFG_STEPS_Msk; - tmp |= SLCD_ACMCFG_STEPS(data); - ((Slcd *)hw)->ACMCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_STEPS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_STEPS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_STEPS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_STEPS_Msk) >> SLCD_ACMCFG_STEPS_Pos; - return tmp; -} - -static inline void hri_slcd_set_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NDROW(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_NDROW(mask)) >> SLCD_ACMCFG_NDROW_Pos; - return tmp; -} - -static inline void hri_slcd_write_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp &= ~SLCD_ACMCFG_NDROW_Msk; - tmp |= SLCD_ACMCFG_NDROW(data); - ((Slcd *)hw)->ACMCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NDROW(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NDROW(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NDROW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_NDROW_Msk) >> SLCD_ACMCFG_NDROW_Pos; - return tmp; -} - -static inline void hri_slcd_set_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_STSEG(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_STSEG(mask)) >> SLCD_ACMCFG_STSEG_Pos; - return tmp; -} - -static inline void hri_slcd_write_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp &= ~SLCD_ACMCFG_STSEG_Msk; - tmp |= SLCD_ACMCFG_STSEG(data); - ((Slcd *)hw)->ACMCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_STSEG(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_STSEG(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_STSEG_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_STSEG_Msk) >> SLCD_ACMCFG_STSEG_Pos; - return tmp; -} - -static inline void hri_slcd_set_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_FCS(mask)) >> SLCD_ACMCFG_FCS_Pos; - return tmp; -} - -static inline void hri_slcd_write_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp &= ~SLCD_ACMCFG_FCS_Msk; - tmp |= SLCD_ACMCFG_FCS(data); - ((Slcd *)hw)->ACMCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_FCS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp = (tmp & SLCD_ACMCFG_FCS_Msk) >> SLCD_ACMCFG_FCS_Pos; - return tmp; -} - -static inline void hri_slcd_set_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->ACMCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ACMCFG.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_reg(const void *const hw) -{ - return ((Slcd *)hw)->ACMCFG.reg; -} - -static inline void hri_slcd_set_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ABMCFG.reg |= SLCD_ABMCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->ABMCFG.reg; - tmp = (tmp & SLCD_ABMCFG_FCS(mask)) >> SLCD_ABMCFG_FCS_Pos; - return tmp; -} - -static inline void hri_slcd_write_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t data) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->ABMCFG.reg; - tmp &= ~SLCD_ABMCFG_FCS_Msk; - tmp |= SLCD_ABMCFG_FCS(data); - ((Slcd *)hw)->ABMCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ABMCFG.reg &= ~SLCD_ABMCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ABMCFG.reg ^= SLCD_ABMCFG_FCS(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_FCS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->ABMCFG.reg; - tmp = (tmp & SLCD_ABMCFG_FCS_Msk) >> SLCD_ABMCFG_FCS_Pos; - return tmp; -} - -static inline void hri_slcd_set_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ABMCFG.reg |= SLCD_ABMCFG_SIZE(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->ABMCFG.reg; - tmp = (tmp & SLCD_ABMCFG_SIZE(mask)) >> SLCD_ABMCFG_SIZE_Pos; - return tmp; -} - -static inline void hri_slcd_write_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t data) -{ - uint8_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->ABMCFG.reg; - tmp &= ~SLCD_ABMCFG_SIZE_Msk; - tmp |= SLCD_ABMCFG_SIZE(data); - ((Slcd *)hw)->ABMCFG.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ABMCFG.reg &= ~SLCD_ABMCFG_SIZE(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ABMCFG.reg ^= SLCD_ABMCFG_SIZE(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_SIZE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->ABMCFG.reg; - tmp = (tmp & SLCD_ABMCFG_SIZE_Msk) >> SLCD_ABMCFG_SIZE_Pos; - return tmp; -} - -static inline void hri_slcd_set_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ABMCFG.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Slcd *)hw)->ABMCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ABMCFG.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ABMCFG.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ABMCFG.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_reg(const void *const hw) -{ - return ((Slcd *)hw)->ABMCFG.reg; -} - -static inline void hri_slcd_set_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMDMASK.reg |= SLCD_CMDMASK_SDMASK(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmdmask_reg_t hri_slcd_get_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CMDMASK.reg; - tmp = (tmp & SLCD_CMDMASK_SDMASK(mask)) >> SLCD_CMDMASK_SDMASK_Pos; - return tmp; -} - -static inline void hri_slcd_write_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t data) -{ - uint32_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CMDMASK.reg; - tmp &= ~SLCD_CMDMASK_SDMASK_Msk; - tmp |= SLCD_CMDMASK_SDMASK(data); - ((Slcd *)hw)->CMDMASK.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMDMASK.reg &= ~SLCD_CMDMASK_SDMASK(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMDMASK.reg ^= SLCD_CMDMASK_SDMASK(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmdmask_reg_t hri_slcd_read_CMDMASK_SDMASK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CMDMASK.reg; - tmp = (tmp & SLCD_CMDMASK_SDMASK_Msk) >> SLCD_CMDMASK_SDMASK_Pos; - return tmp; -} - -static inline void hri_slcd_set_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMDMASK.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmdmask_reg_t hri_slcd_get_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Slcd *)hw)->CMDMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMDMASK.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMDMASK.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMDMASK.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmdmask_reg_t hri_slcd_read_CMDMASK_reg(const void *const hw) -{ - return ((Slcd *)hw)->CMDMASK.reg; -} - -static inline void hri_slcd_set_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMINDEX.reg |= SLCD_CMINDEX_SINDEX(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CMINDEX.reg; - tmp = (tmp & SLCD_CMINDEX_SINDEX(mask)) >> SLCD_CMINDEX_SINDEX_Pos; - return tmp; -} - -static inline void hri_slcd_write_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t data) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CMINDEX.reg; - tmp &= ~SLCD_CMINDEX_SINDEX_Msk; - tmp |= SLCD_CMINDEX_SINDEX(data); - ((Slcd *)hw)->CMINDEX.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMINDEX.reg &= ~SLCD_CMINDEX_SINDEX(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMINDEX.reg ^= SLCD_CMINDEX_SINDEX(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_SINDEX_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CMINDEX.reg; - tmp = (tmp & SLCD_CMINDEX_SINDEX_Msk) >> SLCD_CMINDEX_SINDEX_Pos; - return tmp; -} - -static inline void hri_slcd_set_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMINDEX.reg |= SLCD_CMINDEX_CINDEX(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CMINDEX.reg; - tmp = (tmp & SLCD_CMINDEX_CINDEX(mask)) >> SLCD_CMINDEX_CINDEX_Pos; - return tmp; -} - -static inline void hri_slcd_write_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t data) -{ - uint16_t tmp; - SLCD_CRITICAL_SECTION_ENTER(); - tmp = ((Slcd *)hw)->CMINDEX.reg; - tmp &= ~SLCD_CMINDEX_CINDEX_Msk; - tmp |= SLCD_CMINDEX_CINDEX(data); - ((Slcd *)hw)->CMINDEX.reg = tmp; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMINDEX.reg &= ~SLCD_CMINDEX_CINDEX(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMINDEX.reg ^= SLCD_CMINDEX_CINDEX(mask); - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_CINDEX_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CMINDEX.reg; - tmp = (tmp & SLCD_CMINDEX_CINDEX_Msk) >> SLCD_CMINDEX_CINDEX_Pos; - return tmp; -} - -static inline void hri_slcd_set_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMINDEX.reg |= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - uint16_t tmp; - tmp = ((Slcd *)hw)->CMINDEX.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_slcd_write_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMINDEX.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_clear_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMINDEX.reg &= ~mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_toggle_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMINDEX.reg ^= mask; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_reg(const void *const hw) -{ - return ((Slcd *)hw)->CMINDEX.reg; -} - -static inline void hri_slcd_write_ISDATA_reg(const void *const hw, hri_slcd_isdata_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->ISDATA.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_slcd_write_CMDATA_reg(const void *const hw, hri_slcd_cmdata_reg_t data) -{ - SLCD_CRITICAL_SECTION_ENTER(); - ((Slcd *)hw)->CMDATA.reg = data; - SLCD_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SLCD_L22_H_INCLUDED */ -#endif /* _SAML22_SLCD_COMPONENT_ */ diff --git a/watch-library/hri/hri_supc_l22.h b/watch-library/hri/hri_supc_l22.h deleted file mode 100644 index 9488ef0b..00000000 --- a/watch-library/hri/hri_supc_l22.h +++ /dev/null @@ -1,2532 +0,0 @@ -/** - * \file - * - * \brief SAM SUPC - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_SUPC_COMPONENT_ -#ifndef _HRI_SUPC_L22_H_INCLUDED_ -#define _HRI_SUPC_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) -#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SUPC_CRITICAL_SECTION_ENTER() -#define SUPC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_supc_bbps_reg_t; -typedef uint32_t hri_supc_bkin_reg_t; -typedef uint32_t hri_supc_bkout_reg_t; -typedef uint32_t hri_supc_bod12_reg_t; -typedef uint32_t hri_supc_bod33_reg_t; -typedef uint32_t hri_supc_intenset_reg_t; -typedef uint32_t hri_supc_intflag_reg_t; -typedef uint32_t hri_supc_status_reg_t; -typedef uint32_t hri_supc_vref_reg_t; -typedef uint32_t hri_supc_vreg_reg_t; - -static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; -} - -static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; -} - -static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; -} - -static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; -} - -static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; -} - -static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; -} - -static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; -} - -static inline bool hri_supc_get_INTFLAG_APWSRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_APWSRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY; -} - -static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; -} - -static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; -} - -static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; -} - -static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; -} - -static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; -} - -static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; -} - -static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; -} - -static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; -} - -static inline bool hri_supc_get_interrupt_APWSRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_APWSRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY; -} - -static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; -} - -static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; -} - -static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) -{ - return ((Supc *)hw)->INTFLAG.reg; -} - -static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) -{ - ((Supc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; -} - -static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; -} - -static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; - } -} - -static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; -} - -static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; -} - -static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; -} - -static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; - } -} - -static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; -} - -static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; -} - -static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; -} - -static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; - } -} - -static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; -} - -static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; -} - -static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos; -} - -static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; - } -} - -static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; -} - -static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; -} - -static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos; -} - -static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; - } -} - -static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; -} - -static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; -} - -static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos; -} - -static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; - } -} - -static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; -} - -static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; -} - -static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; -} - -static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; - } -} - -static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; -} - -static inline void hri_supc_set_INTEN_APWSRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY; -} - -static inline bool hri_supc_get_INTEN_APWSRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_APWSRDY) >> SUPC_INTENSET_APWSRDY_Pos; -} - -static inline void hri_supc_write_INTEN_APWSRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY; - } -} - -static inline void hri_supc_clear_INTEN_APWSRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY; -} - -static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; -} - -static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; -} - -static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; - } -} - -static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; -} - -static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - ((Supc *)hw)->INTENSET.reg = mask; -} - -static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) -{ - return ((Supc *)hw)->INTENSET.reg; -} - -static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) -{ - ((Supc *)hw)->INTENSET.reg = data; - ((Supc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - ((Supc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; -} - -static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; -} - -static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; -} - -static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos; -} - -static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos; -} - -static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos; -} - -static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; -} - -static inline bool hri_supc_get_STATUS_APWSRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_APWSRDY) >> SUPC_STATUS_APWSRDY_Pos; -} - -static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; -} - -static inline bool hri_supc_get_STATUS_BBPS_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BBPS) >> SUPC_STATUS_BBPS_Pos; -} - -static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) -{ - return ((Supc *)hw)->STATUS.reg; -} - -static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) -{ - return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; -} - -static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) -{ - return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; -} - -static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKIN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) -{ - return ((Supc *)hw)->BKIN.reg; -} - -static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_ENABLE; - tmp |= value << SUPC_BOD33_ENABLE_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_HYST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_HYST) >> SUPC_BOD33_HYST_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_HYST_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_HYST; - tmp |= value << SUPC_BOD33_HYST_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_STDBYCFG; - tmp |= value << SUPC_BOD33_STDBYCFG_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_RUNSTDBY; - tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_RUNBKUP; - tmp |= value << SUPC_BOD33_RUNBKUP_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_ACTCFG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ACTCFG) >> SUPC_BOD33_ACTCFG_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_ACTCFG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_ACTCFG; - tmp |= value << SUPC_BOD33_ACTCFG_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_VMON_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VMON; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_VMON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_VMON) >> SUPC_BOD33_VMON_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_VMON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_VMON; - tmp |= value << SUPC_BOD33_VMON_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_VMON_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VMON; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_VMON_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VMON; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_ACTION_Msk; - tmp |= SUPC_BOD33_ACTION(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_PSEL_Msk; - tmp |= SUPC_BOD33_PSEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_LEVEL_Msk; - tmp |= SUPC_BOD33_LEVEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_BKUPLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_BKUPLEVEL(mask)) >> SUPC_BOD33_BKUPLEVEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_BKUPLEVEL_Msk; - tmp |= SUPC_BOD33_BKUPLEVEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_BKUPLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_BKUPLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_BKUPLEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_BKUPLEVEL_Msk) >> SUPC_BOD33_BKUPLEVEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) -{ - return ((Supc *)hw)->BOD33.reg; -} - -static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_ENABLE; - tmp |= value << SUPC_BOD12_ENABLE_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_HYST; - tmp |= value << SUPC_BOD12_HYST_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_STDBYCFG; - tmp |= value << SUPC_BOD12_STDBYCFG_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_RUNSTDBY; - tmp |= value << SUPC_BOD12_RUNSTDBY_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_ACTCFG; - tmp |= value << SUPC_BOD12_ACTCFG_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_ACTION_Msk; - tmp |= SUPC_BOD12_ACTION(data); - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_PSEL_Msk; - tmp |= SUPC_BOD12_PSEL(data); - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_LEVEL_Msk; - tmp |= SUPC_BOD12_LEVEL(data); - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw) -{ - return ((Supc *)hw)->BOD12.reg; -} - -static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_ENABLE; - tmp |= value << SUPC_VREG_ENABLE_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_STDBYPL0_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_STDBYPL0; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_STDBYPL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_STDBYPL0) >> SUPC_VREG_STDBYPL0_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_STDBYPL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_STDBYPL0; - tmp |= value << SUPC_VREG_STDBYPL0_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_STDBYPL0_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_STDBYPL0; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_STDBYPL0_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_STDBYPL0; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_RUNSTDBY) >> SUPC_VREG_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_RUNSTDBY; - tmp |= value << SUPC_VREG_RUNSTDBY_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_LPEFF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_LPEFF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_LPEFF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_LPEFF) >> SUPC_VREG_LPEFF_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_LPEFF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_LPEFF; - tmp |= value << SUPC_VREG_LPEFF_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_LPEFF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_LPEFF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_LPEFF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_LPEFF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_get_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_SEL(mask)) >> SUPC_VREG_SEL_Pos; - return tmp; -} - -static inline void hri_supc_write_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_SEL_Msk; - tmp |= SUPC_VREG_SEL(data); - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_read_VREG_SEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_SEL_Msk) >> SUPC_VREG_SEL_Pos; - return tmp; -} - -static inline void hri_supc_set_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSVSTEP(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSVSTEP(mask)) >> SUPC_VREG_VSVSTEP_Pos; - return tmp; -} - -static inline void hri_supc_write_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_VSVSTEP_Msk; - tmp |= SUPC_VREG_VSVSTEP(data); - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSVSTEP(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSVSTEP(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSVSTEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSVSTEP_Msk) >> SUPC_VREG_VSVSTEP_Pos; - return tmp; -} - -static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; - return tmp; -} - -static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_VSPER_Msk; - tmp |= SUPC_VREG_VSPER(data); - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; - return tmp; -} - -static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) -{ - return ((Supc *)hw)->VREG.reg; -} - -static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_TSEN; - tmp |= value << SUPC_VREF_TSEN_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_VREFOE; - tmp |= value << SUPC_VREF_VREFOE_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_TSSEL; - tmp |= value << SUPC_VREF_TSSEL_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_RUNSTDBY; - tmp |= value << SUPC_VREF_RUNSTDBY_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_ONDEMAND; - tmp |= value << SUPC_VREF_ONDEMAND_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; - return tmp; -} - -static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_SEL_Msk; - tmp |= SUPC_VREF_SEL(data); - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; - return tmp; -} - -static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) -{ - return ((Supc *)hw)->VREF.reg; -} - -static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= ~SUPC_BBPS_WAKEEN; - tmp |= value << SUPC_BBPS_WAKEEN_Pos; - ((Supc *)hw)->BBPS.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BBPS_PSOKEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_PSOKEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BBPS_PSOKEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp = (tmp & SUPC_BBPS_PSOKEN) >> SUPC_BBPS_PSOKEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BBPS_PSOKEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= ~SUPC_BBPS_PSOKEN; - tmp |= value << SUPC_BBPS_PSOKEN_Pos; - ((Supc *)hw)->BBPS.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_PSOKEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_PSOKEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_PSOKEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_PSOKEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp = (tmp & SUPC_BBPS_CONF(mask)) >> SUPC_BBPS_CONF_Pos; - return tmp; -} - -static inline void hri_supc_write_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= ~SUPC_BBPS_CONF_Msk; - tmp |= SUPC_BBPS_CONF(data); - ((Supc *)hw)->BBPS.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_CONF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp = (tmp & SUPC_BBPS_CONF_Msk) >> SUPC_BBPS_CONF_Pos; - return tmp; -} - -static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) -{ - return ((Supc *)hw)->BBPS.reg; -} - -static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_EN_Msk; - tmp |= SUPC_BKOUT_EN(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_CLR_Msk; - tmp |= SUPC_BKOUT_CLR(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_SET_Msk; - tmp |= SUPC_BKOUT_SET(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_RTCTGL_Msk; - tmp |= SUPC_BKOUT_RTCTGL(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) -{ - return ((Supc *)hw)->BKOUT.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SUPC_L22_H_INCLUDED */ -#endif /* _SAML22_SUPC_COMPONENT_ */ diff --git a/watch-library/hri/hri_systemcontrol_l22.h b/watch-library/hri/hri_systemcontrol_l22.h deleted file mode 100644 index 9553d51a..00000000 --- a/watch-library/hri/hri_systemcontrol_l22.h +++ /dev/null @@ -1,498 +0,0 @@ -/** - * \file - * - * \brief SAM SystemControl - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_SystemControl_COMPONENT_ -#ifndef _HRI_SystemControl_L22_H_INCLUDED_ -#define _HRI_SystemControl_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS) -#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SystemControl_CRITICAL_SECTION_ENTER() -#define SystemControl_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_systemcontrol_aircr_reg_t; -typedef uint32_t hri_systemcontrol_ccr_reg_t; -typedef uint32_t hri_systemcontrol_cpuid_reg_t; -typedef uint32_t hri_systemcontrol_dfsr_reg_t; -typedef uint32_t hri_systemcontrol_icsr_reg_t; -typedef uint32_t hri_systemcontrol_scr_reg_t; -typedef uint32_t hri_systemcontrol_shcsr_reg_t; -typedef uint32_t hri_systemcontrol_shpr2_reg_t; -typedef uint32_t hri_systemcontrol_shpr3_reg_t; -typedef uint32_t hri_systemcontrol_vtor_reg_t; - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0; -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw) -{ - return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0; -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4; -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw) -{ - return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4; -} - -static inline hri_systemcontrol_cpuid_reg_t -hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16; -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw) -{ - return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16; -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20; -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw) -{ - return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20; -} - -static inline hri_systemcontrol_cpuid_reg_t -hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24; -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw) -{ - return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24; -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp &= mask; - return tmp; -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->CPUID.reg; -} - -static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw) -{ - return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_UNALIGN_TRP) >> 3; -} - -static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw) -{ - return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_STKALIGN) >> 9; -} - -static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw, - hri_systemcontrol_ccr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CCR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->CCR.reg; -} - -static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw, - hri_systemcontrol_icsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->ICSR.reg; -} - -static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->VTOR.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw, - hri_systemcontrol_vtor_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->VTOR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->VTOR.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->VTOR.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->VTOR.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->VTOR.reg; -} - -static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw, - hri_systemcontrol_aircr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->AIRCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->AIRCR.reg; -} - -static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw, - hri_systemcontrol_scr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->SCR.reg; -} - -static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR2.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw, - hri_systemcontrol_shpr2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SHPR2.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR2.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR2.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR2.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->SHPR2.reg; -} - -static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw, - hri_systemcontrol_shpr3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SHPR3.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->SHPR3.reg; -} - -static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHCSR.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const hw, - hri_systemcontrol_shcsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SHCSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHCSR.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHCSR.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHCSR.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->SHCSR.reg; -} - -static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->DFSR.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const hw, - hri_systemcontrol_dfsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->DFSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->DFSR.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->DFSR.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->DFSR.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->DFSR.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SystemControl_L22_H_INCLUDED */ -#endif /* _SAML22_SystemControl_COMPONENT_ */ diff --git a/watch-library/hri/hri_systick_l22.h b/watch-library/hri/hri_systick_l22.h deleted file mode 100644 index aa09233f..00000000 --- a/watch-library/hri/hri_systick_l22.h +++ /dev/null @@ -1,219 +0,0 @@ -/** - * \file - * - * \brief SAM SysTick - * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_SysTick_COMPONENT_ -#ifndef _HRI_SysTick_L22_H_INCLUDED_ -#define _HRI_SysTick_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SysTick_CRITICAL_SECTIONS) -#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SysTick_CRITICAL_SECTION_ENTER() -#define SysTick_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_systick_calib_reg_t; -typedef uint32_t hri_systick_csr_reg_t; -typedef uint32_t hri_systick_cvr_reg_t; -typedef uint32_t hri_systick_rvr_reg_t; - -static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw) -{ - return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_SKEW) >> 30; -} - -static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw) -{ - return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_NOREF) >> 31; -} - -static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) -{ - return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS(mask)) >> 0; -} - -static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw) -{ - return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS_Msk) >> 0; -} - -static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CALIB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw) -{ - return ((Systick *)hw)->CALIB.reg; -} - -static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg |= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg = data; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg &= ~mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg ^= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw) -{ - return ((Systick *)hw)->CSR.reg; -} - -static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->RVR.reg |= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->RVR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->RVR.reg = data; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->RVR.reg &= ~mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->RVR.reg ^= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw) -{ - return ((Systick *)hw)->RVR.reg; -} - -static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CVR.reg |= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CVR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CVR.reg = data; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CVR.reg &= ~mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CVR.reg ^= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw) -{ - return ((Systick *)hw)->CVR.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SysTick_L22_H_INCLUDED */ -#endif /* _SAML22_SysTick_COMPONENT_ */ diff --git a/watch-library/hri/hri_tc_l22.h b/watch-library/hri/hri_tc_l22.h deleted file mode 100644 index 8fab128c..00000000 --- a/watch-library/hri/hri_tc_l22.h +++ /dev/null @@ -1,2899 +0,0 @@ -/** - * \file - * - * \brief SAM TC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_TC_COMPONENT_ -#ifndef _HRI_TC_L22_H_INCLUDED_ -#define _HRI_TC_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TC_CRITICAL_SECTIONS) -#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TC_CRITICAL_SECTION_ENTER() -#define TC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_tc_evctrl_reg_t; -typedef uint16_t hri_tccount16_cc_reg_t; -typedef uint16_t hri_tccount16_ccbuf_reg_t; -typedef uint16_t hri_tccount16_count_reg_t; -typedef uint32_t hri_tc_ctrla_reg_t; -typedef uint32_t hri_tc_syncbusy_reg_t; -typedef uint32_t hri_tccount32_cc_reg_t; -typedef uint32_t hri_tccount32_ccbuf_reg_t; -typedef uint32_t hri_tccount32_count_reg_t; -typedef uint8_t hri_tc_ctrlbset_reg_t; -typedef uint8_t hri_tc_dbgctrl_reg_t; -typedef uint8_t hri_tc_drvctrl_reg_t; -typedef uint8_t hri_tc_intenset_reg_t; -typedef uint8_t hri_tc_intflag_reg_t; -typedef uint8_t hri_tc_status_reg_t; -typedef uint8_t hri_tc_wave_reg_t; -typedef uint8_t hri_tccount8_cc_reg_t; -typedef uint8_t hri_tccount8_ccbuf_reg_t; -typedef uint8_t hri_tccount8_count_reg_t; -typedef uint8_t hri_tccount8_per_reg_t; -typedef uint8_t hri_tccount8_perbuf_reg_t; - -static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) -{ - while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) -{ - return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; -} - -static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; -} - -static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; -} - -static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; -} - -static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; -} - -static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; -} - -static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; -} - -static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; -} - -static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; -} - -static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; -} - -static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; -} - -static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; -} - -static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; -} - -static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; -} - -static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; -} - -static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; -} - -static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; -} - -static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.INTFLAG.reg; -} - -static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; -} - -static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; -} - -static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; -} - -static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; - } else { - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; - } -} - -static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; -} - -static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; -} - -static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; - } else { - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; - } -} - -static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; -} - -static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; -} - -static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; -} - -static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; - } else { - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; - } -} - -static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; -} - -static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; - tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; - tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); -} - -static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); -} - -static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.CTRLBSET.reg; -} - -static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; -} - -static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; -} - -static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; -} - -static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; -} - -static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; - } -} - -static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; -} - -static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; -} - -static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; -} - -static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; - } -} - -static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; -} - -static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; -} - -static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; -} - -static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; - } -} - -static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; -} - -static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; -} - -static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; -} - -static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; - } -} - -static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; -} - -static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = mask; -} - -static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.INTENSET.reg; -} - -static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = data; - ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; -} - -static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; -} - -static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; -} - -static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; -} - -static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_ENABLE; - tmp |= value << TC_CTRLA_ENABLE_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_RUNSTDBY; - tmp |= value << TC_CTRLA_RUNSTDBY_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_ONDEMAND; - tmp |= value << TC_CTRLA_ONDEMAND_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_ALOCK; - tmp |= value << TC_CTRLA_ALOCK_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTEN0; - tmp |= value << TC_CTRLA_CAPTEN0_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTEN1; - tmp |= value << TC_CTRLA_CAPTEN1_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_COPEN0; - tmp |= value << TC_CTRLA_COPEN0_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_COPEN1; - tmp |= value << TC_CTRLA_COPEN1_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_MODE_Msk; - tmp |= TC_CTRLA_MODE(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_PRESCSYNC_Msk; - tmp |= TC_CTRLA_PRESCSYNC(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_PRESCALER_Msk; - tmp |= TC_CTRLA_PRESCALER(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - return ((Tc *)hw)->COUNT16.CTRLA.reg; -} - -static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_TCINV; - tmp |= value << TC_EVCTRL_TCINV_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_TCEI; - tmp |= value << TC_EVCTRL_TCEI_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_OVFEO; - tmp |= value << TC_EVCTRL_OVFEO_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_MCEO0; - tmp |= value << TC_EVCTRL_MCEO0_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_MCEO1; - tmp |= value << TC_EVCTRL_MCEO1_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_EVACT_Msk; - tmp |= TC_EVCTRL_EVACT(data); - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.EVCTRL.reg; -} - -static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp &= ~TC_WAVE_WAVEGEN_Msk; - tmp |= TC_WAVE_WAVEGEN(data); - ((Tc *)hw)->COUNT16.WAVE.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.WAVE.reg; -} - -static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp &= ~TC_DRVCTRL_INVEN0; - tmp |= value << TC_DRVCTRL_INVEN0_Pos; - ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp &= ~TC_DRVCTRL_INVEN1; - tmp |= value << TC_DRVCTRL_INVEN1_Pos; - ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.DRVCTRL.reg; -} - -static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; - tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; - tmp &= ~TC_DBGCTRL_DBGRUN; - tmp |= value << TC_DBGCTRL_DBGRUN_Pos; - ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.DBGCTRL.reg; -} - -static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, - hri_tccount8_count_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; - tmp |= TC_COUNT8_COUNT_COUNT(data); - ((Tc *)hw)->COUNT8.COUNT.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - return ((Tc *)hw)->COUNT8.COUNT.reg; -} - -static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, - hri_tccount16_count_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; - tmp |= TC_COUNT16_COUNT_COUNT(data); - ((Tc *)hw)->COUNT16.COUNT.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, - hri_tccount16_count_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - return ((Tc *)hw)->COUNT16.COUNT.reg; -} - -static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, - hri_tccount32_count_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; - tmp |= TC_COUNT32_COUNT_COUNT(data); - ((Tc *)hw)->COUNT32.COUNT.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, - hri_tccount32_count_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - return ((Tc *)hw)->COUNT32.COUNT.reg; -} - -static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; - return tmp; -} - -static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp &= ~TC_COUNT8_PER_PER_Msk; - tmp |= TC_COUNT8_PER_PER(data); - ((Tc *)hw)->COUNT8.PER.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; - return tmp; -} - -static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - return ((Tc *)hw)->COUNT8.PER.reg; -} - -static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, - hri_tccount8_cc_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp &= ~TC_COUNT8_CC_CC_Msk; - tmp |= TC_COUNT8_CC_CC(data); - ((Tc *)hw)->COUNT8.CC[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, - hri_tccount8_cc_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - return ((Tc *)hw)->COUNT8.CC[index].reg; -} - -static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, - hri_tccount16_cc_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp &= ~TC_COUNT16_CC_CC_Msk; - tmp |= TC_COUNT16_CC_CC(data); - ((Tc *)hw)->COUNT16.CC[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, - hri_tccount16_cc_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - return ((Tc *)hw)->COUNT16.CC[index].reg; -} - -static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, - hri_tccount32_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp &= ~TC_COUNT32_CC_CC_Msk; - tmp |= TC_COUNT32_CC_CC(data); - ((Tc *)hw)->COUNT32.CC[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, - hri_tccount32_cc_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - return ((Tc *)hw)->COUNT32.CC[index].reg; -} - -static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, - hri_tccount8_perbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; - tmp |= TC_COUNT8_PERBUF_PERBUF(data); - ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, - hri_tccount8_perbuf_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT8.PERBUF.reg; -} - -static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount8_ccbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT8_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tccount8_ccbuf_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT8.CCBUF[index].reg; -} - -static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT16_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT16.CCBUF[index].reg; -} - -static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT32_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT32.CCBUF[index].reg; -} - -static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; -} - -static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; -} - -static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; -} - -static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; -} - -static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; -} - -static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT16.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT16.STATUS.reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) -#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) -#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) -#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) -#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) -#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) -#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) -#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) -#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) -#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) -#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) -#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) -#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) -#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) -#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) -#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) -#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) -#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) -#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) -#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) -#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) -#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) -#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) -#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TC_L22_H_INCLUDED */ -#endif /* _SAML22_TC_COMPONENT_ */ diff --git a/watch-library/hri/hri_tcc_l22.h b/watch-library/hri/hri_tcc_l22.h deleted file mode 100644 index c10442af..00000000 --- a/watch-library/hri/hri_tcc_l22.h +++ /dev/null @@ -1,9462 +0,0 @@ -/** - * \file - * - * \brief SAM TCC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_TCC_COMPONENT_ -#ifndef _HRI_TCC_L22_H_INCLUDED_ -#define _HRI_TCC_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TCC_CRITICAL_SECTIONS) -#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TCC_CRITICAL_SECTION_ENTER() -#define TCC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_tcc_patt_reg_t; -typedef uint16_t hri_tcc_pattbuf_reg_t; -typedef uint32_t hri_tcc_cc_reg_t; -typedef uint32_t hri_tcc_ccbuf_reg_t; -typedef uint32_t hri_tcc_count_reg_t; -typedef uint32_t hri_tcc_ctrla_reg_t; -typedef uint32_t hri_tcc_drvctrl_reg_t; -typedef uint32_t hri_tcc_evctrl_reg_t; -typedef uint32_t hri_tcc_fctrla_reg_t; -typedef uint32_t hri_tcc_fctrlb_reg_t; -typedef uint32_t hri_tcc_intenset_reg_t; -typedef uint32_t hri_tcc_intflag_reg_t; -typedef uint32_t hri_tcc_per_reg_t; -typedef uint32_t hri_tcc_perbuf_reg_t; -typedef uint32_t hri_tcc_status_reg_t; -typedef uint32_t hri_tcc_syncbusy_reg_t; -typedef uint32_t hri_tcc_wave_reg_t; -typedef uint32_t hri_tcc_wexctrl_reg_t; -typedef uint8_t hri_tcc_ctrlbset_reg_t; -typedef uint8_t hri_tcc_dbgctrl_reg_t; - -static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) -{ - while (((Tcc *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) -{ - return ((Tcc *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; -} - -static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; -} - -static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; -} - -static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; -} - -static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; -} - -static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; -} - -static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; -} - -static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; -} - -static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; -} - -static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; -} - -static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; -} - -static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; -} - -static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; -} - -static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; -} - -static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; -} - -static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; -} - -static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; -} - -static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; -} - -static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; -} - -static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; -} - -static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; -} - -static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; -} - -static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; -} - -static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; -} - -static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; -} - -static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; -} - -static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; -} - -static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; -} - -static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; -} - -static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; -} - -static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; -} - -static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; -} - -static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; -} - -static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; -} - -static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) -{ - return ((Tcc *)hw)->INTFLAG.reg; -} - -static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) -{ - ((Tcc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; -} - -static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; -} - -static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; - } -} - -static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; -} - -static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; -} - -static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; - } -} - -static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; -} - -static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; -} - -static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; -} - -static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; - } -} - -static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; -} - -static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); - ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); -} - -static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); -} - -static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); - ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); -} - -static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); -} - -static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = mask; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) -{ - return ((Tcc *)hw)->CTRLBSET.reg; -} - -static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = data; - ((Tcc *)hw)->CTRLBCLR.reg = ~data; -} - -static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = mask; -} - -static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; -} - -static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; -} - -static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; - } -} - -static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; -} - -static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; -} - -static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; -} - -static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; - } -} - -static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; -} - -static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; -} - -static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; -} - -static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; - } -} - -static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; -} - -static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; -} - -static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; -} - -static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; - } -} - -static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; -} - -static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; -} - -static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; -} - -static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; - } -} - -static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; -} - -static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; -} - -static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; -} - -static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; - } -} - -static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; -} - -static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; -} - -static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; - } -} - -static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; -} - -static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; -} - -static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; - } -} - -static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; -} - -static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; -} - -static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; - } -} - -static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; -} - -static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; -} - -static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; - } -} - -static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; -} - -static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; -} - -static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; -} - -static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; - } -} - -static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; -} - -static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; -} - -static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; -} - -static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; - } -} - -static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; -} - -static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; -} - -static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; -} - -static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; - } -} - -static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; -} - -static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; -} - -static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; -} - -static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; - } -} - -static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; -} - -static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - ((Tcc *)hw)->INTENSET.reg = mask; -} - -static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) -{ - return ((Tcc *)hw)->INTENSET.reg; -} - -static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) -{ - ((Tcc *)hw)->INTENSET.reg = data; - ((Tcc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - ((Tcc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; -} - -static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Tcc *)hw)->SYNCBUSY.reg; -} - -static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_ENABLE; - tmp |= value << TCC_CTRLA_ENABLE_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_RUNSTDBY; - tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_ALOCK; - tmp |= value << TCC_CTRLA_ALOCK_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_MSYNC; - tmp |= value << TCC_CTRLA_MSYNC_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_DMAOS; - tmp |= value << TCC_CTRLA_DMAOS_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN0; - tmp |= value << TCC_CTRLA_CPTEN0_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN1; - tmp |= value << TCC_CTRLA_CPTEN1_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN2; - tmp |= value << TCC_CTRLA_CPTEN2_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN3; - tmp |= value << TCC_CTRLA_CPTEN3_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_RESOLUTION_Msk; - tmp |= TCC_CTRLA_RESOLUTION(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_PRESCALER_Msk; - tmp |= TCC_CTRLA_PRESCALER(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; - tmp |= TCC_CTRLA_PRESCSYNC(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - return ((Tcc *)hw)->CTRLA.reg; -} - -static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_KEEP; - tmp |= value << TCC_FCTRLA_KEEP_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_QUAL; - tmp |= value << TCC_FCTRLA_QUAL_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_RESTART; - tmp |= value << TCC_FCTRLA_RESTART_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANKPRESC; - tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_SRC_Msk; - tmp |= TCC_FCTRLA_SRC(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANK_Msk; - tmp |= TCC_FCTRLA_BLANK(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_HALT_Msk; - tmp |= TCC_FCTRLA_HALT(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_CHSEL_Msk; - tmp |= TCC_FCTRLA_CHSEL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_CAPTURE_Msk; - tmp |= TCC_FCTRLA_CAPTURE(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; - tmp |= TCC_FCTRLA_BLANKVAL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; - tmp |= TCC_FCTRLA_FILTERVAL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) -{ - return ((Tcc *)hw)->FCTRLA.reg; -} - -static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_KEEP; - tmp |= value << TCC_FCTRLB_KEEP_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_QUAL; - tmp |= value << TCC_FCTRLB_QUAL_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_RESTART; - tmp |= value << TCC_FCTRLB_RESTART_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANKPRESC; - tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_SRC_Msk; - tmp |= TCC_FCTRLB_SRC(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANK_Msk; - tmp |= TCC_FCTRLB_BLANK(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_HALT_Msk; - tmp |= TCC_FCTRLB_HALT(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_CHSEL_Msk; - tmp |= TCC_FCTRLB_CHSEL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_CAPTURE_Msk; - tmp |= TCC_FCTRLB_CAPTURE(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; - tmp |= TCC_FCTRLB_BLANKVAL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; - tmp |= TCC_FCTRLB_FILTERVAL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) -{ - return ((Tcc *)hw)->FCTRLB.reg; -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN0; - tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN1; - tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN2; - tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN3; - tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_OTMX_Msk; - tmp |= TCC_WEXCTRL_OTMX(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTLS_Msk; - tmp |= TCC_WEXCTRL_DTLS(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTHS_Msk; - tmp |= TCC_WEXCTRL_DTHS(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->WEXCTRL.reg; -} - -static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE0; - tmp |= value << TCC_DRVCTRL_NRE0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE1; - tmp |= value << TCC_DRVCTRL_NRE1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE2; - tmp |= value << TCC_DRVCTRL_NRE2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE3; - tmp |= value << TCC_DRVCTRL_NRE3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE4; - tmp |= value << TCC_DRVCTRL_NRE4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE5; - tmp |= value << TCC_DRVCTRL_NRE5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE6; - tmp |= value << TCC_DRVCTRL_NRE6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE7; - tmp |= value << TCC_DRVCTRL_NRE7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV0; - tmp |= value << TCC_DRVCTRL_NRV0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV1; - tmp |= value << TCC_DRVCTRL_NRV1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV2; - tmp |= value << TCC_DRVCTRL_NRV2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV3; - tmp |= value << TCC_DRVCTRL_NRV3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV4; - tmp |= value << TCC_DRVCTRL_NRV4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV5; - tmp |= value << TCC_DRVCTRL_NRV5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV6; - tmp |= value << TCC_DRVCTRL_NRV6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV7; - tmp |= value << TCC_DRVCTRL_NRV7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN0; - tmp |= value << TCC_DRVCTRL_INVEN0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN1; - tmp |= value << TCC_DRVCTRL_INVEN1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN2; - tmp |= value << TCC_DRVCTRL_INVEN2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN3; - tmp |= value << TCC_DRVCTRL_INVEN3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN4; - tmp |= value << TCC_DRVCTRL_INVEN4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN5; - tmp |= value << TCC_DRVCTRL_INVEN5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN6; - tmp |= value << TCC_DRVCTRL_INVEN6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN7; - tmp |= value << TCC_DRVCTRL_INVEN7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; - tmp |= TCC_DRVCTRL_FILTERVAL0(data); - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; - return tmp; -} - -static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; - tmp |= TCC_DRVCTRL_FILTERVAL1(data); - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; - return tmp; -} - -static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->DRVCTRL.reg; -} - -static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= ~TCC_DBGCTRL_DBGRUN; - tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; - ((Tcc *)hw)->DBGCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= ~TCC_DBGCTRL_FDDBD; - tmp |= value << TCC_DBGCTRL_FDDBD_Pos; - ((Tcc *)hw)->DBGCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->DBGCTRL.reg; -} - -static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_OVFEO; - tmp |= value << TCC_EVCTRL_OVFEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TRGEO; - tmp |= value << TCC_EVCTRL_TRGEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_CNTEO; - tmp |= value << TCC_EVCTRL_CNTEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCINV0; - tmp |= value << TCC_EVCTRL_TCINV0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCINV1; - tmp |= value << TCC_EVCTRL_TCINV1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCEI0; - tmp |= value << TCC_EVCTRL_TCEI0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCEI1; - tmp |= value << TCC_EVCTRL_TCEI1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI0; - tmp |= value << TCC_EVCTRL_MCEI0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI1; - tmp |= value << TCC_EVCTRL_MCEI1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI2; - tmp |= value << TCC_EVCTRL_MCEI2_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI3; - tmp |= value << TCC_EVCTRL_MCEI3_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO0; - tmp |= value << TCC_EVCTRL_MCEO0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO1; - tmp |= value << TCC_EVCTRL_MCEO1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO2; - tmp |= value << TCC_EVCTRL_MCEO2_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO3; - tmp |= value << TCC_EVCTRL_MCEO3_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_EVACT0_Msk; - tmp |= TCC_EVCTRL_EVACT0(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_EVACT1_Msk; - tmp |= TCC_EVCTRL_EVACT1(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_CNTSEL_Msk; - tmp |= TCC_EVCTRL_CNTSEL(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->EVCTRL.reg; -} - -static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - return ((Tcc *)hw)->COUNT.reg; -} - -static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE0; - tmp |= value << TCC_PATT_PGE0_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE1; - tmp |= value << TCC_PATT_PGE1_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE2; - tmp |= value << TCC_PATT_PGE2_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE3; - tmp |= value << TCC_PATT_PGE3_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE4; - tmp |= value << TCC_PATT_PGE4_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE5; - tmp |= value << TCC_PATT_PGE5_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE6; - tmp |= value << TCC_PATT_PGE6_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE7; - tmp |= value << TCC_PATT_PGE7_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV0; - tmp |= value << TCC_PATT_PGV0_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV1; - tmp |= value << TCC_PATT_PGV1_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV2; - tmp |= value << TCC_PATT_PGV2_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV3; - tmp |= value << TCC_PATT_PGV3_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV4; - tmp |= value << TCC_PATT_PGV4_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV5; - tmp |= value << TCC_PATT_PGV5_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV6; - tmp |= value << TCC_PATT_PGV6_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV7; - tmp |= value << TCC_PATT_PGV7_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - uint16_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - return ((Tcc *)hw)->PATT.reg; -} - -static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CIPEREN; - tmp |= value << TCC_WAVE_CIPEREN_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN0; - tmp |= value << TCC_WAVE_CICCEN0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN1; - tmp |= value << TCC_WAVE_CICCEN1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN2; - tmp |= value << TCC_WAVE_CICCEN2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN3; - tmp |= value << TCC_WAVE_CICCEN3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL0; - tmp |= value << TCC_WAVE_POL0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL1; - tmp |= value << TCC_WAVE_POL1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL2; - tmp |= value << TCC_WAVE_POL2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL3; - tmp |= value << TCC_WAVE_POL3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP0; - tmp |= value << TCC_WAVE_SWAP0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP1; - tmp |= value << TCC_WAVE_SWAP1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP2; - tmp |= value << TCC_WAVE_SWAP2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP3; - tmp |= value << TCC_WAVE_SWAP3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_WAVEGEN_Msk; - tmp |= TCC_WAVE_WAVEGEN(data); - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_RAMP_Msk; - tmp |= TCC_WAVE_RAMP(data); - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - return ((Tcc *)hw)->WAVE.reg; -} - -static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH4_DITHER_Msk; - tmp |= TCC_PER_DITH4_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH5_DITHER_Msk; - tmp |= TCC_PER_DITH5_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH6_DITHER_Msk; - tmp |= TCC_PER_DITH6_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - return ((Tcc *)hw)->PER.reg; -} - -static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH4_DITHER_Msk; - tmp |= TCC_CC_DITH4_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH5_DITHER_Msk; - tmp |= TCC_CC_DITH5_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH6_DITHER_Msk; - tmp |= TCC_CC_DITH6_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); - return ((Tcc *)hw)->CC[index].reg; -} - -static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB0; - tmp |= value << TCC_PATTBUF_PGEB0_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB1; - tmp |= value << TCC_PATTBUF_PGEB1_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB2; - tmp |= value << TCC_PATTBUF_PGEB2_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB3; - tmp |= value << TCC_PATTBUF_PGEB3_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB4; - tmp |= value << TCC_PATTBUF_PGEB4_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB5; - tmp |= value << TCC_PATTBUF_PGEB5_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB6; - tmp |= value << TCC_PATTBUF_PGEB6_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB7; - tmp |= value << TCC_PATTBUF_PGEB7_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB0; - tmp |= value << TCC_PATTBUF_PGVB0_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB1; - tmp |= value << TCC_PATTBUF_PGVB1_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB2; - tmp |= value << TCC_PATTBUF_PGVB2_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB3; - tmp |= value << TCC_PATTBUF_PGVB3_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB4; - tmp |= value << TCC_PATTBUF_PGVB4_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB5; - tmp |= value << TCC_PATTBUF_PGVB5_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB6; - tmp |= value << TCC_PATTBUF_PGVB6_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB7; - tmp |= value << TCC_PATTBUF_PGVB7_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) -{ - return ((Tcc *)hw)->PATTBUF.reg; -} - -static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) -{ - return ((Tcc *)hw)->PERBUF.reg; -} - -static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CCBUF[index].reg; -} - -static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; -} - -static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; -} - -static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; -} - -static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; -} - -static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; -} - -static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; -} - -static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; -} - -static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - return ((Tcc *)hw)->STATUS.reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) -#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) -#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) -#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) -#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) -#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) -#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) -#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) -#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) -#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) -#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) -#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) -#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) -#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) -#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) -#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) -#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) -#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) -#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) -#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) -#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) -#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) -#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) -#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) -#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) -#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) -#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) -#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) -#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) -#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) -#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) -#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) -#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) -#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) -#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) -#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) -#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) -#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) -#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) -#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) -#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) -#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) -#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) -#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) -#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) -#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) -#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) -#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) -#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) -#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) -#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) -#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) -#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) -#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) -#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) -#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) -#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) -#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) -#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) -#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) -#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) -#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) -#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) -#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) -#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) -#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) -#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) -#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) -#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) -#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) -#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) -#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) -#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) -#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) -#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) -#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) -#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) -#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) -#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) -#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) -#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) -#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) -#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) -#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) -#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) -#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) -#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) -#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) -#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) -#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TCC_L22_H_INCLUDED */ -#endif /* _SAML22_TCC_COMPONENT_ */ diff --git a/watch-library/hri/hri_trng_l22.h b/watch-library/hri/hri_trng_l22.h deleted file mode 100644 index 8aad3aca..00000000 --- a/watch-library/hri/hri_trng_l22.h +++ /dev/null @@ -1,380 +0,0 @@ -/** - * \file - * - * \brief SAM TRNG - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_TRNG_COMPONENT_ -#ifndef _HRI_TRNG_L22_H_INCLUDED_ -#define _HRI_TRNG_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) -#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TRNG_CRITICAL_SECTION_ENTER() -#define TRNG_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_trng_data_reg_t; -typedef uint8_t hri_trng_ctrla_reg_t; -typedef uint8_t hri_trng_evctrl_reg_t; -typedef uint8_t hri_trng_intenset_reg_t; -typedef uint8_t hri_trng_intflag_reg_t; - -static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; -} - -static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; -} - -static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; -} - -static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; -} - -static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) -{ - return ((Trng *)hw)->INTFLAG.reg; -} - -static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) -{ - ((Trng *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; -} - -static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; -} - -static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; - } else { - ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; - } -} - -static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; -} - -static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - ((Trng *)hw)->INTENSET.reg = mask; -} - -static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) -{ - return ((Trng *)hw)->INTENSET.reg; -} - -static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) -{ - ((Trng *)hw)->INTENSET.reg = data; - ((Trng *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - ((Trng *)hw)->INTENCLR.reg = mask; -} - -static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) -{ - return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; -} - -static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) -{ - return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; -} - -static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Trng *)hw)->DATA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) -{ - return ((Trng *)hw)->DATA.reg; -} - -static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= ~TRNG_CTRLA_ENABLE; - tmp |= value << TRNG_CTRLA_ENABLE_Pos; - ((Trng *)hw)->CTRLA.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= ~TRNG_CTRLA_RUNSTDBY; - tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; - ((Trng *)hw)->CTRLA.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg = data; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) -{ - return ((Trng *)hw)->CTRLA.reg; -} - -static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp &= ~TRNG_EVCTRL_DATARDYEO; - tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; - ((Trng *)hw)->EVCTRL.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg |= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg = data; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg &= ~mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg ^= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) -{ - return ((Trng *)hw)->EVCTRL.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TRNG_L22_H_INCLUDED */ -#endif /* _SAML22_TRNG_COMPONENT_ */ diff --git a/watch-library/hri/hri_usb_l22.h b/watch-library/hri/hri_usb_l22.h deleted file mode 100644 index 57a9419d..00000000 --- a/watch-library/hri/hri_usb_l22.h +++ /dev/null @@ -1,4713 +0,0 @@ -/** - * \file - * - * \brief SAM USB - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_USB_COMPONENT_ -#ifndef _HRI_USB_L22_H_INCLUDED_ -#define _HRI_USB_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_USB_CRITICAL_SECTIONS) -#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define USB_CRITICAL_SECTION_ENTER() -#define USB_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_usb_padcal_reg_t; -typedef uint16_t hri_usbdesc_bank_extreg_reg_t; -typedef uint16_t hri_usbdescriptordevice_extreg_reg_t; -typedef uint16_t hri_usbdevice_ctrlb_reg_t; -typedef uint16_t hri_usbdevice_epintsmry_reg_t; -typedef uint16_t hri_usbdevice_fnum_reg_t; -typedef uint16_t hri_usbdevice_intenset_reg_t; -typedef uint16_t hri_usbdevice_intflag_reg_t; -typedef uint32_t hri_usb_descadd_reg_t; -typedef uint32_t hri_usbdesc_bank_addr_reg_t; -typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; -typedef uint32_t hri_usbdescriptordevice_addr_reg_t; -typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t; -typedef uint8_t hri_usb_ctrla_reg_t; -typedef uint8_t hri_usb_fsmstatus_reg_t; -typedef uint8_t hri_usb_qosctrl_reg_t; -typedef uint8_t hri_usb_syncbusy_reg_t; -typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; -typedef uint8_t hri_usbdescriptordevice_status_bk_reg_t; -typedef uint8_t hri_usbdevice_dadd_reg_t; -typedef uint8_t hri_usbdevice_epcfg_reg_t; -typedef uint8_t hri_usbdevice_epintenset_reg_t; -typedef uint8_t hri_usbdevice_epintflag_reg_t; -typedef uint8_t hri_usbdevice_epstatus_reg_t; -typedef uint8_t hri_usbdevice_status_reg_t; -typedef uint8_t hri_usbendpoint_epcfg_reg_t; -typedef uint8_t hri_usbendpoint_epintenset_reg_t; -typedef uint8_t hri_usbendpoint_epintflag_reg_t; -typedef uint8_t hri_usbendpoint_epstatus_reg_t; - -static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg) -{ - while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg) -{ - return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline hri_usbendpoint_epintflag_reg_t -hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintflag_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; -} - -static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) - >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) - >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) - >> USB_DEVICE_EPSTATUS_CURBK_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) - >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) - >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) - >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) - >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; -} - -static inline hri_usbendpoint_epstatus_reg_t -hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; -} - -static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t data) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; -} - -static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) - >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) - >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) - >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) - >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) - >> USB_DEVICE_EPINTENSET_RXSTP_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) - >> USB_DEVICE_EPINTENSET_STALL0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) - >> USB_DEVICE_EPINTENSET_STALL1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; -} - -static inline hri_usbendpoint_epintenset_reg_t -hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; -} - -static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t data) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; -} - -static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; -} - -static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; - return (bool)tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_NYETDIS; - tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t -hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t -hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline hri_usbdevice_epintflag_reg_t -hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintflag_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; -} - -static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) - >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) - >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) - >> USB_DEVICE_EPSTATUS_CURBK_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) - >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) - >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) - >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) - >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; -} - -static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; -} - -static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t data) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; -} - -static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) - >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) - >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) - >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) - >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) - >> USB_DEVICE_EPINTENSET_RXSTP_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) - >> USB_DEVICE_EPINTENSET_STALL0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) - >> USB_DEVICE_EPINTENSET_STALL1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; -} - -static inline hri_usbdevice_epintenset_reg_t -hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; -} - -static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t data) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; -} - -static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_NYETDIS; - tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t -hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t -hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; -} - -static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; -} - -static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; -} - -static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; -} - -static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; -} - -static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; -} - -static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; -} - -static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; -} - -static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; -} - -static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; -} - -static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; -} - -static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; -} - -static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; -} - -static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; -} - -static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; -} - -static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; -} - -static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; -} - -static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; -} - -static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; -} - -static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; -} - -static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; -} - -static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, - hri_usbdevice_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.INTFLAG.reg; -} - -static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; -} - -static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; -} - -static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; -} - -static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; - } -} - -static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; -} - -static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; -} - -static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; -} - -static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; - } -} - -static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; -} - -static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; -} - -static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; -} - -static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; - } -} - -static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; -} - -static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; -} - -static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; -} - -static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; - } -} - -static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; -} - -static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; -} - -static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; -} - -static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; - } -} - -static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; -} - -static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; -} - -static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; -} - -static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; - } -} - -static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; -} - -static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; -} - -static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; -} - -static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; - } -} - -static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; -} - -static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; -} - -static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; -} - -static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; - } -} - -static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; -} - -static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; -} - -static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; -} - -static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; - } -} - -static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; -} - -static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; -} - -static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; - } -} - -static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; -} - -static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = mask; -} - -static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, - hri_usbdevice_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.INTENSET.reg; -} - -static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = data; - ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; -} - -static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.SYNCBUSY.reg; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.STATUS.reg; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, - hri_usb_fsmstatus_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.FSMSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.FSMSTATUS.reg; -} - -static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, - hri_usbdevice_fnum_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, - hri_usbdevice_fnum_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.FNUM.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.FNUM.reg; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; -} - -static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, - hri_usbdevice_epintsmry_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; -} - -static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_SWRST; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= ~USB_CTRLA_ENABLE; - tmp |= value << USB_CTRLA_ENABLE_Pos; - ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_ENABLE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_RUNSTDBY; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= ~USB_CTRLA_RUNSTDBY; - tmp |= value << USB_CTRLA_RUNSTDBY_Pos; - ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_MODE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= ~USB_CTRLA_MODE; - tmp |= value << USB_CTRLA_MODE_Pos; - ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_MODE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_MODE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg |= mask; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg = data; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~mask; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= mask; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw) -{ - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - return ((Usb *)hw)->DEVICE.CTRLA.reg; -} - -static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_CQOS_Msk; - tmp |= USB_QOSCTRL_CQOS(data); - ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_DQOS_Msk; - tmp |= USB_QOSCTRL_DQOS(data); - ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.QOSCTRL.reg; -} - -static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_DETACH; - tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_UPRSM; - tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_NREPLY; - tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTJ; - tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTK; - tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; - tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_OPMODE2; - tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_GNAK; - tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; - tmp |= USB_DEVICE_CTRLB_SPDCONF(data); - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; - tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.CTRLB.reg; -} - -static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= ~USB_DEVICE_DADD_ADDEN; - tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; - ((Usb *)hw)->DEVICE.DADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, - hri_usbdevice_dadd_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= ~USB_DEVICE_DADD_DADD_Msk; - tmp |= USB_DEVICE_DADD_DADD(data); - ((Usb *)hw)->DEVICE.DADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.DADD.reg; -} - -static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg |= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp &= ~USB_DESCADD_DESCADD_Msk; - tmp |= USB_DESCADD_DESCADD(data); - ((Usb *)hw)->DEVICE.DESCADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.DESCADD.reg; -} - -static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSP_Msk; - tmp |= USB_PADCAL_TRANSP(data); - ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSN_Msk; - tmp |= USB_PADCAL_TRANSN(data); - ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= ~USB_PADCAL_TRIM_Msk; - tmp |= USB_PADCAL_TRIM(data); - ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.PADCAL.reg; -} - -static inline void hri_usbdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_get_ADDR_ADDR_bf(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; - tmp |= USB_DEVICE_ADDR_ADDR(data); - ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_get_ADDR_reg(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_read_ADDR_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->ADDR.reg; -} - -static inline void hri_usbdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_SIZE(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_get_PCKSIZE_reg(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; -} - -static inline void hri_usbdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; - tmp |= USB_DEVICE_EXTREG_SUBPID(data); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_SUBPID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; - tmp |= USB_DEVICE_EXTREG_VARIABLE(data); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_reg(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->EXTREG.reg; -} - -static inline bool hri_usbdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) -{ - return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) - >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdescbank_get_STATUS_BK_reg(const void *const hw, - hri_usbdesc_bank_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdescbank_read_STATUS_BK_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; -} - -static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t -hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; - tmp |= USB_DEVICE_ADDR_ADDR(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t -hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void -hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void -hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void -hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_SIZE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; - tmp |= USB_DEVICE_EXTREG_SUBPID(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; - tmp |= USB_DEVICE_EXTREG_VARIABLE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; -} - -static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) - >> USB_DEVICE_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) - >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_status_bk_reg_t -hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_status_bk_reg_t -hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) -#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b) -#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) -#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) -#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) -#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) -#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) -#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) -#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) -#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) -#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) -#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) -#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) -#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) -#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) -#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) -#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) -#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) -#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) -#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) -#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) -#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) -#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) -#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) -#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) -#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) -#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) -#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) -#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) -#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) -#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) -#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) -#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) -#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) -#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) -#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) -#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) -#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) -#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) -#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) -#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) -#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) -#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) -#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) -#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) -#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) -#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) -#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) -#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_USB_L22_H_INCLUDED */ -#endif /* _SAML22_USB_COMPONENT_ */ diff --git a/watch-library/hri/hri_wdt_l22.h b/watch-library/hri/hri_wdt_l22.h deleted file mode 100644 index 4794b254..00000000 --- a/watch-library/hri/hri_wdt_l22.h +++ /dev/null @@ -1,617 +0,0 @@ -/** - * \file - * - * \brief SAM WDT - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAML22_WDT_COMPONENT_ -#ifndef _HRI_WDT_L22_H_INCLUDED_ -#define _HRI_WDT_L22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_WDT_CRITICAL_SECTIONS) -#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define WDT_CRITICAL_SECTION_ENTER() -#define WDT_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_wdt_syncbusy_reg_t; -typedef uint8_t hri_wdt_clear_reg_t; -typedef uint8_t hri_wdt_config_reg_t; -typedef uint8_t hri_wdt_ctrla_reg_t; -typedef uint8_t hri_wdt_ewctrl_reg_t; -typedef uint8_t hri_wdt_intenset_reg_t; -typedef uint8_t hri_wdt_intflag_reg_t; - -static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) -{ - while (((Wdt *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) -{ - return ((Wdt *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; -} - -static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; -} - -static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; -} - -static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; -} - -static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) -{ - return ((Wdt *)hw)->INTFLAG.reg; -} - -static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) -{ - ((Wdt *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; -} - -static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; -} - -static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; - } else { - ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; - } -} - -static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; -} - -static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - ((Wdt *)hw)->INTENSET.reg = mask; -} - -static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) -{ - return ((Wdt *)hw)->INTENSET.reg; -} - -static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) -{ - ((Wdt *)hw)->INTENSET.reg = data; - ((Wdt *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - ((Wdt *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; -} - -static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Wdt *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Wdt *)hw)->SYNCBUSY.reg; -} - -static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_ENABLE; - tmp |= value << WDT_CTRLA_ENABLE_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_WEN; - tmp |= value << WDT_CTRLA_WEN_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_ALWAYSON; - tmp |= value << WDT_CTRLA_ALWAYSON_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= mask; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg = data; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~mask; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= mask; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) -{ - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - return ((Wdt *)hw)->CTRLA.reg; -} - -static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= ~WDT_CONFIG_PER_Msk; - tmp |= WDT_CONFIG_PER(data); - ((Wdt *)hw)->CONFIG.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; - return tmp; -} - -static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= ~WDT_CONFIG_WINDOW_Msk; - tmp |= WDT_CONFIG_WINDOW(data); - ((Wdt *)hw)->CONFIG.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; - return tmp; -} - -static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) -{ - return ((Wdt *)hw)->CONFIG.reg; -} - -static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; - return tmp; -} - -static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; - tmp |= WDT_EWCTRL_EWOFFSET(data); - ((Wdt *)hw)->EWCTRL.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; - return tmp; -} - -static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) -{ - return ((Wdt *)hw)->EWCTRL.reg; -} - -static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CLEAR.reg = data; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); - WDT_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_WDT_L22_H_INCLUDED */ -#endif /* _SAML22_WDT_COMPONENT_ */ diff --git a/watch-library/hw/driver_init.c b/watch-library/hw/driver_init.c deleted file mode 100644 index 09723bec..00000000 --- a/watch-library/hw/driver_init.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ - -#include "driver_init.h" -#include -#include -#include - -struct slcd_sync_descriptor SEGMENT_LCD_0; - -struct i2c_m_sync_desc I2C_0; - -void I2C_0_PORT_init(void) { - - gpio_set_pin_pull_mode(SDA, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(SDA, PINMUX_PB30C_SERCOM1_PAD0); - - gpio_set_pin_pull_mode(SCL, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(SCL, PINMUX_PB31C_SERCOM1_PAD1); -} - -void I2C_0_CLOCK_init(void) { - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_mclk_set_APBCMASK_SERCOM1_bit(MCLK); -} - -void I2C_0_init(void) { - I2C_0_CLOCK_init(); - i2c_m_sync_init(&I2C_0, SERCOM1); - I2C_0_PORT_init(); -} - -void delay_driver_init(void) { - delay_init(SysTick); -} - -void SEGMENT_LCD_0_PORT_init(void) { - gpio_set_pin_function(SLCD0, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD1, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD2, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD3, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD4, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD5, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD6, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD7, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD8, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD9, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD10, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD11, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD12, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD13, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD14, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD15, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD16, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD17, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD18, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD19, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD20, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD21, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD22, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD23, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD24, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD25, GPIO_PIN_FUNCTION_B); - gpio_set_pin_function(SLCD26, GPIO_PIN_FUNCTION_B); -} - -/** - * \brief SLCD initialization function - * - * Enables SLCD peripheral, clocks and initializes SLCD driver - */ -void SEGMENT_LCD_0_init(void) { - hri_mclk_set_APBCMASK_SLCD_bit(SLCD); - slcd_sync_init(&SEGMENT_LCD_0, SLCD); - SEGMENT_LCD_0_PORT_init(); -} diff --git a/watch-library/hw/driver_init.h b/watch-library/hw/driver_init.h deleted file mode 100644 index d1c33218..00000000 --- a/watch-library/hw/driver_init.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef DRIVER_INIT_INCLUDED -#define DRIVER_INIT_INCLUDED - -#define GPIO_PIN_FUNCTION_A 0 -#define GPIO_PIN_FUNCTION_B 1 -#define GPIO_PIN_FUNCTION_C 2 -#define GPIO_PIN_FUNCTION_D 3 -#define GPIO_PIN_FUNCTION_E 4 -#define GPIO_PIN_FUNCTION_F 5 -#define GPIO_PIN_FUNCTION_G 6 -#define GPIO_PIN_FUNCTION_H 7 -#define GPIO_PIN_FUNCTION_I 8 - -#include "pins.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern struct adc_sync_descriptor ADC_0; - -extern struct i2c_m_sync_desc I2C_0; - -extern struct slcd_sync_descriptor SEGMENT_LCD_0; - -void I2C_0_CLOCK_init(void); -void I2C_0_init(void); -void I2C_0_PORT_init(void); - -void delay_driver_init(void); - -void EXTERNAL_IRQ_0_init(void); - -void SEGMENT_LCD_0_PORT_init(void); -void SEGMENT_LCD_0_init(void); - -#ifdef __cplusplus -} -#endif -#endif // DRIVER_INIT_INCLUDED diff --git a/watch-library/include/component-version.h b/watch-library/include/component-version.h deleted file mode 100644 index a84744e9..00000000 --- a/watch-library/include/component-version.h +++ /dev/null @@ -1,64 +0,0 @@ -/** - * \file - * - * \brief Component version header file - * - * Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _COMPONENT_VERSION_H_INCLUDED -#define _COMPONENT_VERSION_H_INCLUDED - -#define COMPONENT_VERSION_MAJOR 1 -#define COMPONENT_VERSION_MINOR 2 - -// -// The COMPONENT_VERSION define is composed of the major and the minor version number. -// -// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. -// The rest of the COMPONENT_VERSION is the major version. -// -#define COMPONENT_VERSION 10002 - -// -// The build number does not refer to the component, but to the build number -// of the device pack that provides the component. -// -#define BUILD_NUMBER 77 - -// -// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. -// -#define COMPONENT_VERSION_STRING "1.2" - -// -// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. -// -// The COMPONENT_DATE_STRING is written out using the following strftime pattern. -// -// "%Y-%m-%d %H:%M:%S" -// -// -#define COMPONENT_DATE_STRING "2018-08-31 15:05:02" - -#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ - diff --git a/watch-library/include/component/ac.h b/watch-library/include/component/ac.h deleted file mode 100644 index e1df65fa..00000000 --- a/watch-library/include/component/ac.h +++ /dev/null @@ -1,586 +0,0 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_AC_COMPONENT_ -#define _SAML22_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAML22_AC Analog Comparators */ -/*@{*/ - -#define AC_U2245 -#define REV_AC 0x101 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ - uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ -#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ -#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ -#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) -#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) -#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ -#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) -#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) -#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ -#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ - -#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ -#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) -#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ - uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :1; /*!< bit: 27 Reserved */ - uint32_t OUT:2; /*!< bit: 28..29 Output */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ -#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_LOW_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Low speed */ -#define AC_COMPCTRL_SPEED_MEDLOW_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Medium low speed */ -#define AC_COMPCTRL_SPEED_MEDHIGH_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Medium high speed */ -#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_MEDLOW (AC_COMPCTRL_SPEED_MEDLOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_MEDHIGH (AC_COMPCTRL_SPEED_MEDHIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) -#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ -#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) -#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ -#define AC_COMPCTRL_HYST_HYST70_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 70mV */ -#define AC_COMPCTRL_HYST_HYST90_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 90mV */ -#define AC_COMPCTRL_HYST_HYST110_Val _U_(0x3) /**< \brief (AC_COMPCTRL) 110mV */ -#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST70 (AC_COMPCTRL_HYST_HYST70_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST90 (AC_COMPCTRL_HYST_HYST90_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST110 (AC_COMPCTRL_HYST_HYST110_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ - uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ - uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :3; /*!< bit: 0.. 2 Reserved */ - uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} AC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ -#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ - -#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ -#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) -#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ -#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) -#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ -#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) -#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) -#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) -#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ - __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ - RoReg8 Reserved1[0x1]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ - RoReg8 Reserved2[0x2]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved3[0x8]; - __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML22_AC_COMPONENT_ */ diff --git a/watch-library/include/component/adc.h b/watch-library/include/component/adc.h deleted file mode 100644 index f51dc639..00000000 --- a/watch-library/include/component/adc.h +++ /dev/null @@ -1,748 +0,0 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_ADC_COMPONENT_ -#define _SAML22_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAML22_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2247 -#define REV_ADC 0x210 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run During Standby */ - uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run During Standby */ -#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ -#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) -#define ADC_CTRLA_MASK _U_(0xC3) /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */ -#define ADC_CTRLB_PRESCALER_Msk (_U_(0x7) << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) -#define ADC_CTRLB_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */ -#define ADC_CTRLB_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ -#define ADC_CTRLB_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ -#define ADC_CTRLB_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ -#define ADC_CTRLB_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ -#define ADC_CTRLB_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ -#define ADC_CTRLB_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ -#define ADC_CTRLB_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ -#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_MASK _U_(0x07) /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x1) /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ -#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x3) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC2_Val _U_(0x5) /**< \brief (ADC_REFCTRL) VCCANA */ -#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ - uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ - uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ - uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ -#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) -#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ -#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ -#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) -#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */ -#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ -#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ -#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ -#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ -#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ -#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ -#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SEQSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */ -#define ADC_SEQSTATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */ - -#define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */ -#define ADC_SEQSTATUS_SEQSTATE_Msk (_U_(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos) -#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos)) -#define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */ -#define ADC_SEQSTATUS_SEQBUSY (_U_(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos) -#define ADC_SEQSTATUS_MASK _U_(0x9F) /**< \brief (ADC_SEQSTATUS) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ -#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) CTAT output */ -#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal GND */ -#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MASK _U_(0x1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :1; /*!< bit: 6 Reserved */ - uint16_t R2R:1; /*!< bit: 7 Rail-to-Rail mode enable */ - uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t DUALSEL:2; /*!< bit: 12..13 Dual Mode Trigger Selection */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */ -#define ADC_CTRLC_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLC reset_value) Control C */ - -#define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */ -#define ADC_CTRLC_DIFFMODE (_U_(0x1) << ADC_CTRLC_DIFFMODE_Pos) -#define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */ -#define ADC_CTRLC_LEFTADJ (_U_(0x1) << ADC_CTRLC_LEFTADJ_Pos) -#define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */ -#define ADC_CTRLC_FREERUN (_U_(0x1) << ADC_CTRLC_FREERUN_Pos) -#define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */ -#define ADC_CTRLC_CORREN (_U_(0x1) << ADC_CTRLC_CORREN_Pos) -#define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */ -#define ADC_CTRLC_RESSEL_Msk (_U_(0x3) << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos)) -#define ADC_CTRLC_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLC) 12-bit result */ -#define ADC_CTRLC_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLC) For averaging mode output */ -#define ADC_CTRLC_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLC) 10-bit result */ -#define ADC_CTRLC_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLC) 8-bit result */ -#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_R2R_Pos 7 /**< \brief (ADC_CTRLC) Rail-to-Rail mode enable */ -#define ADC_CTRLC_R2R (_U_(0x1) << ADC_CTRLC_R2R_Pos) -#define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */ -#define ADC_CTRLC_WINMODE_Msk (_U_(0x7) << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos)) -#define ADC_CTRLC_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLC) No window mode (default) */ -#define ADC_CTRLC_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLC) RESULT > WINLT */ -#define ADC_CTRLC_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLC) RESULT < WINUT */ -#define ADC_CTRLC_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */ -#define ADC_CTRLC_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ -#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_DUALSEL_Pos 12 /**< \brief (ADC_CTRLC) Dual Mode Trigger Selection */ -#define ADC_CTRLC_DUALSEL_Msk (_U_(0x3) << ADC_CTRLC_DUALSEL_Pos) -#define ADC_CTRLC_DUALSEL(value) (ADC_CTRLC_DUALSEL_Msk & ((value) << ADC_CTRLC_DUALSEL_Pos)) -#define ADC_CTRLC_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs */ -#define ADC_CTRLC_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLC) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ -#define ADC_CTRLC_DUALSEL_BOTH (ADC_CTRLC_DUALSEL_BOTH_Val << ADC_CTRLC_DUALSEL_Pos) -#define ADC_CTRLC_DUALSEL_INTERLEAVE (ADC_CTRLC_DUALSEL_INTERLEAVE_Val << ADC_CTRLC_DUALSEL_Pos) -#define ADC_CTRLC_MASK _U_(0x37BF) /**< \brief (ADC_CTRLC) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ -#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ -#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) -#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */ - uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */ -#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ -#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ - -/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ - uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ - uint16_t INPUTCTRL:1; /*!< bit: 2 INPUTCTRL Synchronization Busy */ - uint16_t CTRLC:1; /*!< bit: 3 CTRLC Synchronization Busy */ - uint16_t AVGCTRL:1; /*!< bit: 4 AVGCTRL Synchronization Busy */ - uint16_t SAMPCTRL:1; /*!< bit: 5 SAMPCTRL Synchronization Busy */ - uint16_t WINLT:1; /*!< bit: 6 WINLT Synchronization Busy */ - uint16_t WINUT:1; /*!< bit: 7 WINUT Synchronization Busy */ - uint16_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */ - uint16_t OFFSETCORR:1; /*!< bit: 9 OFFSETCTRL Synchronization Busy */ - uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ -#define ADC_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ - -#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ -#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) -#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ -#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) -#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) -#define ADC_SYNCBUSY_CTRLC_Pos 3 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */ -#define ADC_SYNCBUSY_CTRLC (_U_(0x1) << ADC_SYNCBUSY_CTRLC_Pos) -#define ADC_SYNCBUSY_AVGCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) -#define ADC_SYNCBUSY_SAMPCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) -#define ADC_SYNCBUSY_WINLT_Pos 6 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */ -#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) -#define ADC_SYNCBUSY_WINUT_Pos 7 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */ -#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) -#define ADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */ -#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) -#define ADC_SYNCBUSY_OFFSETCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) -#define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */ -#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) -#define ADC_SYNCBUSY_MASK _U_(0x07FF) /**< \brief (ADC_SYNCBUSY) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */ -#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */ -#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */ -#define ADC_SEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */ - -#define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */ -#define ADC_SEQCTRL_SEQEN_Msk (_U_(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos) -#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos)) -#define ADC_SEQCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_SEQCTRL) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ -#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) -#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) -#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ -#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) -#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) -#define ADC_CALIB_MASK _U_(0x0707) /**< \brief (ADC_CALIB) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */ - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */ - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */ - __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */ - RoReg8 Reserved1[0x2]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */ - RoReg8 Reserved2[0x3]; - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */ - RoReg8 Reserved3[0x3]; - __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */ - RoReg8 Reserved4[0x2]; - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */ - RoReg8 Reserved5[0x2]; - __IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML22_ADC_COMPONENT_ */ diff --git a/watch-library/include/component/aes.h b/watch-library/include/component/aes.h deleted file mode 100644 index 439ce987..00000000 --- a/watch-library/include/component/aes.h +++ /dev/null @@ -1,325 +0,0 @@ -/** - * \file - * - * \brief Component description for AES - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_AES_COMPONENT_ -#define _SAML22_AES_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AES */ -/* ========================================================================== */ -/** \addtogroup SAML22_AES Advanced Encryption Standard */ -/*@{*/ - -#define AES_U2238 -#define REV_AES 0x210 - -/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ - uint32_t CFBS:3; /*!< bit: 5.. 7 CFB Types */ - uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Keysize */ - uint32_t CIPHER:1; /*!< bit: 10 Cipher mode */ - uint32_t STARTMODE:1; /*!< bit: 11 Start mode */ - uint32_t LOD:1; /*!< bit: 12 LOD Enable */ - uint32_t KEYGEN:1; /*!< bit: 13 Last key generation */ - uint32_t XORKEY:1; /*!< bit: 14 Xor Key operation */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t CTYPE:4; /*!< bit: 16..19 Counter measure types */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AES_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ -#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ - -#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ -#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) -#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ -#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) -#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ -#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) -#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) CFB Types */ -#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) -#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Keysize */ -#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) -#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher mode */ -#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start mode */ -#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) LOD Enable */ -#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last key generation */ -#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) Xor Key operation */ -#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter measure types */ -#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) -#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) -#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ - -/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START:1; /*!< bit: 0 Manual Start */ - uint8_t NEWMSG:1; /*!< bit: 1 New message */ - uint8_t EOM:1; /*!< bit: 2 End of message */ - uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ -#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ - -#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Manual Start */ -#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) -#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ -#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) -#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ -#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) -#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ -#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) -#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ - -/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ -#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete */ -#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete */ -#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) -#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ - -/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ -#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ - -#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete */ -#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) -#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete */ -#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) -#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ - -/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ -#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ - -#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ -#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) -#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ -#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) -#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ - -/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DATABUFPTR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ -#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ - -#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ -#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) -#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) -#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ - -/* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W 8) Debug control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ -#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ - -#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ -#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) -#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ - -/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_KEYWORD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ -#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ -#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ - -/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ -#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ -#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ - -/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INTVECTV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ -#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ -#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ - -/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_HASHKEY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ -#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ -#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ - -/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_GHASH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ -#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ -#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ - -/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_CIPLEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ -#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ -#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ - -/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_RANDSEED_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ -#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ -#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ - -/** \brief AES hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ - __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ - __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ - __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ - __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ - __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */ - RoReg8 Reserved1[0x2]; - __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ - RoReg8 Reserved2[0xC]; - __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ - __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ - RoReg8 Reserved3[0x10]; - __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ - __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ - RoReg8 Reserved4[0x4]; - __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ - __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ -} Aes; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML22_AES_COMPONENT_ */ diff --git a/watch-library/include/component/ccl.h b/watch-library/include/component/ccl.h deleted file mode 100644 index ce10ebc6..00000000 --- a/watch-library/include/component/ccl.h +++ /dev/null @@ -1,188 +0,0 @@ -/** - * \file - * - * \brief Component description for CCL - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_CCL_COMPONENT_ -#define _SAML22_CCL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CCL */ -/* ========================================================================== */ -/** \addtogroup SAML22_CCL Configurable Custom Logic */ -/*@{*/ - -#define CCL_U2225 -#define REV_CCL 0x101 - -/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ -#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ - -#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ -#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) -#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ -#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) -#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ -#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) -#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ - -/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ -#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ - -#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ -#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) -#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ -#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ -#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ -#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ -#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ -#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ - -/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ - uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ - uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ - uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ - uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ - uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ - uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CCL_LUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ -#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ - -#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ -#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) -#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ -#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) -#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ -#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ -#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ -#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ -#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) -#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ -#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) -#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event in put source */ -#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM inout source */ -#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ -#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) -#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ -#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) -#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ -#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) -#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ -#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) -#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ -#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) -#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ -#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) -#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) -#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ - -/** \brief CCL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ - RoReg8 Reserved2[0x2]; - __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ -} Ccl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML22_CCL_COMPONENT_ */ diff --git a/watch-library/include/component/dmac.h b/watch-library/include/component/dmac.h deleted file mode 100644 index 85b2ce02..00000000 --- a/watch-library/include/component/dmac.h +++ /dev/null @@ -1,1117 +0,0 @@ -/** - * \file - * - * \brief Component description for DMAC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_DMAC_COMPONENT_ -#define _SAML22_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAML22_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2223 -#define REV_DMAC 0x222 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ -#define DMAC_CTRL_CRCENABLE (_U_(0x1) << DMAC_CTRL_CRCENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) -#define DMAC_CTRL_MASK _U_(0x0F07) /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) -#define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) No action */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_MASK _U_(0x3F0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) -#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) -#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_MASK _U_(0x03) /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ - uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ - uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_QOSCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ -#define DMAC_QOSCTRL_RESETVALUE _U_(0x2A) /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ - -#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ -#define DMAC_QOSCTRL_WRBQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) -#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_WRBQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_WRBQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ -#define DMAC_QOSCTRL_FQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) -#define DMAC_QOSCTRL_FQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_FQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_FQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_FQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ -#define DMAC_QOSCTRL_DQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) -#define DMAC_QOSCTRL_DQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_DQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_DQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_DQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_MASK _U_(0x3F) /**< \brief (DMAC_QOSCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ - uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ - uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ - uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:16; /*!< bit: 0..15 Channel x Software Trigger */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) -#define DMAC_SWTRIGCTRL_MASK _U_(0x0000FFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ - uint32_t :3; /*!< bit: 4.. 6 Reserved */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ - uint32_t :3; /*!< bit: 20..22 Reserved */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ - uint32_t :3; /*!< bit: 28..30 Reserved */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK _U_(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :2; /*!< bit: 11..12 Reserved */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (_U_(0xF) << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK _U_(0xE70F) /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ - uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ - uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ - uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:16; /*!< bit: 0..15 Channel x Pending Interrupt */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos) -#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos) -#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos) -#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFF) << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) -#define DMAC_INTSTATUS_MASK _U_(0x0000FFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ - uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ - uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ - uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:16; /*!< bit: 0..15 Busy Channel x */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ -#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos) -#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ -#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos) -#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ -#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos) -#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ -#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFF) << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) -#define DMAC_BUSYCH_MASK _U_(0x0000FFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ - uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ - uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ - uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:16; /*!< bit: 0..15 Pending Channel x */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ -#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos) -#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ -#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos) -#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ -#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos) -#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ -#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFF) << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) -#define DMAC_PENDCH_MASK _U_(0x0000FFFF) /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) -#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) -#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) -#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ -#define DMAC_CHID_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHID reset_value) Channel ID */ - -#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ -#define DMAC_CHID_ID_Msk (_U_(0xF) << DMAC_CHID_ID_Pos) -#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) -#define DMAC_CHID_MASK _U_(0x0F) /**< \brief (DMAC_CHID) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Channel run in standby */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ -#define DMAC_CHCTRLA_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel run in standby */ -#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) -#define DMAC_CHCTRLA_MASK _U_(0x43) /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ - uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ - uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ - uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ - uint32_t :8; /*!< bit: 14..21 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ - uint32_t CMD:2; /*!< bit: 24..25 Software Command */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ -#define DMAC_CHCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ - -#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ -#define DMAC_CHCTRLB_EVACT_Msk (_U_(0x7) << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) -#define DMAC_CHCTRLB_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ -#define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ -#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ -#define DMAC_CHCTRLB_EVIE (_U_(0x1) << DMAC_CHCTRLB_EVIE_Pos) -#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ -#define DMAC_CHCTRLB_EVOE (_U_(0x1) << DMAC_CHCTRLB_EVOE_Pos) -#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ -#define DMAC_CHCTRLB_LVL_Msk (_U_(0x3) << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) -#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ -#define DMAC_CHCTRLB_TRIGSRC_Msk (_U_(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) -#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ -#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ -#define DMAC_CHCTRLB_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) -#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ -#define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ -#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) -#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK _U_(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ -#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ -#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ -#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ -#define DMAC_BTCTRL_EVOSEL_BEAT_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< - Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/watch-library/include/core_cmFunc.h b/watch-library/include/core_cmFunc.h deleted file mode 100755 index a1bd88c2..00000000 --- a/watch-library/include/core_cmFunc.h +++ /dev/null @@ -1,637 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.00 - * @date 28. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/watch-library/include/core_cmInstr.h b/watch-library/include/core_cmInstr.h deleted file mode 100755 index cfdea144..00000000 --- a/watch-library/include/core_cmInstr.h +++ /dev/null @@ -1,880 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.00 - * @date 28. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300)) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/watch-library/include/instance/ac.h b/watch-library/include/instance/ac.h deleted file mode 100644 index d2bf7fb9..00000000 --- a/watch-library/include/instance/ac.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * \file - * - * \brief Instance description for AC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_AC_INSTANCE_ -#define _SAML22_AC_INSTANCE_ - -/* ========== Register definition for AC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AC_CTRLA (0x42003400) /**< \brief (AC) Control A */ -#define REG_AC_CTRLB (0x42003401) /**< \brief (AC) Control B */ -#define REG_AC_EVCTRL (0x42003402) /**< \brief (AC) Event Control */ -#define REG_AC_INTENCLR (0x42003404) /**< \brief (AC) Interrupt Enable Clear */ -#define REG_AC_INTENSET (0x42003405) /**< \brief (AC) Interrupt Enable Set */ -#define REG_AC_INTFLAG (0x42003406) /**< \brief (AC) Interrupt Flag Status and Clear */ -#define REG_AC_STATUSA (0x42003407) /**< \brief (AC) Status A */ -#define REG_AC_STATUSB (0x42003408) /**< \brief (AC) Status B */ -#define REG_AC_DBGCTRL (0x42003409) /**< \brief (AC) Debug Control */ -#define REG_AC_WINCTRL (0x4200340A) /**< \brief (AC) Window Control */ -#define REG_AC_SCALER0 (0x4200340C) /**< \brief (AC) Scaler 0 */ -#define REG_AC_SCALER1 (0x4200340D) /**< \brief (AC) Scaler 1 */ -#define REG_AC_COMPCTRL0 (0x42003410) /**< \brief (AC) Comparator Control 0 */ -#define REG_AC_COMPCTRL1 (0x42003414) /**< \brief (AC) Comparator Control 1 */ -#define REG_AC_SYNCBUSY (0x42003420) /**< \brief (AC) Synchronization Busy */ -#else -#define REG_AC_CTRLA (*(RwReg8 *)0x42003400UL) /**< \brief (AC) Control A */ -#define REG_AC_CTRLB (*(WoReg8 *)0x42003401UL) /**< \brief (AC) Control B */ -#define REG_AC_EVCTRL (*(RwReg16*)0x42003402UL) /**< \brief (AC) Event Control */ -#define REG_AC_INTENCLR (*(RwReg8 *)0x42003404UL) /**< \brief (AC) Interrupt Enable Clear */ -#define REG_AC_INTENSET (*(RwReg8 *)0x42003405UL) /**< \brief (AC) Interrupt Enable Set */ -#define REG_AC_INTFLAG (*(RwReg8 *)0x42003406UL) /**< \brief (AC) Interrupt Flag Status and Clear */ -#define REG_AC_STATUSA (*(RoReg8 *)0x42003407UL) /**< \brief (AC) Status A */ -#define REG_AC_STATUSB (*(RoReg8 *)0x42003408UL) /**< \brief (AC) Status B */ -#define REG_AC_DBGCTRL (*(RwReg8 *)0x42003409UL) /**< \brief (AC) Debug Control */ -#define REG_AC_WINCTRL (*(RwReg8 *)0x4200340AUL) /**< \brief (AC) Window Control */ -#define REG_AC_SCALER0 (*(RwReg8 *)0x4200340CUL) /**< \brief (AC) Scaler 0 */ -#define REG_AC_SCALER1 (*(RwReg8 *)0x4200340DUL) /**< \brief (AC) Scaler 1 */ -#define REG_AC_COMPCTRL0 (*(RwReg *)0x42003410UL) /**< \brief (AC) Comparator Control 0 */ -#define REG_AC_COMPCTRL1 (*(RwReg *)0x42003414UL) /**< \brief (AC) Comparator Control 1 */ -#define REG_AC_SYNCBUSY (*(RoReg *)0x42003420UL) /**< \brief (AC) Synchronization Busy */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for AC peripheral ========== */ -#define AC_COMPCTRL_MUXNEG_OPAMP 7 // OPAMP selection for MUXNEG -#define AC_GCLK_ID 26 // Index of Generic Clock -#define AC_NUM_CMP 2 // Number of comparators -#define AC_PAIRS 1 // Number of pairs of comparators - -#endif /* _SAML22_AC_INSTANCE_ */ diff --git a/watch-library/include/instance/adc.h b/watch-library/include/instance/adc.h deleted file mode 100644 index 593cf070..00000000 --- a/watch-library/include/instance/adc.h +++ /dev/null @@ -1,89 +0,0 @@ -/** - * \file - * - * \brief Instance description for ADC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_ADC_INSTANCE_ -#define _SAML22_ADC_INSTANCE_ - -/* ========== Register definition for ADC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_ADC_CTRLA (0x42003000) /**< \brief (ADC) Control A */ -#define REG_ADC_CTRLB (0x42003001) /**< \brief (ADC) Control B */ -#define REG_ADC_REFCTRL (0x42003002) /**< \brief (ADC) Reference Control */ -#define REG_ADC_EVCTRL (0x42003003) /**< \brief (ADC) Event Control */ -#define REG_ADC_INTENCLR (0x42003004) /**< \brief (ADC) Interrupt Enable Clear */ -#define REG_ADC_INTENSET (0x42003005) /**< \brief (ADC) Interrupt Enable Set */ -#define REG_ADC_INTFLAG (0x42003006) /**< \brief (ADC) Interrupt Flag Status and Clear */ -#define REG_ADC_SEQSTATUS (0x42003007) /**< \brief (ADC) Sequence Status */ -#define REG_ADC_INPUTCTRL (0x42003008) /**< \brief (ADC) Input Control */ -#define REG_ADC_CTRLC (0x4200300A) /**< \brief (ADC) Control C */ -#define REG_ADC_AVGCTRL (0x4200300C) /**< \brief (ADC) Average Control */ -#define REG_ADC_SAMPCTRL (0x4200300D) /**< \brief (ADC) Sample Time Control */ -#define REG_ADC_WINLT (0x4200300E) /**< \brief (ADC) Window Monitor Lower Threshold */ -#define REG_ADC_WINUT (0x42003010) /**< \brief (ADC) Window Monitor Upper Threshold */ -#define REG_ADC_GAINCORR (0x42003012) /**< \brief (ADC) Gain Correction */ -#define REG_ADC_OFFSETCORR (0x42003014) /**< \brief (ADC) Offset Correction */ -#define REG_ADC_SWTRIG (0x42003018) /**< \brief (ADC) Software Trigger */ -#define REG_ADC_DBGCTRL (0x4200301C) /**< \brief (ADC) Debug Control */ -#define REG_ADC_SYNCBUSY (0x42003020) /**< \brief (ADC) Synchronization Busy */ -#define REG_ADC_RESULT (0x42003024) /**< \brief (ADC) Result */ -#define REG_ADC_SEQCTRL (0x42003028) /**< \brief (ADC) Sequence Control */ -#define REG_ADC_CALIB (0x4200302C) /**< \brief (ADC) Calibration */ -#else -#define REG_ADC_CTRLA (*(RwReg8 *)0x42003000UL) /**< \brief (ADC) Control A */ -#define REG_ADC_CTRLB (*(RwReg8 *)0x42003001UL) /**< \brief (ADC) Control B */ -#define REG_ADC_REFCTRL (*(RwReg8 *)0x42003002UL) /**< \brief (ADC) Reference Control */ -#define REG_ADC_EVCTRL (*(RwReg8 *)0x42003003UL) /**< \brief (ADC) Event Control */ -#define REG_ADC_INTENCLR (*(RwReg8 *)0x42003004UL) /**< \brief (ADC) Interrupt Enable Clear */ -#define REG_ADC_INTENSET (*(RwReg8 *)0x42003005UL) /**< \brief (ADC) Interrupt Enable Set */ -#define REG_ADC_INTFLAG (*(RwReg8 *)0x42003006UL) /**< \brief (ADC) Interrupt Flag Status and Clear */ -#define REG_ADC_SEQSTATUS (*(RoReg8 *)0x42003007UL) /**< \brief (ADC) Sequence Status */ -#define REG_ADC_INPUTCTRL (*(RwReg16*)0x42003008UL) /**< \brief (ADC) Input Control */ -#define REG_ADC_CTRLC (*(RwReg16*)0x4200300AUL) /**< \brief (ADC) Control C */ -#define REG_ADC_AVGCTRL (*(RwReg8 *)0x4200300CUL) /**< \brief (ADC) Average Control */ -#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x4200300DUL) /**< \brief (ADC) Sample Time Control */ -#define REG_ADC_WINLT (*(RwReg16*)0x4200300EUL) /**< \brief (ADC) Window Monitor Lower Threshold */ -#define REG_ADC_WINUT (*(RwReg16*)0x42003010UL) /**< \brief (ADC) Window Monitor Upper Threshold */ -#define REG_ADC_GAINCORR (*(RwReg16*)0x42003012UL) /**< \brief (ADC) Gain Correction */ -#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42003014UL) /**< \brief (ADC) Offset Correction */ -#define REG_ADC_SWTRIG (*(RwReg8 *)0x42003018UL) /**< \brief (ADC) Software Trigger */ -#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200301CUL) /**< \brief (ADC) Debug Control */ -#define REG_ADC_SYNCBUSY (*(RoReg16*)0x42003020UL) /**< \brief (ADC) Synchronization Busy */ -#define REG_ADC_RESULT (*(RoReg16*)0x42003024UL) /**< \brief (ADC) Result */ -#define REG_ADC_SEQCTRL (*(RwReg *)0x42003028UL) /**< \brief (ADC) Sequence Control */ -#define REG_ADC_CALIB (*(RwReg16*)0x4200302CUL) /**< \brief (ADC) Calibration */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for ADC peripheral ========== */ -#define ADC_DMAC_ID_RESRDY 31 // index of DMA RESRDY trigger -#define ADC_EXTCHANNEL_MSB 19 // Number of external channels -#define ADC_GCLK_ID 25 // index of Generic Clock -#define ADC_INT_CH30 2 // Select OPAMP or CTAT on Channel 30 -#define ADC_MASTER_SLAVE_MODE 0 // ADC Master/Slave Mode - -#endif /* _SAML22_ADC_INSTANCE_ */ diff --git a/watch-library/include/instance/aes.h b/watch-library/include/instance/aes.h deleted file mode 100644 index 1d39e171..00000000 --- a/watch-library/include/instance/aes.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - * \file - * - * \brief Instance description for AES - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_AES_INSTANCE_ -#define _SAML22_AES_INSTANCE_ - -/* ========== Register definition for AES peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AES_CTRLA (0x42004000) /**< \brief (AES) Control A */ -#define REG_AES_CTRLB (0x42004004) /**< \brief (AES) Control B */ -#define REG_AES_INTENCLR (0x42004005) /**< \brief (AES) Interrupt Enable Clear */ -#define REG_AES_INTENSET (0x42004006) /**< \brief (AES) Interrupt Enable Set */ -#define REG_AES_INTFLAG (0x42004007) /**< \brief (AES) Interrupt Flag Status */ -#define REG_AES_DATABUFPTR (0x42004008) /**< \brief (AES) Data buffer pointer */ -#define REG_AES_DBGCTRL (0x42004009) /**< \brief (AES) Debug control */ -#define REG_AES_KEYWORD0 (0x4200400C) /**< \brief (AES) Keyword 0 */ -#define REG_AES_KEYWORD1 (0x42004010) /**< \brief (AES) Keyword 1 */ -#define REG_AES_KEYWORD2 (0x42004014) /**< \brief (AES) Keyword 2 */ -#define REG_AES_KEYWORD3 (0x42004018) /**< \brief (AES) Keyword 3 */ -#define REG_AES_KEYWORD4 (0x4200401C) /**< \brief (AES) Keyword 4 */ -#define REG_AES_KEYWORD5 (0x42004020) /**< \brief (AES) Keyword 5 */ -#define REG_AES_KEYWORD6 (0x42004024) /**< \brief (AES) Keyword 6 */ -#define REG_AES_KEYWORD7 (0x42004028) /**< \brief (AES) Keyword 7 */ -#define REG_AES_INDATA (0x42004038) /**< \brief (AES) Indata */ -#define REG_AES_INTVECTV0 (0x4200403C) /**< \brief (AES) Initialisation Vector 0 */ -#define REG_AES_INTVECTV1 (0x42004040) /**< \brief (AES) Initialisation Vector 1 */ -#define REG_AES_INTVECTV2 (0x42004044) /**< \brief (AES) Initialisation Vector 2 */ -#define REG_AES_INTVECTV3 (0x42004048) /**< \brief (AES) Initialisation Vector 3 */ -#define REG_AES_HASHKEY0 (0x4200405C) /**< \brief (AES) Hash key 0 */ -#define REG_AES_HASHKEY1 (0x42004060) /**< \brief (AES) Hash key 1 */ -#define REG_AES_HASHKEY2 (0x42004064) /**< \brief (AES) Hash key 2 */ -#define REG_AES_HASHKEY3 (0x42004068) /**< \brief (AES) Hash key 3 */ -#define REG_AES_GHASH0 (0x4200406C) /**< \brief (AES) Galois Hash 0 */ -#define REG_AES_GHASH1 (0x42004070) /**< \brief (AES) Galois Hash 1 */ -#define REG_AES_GHASH2 (0x42004074) /**< \brief (AES) Galois Hash 2 */ -#define REG_AES_GHASH3 (0x42004078) /**< \brief (AES) Galois Hash 3 */ -#define REG_AES_CIPLEN (0x42004080) /**< \brief (AES) Cipher Length */ -#define REG_AES_RANDSEED (0x42004084) /**< \brief (AES) Random Seed */ -#else -#define REG_AES_CTRLA (*(RwReg *)0x42004000UL) /**< \brief (AES) Control A */ -#define REG_AES_CTRLB (*(RwReg8 *)0x42004004UL) /**< \brief (AES) Control B */ -#define REG_AES_INTENCLR (*(RwReg8 *)0x42004005UL) /**< \brief (AES) Interrupt Enable Clear */ -#define REG_AES_INTENSET (*(RwReg8 *)0x42004006UL) /**< \brief (AES) Interrupt Enable Set */ -#define REG_AES_INTFLAG (*(RwReg8 *)0x42004007UL) /**< \brief (AES) Interrupt Flag Status */ -#define REG_AES_DATABUFPTR (*(RwReg8 *)0x42004008UL) /**< \brief (AES) Data buffer pointer */ -#define REG_AES_DBGCTRL (*(WoReg8 *)0x42004009UL) /**< \brief (AES) Debug control */ -#define REG_AES_KEYWORD0 (*(WoReg *)0x4200400CUL) /**< \brief (AES) Keyword 0 */ -#define REG_AES_KEYWORD1 (*(WoReg *)0x42004010UL) /**< \brief (AES) Keyword 1 */ -#define REG_AES_KEYWORD2 (*(WoReg *)0x42004014UL) /**< \brief (AES) Keyword 2 */ -#define REG_AES_KEYWORD3 (*(WoReg *)0x42004018UL) /**< \brief (AES) Keyword 3 */ -#define REG_AES_KEYWORD4 (*(WoReg *)0x4200401CUL) /**< \brief (AES) Keyword 4 */ -#define REG_AES_KEYWORD5 (*(WoReg *)0x42004020UL) /**< \brief (AES) Keyword 5 */ -#define REG_AES_KEYWORD6 (*(WoReg *)0x42004024UL) /**< \brief (AES) Keyword 6 */ -#define REG_AES_KEYWORD7 (*(WoReg *)0x42004028UL) /**< \brief (AES) Keyword 7 */ -#define REG_AES_INDATA (*(RwReg *)0x42004038UL) /**< \brief (AES) Indata */ -#define REG_AES_INTVECTV0 (*(WoReg *)0x4200403CUL) /**< \brief (AES) Initialisation Vector 0 */ -#define REG_AES_INTVECTV1 (*(WoReg *)0x42004040UL) /**< \brief (AES) Initialisation Vector 1 */ -#define REG_AES_INTVECTV2 (*(WoReg *)0x42004044UL) /**< \brief (AES) Initialisation Vector 2 */ -#define REG_AES_INTVECTV3 (*(WoReg *)0x42004048UL) /**< \brief (AES) Initialisation Vector 3 */ -#define REG_AES_HASHKEY0 (*(RwReg *)0x4200405CUL) /**< \brief (AES) Hash key 0 */ -#define REG_AES_HASHKEY1 (*(RwReg *)0x42004060UL) /**< \brief (AES) Hash key 1 */ -#define REG_AES_HASHKEY2 (*(RwReg *)0x42004064UL) /**< \brief (AES) Hash key 2 */ -#define REG_AES_HASHKEY3 (*(RwReg *)0x42004068UL) /**< \brief (AES) Hash key 3 */ -#define REG_AES_GHASH0 (*(RwReg *)0x4200406CUL) /**< \brief (AES) Galois Hash 0 */ -#define REG_AES_GHASH1 (*(RwReg *)0x42004070UL) /**< \brief (AES) Galois Hash 1 */ -#define REG_AES_GHASH2 (*(RwReg *)0x42004074UL) /**< \brief (AES) Galois Hash 2 */ -#define REG_AES_GHASH3 (*(RwReg *)0x42004078UL) /**< \brief (AES) Galois Hash 3 */ -#define REG_AES_CIPLEN (*(RwReg *)0x42004080UL) /**< \brief (AES) Cipher Length */ -#define REG_AES_RANDSEED (*(RwReg *)0x42004084UL) /**< \brief (AES) Random Seed */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for AES peripheral ========== */ -#define AES_DMAC_ID_RD 36 // DMA DATA Read trigger -#define AES_DMAC_ID_WR 35 // DMA DATA Write trigger - -#endif /* _SAML22_AES_INSTANCE_ */ diff --git a/watch-library/include/instance/ccl.h b/watch-library/include/instance/ccl.h deleted file mode 100644 index b1e6e8e5..00000000 --- a/watch-library/include/instance/ccl.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * \file - * - * \brief Instance description for CCL - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_CCL_INSTANCE_ -#define _SAML22_CCL_INSTANCE_ - -/* ========== Register definition for CCL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CCL_CTRL (0x42004800) /**< \brief (CCL) Control */ -#define REG_CCL_SEQCTRL0 (0x42004804) /**< \brief (CCL) SEQ Control x 0 */ -#define REG_CCL_SEQCTRL1 (0x42004805) /**< \brief (CCL) SEQ Control x 1 */ -#define REG_CCL_LUTCTRL0 (0x42004808) /**< \brief (CCL) LUT Control x 0 */ -#define REG_CCL_LUTCTRL1 (0x4200480C) /**< \brief (CCL) LUT Control x 1 */ -#define REG_CCL_LUTCTRL2 (0x42004810) /**< \brief (CCL) LUT Control x 2 */ -#define REG_CCL_LUTCTRL3 (0x42004814) /**< \brief (CCL) LUT Control x 3 */ -#else -#define REG_CCL_CTRL (*(RwReg8 *)0x42004800UL) /**< \brief (CCL) Control */ -#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42004804UL) /**< \brief (CCL) SEQ Control x 0 */ -#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42004805UL) /**< \brief (CCL) SEQ Control x 1 */ -#define REG_CCL_LUTCTRL0 (*(RwReg *)0x42004808UL) /**< \brief (CCL) LUT Control x 0 */ -#define REG_CCL_LUTCTRL1 (*(RwReg *)0x4200480CUL) /**< \brief (CCL) LUT Control x 1 */ -#define REG_CCL_LUTCTRL2 (*(RwReg *)0x42004810UL) /**< \brief (CCL) LUT Control x 2 */ -#define REG_CCL_LUTCTRL3 (*(RwReg *)0x42004814UL) /**< \brief (CCL) LUT Control x 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for CCL peripheral ========== */ -#define CCL_GCLK_ID 28 // GCLK index for CCL -#define CCL_IO_NUM 12 // Numer of input pins -#define CCL_LUT_NUM 4 // Number of LUT in a CCL -#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL - -#endif /* _SAML22_CCL_INSTANCE_ */ diff --git a/watch-library/include/instance/dmac.h b/watch-library/include/instance/dmac.h deleted file mode 100644 index 2b7580d2..00000000 --- a/watch-library/include/instance/dmac.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * \file - * - * \brief Instance description for DMAC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_DMAC_INSTANCE_ -#define _SAML22_DMAC_INSTANCE_ - -/* ========== Register definition for DMAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DMAC_CTRL (0x41008000) /**< \brief (DMAC) Control */ -#define REG_DMAC_CRCCTRL (0x41008002) /**< \brief (DMAC) CRC Control */ -#define REG_DMAC_CRCDATAIN (0x41008004) /**< \brief (DMAC) CRC Data Input */ -#define REG_DMAC_CRCCHKSUM (0x41008008) /**< \brief (DMAC) CRC Checksum */ -#define REG_DMAC_CRCSTATUS (0x4100800C) /**< \brief (DMAC) CRC Status */ -#define REG_DMAC_DBGCTRL (0x4100800D) /**< \brief (DMAC) Debug Control */ -#define REG_DMAC_QOSCTRL (0x4100800E) /**< \brief (DMAC) QOS Control */ -#define REG_DMAC_SWTRIGCTRL (0x41008010) /**< \brief (DMAC) Software Trigger Control */ -#define REG_DMAC_PRICTRL0 (0x41008014) /**< \brief (DMAC) Priority Control 0 */ -#define REG_DMAC_INTPEND (0x41008020) /**< \brief (DMAC) Interrupt Pending */ -#define REG_DMAC_INTSTATUS (0x41008024) /**< \brief (DMAC) Interrupt Status */ -#define REG_DMAC_BUSYCH (0x41008028) /**< \brief (DMAC) Busy Channels */ -#define REG_DMAC_PENDCH (0x4100802C) /**< \brief (DMAC) Pending Channels */ -#define REG_DMAC_ACTIVE (0x41008030) /**< \brief (DMAC) Active Channel and Levels */ -#define REG_DMAC_BASEADDR (0x41008034) /**< \brief (DMAC) Descriptor Memory Section Base Address */ -#define REG_DMAC_WRBADDR (0x41008038) /**< \brief (DMAC) Write-Back Memory Section Base Address */ -#define REG_DMAC_CHID (0x4100803F) /**< \brief (DMAC) Channel ID */ -#define REG_DMAC_CHCTRLA (0x41008040) /**< \brief (DMAC) Channel Control A */ -#define REG_DMAC_CHCTRLB (0x41008044) /**< \brief (DMAC) Channel Control B */ -#define REG_DMAC_CHINTENCLR (0x4100804C) /**< \brief (DMAC) Channel Interrupt Enable Clear */ -#define REG_DMAC_CHINTENSET (0x4100804D) /**< \brief (DMAC) Channel Interrupt Enable Set */ -#define REG_DMAC_CHINTFLAG (0x4100804E) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ -#define REG_DMAC_CHSTATUS (0x4100804F) /**< \brief (DMAC) Channel Status */ -#else -#define REG_DMAC_CTRL (*(RwReg16*)0x41008000UL) /**< \brief (DMAC) Control */ -#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41008002UL) /**< \brief (DMAC) CRC Control */ -#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41008004UL) /**< \brief (DMAC) CRC Data Input */ -#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41008008UL) /**< \brief (DMAC) CRC Checksum */ -#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100800CUL) /**< \brief (DMAC) CRC Status */ -#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100800DUL) /**< \brief (DMAC) Debug Control */ -#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100800EUL) /**< \brief (DMAC) QOS Control */ -#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41008010UL) /**< \brief (DMAC) Software Trigger Control */ -#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41008014UL) /**< \brief (DMAC) Priority Control 0 */ -#define REG_DMAC_INTPEND (*(RwReg16*)0x41008020UL) /**< \brief (DMAC) Interrupt Pending */ -#define REG_DMAC_INTSTATUS (*(RoReg *)0x41008024UL) /**< \brief (DMAC) Interrupt Status */ -#define REG_DMAC_BUSYCH (*(RoReg *)0x41008028UL) /**< \brief (DMAC) Busy Channels */ -#define REG_DMAC_PENDCH (*(RoReg *)0x4100802CUL) /**< \brief (DMAC) Pending Channels */ -#define REG_DMAC_ACTIVE (*(RoReg *)0x41008030UL) /**< \brief (DMAC) Active Channel and Levels */ -#define REG_DMAC_BASEADDR (*(RwReg *)0x41008034UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */ -#define REG_DMAC_WRBADDR (*(RwReg *)0x41008038UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */ -#define REG_DMAC_CHID (*(RwReg8 *)0x4100803FUL) /**< \brief (DMAC) Channel ID */ -#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41008040UL) /**< \brief (DMAC) Channel Control A */ -#define REG_DMAC_CHCTRLB (*(RwReg *)0x41008044UL) /**< \brief (DMAC) Channel Control B */ -#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100804CUL) /**< \brief (DMAC) Channel Interrupt Enable Clear */ -#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100804DUL) /**< \brief (DMAC) Channel Interrupt Enable Set */ -#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100804EUL) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ -#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100804FUL) /**< \brief (DMAC) Channel Status */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DMAC peripheral ========== */ -#define DMAC_CH_BITS 4 // Number of bits to select channel -#define DMAC_CH_NUM 16 // Number of channels -#define DMAC_CLK_AHB_ID 3 // AHB clock index -#define DMAC_EVIN_NUM 4 // Number of input events -#define DMAC_EVOUT_NUM 4 // Number of output events -#define DMAC_LVL_BITS 2 // Number of bit to select level priority -#define DMAC_LVL_NUM 4 // Enable priority level number -#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value -#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value -#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value -#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source -#define DMAC_TRIG_NUM 40 // Number of peripheral triggers - -#endif /* _SAML22_DMAC_INSTANCE_ */ diff --git a/watch-library/include/instance/dsu.h b/watch-library/include/instance/dsu.h deleted file mode 100644 index 8c13d4f1..00000000 --- a/watch-library/include/instance/dsu.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * \file - * - * \brief Instance description for DSU - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_DSU_INSTANCE_ -#define _SAML22_DSU_INSTANCE_ - -/* ========== Register definition for DSU peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */ -#define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */ -#define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */ -#define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */ -#define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */ -#define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */ -#define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */ -#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */ -#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */ -#define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */ -#define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */ -#define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */ -#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */ -#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */ -#define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */ -#define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */ -#define REG_DSU_PID5 (0x41003FD4) /**< \brief (DSU) Peripheral Identification 5 */ -#define REG_DSU_PID6 (0x41003FD8) /**< \brief (DSU) Peripheral Identification 6 */ -#define REG_DSU_PID7 (0x41003FDC) /**< \brief (DSU) Peripheral Identification 7 */ -#define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */ -#define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */ -#define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */ -#define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */ -#define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */ -#define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */ -#define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */ -#define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */ -#else -#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */ -#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */ -#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */ -#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */ -#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */ -#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */ -#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */ -#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */ -#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */ -#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */ -#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */ -#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */ -#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */ -#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */ -#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */ -#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */ -#define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identification 5 */ -#define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identification 6 */ -#define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identification 7 */ -#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */ -#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */ -#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */ -#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */ -#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */ -#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */ -#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */ -#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DSU peripheral ========== */ -#define DSU_CLK_AHB_ID 5 - -#endif /* _SAML22_DSU_INSTANCE_ */ diff --git a/watch-library/include/instance/eic.h b/watch-library/include/instance/eic.h deleted file mode 100644 index 31a5a31f..00000000 --- a/watch-library/include/instance/eic.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * \file - * - * \brief Instance description for EIC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_EIC_INSTANCE_ -#define _SAML22_EIC_INSTANCE_ - -/* ========== Register definition for EIC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EIC_CTRLA (0x40002800) /**< \brief (EIC) Control */ -#define REG_EIC_NMICTRL (0x40002801) /**< \brief (EIC) NMI Control */ -#define REG_EIC_NMIFLAG (0x40002802) /**< \brief (EIC) NMI Interrupt Flag */ -#define REG_EIC_SYNCBUSY (0x40002804) /**< \brief (EIC) Syncbusy register */ -#define REG_EIC_EVCTRL (0x40002808) /**< \brief (EIC) Event Control */ -#define REG_EIC_INTENCLR (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */ -#define REG_EIC_INTENSET (0x40002810) /**< \brief (EIC) Interrupt Enable Set */ -#define REG_EIC_INTFLAG (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */ -#define REG_EIC_ASYNCH (0x40002818) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ -#define REG_EIC_CONFIG0 (0x4000281C) /**< \brief (EIC) Configuration 0 */ -#define REG_EIC_CONFIG1 (0x40002820) /**< \brief (EIC) Configuration 1 */ -#else -#define REG_EIC_CTRLA (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control */ -#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) NMI Control */ -#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802UL) /**< \brief (EIC) NMI Interrupt Flag */ -#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804UL) /**< \brief (EIC) Syncbusy register */ -#define REG_EIC_EVCTRL (*(RwReg *)0x40002808UL) /**< \brief (EIC) Event Control */ -#define REG_EIC_INTENCLR (*(RwReg *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */ -#define REG_EIC_INTENSET (*(RwReg *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */ -#define REG_EIC_INTFLAG (*(RwReg *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */ -#define REG_EIC_ASYNCH (*(RwReg *)0x40002818UL) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ -#define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CUL) /**< \brief (EIC) Configuration 0 */ -#define REG_EIC_CONFIG1 (*(RwReg *)0x40002820UL) /**< \brief (EIC) Configuration 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for EIC peripheral ========== */ -#define EIC_EXTINT_NUM 16 -#define EIC_GCLK_ID 3 -#define EIC_NUMBER_OF_CONFIG_REGS 2 -#define EIC_NUMBER_OF_INTERRUPTS 16 - -#endif /* _SAML22_EIC_INSTANCE_ */ diff --git a/watch-library/include/instance/evsys.h b/watch-library/include/instance/evsys.h deleted file mode 100644 index a78277ac..00000000 --- a/watch-library/include/instance/evsys.h +++ /dev/null @@ -1,250 +0,0 @@ -/** - * \file - * - * \brief Instance description for EVSYS - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_EVSYS_INSTANCE_ -#define _SAML22_EVSYS_INSTANCE_ - -/* ========== Register definition for EVSYS peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EVSYS_CTRLA (0x42000000) /**< \brief (EVSYS) Control */ -#define REG_EVSYS_CHSTATUS (0x4200000C) /**< \brief (EVSYS) Channel Status */ -#define REG_EVSYS_INTENCLR (0x42000010) /**< \brief (EVSYS) Interrupt Enable Clear */ -#define REG_EVSYS_INTENSET (0x42000014) /**< \brief (EVSYS) Interrupt Enable Set */ -#define REG_EVSYS_INTFLAG (0x42000018) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ -#define REG_EVSYS_SWEVT (0x4200001C) /**< \brief (EVSYS) Software Event */ -#define REG_EVSYS_CHANNEL0 (0x42000020) /**< \brief (EVSYS) Channel 0 */ -#define REG_EVSYS_CHANNEL1 (0x42000024) /**< \brief (EVSYS) Channel 1 */ -#define REG_EVSYS_CHANNEL2 (0x42000028) /**< \brief (EVSYS) Channel 2 */ -#define REG_EVSYS_CHANNEL3 (0x4200002C) /**< \brief (EVSYS) Channel 3 */ -#define REG_EVSYS_CHANNEL4 (0x42000030) /**< \brief (EVSYS) Channel 4 */ -#define REG_EVSYS_CHANNEL5 (0x42000034) /**< \brief (EVSYS) Channel 5 */ -#define REG_EVSYS_CHANNEL6 (0x42000038) /**< \brief (EVSYS) Channel 6 */ -#define REG_EVSYS_CHANNEL7 (0x4200003C) /**< \brief (EVSYS) Channel 7 */ -#define REG_EVSYS_USER0 (0x42000080) /**< \brief (EVSYS) User Multiplexer 0 */ -#define REG_EVSYS_USER1 (0x42000084) /**< \brief (EVSYS) User Multiplexer 1 */ -#define REG_EVSYS_USER2 (0x42000088) /**< \brief (EVSYS) User Multiplexer 2 */ -#define REG_EVSYS_USER3 (0x4200008C) /**< \brief (EVSYS) User Multiplexer 3 */ -#define REG_EVSYS_USER4 (0x42000090) /**< \brief (EVSYS) User Multiplexer 4 */ -#define REG_EVSYS_USER5 (0x42000094) /**< \brief (EVSYS) User Multiplexer 5 */ -#define REG_EVSYS_USER6 (0x42000098) /**< \brief (EVSYS) User Multiplexer 6 */ -#define REG_EVSYS_USER7 (0x4200009C) /**< \brief (EVSYS) User Multiplexer 7 */ -#define REG_EVSYS_USER8 (0x420000A0) /**< \brief (EVSYS) User Multiplexer 8 */ -#define REG_EVSYS_USER9 (0x420000A4) /**< \brief (EVSYS) User Multiplexer 9 */ -#define REG_EVSYS_USER10 (0x420000A8) /**< \brief (EVSYS) User Multiplexer 10 */ -#define REG_EVSYS_USER11 (0x420000AC) /**< \brief (EVSYS) User Multiplexer 11 */ -#define REG_EVSYS_USER12 (0x420000B0) /**< \brief (EVSYS) User Multiplexer 12 */ -#define REG_EVSYS_USER13 (0x420000B4) /**< \brief (EVSYS) User Multiplexer 13 */ -#define REG_EVSYS_USER14 (0x420000B8) /**< \brief (EVSYS) User Multiplexer 14 */ -#define REG_EVSYS_USER15 (0x420000BC) /**< \brief (EVSYS) User Multiplexer 15 */ -#define REG_EVSYS_USER16 (0x420000C0) /**< \brief (EVSYS) User Multiplexer 16 */ -#define REG_EVSYS_USER17 (0x420000C4) /**< \brief (EVSYS) User Multiplexer 17 */ -#define REG_EVSYS_USER18 (0x420000C8) /**< \brief (EVSYS) User Multiplexer 18 */ -#define REG_EVSYS_USER19 (0x420000CC) /**< \brief (EVSYS) User Multiplexer 19 */ -#define REG_EVSYS_USER20 (0x420000D0) /**< \brief (EVSYS) User Multiplexer 20 */ -#define REG_EVSYS_USER21 (0x420000D4) /**< \brief (EVSYS) User Multiplexer 21 */ -#define REG_EVSYS_USER22 (0x420000D8) /**< \brief (EVSYS) User Multiplexer 22 */ -#define REG_EVSYS_USER23 (0x420000DC) /**< \brief (EVSYS) User Multiplexer 23 */ -#define REG_EVSYS_USER24 (0x420000E0) /**< \brief (EVSYS) User Multiplexer 24 */ -#define REG_EVSYS_USER25 (0x420000E4) /**< \brief (EVSYS) User Multiplexer 25 */ -#define REG_EVSYS_USER26 (0x420000E8) /**< \brief (EVSYS) User Multiplexer 26 */ -#define REG_EVSYS_USER27 (0x420000EC) /**< \brief (EVSYS) User Multiplexer 27 */ -#define REG_EVSYS_USER28 (0x420000F0) /**< \brief (EVSYS) User Multiplexer 28 */ -#define REG_EVSYS_USER29 (0x420000F4) /**< \brief (EVSYS) User Multiplexer 29 */ -#define REG_EVSYS_USER30 (0x420000F8) /**< \brief (EVSYS) User Multiplexer 30 */ -#else -#define REG_EVSYS_CTRLA (*(RwReg8 *)0x42000000UL) /**< \brief (EVSYS) Control */ -#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200000CUL) /**< \brief (EVSYS) Channel Status */ -#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000010UL) /**< \brief (EVSYS) Interrupt Enable Clear */ -#define REG_EVSYS_INTENSET (*(RwReg *)0x42000014UL) /**< \brief (EVSYS) Interrupt Enable Set */ -#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000018UL) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ -#define REG_EVSYS_SWEVT (*(WoReg *)0x4200001CUL) /**< \brief (EVSYS) Software Event */ -#define REG_EVSYS_CHANNEL0 (*(RwReg *)0x42000020UL) /**< \brief (EVSYS) Channel 0 */ -#define REG_EVSYS_CHANNEL1 (*(RwReg *)0x42000024UL) /**< \brief (EVSYS) Channel 1 */ -#define REG_EVSYS_CHANNEL2 (*(RwReg *)0x42000028UL) /**< \brief (EVSYS) Channel 2 */ -#define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4200002CUL) /**< \brief (EVSYS) Channel 3 */ -#define REG_EVSYS_CHANNEL4 (*(RwReg *)0x42000030UL) /**< \brief (EVSYS) Channel 4 */ -#define REG_EVSYS_CHANNEL5 (*(RwReg *)0x42000034UL) /**< \brief (EVSYS) Channel 5 */ -#define REG_EVSYS_CHANNEL6 (*(RwReg *)0x42000038UL) /**< \brief (EVSYS) Channel 6 */ -#define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4200003CUL) /**< \brief (EVSYS) Channel 7 */ -#define REG_EVSYS_USER0 (*(RwReg *)0x42000080UL) /**< \brief (EVSYS) User Multiplexer 0 */ -#define REG_EVSYS_USER1 (*(RwReg *)0x42000084UL) /**< \brief (EVSYS) User Multiplexer 1 */ -#define REG_EVSYS_USER2 (*(RwReg *)0x42000088UL) /**< \brief (EVSYS) User Multiplexer 2 */ -#define REG_EVSYS_USER3 (*(RwReg *)0x4200008CUL) /**< \brief (EVSYS) User Multiplexer 3 */ -#define REG_EVSYS_USER4 (*(RwReg *)0x42000090UL) /**< \brief (EVSYS) User Multiplexer 4 */ -#define REG_EVSYS_USER5 (*(RwReg *)0x42000094UL) /**< \brief (EVSYS) User Multiplexer 5 */ -#define REG_EVSYS_USER6 (*(RwReg *)0x42000098UL) /**< \brief (EVSYS) User Multiplexer 6 */ -#define REG_EVSYS_USER7 (*(RwReg *)0x4200009CUL) /**< \brief (EVSYS) User Multiplexer 7 */ -#define REG_EVSYS_USER8 (*(RwReg *)0x420000A0UL) /**< \brief (EVSYS) User Multiplexer 8 */ -#define REG_EVSYS_USER9 (*(RwReg *)0x420000A4UL) /**< \brief (EVSYS) User Multiplexer 9 */ -#define REG_EVSYS_USER10 (*(RwReg *)0x420000A8UL) /**< \brief (EVSYS) User Multiplexer 10 */ -#define REG_EVSYS_USER11 (*(RwReg *)0x420000ACUL) /**< \brief (EVSYS) User Multiplexer 11 */ -#define REG_EVSYS_USER12 (*(RwReg *)0x420000B0UL) /**< \brief (EVSYS) User Multiplexer 12 */ -#define REG_EVSYS_USER13 (*(RwReg *)0x420000B4UL) /**< \brief (EVSYS) User Multiplexer 13 */ -#define REG_EVSYS_USER14 (*(RwReg *)0x420000B8UL) /**< \brief (EVSYS) User Multiplexer 14 */ -#define REG_EVSYS_USER15 (*(RwReg *)0x420000BCUL) /**< \brief (EVSYS) User Multiplexer 15 */ -#define REG_EVSYS_USER16 (*(RwReg *)0x420000C0UL) /**< \brief (EVSYS) User Multiplexer 16 */ -#define REG_EVSYS_USER17 (*(RwReg *)0x420000C4UL) /**< \brief (EVSYS) User Multiplexer 17 */ -#define REG_EVSYS_USER18 (*(RwReg *)0x420000C8UL) /**< \brief (EVSYS) User Multiplexer 18 */ -#define REG_EVSYS_USER19 (*(RwReg *)0x420000CCUL) /**< \brief (EVSYS) User Multiplexer 19 */ -#define REG_EVSYS_USER20 (*(RwReg *)0x420000D0UL) /**< \brief (EVSYS) User Multiplexer 20 */ -#define REG_EVSYS_USER21 (*(RwReg *)0x420000D4UL) /**< \brief (EVSYS) User Multiplexer 21 */ -#define REG_EVSYS_USER22 (*(RwReg *)0x420000D8UL) /**< \brief (EVSYS) User Multiplexer 22 */ -#define REG_EVSYS_USER23 (*(RwReg *)0x420000DCUL) /**< \brief (EVSYS) User Multiplexer 23 */ -#define REG_EVSYS_USER24 (*(RwReg *)0x420000E0UL) /**< \brief (EVSYS) User Multiplexer 24 */ -#define REG_EVSYS_USER25 (*(RwReg *)0x420000E4UL) /**< \brief (EVSYS) User Multiplexer 25 */ -#define REG_EVSYS_USER26 (*(RwReg *)0x420000E8UL) /**< \brief (EVSYS) User Multiplexer 26 */ -#define REG_EVSYS_USER27 (*(RwReg *)0x420000ECUL) /**< \brief (EVSYS) User Multiplexer 27 */ -#define REG_EVSYS_USER28 (*(RwReg *)0x420000F0UL) /**< \brief (EVSYS) User Multiplexer 28 */ -#define REG_EVSYS_USER29 (*(RwReg *)0x420000F4UL) /**< \brief (EVSYS) User Multiplexer 29 */ -#define REG_EVSYS_USER30 (*(RwReg *)0x420000F8UL) /**< \brief (EVSYS) User Multiplexer 30 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for EVSYS peripheral ========== */ -#define EVSYS_CHANNELS 8 // Number of Channels -#define EVSYS_CHANNELS_BITS 3 // Number of bits to select Channel -#define EVSYS_CHANNELS_MSB 7 // Number of Channels - 1 -#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators -#define EVSYS_GCLK_ID_0 7 -#define EVSYS_GCLK_ID_1 8 -#define EVSYS_GCLK_ID_2 9 -#define EVSYS_GCLK_ID_3 10 -#define EVSYS_GCLK_ID_4 11 -#define EVSYS_GCLK_ID_5 12 -#define EVSYS_GCLK_ID_6 13 -#define EVSYS_GCLK_ID_7 14 -#define EVSYS_GCLK_ID_LSB 7 -#define EVSYS_GCLK_ID_MSB 14 -#define EVSYS_GCLK_ID_SIZE 8 -#define EVSYS_GENERATORS 71 // Total Number of Event Generators -#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator -#define EVSYS_USERS 31 // Total Number of Event Users -#define EVSYS_USERS_BITS 5 // Number of bits to select Event User - -// GENERATORS -#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL 1 -#define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 2 -#define EVSYS_ID_GEN_RTC_CMP_0 3 -#define EVSYS_ID_GEN_RTC_CMP_1 4 -#define EVSYS_ID_GEN_RTC_TAMPER 5 -#define EVSYS_ID_GEN_RTC_OVF 6 -#define EVSYS_ID_GEN_RTC_PER_0 7 -#define EVSYS_ID_GEN_RTC_PER_1 8 -#define EVSYS_ID_GEN_RTC_PER_2 9 -#define EVSYS_ID_GEN_RTC_PER_3 10 -#define EVSYS_ID_GEN_RTC_PER_4 11 -#define EVSYS_ID_GEN_RTC_PER_5 12 -#define EVSYS_ID_GEN_RTC_PER_6 13 -#define EVSYS_ID_GEN_RTC_PER_7 14 -#define EVSYS_ID_GEN_EIC_EXTINT_0 15 -#define EVSYS_ID_GEN_EIC_EXTINT_1 16 -#define EVSYS_ID_GEN_EIC_EXTINT_2 17 -#define EVSYS_ID_GEN_EIC_EXTINT_3 18 -#define EVSYS_ID_GEN_EIC_EXTINT_4 19 -#define EVSYS_ID_GEN_EIC_EXTINT_5 20 -#define EVSYS_ID_GEN_EIC_EXTINT_6 21 -#define EVSYS_ID_GEN_EIC_EXTINT_7 22 -#define EVSYS_ID_GEN_EIC_EXTINT_8 23 -#define EVSYS_ID_GEN_EIC_EXTINT_9 24 -#define EVSYS_ID_GEN_EIC_EXTINT_10 25 -#define EVSYS_ID_GEN_EIC_EXTINT_11 26 -#define EVSYS_ID_GEN_EIC_EXTINT_12 27 -#define EVSYS_ID_GEN_EIC_EXTINT_13 28 -#define EVSYS_ID_GEN_EIC_EXTINT_14 29 -#define EVSYS_ID_GEN_EIC_EXTINT_15 30 -#define EVSYS_ID_GEN_DMAC_CH_0 31 -#define EVSYS_ID_GEN_DMAC_CH_1 32 -#define EVSYS_ID_GEN_DMAC_CH_2 33 -#define EVSYS_ID_GEN_DMAC_CH_3 34 -#define EVSYS_ID_GEN_TCC0_OVF 35 -#define EVSYS_ID_GEN_TCC0_TRG 36 -#define EVSYS_ID_GEN_TCC0_CNT 37 -#define EVSYS_ID_GEN_TCC0_MCX_0 38 -#define EVSYS_ID_GEN_TCC0_MCX_1 39 -#define EVSYS_ID_GEN_TCC0_MCX_2 40 -#define EVSYS_ID_GEN_TCC0_MCX_3 41 -#define EVSYS_ID_GEN_TC0_OVF 42 -#define EVSYS_ID_GEN_TC0_MCX_0 43 -#define EVSYS_ID_GEN_TC0_MCX_1 44 -#define EVSYS_ID_GEN_TC1_OVF 45 -#define EVSYS_ID_GEN_TC1_MCX_0 46 -#define EVSYS_ID_GEN_TC1_MCX_1 47 -#define EVSYS_ID_GEN_TC2_OVF 48 -#define EVSYS_ID_GEN_TC2_MCX_0 49 -#define EVSYS_ID_GEN_TC2_MCX_1 50 -#define EVSYS_ID_GEN_TC3_OVF 51 -#define EVSYS_ID_GEN_TC3_MCX_0 52 -#define EVSYS_ID_GEN_TC3_MCX_1 53 -#define EVSYS_ID_GEN_ADC_RESRDY 54 -#define EVSYS_ID_GEN_ADC_WINMON 55 -#define EVSYS_ID_GEN_AC_COMP_0 56 -#define EVSYS_ID_GEN_AC_COMP_1 57 -#define EVSYS_ID_GEN_AC_WIN_0 58 -#define EVSYS_ID_GEN_SLCD_FC0OVERFLOW 61 -#define EVSYS_ID_GEN_SLCD_FC1OVERFLOW 62 -#define EVSYS_ID_GEN_SLCD_FC2OVERFLOW 63 -#define EVSYS_ID_GEN_SLCD_DT 64 -#define EVSYS_ID_GEN_TRNG_READY 65 -#define EVSYS_ID_GEN_CCL_LUTOUT_0 66 -#define EVSYS_ID_GEN_CCL_LUTOUT_1 67 -#define EVSYS_ID_GEN_CCL_LUTOUT_2 68 -#define EVSYS_ID_GEN_CCL_LUTOUT_3 69 -#define EVSYS_ID_GEN_PAC_ACCERR 70 - -// USERS -#define EVSYS_ID_USER_RTC_TAMPER 0 -#define EVSYS_ID_USER_PORT_EV_0 1 -#define EVSYS_ID_USER_PORT_EV_1 2 -#define EVSYS_ID_USER_PORT_EV_2 3 -#define EVSYS_ID_USER_PORT_EV_3 4 -#define EVSYS_ID_USER_DMAC_CH_0 5 -#define EVSYS_ID_USER_DMAC_CH_1 6 -#define EVSYS_ID_USER_DMAC_CH_2 7 -#define EVSYS_ID_USER_DMAC_CH_3 8 -#define EVSYS_ID_USER_TCC0_EV_0 9 -#define EVSYS_ID_USER_TCC0_EV_1 10 -#define EVSYS_ID_USER_TCC0_MC_0 11 -#define EVSYS_ID_USER_TCC0_MC_1 12 -#define EVSYS_ID_USER_TCC0_MC_2 13 -#define EVSYS_ID_USER_TCC0_MC_3 14 -#define EVSYS_ID_USER_TC0_EVU 15 -#define EVSYS_ID_USER_TC1_EVU 16 -#define EVSYS_ID_USER_TC2_EVU 17 -#define EVSYS_ID_USER_TC3_EVU 18 -#define EVSYS_ID_USER_ADC_START 19 -#define EVSYS_ID_USER_ADC_SYNC 20 -#define EVSYS_ID_USER_AC_SOC_0 21 -#define EVSYS_ID_USER_AC_SOC_1 22 -#define EVSYS_ID_USER_CCL_LUTIN_0 24 -#define EVSYS_ID_USER_CCL_LUTIN_1 25 -#define EVSYS_ID_USER_CCL_LUTIN_2 26 -#define EVSYS_ID_USER_CCL_LUTIN_3 27 -#define EVSYS_ID_USER_MTB_START 29 -#define EVSYS_ID_USER_MTB_STOP 30 - -#endif /* _SAML22_EVSYS_INSTANCE_ */ diff --git a/watch-library/include/instance/freqm.h b/watch-library/include/instance/freqm.h deleted file mode 100644 index 4c2e2102..00000000 --- a/watch-library/include/instance/freqm.h +++ /dev/null @@ -1,60 +0,0 @@ -/** - * \file - * - * \brief Instance description for FREQM - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_FREQM_INSTANCE_ -#define _SAML22_FREQM_INSTANCE_ - -/* ========== Register definition for FREQM peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_FREQM_CTRLA (0x40002C00) /**< \brief (FREQM) Control A Register */ -#define REG_FREQM_CTRLB (0x40002C01) /**< \brief (FREQM) Control B Register */ -#define REG_FREQM_CFGA (0x40002C02) /**< \brief (FREQM) Config A register */ -#define REG_FREQM_INTENCLR (0x40002C08) /**< \brief (FREQM) Interrupt Enable Clear Register */ -#define REG_FREQM_INTENSET (0x40002C09) /**< \brief (FREQM) Interrupt Enable Set Register */ -#define REG_FREQM_INTFLAG (0x40002C0A) /**< \brief (FREQM) Interrupt Flag Register */ -#define REG_FREQM_STATUS (0x40002C0B) /**< \brief (FREQM) Status Register */ -#define REG_FREQM_SYNCBUSY (0x40002C0C) /**< \brief (FREQM) Synchronization Busy Register */ -#define REG_FREQM_VALUE (0x40002C10) /**< \brief (FREQM) Count Value Register */ -#else -#define REG_FREQM_CTRLA (*(RwReg8 *)0x40002C00UL) /**< \brief (FREQM) Control A Register */ -#define REG_FREQM_CTRLB (*(WoReg8 *)0x40002C01UL) /**< \brief (FREQM) Control B Register */ -#define REG_FREQM_CFGA (*(RwReg16*)0x40002C02UL) /**< \brief (FREQM) Config A register */ -#define REG_FREQM_INTENCLR (*(RwReg8 *)0x40002C08UL) /**< \brief (FREQM) Interrupt Enable Clear Register */ -#define REG_FREQM_INTENSET (*(RwReg8 *)0x40002C09UL) /**< \brief (FREQM) Interrupt Enable Set Register */ -#define REG_FREQM_INTFLAG (*(RwReg8 *)0x40002C0AUL) /**< \brief (FREQM) Interrupt Flag Register */ -#define REG_FREQM_STATUS (*(RwReg8 *)0x40002C0BUL) /**< \brief (FREQM) Status Register */ -#define REG_FREQM_SYNCBUSY (*(RoReg *)0x40002C0CUL) /**< \brief (FREQM) Synchronization Busy Register */ -#define REG_FREQM_VALUE (*(RoReg *)0x40002C10UL) /**< \brief (FREQM) Count Value Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for FREQM peripheral ========== */ -#define FREQM_GCLK_ID_MSR 4 // Index of measure generic clock -#define FREQM_GCLK_ID_REF 5 // Index of reference generic clock - -#endif /* _SAML22_FREQM_INSTANCE_ */ diff --git a/watch-library/include/instance/gclk.h b/watch-library/include/instance/gclk.h deleted file mode 100644 index 869d77c6..00000000 --- a/watch-library/include/instance/gclk.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * \file - * - * \brief Instance description for GCLK - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_GCLK_INSTANCE_ -#define _SAML22_GCLK_INSTANCE_ - -/* ========== Register definition for GCLK peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_GCLK_CTRLA (0x40001C00) /**< \brief (GCLK) Control */ -#define REG_GCLK_SYNCBUSY (0x40001C04) /**< \brief (GCLK) Synchronization Busy */ -#define REG_GCLK_GENCTRL0 (0x40001C20) /**< \brief (GCLK) Generic Clock Generator Control 0 */ -#define REG_GCLK_GENCTRL1 (0x40001C24) /**< \brief (GCLK) Generic Clock Generator Control 1 */ -#define REG_GCLK_GENCTRL2 (0x40001C28) /**< \brief (GCLK) Generic Clock Generator Control 2 */ -#define REG_GCLK_GENCTRL3 (0x40001C2C) /**< \brief (GCLK) Generic Clock Generator Control 3 */ -#define REG_GCLK_GENCTRL4 (0x40001C30) /**< \brief (GCLK) Generic Clock Generator Control 4 */ -#define REG_GCLK_PCHCTRL0 (0x40001C80) /**< \brief (GCLK) Peripheral Clock Control 0 */ -#define REG_GCLK_PCHCTRL1 (0x40001C84) /**< \brief (GCLK) Peripheral Clock Control 1 */ -#define REG_GCLK_PCHCTRL2 (0x40001C88) /**< \brief (GCLK) Peripheral Clock Control 2 */ -#define REG_GCLK_PCHCTRL3 (0x40001C8C) /**< \brief (GCLK) Peripheral Clock Control 3 */ -#define REG_GCLK_PCHCTRL4 (0x40001C90) /**< \brief (GCLK) Peripheral Clock Control 4 */ -#define REG_GCLK_PCHCTRL5 (0x40001C94) /**< \brief (GCLK) Peripheral Clock Control 5 */ -#define REG_GCLK_PCHCTRL6 (0x40001C98) /**< \brief (GCLK) Peripheral Clock Control 6 */ -#define REG_GCLK_PCHCTRL7 (0x40001C9C) /**< \brief (GCLK) Peripheral Clock Control 7 */ -#define REG_GCLK_PCHCTRL8 (0x40001CA0) /**< \brief (GCLK) Peripheral Clock Control 8 */ -#define REG_GCLK_PCHCTRL9 (0x40001CA4) /**< \brief (GCLK) Peripheral Clock Control 9 */ -#define REG_GCLK_PCHCTRL10 (0x40001CA8) /**< \brief (GCLK) Peripheral Clock Control 10 */ -#define REG_GCLK_PCHCTRL11 (0x40001CAC) /**< \brief (GCLK) Peripheral Clock Control 11 */ -#define REG_GCLK_PCHCTRL12 (0x40001CB0) /**< \brief (GCLK) Peripheral Clock Control 12 */ -#define REG_GCLK_PCHCTRL13 (0x40001CB4) /**< \brief (GCLK) Peripheral Clock Control 13 */ -#define REG_GCLK_PCHCTRL14 (0x40001CB8) /**< \brief (GCLK) Peripheral Clock Control 14 */ -#define REG_GCLK_PCHCTRL15 (0x40001CBC) /**< \brief (GCLK) Peripheral Clock Control 15 */ -#define REG_GCLK_PCHCTRL16 (0x40001CC0) /**< \brief (GCLK) Peripheral Clock Control 16 */ -#define REG_GCLK_PCHCTRL17 (0x40001CC4) /**< \brief (GCLK) Peripheral Clock Control 17 */ -#define REG_GCLK_PCHCTRL18 (0x40001CC8) /**< \brief (GCLK) Peripheral Clock Control 18 */ -#define REG_GCLK_PCHCTRL19 (0x40001CCC) /**< \brief (GCLK) Peripheral Clock Control 19 */ -#define REG_GCLK_PCHCTRL20 (0x40001CD0) /**< \brief (GCLK) Peripheral Clock Control 20 */ -#define REG_GCLK_PCHCTRL21 (0x40001CD4) /**< \brief (GCLK) Peripheral Clock Control 21 */ -#define REG_GCLK_PCHCTRL22 (0x40001CD8) /**< \brief (GCLK) Peripheral Clock Control 22 */ -#define REG_GCLK_PCHCTRL23 (0x40001CDC) /**< \brief (GCLK) Peripheral Clock Control 23 */ -#define REG_GCLK_PCHCTRL24 (0x40001CE0) /**< \brief (GCLK) Peripheral Clock Control 24 */ -#define REG_GCLK_PCHCTRL25 (0x40001CE4) /**< \brief (GCLK) Peripheral Clock Control 25 */ -#define REG_GCLK_PCHCTRL26 (0x40001CE8) /**< \brief (GCLK) Peripheral Clock Control 26 */ -#define REG_GCLK_PCHCTRL27 (0x40001CEC) /**< \brief (GCLK) Peripheral Clock Control 27 */ -#define REG_GCLK_PCHCTRL28 (0x40001CF0) /**< \brief (GCLK) Peripheral Clock Control 28 */ -#define REG_GCLK_PCHCTRL29 (0x40001CF4) /**< \brief (GCLK) Peripheral Clock Control 29 */ -#else -#define REG_GCLK_CTRLA (*(RwReg8 *)0x40001C00UL) /**< \brief (GCLK) Control */ -#define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001C04UL) /**< \brief (GCLK) Synchronization Busy */ -#define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001C20UL) /**< \brief (GCLK) Generic Clock Generator Control 0 */ -#define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001C24UL) /**< \brief (GCLK) Generic Clock Generator Control 1 */ -#define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001C28UL) /**< \brief (GCLK) Generic Clock Generator Control 2 */ -#define REG_GCLK_GENCTRL3 (*(RwReg *)0x40001C2CUL) /**< \brief (GCLK) Generic Clock Generator Control 3 */ -#define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001C30UL) /**< \brief (GCLK) Generic Clock Generator Control 4 */ -#define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001C80UL) /**< \brief (GCLK) Peripheral Clock Control 0 */ -#define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001C84UL) /**< \brief (GCLK) Peripheral Clock Control 1 */ -#define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001C88UL) /**< \brief (GCLK) Peripheral Clock Control 2 */ -#define REG_GCLK_PCHCTRL3 (*(RwReg *)0x40001C8CUL) /**< \brief (GCLK) Peripheral Clock Control 3 */ -#define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001C90UL) /**< \brief (GCLK) Peripheral Clock Control 4 */ -#define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001C94UL) /**< \brief (GCLK) Peripheral Clock Control 5 */ -#define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001C98UL) /**< \brief (GCLK) Peripheral Clock Control 6 */ -#define REG_GCLK_PCHCTRL7 (*(RwReg *)0x40001C9CUL) /**< \brief (GCLK) Peripheral Clock Control 7 */ -#define REG_GCLK_PCHCTRL8 (*(RwReg *)0x40001CA0UL) /**< \brief (GCLK) Peripheral Clock Control 8 */ -#define REG_GCLK_PCHCTRL9 (*(RwReg *)0x40001CA4UL) /**< \brief (GCLK) Peripheral Clock Control 9 */ -#define REG_GCLK_PCHCTRL10 (*(RwReg *)0x40001CA8UL) /**< \brief (GCLK) Peripheral Clock Control 10 */ -#define REG_GCLK_PCHCTRL11 (*(RwReg *)0x40001CACUL) /**< \brief (GCLK) Peripheral Clock Control 11 */ -#define REG_GCLK_PCHCTRL12 (*(RwReg *)0x40001CB0UL) /**< \brief (GCLK) Peripheral Clock Control 12 */ -#define REG_GCLK_PCHCTRL13 (*(RwReg *)0x40001CB4UL) /**< \brief (GCLK) Peripheral Clock Control 13 */ -#define REG_GCLK_PCHCTRL14 (*(RwReg *)0x40001CB8UL) /**< \brief (GCLK) Peripheral Clock Control 14 */ -#define REG_GCLK_PCHCTRL15 (*(RwReg *)0x40001CBCUL) /**< \brief (GCLK) Peripheral Clock Control 15 */ -#define REG_GCLK_PCHCTRL16 (*(RwReg *)0x40001CC0UL) /**< \brief (GCLK) Peripheral Clock Control 16 */ -#define REG_GCLK_PCHCTRL17 (*(RwReg *)0x40001CC4UL) /**< \brief (GCLK) Peripheral Clock Control 17 */ -#define REG_GCLK_PCHCTRL18 (*(RwReg *)0x40001CC8UL) /**< \brief (GCLK) Peripheral Clock Control 18 */ -#define REG_GCLK_PCHCTRL19 (*(RwReg *)0x40001CCCUL) /**< \brief (GCLK) Peripheral Clock Control 19 */ -#define REG_GCLK_PCHCTRL20 (*(RwReg *)0x40001CD0UL) /**< \brief (GCLK) Peripheral Clock Control 20 */ -#define REG_GCLK_PCHCTRL21 (*(RwReg *)0x40001CD4UL) /**< \brief (GCLK) Peripheral Clock Control 21 */ -#define REG_GCLK_PCHCTRL22 (*(RwReg *)0x40001CD8UL) /**< \brief (GCLK) Peripheral Clock Control 22 */ -#define REG_GCLK_PCHCTRL23 (*(RwReg *)0x40001CDCUL) /**< \brief (GCLK) Peripheral Clock Control 23 */ -#define REG_GCLK_PCHCTRL24 (*(RwReg *)0x40001CE0UL) /**< \brief (GCLK) Peripheral Clock Control 24 */ -#define REG_GCLK_PCHCTRL25 (*(RwReg *)0x40001CE4UL) /**< \brief (GCLK) Peripheral Clock Control 25 */ -#define REG_GCLK_PCHCTRL26 (*(RwReg *)0x40001CE8UL) /**< \brief (GCLK) Peripheral Clock Control 26 */ -#define REG_GCLK_PCHCTRL27 (*(RwReg *)0x40001CECUL) /**< \brief (GCLK) Peripheral Clock Control 27 */ -#define REG_GCLK_PCHCTRL28 (*(RwReg *)0x40001CF0UL) /**< \brief (GCLK) Peripheral Clock Control 28 */ -#define REG_GCLK_PCHCTRL29 (*(RwReg *)0x40001CF4UL) /**< \brief (GCLK) Peripheral Clock Control 29 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 -#define GCLK_GEN_BITS 3 -#define GCLK_GEN_NUM 5 // Number of Generic Clock Generators -#define GCLK_GEN_NUM_MSB 4 // Number of Generic Clock Generators - 1 -#define GCLK_GEN_SOURCE_NUM_MSB 7 // Number of Generic Clock Sources - 1 -#define GCLK_NUM 30 // Number of Generic Clock Users -#define GCLK_SOURCE_BITS 3 -#define GCLK_SOURCE_DFLL48M 6 -#define GCLK_SOURCE_DPLL96M 7 -#define GCLK_SOURCE_GCLKGEN1 2 -#define GCLK_SOURCE_GCLKIN 1 -#define GCLK_SOURCE_NUM 8 // Number of Generic Clock Sources -#define GCLK_SOURCE_OSCULP32K 3 -#define GCLK_SOURCE_OSC16M 5 -#define GCLK_SOURCE_XOSC 0 -#define GCLK_SOURCE_XOSC32K 4 - -#endif /* _SAML22_GCLK_INSTANCE_ */ diff --git a/watch-library/include/instance/mclk.h b/watch-library/include/instance/mclk.h deleted file mode 100644 index 32af4f13..00000000 --- a/watch-library/include/instance/mclk.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * \file - * - * \brief Instance description for MCLK - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_MCLK_INSTANCE_ -#define _SAML22_MCLK_INSTANCE_ - -/* ========== Register definition for MCLK peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_MCLK_INTENCLR (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */ -#define REG_MCLK_INTENSET (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */ -#define REG_MCLK_INTFLAG (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */ -#define REG_MCLK_CPUDIV (0x40000804) /**< \brief (MCLK) CPU Clock Division */ -#define REG_MCLK_BUPDIV (0x40000806) /**< \brief (MCLK) Backup Clock Division */ -#define REG_MCLK_AHBMASK (0x40000810) /**< \brief (MCLK) AHB Mask */ -#define REG_MCLK_APBAMASK (0x40000814) /**< \brief (MCLK) APBA Mask */ -#define REG_MCLK_APBBMASK (0x40000818) /**< \brief (MCLK) APBB Mask */ -#define REG_MCLK_APBCMASK (0x4000081C) /**< \brief (MCLK) APBC Mask */ -#else -#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */ -#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */ -#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */ -#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804UL) /**< \brief (MCLK) CPU Clock Division */ -#define REG_MCLK_BUPDIV (*(RwReg8 *)0x40000806UL) /**< \brief (MCLK) Backup Clock Division */ -#define REG_MCLK_AHBMASK (*(RwReg *)0x40000810UL) /**< \brief (MCLK) AHB Mask */ -#define REG_MCLK_APBAMASK (*(RwReg *)0x40000814UL) /**< \brief (MCLK) APBA Mask */ -#define REG_MCLK_APBBMASK (*(RwReg *)0x40000818UL) /**< \brief (MCLK) APBB Mask */ -#define REG_MCLK_APBCMASK (*(RwReg *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for MCLK peripheral ========== */ -#define MCLK_BUPDIV_IMPLEMENTED 1 -#define MCLK_CTRLA_MCSEL_GCLK 1 -#define MCLK_CTRLA_MCSEL_OSC8M 0 -#define MCLK_MCLK_CLK_APB_NUM 3 -#define MCLK_SYSTEM_CLOCK 1000000 // System Clock Frequency at Reset - -#endif /* _SAML22_MCLK_INSTANCE_ */ diff --git a/watch-library/include/instance/mtb.h b/watch-library/include/instance/mtb.h deleted file mode 100644 index 02e67161..00000000 --- a/watch-library/include/instance/mtb.h +++ /dev/null @@ -1,89 +0,0 @@ -/** - * \file - * - * \brief Instance description for MTB - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_MTB_INSTANCE_ -#define _SAML22_MTB_INSTANCE_ - -/* ========== Register definition for MTB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_MTB_POSITION (0x4100A000) /**< \brief (MTB) MTB Position */ -#define REG_MTB_MASTER (0x4100A004) /**< \brief (MTB) MTB Master */ -#define REG_MTB_FLOW (0x4100A008) /**< \brief (MTB) MTB Flow */ -#define REG_MTB_BASE (0x4100A00C) /**< \brief (MTB) MTB Base */ -#define REG_MTB_ITCTRL (0x4100AF00) /**< \brief (MTB) MTB Integration Mode Control */ -#define REG_MTB_CLAIMSET (0x4100AFA0) /**< \brief (MTB) MTB Claim Set */ -#define REG_MTB_CLAIMCLR (0x4100AFA4) /**< \brief (MTB) MTB Claim Clear */ -#define REG_MTB_LOCKACCESS (0x4100AFB0) /**< \brief (MTB) MTB Lock Access */ -#define REG_MTB_LOCKSTATUS (0x4100AFB4) /**< \brief (MTB) MTB Lock Status */ -#define REG_MTB_AUTHSTATUS (0x4100AFB8) /**< \brief (MTB) MTB Authentication Status */ -#define REG_MTB_DEVARCH (0x4100AFBC) /**< \brief (MTB) MTB Device Architecture */ -#define REG_MTB_DEVID (0x4100AFC8) /**< \brief (MTB) MTB Device Configuration */ -#define REG_MTB_DEVTYPE (0x4100AFCC) /**< \brief (MTB) MTB Device Type */ -#define REG_MTB_PID4 (0x4100AFD0) /**< \brief (MTB) Peripheral Identification 4 */ -#define REG_MTB_PID5 (0x4100AFD4) /**< \brief (MTB) Peripheral Identification 5 */ -#define REG_MTB_PID6 (0x4100AFD8) /**< \brief (MTB) Peripheral Identification 6 */ -#define REG_MTB_PID7 (0x4100AFDC) /**< \brief (MTB) Peripheral Identification 7 */ -#define REG_MTB_PID0 (0x4100AFE0) /**< \brief (MTB) Peripheral Identification 0 */ -#define REG_MTB_PID1 (0x4100AFE4) /**< \brief (MTB) Peripheral Identification 1 */ -#define REG_MTB_PID2 (0x4100AFE8) /**< \brief (MTB) Peripheral Identification 2 */ -#define REG_MTB_PID3 (0x4100AFEC) /**< \brief (MTB) Peripheral Identification 3 */ -#define REG_MTB_CID0 (0x4100AFF0) /**< \brief (MTB) Component Identification 0 */ -#define REG_MTB_CID1 (0x4100AFF4) /**< \brief (MTB) Component Identification 1 */ -#define REG_MTB_CID2 (0x4100AFF8) /**< \brief (MTB) Component Identification 2 */ -#define REG_MTB_CID3 (0x4100AFFC) /**< \brief (MTB) Component Identification 3 */ -#else -#define REG_MTB_POSITION (*(RwReg *)0x4100A000UL) /**< \brief (MTB) MTB Position */ -#define REG_MTB_MASTER (*(RwReg *)0x4100A004UL) /**< \brief (MTB) MTB Master */ -#define REG_MTB_FLOW (*(RwReg *)0x4100A008UL) /**< \brief (MTB) MTB Flow */ -#define REG_MTB_BASE (*(RoReg *)0x4100A00CUL) /**< \brief (MTB) MTB Base */ -#define REG_MTB_ITCTRL (*(RwReg *)0x4100AF00UL) /**< \brief (MTB) MTB Integration Mode Control */ -#define REG_MTB_CLAIMSET (*(RwReg *)0x4100AFA0UL) /**< \brief (MTB) MTB Claim Set */ -#define REG_MTB_CLAIMCLR (*(RwReg *)0x4100AFA4UL) /**< \brief (MTB) MTB Claim Clear */ -#define REG_MTB_LOCKACCESS (*(RwReg *)0x4100AFB0UL) /**< \brief (MTB) MTB Lock Access */ -#define REG_MTB_LOCKSTATUS (*(RoReg *)0x4100AFB4UL) /**< \brief (MTB) MTB Lock Status */ -#define REG_MTB_AUTHSTATUS (*(RoReg *)0x4100AFB8UL) /**< \brief (MTB) MTB Authentication Status */ -#define REG_MTB_DEVARCH (*(RoReg *)0x4100AFBCUL) /**< \brief (MTB) MTB Device Architecture */ -#define REG_MTB_DEVID (*(RoReg *)0x4100AFC8UL) /**< \brief (MTB) MTB Device Configuration */ -#define REG_MTB_DEVTYPE (*(RoReg *)0x4100AFCCUL) /**< \brief (MTB) MTB Device Type */ -#define REG_MTB_PID4 (*(RoReg *)0x4100AFD0UL) /**< \brief (MTB) Peripheral Identification 4 */ -#define REG_MTB_PID5 (*(RoReg *)0x4100AFD4UL) /**< \brief (MTB) Peripheral Identification 5 */ -#define REG_MTB_PID6 (*(RoReg *)0x4100AFD8UL) /**< \brief (MTB) Peripheral Identification 6 */ -#define REG_MTB_PID7 (*(RoReg *)0x4100AFDCUL) /**< \brief (MTB) Peripheral Identification 7 */ -#define REG_MTB_PID0 (*(RoReg *)0x4100AFE0UL) /**< \brief (MTB) Peripheral Identification 0 */ -#define REG_MTB_PID1 (*(RoReg *)0x4100AFE4UL) /**< \brief (MTB) Peripheral Identification 1 */ -#define REG_MTB_PID2 (*(RoReg *)0x4100AFE8UL) /**< \brief (MTB) Peripheral Identification 2 */ -#define REG_MTB_PID3 (*(RoReg *)0x4100AFECUL) /**< \brief (MTB) Peripheral Identification 3 */ -#define REG_MTB_CID0 (*(RoReg *)0x4100AFF0UL) /**< \brief (MTB) Component Identification 0 */ -#define REG_MTB_CID1 (*(RoReg *)0x4100AFF4UL) /**< \brief (MTB) Component Identification 1 */ -#define REG_MTB_CID2 (*(RoReg *)0x4100AFF8UL) /**< \brief (MTB) Component Identification 2 */ -#define REG_MTB_CID3 (*(RoReg *)0x4100AFFCUL) /**< \brief (MTB) Component Identification 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAML22_MTB_INSTANCE_ */ diff --git a/watch-library/include/instance/nvmctrl.h b/watch-library/include/instance/nvmctrl.h deleted file mode 100644 index 89adf7ee..00000000 --- a/watch-library/include/instance/nvmctrl.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * \brief Instance description for NVMCTRL - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_NVMCTRL_INSTANCE_ -#define _SAML22_NVMCTRL_INSTANCE_ - -/* ========== Register definition for NVMCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */ -#define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */ -#define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */ -#define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */ -#define REG_NVMCTRL_INTENSET (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */ -#define REG_NVMCTRL_INTFLAG (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ -#define REG_NVMCTRL_STATUS (0x41004018) /**< \brief (NVMCTRL) Status */ -#define REG_NVMCTRL_ADDR (0x4100401C) /**< \brief (NVMCTRL) Address */ -#define REG_NVMCTRL_LOCK (0x41004020) /**< \brief (NVMCTRL) Lock Section */ -#else -#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */ -#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004UL) /**< \brief (NVMCTRL) Control B */ -#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */ -#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */ -#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */ -#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ -#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */ -#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CUL) /**< \brief (NVMCTRL) Address */ -#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for NVMCTRL peripheral ========== */ -#define NVMCTRL_AUX0_ADDRESS 0x00804000 -#define NVMCTRL_AUX1_ADDRESS 0x00806000 -#define NVMCTRL_AUX2_ADDRESS 0x00808000 -#define NVMCTRL_AUX3_ADDRESS 0x0080A000 -#define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register -#define NVMCTRL_CLK_AHB_ID_PICACHU 10 // Index of PICACHU AHB Clock -#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 262144 -#define NVMCTRL_GCLK_ID 29 // Index of Generic Clock for test -#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 -#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 -#define NVMCTRL_USER_PAGE_OFFSET 0x00800000 -#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF -#define NVMCTRL_RWWEE_PAGES 128 -#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area - -#endif /* _SAML22_NVMCTRL_INSTANCE_ */ diff --git a/watch-library/include/instance/osc32kctrl.h b/watch-library/include/instance/osc32kctrl.h deleted file mode 100644 index 6edc7597..00000000 --- a/watch-library/include/instance/osc32kctrl.h +++ /dev/null @@ -1,61 +0,0 @@ -/** - * \file - * - * \brief Instance description for OSC32KCTRL - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_OSC32KCTRL_INSTANCE_ -#define _SAML22_OSC32KCTRL_INSTANCE_ - -/* ========== Register definition for OSC32KCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_OSC32KCTRL_INTENCLR (0x40001400) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ -#define REG_OSC32KCTRL_INTENSET (0x40001404) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ -#define REG_OSC32KCTRL_INTFLAG (0x40001408) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ -#define REG_OSC32KCTRL_STATUS (0x4000140C) /**< \brief (OSC32KCTRL) Power and Clocks Status */ -#define REG_OSC32KCTRL_RTCCTRL (0x40001410) /**< \brief (OSC32KCTRL) RTC Clock Selection */ -#define REG_OSC32KCTRL_SLCDCTRL (0x40001411) /**< \brief (OSC32KCTRL) SLCD Clock Selection */ -#define REG_OSC32KCTRL_XOSC32K (0x40001414) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define REG_OSC32KCTRL_CFDCTRL (0x40001416) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */ -#define REG_OSC32KCTRL_EVCTRL (0x40001417) /**< \brief (OSC32KCTRL) Event Control */ -#define REG_OSC32KCTRL_OSCULP32K (0x4000141C) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#else -#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001400UL) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ -#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ -#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001408UL) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ -#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000140CUL) /**< \brief (OSC32KCTRL) Power and Clocks Status */ -#define REG_OSC32KCTRL_RTCCTRL (*(RwReg8 *)0x40001410UL) /**< \brief (OSC32KCTRL) RTC Clock Selection */ -#define REG_OSC32KCTRL_SLCDCTRL (*(RwReg8 *)0x40001411UL) /**< \brief (OSC32KCTRL) SLCD Clock Selection */ -#define REG_OSC32KCTRL_XOSC32K (*(RwReg16*)0x40001414UL) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define REG_OSC32KCTRL_CFDCTRL (*(RwReg8 *)0x40001416UL) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */ -#define REG_OSC32KCTRL_EVCTRL (*(RwReg8 *)0x40001417UL) /**< \brief (OSC32KCTRL) Event Control */ -#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000141CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for OSC32KCTRL peripheral ========== */ -#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6 - -#endif /* _SAML22_OSC32KCTRL_INSTANCE_ */ diff --git a/watch-library/include/instance/oscctrl.h b/watch-library/include/instance/oscctrl.h deleted file mode 100644 index bd390207..00000000 --- a/watch-library/include/instance/oscctrl.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - * \file - * - * \brief Instance description for OSCCTRL - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_OSCCTRL_INSTANCE_ -#define _SAML22_OSCCTRL_INSTANCE_ - -/* ========== Register definition for OSCCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_OSCCTRL_INTENCLR (0x40001000) /**< \brief (OSCCTRL) Interrupt Enable Clear */ -#define REG_OSCCTRL_INTENSET (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Set */ -#define REG_OSCCTRL_INTFLAG (0x40001008) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ -#define REG_OSCCTRL_STATUS (0x4000100C) /**< \brief (OSCCTRL) Power and Clocks Status */ -#define REG_OSCCTRL_XOSCCTRL (0x40001010) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define REG_OSCCTRL_CFDPRESC (0x40001012) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */ -#define REG_OSCCTRL_EVCTRL (0x40001013) /**< \brief (OSCCTRL) Event Control */ -#define REG_OSCCTRL_OSC16MCTRL (0x40001014) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ -#define REG_OSCCTRL_DFLLCTRL (0x40001018) /**< \brief (OSCCTRL) DFLL48M Control */ -#define REG_OSCCTRL_DFLLVAL (0x4000101C) /**< \brief (OSCCTRL) DFLL48M Value */ -#define REG_OSCCTRL_DFLLMUL (0x40001020) /**< \brief (OSCCTRL) DFLL48M Multiplier */ -#define REG_OSCCTRL_DFLLSYNC (0x40001024) /**< \brief (OSCCTRL) DFLL48M Synchronization */ -#define REG_OSCCTRL_DPLLCTRLA (0x40001028) /**< \brief (OSCCTRL) DPLL Control */ -#define REG_OSCCTRL_DPLLRATIO (0x4000102C) /**< \brief (OSCCTRL) DPLL Ratio Control */ -#define REG_OSCCTRL_DPLLCTRLB (0x40001030) /**< \brief (OSCCTRL) Digital Core Configuration */ -#define REG_OSCCTRL_DPLLPRESC (0x40001034) /**< \brief (OSCCTRL) DPLL Prescaler */ -#define REG_OSCCTRL_DPLLSYNCBUSY (0x40001038) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ -#define REG_OSCCTRL_DPLLSTATUS (0x4000103C) /**< \brief (OSCCTRL) DPLL Status */ -#else -#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001000UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */ -#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Set */ -#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ -#define REG_OSCCTRL_STATUS (*(RoReg *)0x4000100CUL) /**< \brief (OSCCTRL) Power and Clocks Status */ -#define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40001010UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define REG_OSCCTRL_CFDPRESC (*(RwReg8 *)0x40001012UL) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */ -#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001013UL) /**< \brief (OSCCTRL) Event Control */ -#define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40001014UL) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ -#define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40001018UL) /**< \brief (OSCCTRL) DFLL48M Control */ -#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x4000101CUL) /**< \brief (OSCCTRL) DFLL48M Value */ -#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001020UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */ -#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40001024UL) /**< \brief (OSCCTRL) DFLL48M Synchronization */ -#define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40001028UL) /**< \brief (OSCCTRL) DPLL Control */ -#define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x4000102CUL) /**< \brief (OSCCTRL) DPLL Ratio Control */ -#define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40001030UL) /**< \brief (OSCCTRL) Digital Core Configuration */ -#define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40001034UL) /**< \brief (OSCCTRL) DPLL Prescaler */ -#define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40001038UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ -#define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x4000103CUL) /**< \brief (OSCCTRL) DPLL Status */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for OSCCTRL peripheral ========== */ -#define OSCCTRL_DFLL48M_COARSE_MSB 5 -#define OSCCTRL_DFLL48M_FINE_MSB 9 -#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 -#define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL -#define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define OSCCTRL_CFD_VERSION 0x100 -#define OSCCTRL_DFLL48M_VERSION 0x320 -#define OSCCTRL_FDPLL_VERSION 0x211 -#define OSCCTRL_OSC16M_VERSION 0x101 -#define OSCCTRL_XOSC_VERSION 0x201 - -#endif /* _SAML22_OSCCTRL_INSTANCE_ */ diff --git a/watch-library/include/instance/pac.h b/watch-library/include/instance/pac.h deleted file mode 100644 index cc3d94d5..00000000 --- a/watch-library/include/instance/pac.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * \file - * - * \brief Instance description for PAC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_PAC_INSTANCE_ -#define _SAML22_PAC_INSTANCE_ - -/* ========== Register definition for PAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PAC_WRCTRL (0x40000000) /**< \brief (PAC) Write control */ -#define REG_PAC_EVCTRL (0x40000004) /**< \brief (PAC) Event control */ -#define REG_PAC_INTENCLR (0x40000008) /**< \brief (PAC) Interrupt enable clear */ -#define REG_PAC_INTENSET (0x40000009) /**< \brief (PAC) Interrupt enable set */ -#define REG_PAC_INTFLAGAHB (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */ -#define REG_PAC_INTFLAGA (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ -#define REG_PAC_INTFLAGB (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ -#define REG_PAC_INTFLAGC (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ -#define REG_PAC_STATUSA (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */ -#define REG_PAC_STATUSB (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */ -#define REG_PAC_STATUSC (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */ -#else -#define REG_PAC_WRCTRL (*(RwReg *)0x40000000UL) /**< \brief (PAC) Write control */ -#define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */ -#define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */ -#define REG_PAC_INTENSET (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */ -#define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */ -#define REG_PAC_INTFLAGA (*(RwReg *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ -#define REG_PAC_INTFLAGB (*(RwReg *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ -#define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ -#define REG_PAC_STATUSA (*(RoReg *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */ -#define REG_PAC_STATUSB (*(RoReg *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */ -#define REG_PAC_STATUSC (*(RoReg *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PAC peripheral ========== */ -#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock -#define PAC_CLK_AHB_ID 7 // AHB clock index -#define PAC_HPB_NUM 3 // Number of bridges AHB/APB -#define PAC_INTFLAG_NUM 4 // Number of intflag registers - -#endif /* _SAML22_PAC_INSTANCE_ */ diff --git a/watch-library/include/instance/pm.h b/watch-library/include/instance/pm.h deleted file mode 100644 index 6ca464f2..00000000 --- a/watch-library/include/instance/pm.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * \file - * - * \brief Instance description for PM - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_PM_INSTANCE_ -#define _SAML22_PM_INSTANCE_ - -/* ========== Register definition for PM peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PM_CTRLA (0x40000400) /**< \brief (PM) Control A */ -#define REG_PM_SLEEPCFG (0x40000401) /**< \brief (PM) Sleep Configuration */ -#define REG_PM_PLCFG (0x40000402) /**< \brief (PM) Performance Level Configuration */ -#define REG_PM_INTENCLR (0x40000404) /**< \brief (PM) Interrupt Enable Clear */ -#define REG_PM_INTENSET (0x40000405) /**< \brief (PM) Interrupt Enable Set */ -#define REG_PM_INTFLAG (0x40000406) /**< \brief (PM) Interrupt Flag Status and Clear */ -#define REG_PM_STDBYCFG (0x40000408) /**< \brief (PM) Standby Configuration */ -#else -#define REG_PM_CTRLA (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control A */ -#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Configuration */ -#define REG_PM_PLCFG (*(RwReg8 *)0x40000402UL) /**< \brief (PM) Performance Level Configuration */ -#define REG_PM_INTENCLR (*(RwReg8 *)0x40000404UL) /**< \brief (PM) Interrupt Enable Clear */ -#define REG_PM_INTENSET (*(RwReg8 *)0x40000405UL) /**< \brief (PM) Interrupt Enable Set */ -#define REG_PM_INTFLAG (*(RwReg8 *)0x40000406UL) /**< \brief (PM) Interrupt Flag Status and Clear */ -#define REG_PM_STDBYCFG (*(RwReg16*)0x40000408UL) /**< \brief (PM) Standby Configuration */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PM peripheral ========== */ -#define PM_BIAS_RAM_HS 1 // one if RAM HS can be back biased -#define PM_PD_NUM 0 // Number of switchable Power Domain - -#endif /* _SAML22_PM_INSTANCE_ */ diff --git a/watch-library/include/instance/port.h b/watch-library/include/instance/port.h deleted file mode 100644 index 6ec1564d..00000000 --- a/watch-library/include/instance/port.h +++ /dev/null @@ -1,155 +0,0 @@ -/** - * \file - * - * \brief Instance description for PORT - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_PORT_INSTANCE_ -#define _SAML22_PORT_INSTANCE_ - -/* ========== Register definition for PORT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PORT_DIR0 (0x41006000) /**< \brief (PORT) Data Direction 0 */ -#define REG_PORT_DIRCLR0 (0x41006004) /**< \brief (PORT) Data Direction Clear 0 */ -#define REG_PORT_DIRSET0 (0x41006008) /**< \brief (PORT) Data Direction Set 0 */ -#define REG_PORT_DIRTGL0 (0x4100600C) /**< \brief (PORT) Data Direction Toggle 0 */ -#define REG_PORT_OUT0 (0x41006010) /**< \brief (PORT) Data Output Value 0 */ -#define REG_PORT_OUTCLR0 (0x41006014) /**< \brief (PORT) Data Output Value Clear 0 */ -#define REG_PORT_OUTSET0 (0x41006018) /**< \brief (PORT) Data Output Value Set 0 */ -#define REG_PORT_OUTTGL0 (0x4100601C) /**< \brief (PORT) Data Output Value Toggle 0 */ -#define REG_PORT_IN0 (0x41006020) /**< \brief (PORT) Data Input Value 0 */ -#define REG_PORT_CTRL0 (0x41006024) /**< \brief (PORT) Control 0 */ -#define REG_PORT_WRCONFIG0 (0x41006028) /**< \brief (PORT) Write Configuration 0 */ -#define REG_PORT_EVCTRL0 (0x4100602C) /**< \brief (PORT) Event Input Control 0 */ -#define REG_PORT_PMUX0 (0x41006030) /**< \brief (PORT) Peripheral Multiplexing 0 */ -#define REG_PORT_PINCFG0 (0x41006040) /**< \brief (PORT) Pin Configuration 0 */ -#define REG_PORT_DIR1 (0x41006080) /**< \brief (PORT) Data Direction 1 */ -#define REG_PORT_DIRCLR1 (0x41006084) /**< \brief (PORT) Data Direction Clear 1 */ -#define REG_PORT_DIRSET1 (0x41006088) /**< \brief (PORT) Data Direction Set 1 */ -#define REG_PORT_DIRTGL1 (0x4100608C) /**< \brief (PORT) Data Direction Toggle 1 */ -#define REG_PORT_OUT1 (0x41006090) /**< \brief (PORT) Data Output Value 1 */ -#define REG_PORT_OUTCLR1 (0x41006094) /**< \brief (PORT) Data Output Value Clear 1 */ -#define REG_PORT_OUTSET1 (0x41006098) /**< \brief (PORT) Data Output Value Set 1 */ -#define REG_PORT_OUTTGL1 (0x4100609C) /**< \brief (PORT) Data Output Value Toggle 1 */ -#define REG_PORT_IN1 (0x410060A0) /**< \brief (PORT) Data Input Value 1 */ -#define REG_PORT_CTRL1 (0x410060A4) /**< \brief (PORT) Control 1 */ -#define REG_PORT_WRCONFIG1 (0x410060A8) /**< \brief (PORT) Write Configuration 1 */ -#define REG_PORT_EVCTRL1 (0x410060AC) /**< \brief (PORT) Event Input Control 1 */ -#define REG_PORT_PMUX1 (0x410060B0) /**< \brief (PORT) Peripheral Multiplexing 1 */ -#define REG_PORT_PINCFG1 (0x410060C0) /**< \brief (PORT) Pin Configuration 1 */ -#define REG_PORT_DIR2 (0x41006100) /**< \brief (PORT) Data Direction 2 */ -#define REG_PORT_DIRCLR2 (0x41006104) /**< \brief (PORT) Data Direction Clear 2 */ -#define REG_PORT_DIRSET2 (0x41006108) /**< \brief (PORT) Data Direction Set 2 */ -#define REG_PORT_DIRTGL2 (0x4100610C) /**< \brief (PORT) Data Direction Toggle 2 */ -#define REG_PORT_OUT2 (0x41006110) /**< \brief (PORT) Data Output Value 2 */ -#define REG_PORT_OUTCLR2 (0x41006114) /**< \brief (PORT) Data Output Value Clear 2 */ -#define REG_PORT_OUTSET2 (0x41006118) /**< \brief (PORT) Data Output Value Set 2 */ -#define REG_PORT_OUTTGL2 (0x4100611C) /**< \brief (PORT) Data Output Value Toggle 2 */ -#define REG_PORT_IN2 (0x41006120) /**< \brief (PORT) Data Input Value 2 */ -#define REG_PORT_CTRL2 (0x41006124) /**< \brief (PORT) Control 2 */ -#define REG_PORT_WRCONFIG2 (0x41006128) /**< \brief (PORT) Write Configuration 2 */ -#define REG_PORT_EVCTRL2 (0x4100612C) /**< \brief (PORT) Event Input Control 2 */ -#define REG_PORT_PMUX2 (0x41006130) /**< \brief (PORT) Peripheral Multiplexing 2 */ -#define REG_PORT_PINCFG2 (0x41006140) /**< \brief (PORT) Pin Configuration 2 */ -#else -#define REG_PORT_DIR0 (*(RwReg *)0x41006000UL) /**< \brief (PORT) Data Direction 0 */ -#define REG_PORT_DIRCLR0 (*(RwReg *)0x41006004UL) /**< \brief (PORT) Data Direction Clear 0 */ -#define REG_PORT_DIRSET0 (*(RwReg *)0x41006008UL) /**< \brief (PORT) Data Direction Set 0 */ -#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100600CUL) /**< \brief (PORT) Data Direction Toggle 0 */ -#define REG_PORT_OUT0 (*(RwReg *)0x41006010UL) /**< \brief (PORT) Data Output Value 0 */ -#define REG_PORT_OUTCLR0 (*(RwReg *)0x41006014UL) /**< \brief (PORT) Data Output Value Clear 0 */ -#define REG_PORT_OUTSET0 (*(RwReg *)0x41006018UL) /**< \brief (PORT) Data Output Value Set 0 */ -#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100601CUL) /**< \brief (PORT) Data Output Value Toggle 0 */ -#define REG_PORT_IN0 (*(RoReg *)0x41006020UL) /**< \brief (PORT) Data Input Value 0 */ -#define REG_PORT_CTRL0 (*(RwReg *)0x41006024UL) /**< \brief (PORT) Control 0 */ -#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41006028UL) /**< \brief (PORT) Write Configuration 0 */ -#define REG_PORT_EVCTRL0 (*(RwReg *)0x4100602CUL) /**< \brief (PORT) Event Input Control 0 */ -#define REG_PORT_PMUX0 (*(RwReg8 *)0x41006030UL) /**< \brief (PORT) Peripheral Multiplexing 0 */ -#define REG_PORT_PINCFG0 (*(RwReg8 *)0x41006040UL) /**< \brief (PORT) Pin Configuration 0 */ -#define REG_PORT_DIR1 (*(RwReg *)0x41006080UL) /**< \brief (PORT) Data Direction 1 */ -#define REG_PORT_DIRCLR1 (*(RwReg *)0x41006084UL) /**< \brief (PORT) Data Direction Clear 1 */ -#define REG_PORT_DIRSET1 (*(RwReg *)0x41006088UL) /**< \brief (PORT) Data Direction Set 1 */ -#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100608CUL) /**< \brief (PORT) Data Direction Toggle 1 */ -#define REG_PORT_OUT1 (*(RwReg *)0x41006090UL) /**< \brief (PORT) Data Output Value 1 */ -#define REG_PORT_OUTCLR1 (*(RwReg *)0x41006094UL) /**< \brief (PORT) Data Output Value Clear 1 */ -#define REG_PORT_OUTSET1 (*(RwReg *)0x41006098UL) /**< \brief (PORT) Data Output Value Set 1 */ -#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100609CUL) /**< \brief (PORT) Data Output Value Toggle 1 */ -#define REG_PORT_IN1 (*(RoReg *)0x410060A0UL) /**< \brief (PORT) Data Input Value 1 */ -#define REG_PORT_CTRL1 (*(RwReg *)0x410060A4UL) /**< \brief (PORT) Control 1 */ -#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410060A8UL) /**< \brief (PORT) Write Configuration 1 */ -#define REG_PORT_EVCTRL1 (*(RwReg *)0x410060ACUL) /**< \brief (PORT) Event Input Control 1 */ -#define REG_PORT_PMUX1 (*(RwReg8 *)0x410060B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */ -#define REG_PORT_PINCFG1 (*(RwReg8 *)0x410060C0UL) /**< \brief (PORT) Pin Configuration 1 */ -#define REG_PORT_DIR2 (*(RwReg *)0x41006100UL) /**< \brief (PORT) Data Direction 2 */ -#define REG_PORT_DIRCLR2 (*(RwReg *)0x41006104UL) /**< \brief (PORT) Data Direction Clear 2 */ -#define REG_PORT_DIRSET2 (*(RwReg *)0x41006108UL) /**< \brief (PORT) Data Direction Set 2 */ -#define REG_PORT_DIRTGL2 (*(RwReg *)0x4100610CUL) /**< \brief (PORT) Data Direction Toggle 2 */ -#define REG_PORT_OUT2 (*(RwReg *)0x41006110UL) /**< \brief (PORT) Data Output Value 2 */ -#define REG_PORT_OUTCLR2 (*(RwReg *)0x41006114UL) /**< \brief (PORT) Data Output Value Clear 2 */ -#define REG_PORT_OUTSET2 (*(RwReg *)0x41006118UL) /**< \brief (PORT) Data Output Value Set 2 */ -#define REG_PORT_OUTTGL2 (*(RwReg *)0x4100611CUL) /**< \brief (PORT) Data Output Value Toggle 2 */ -#define REG_PORT_IN2 (*(RoReg *)0x41006120UL) /**< \brief (PORT) Data Input Value 2 */ -#define REG_PORT_CTRL2 (*(RwReg *)0x41006124UL) /**< \brief (PORT) Control 2 */ -#define REG_PORT_WRCONFIG2 (*(WoReg *)0x41006128UL) /**< \brief (PORT) Write Configuration 2 */ -#define REG_PORT_EVCTRL2 (*(RwReg *)0x4100612CUL) /**< \brief (PORT) Event Input Control 2 */ -#define REG_PORT_PMUX2 (*(RwReg8 *)0x41006130UL) /**< \brief (PORT) Peripheral Multiplexing 2 */ -#define REG_PORT_PINCFG2 (*(RwReg8 *)0x41006140UL) /**< \brief (PORT) Pin Configuration 2 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PORT peripheral ========== */ -#define PORT_BITS 93 -#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_DIR_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_DRVSTR 1 // DRVSTR supported -#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_DRVSTR_IMPLEMENTED { 0xC8FFFFFF, 0xC3FFFBFF, 0x1F3FF0EF } -#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F03F0EF } -#define PORT_EV_NUM 4 -#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_INEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_ODRAIN 0 // ODRAIN supported -#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_OUT_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_PIN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_PMUXBIT0_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } -#define PORT_PMUXBIT1_IMPLEMENTED { 0xCBFFFFF7, 0xC3FFFB0F, 0x1B003C03 } -#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } -#define PORT_PMUXBIT2_IMPLEMENTED { 0x4BFFFF34, 0xC3FFFB0F, 0x1F000003 } -#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_PMUXBIT3_IMPLEMENTED { 0xC3CF0FF0, 0x00C3CBC7, 0x18300000 } -#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } -#define PORT_PMUXEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_PULLEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_SLEWLIM 0 // SLEWLIM supported -#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } - -#endif /* _SAML22_PORT_INSTANCE_ */ diff --git a/watch-library/include/instance/ptc.h b/watch-library/include/instance/ptc.h deleted file mode 100644 index 03c6b30d..00000000 --- a/watch-library/include/instance/ptc.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * \file - * - * \brief Instance description for PTC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_PTC_INSTANCE_ -#define _SAML22_PTC_INSTANCE_ - -/* ========== Instance parameters for PTC peripheral ========== */ -#define PTC_DMAC_ID_EOC 37 // Index of DMA EOC trigger -#define PTC_DMAC_ID_SEQ 38 // Index of DMA SEQ trigger -#define PTC_DMAC_ID_WCOMP 39 // Index of DMA WCOMP trigger -#define PTC_GCLK_ID 27 // Index of Generic Clock -#define PTC_LINES_MSB 31 -#define PTC_LINES_NUM 32 // Number of PTC lines -#define PTC_Y_LINES_MSB 23 -#define PTC_Y_LINES_NUM 24 // Number of Y lines - -#endif /* _SAML22_PTC_INSTANCE_ */ diff --git a/watch-library/include/instance/rstc.h b/watch-library/include/instance/rstc.h deleted file mode 100644 index e6186fd4..00000000 --- a/watch-library/include/instance/rstc.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * \file - * - * \brief Instance description for RSTC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_RSTC_INSTANCE_ -#define _SAML22_RSTC_INSTANCE_ - -/* ========== Register definition for RSTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RSTC_RCAUSE (0x40000C00) /**< \brief (RSTC) Reset Cause */ -#define REG_RSTC_BKUPEXIT (0x40000C02) /**< \brief (RSTC) Backup Exit Source */ -#else -#define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000C00UL) /**< \brief (RSTC) Reset Cause */ -#define REG_RSTC_BKUPEXIT (*(RoReg8 *)0x40000C02UL) /**< \brief (RSTC) Backup Exit Source */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for RSTC peripheral ========== */ -#define RSTC_BACKUP_IMPLEMENTED 1 -#define RSTC_NUMBER_OF_EXTWAKE 0 // number of external wakeup line - -#endif /* _SAML22_RSTC_INSTANCE_ */ diff --git a/watch-library/include/instance/rtc.h b/watch-library/include/instance/rtc.h deleted file mode 100644 index 5c6bf72d..00000000 --- a/watch-library/include/instance/rtc.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for RTC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_RTC_INSTANCE_ -#define _SAML22_RTC_INSTANCE_ - -/* ========== Register definition for RTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RTC_DBGCTRL (0x4000240E) /**< \brief (RTC) Debug Control */ -#define REG_RTC_FREQCORR (0x40002414) /**< \brief (RTC) Frequency Correction */ -#define REG_RTC_GP0 (0x40002440) /**< \brief (RTC) General Purpose 0 */ -#define REG_RTC_GP1 (0x40002444) /**< \brief (RTC) General Purpose 1 */ -#define REG_RTC_TAMPCTRL (0x40002460) /**< \brief (RTC) Tamper Control */ -#define REG_RTC_TAMPID (0x40002468) /**< \brief (RTC) Tamper ID */ -#define REG_RTC_BKUP0 (0x40002480) /**< \brief (RTC) Backup 0 */ -#define REG_RTC_BKUP1 (0x40002484) /**< \brief (RTC) Backup 1 */ -#define REG_RTC_BKUP2 (0x40002488) /**< \brief (RTC) Backup 2 */ -#define REG_RTC_BKUP3 (0x4000248C) /**< \brief (RTC) Backup 3 */ -#define REG_RTC_BKUP4 (0x40002490) /**< \brief (RTC) Backup 4 */ -#define REG_RTC_BKUP5 (0x40002494) /**< \brief (RTC) Backup 5 */ -#define REG_RTC_BKUP6 (0x40002498) /**< \brief (RTC) Backup 6 */ -#define REG_RTC_BKUP7 (0x4000249C) /**< \brief (RTC) Backup 7 */ -#define REG_RTC_MODE0_CTRLA (0x40002400) /**< \brief (RTC) MODE0 Control A */ -#define REG_RTC_MODE0_CTRLB (0x40002402) /**< \brief (RTC) MODE0 Control B */ -#define REG_RTC_MODE0_EVCTRL (0x40002404) /**< \brief (RTC) MODE0 Event Control */ -#define REG_RTC_MODE0_INTENCLR (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ -#define REG_RTC_MODE0_INTENSET (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */ -#define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */ -#define REG_RTC_MODE0_COUNT (0x40002418) /**< \brief (RTC) MODE0 Counter Value */ -#define REG_RTC_MODE0_COMP0 (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */ -#define REG_RTC_MODE0_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE0 Timestamp */ -#define REG_RTC_MODE1_CTRLA (0x40002400) /**< \brief (RTC) MODE1 Control A */ -#define REG_RTC_MODE1_CTRLB (0x40002402) /**< \brief (RTC) MODE1 Control B */ -#define REG_RTC_MODE1_EVCTRL (0x40002404) /**< \brief (RTC) MODE1 Event Control */ -#define REG_RTC_MODE1_INTENCLR (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ -#define REG_RTC_MODE1_INTENSET (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */ -#define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */ -#define REG_RTC_MODE1_COUNT (0x40002418) /**< \brief (RTC) MODE1 Counter Value */ -#define REG_RTC_MODE1_PER (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */ -#define REG_RTC_MODE1_COMP0 (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */ -#define REG_RTC_MODE1_COMP1 (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */ -#define REG_RTC_MODE1_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE1 Timestamp */ -#define REG_RTC_MODE2_CTRLA (0x40002400) /**< \brief (RTC) MODE2 Control A */ -#define REG_RTC_MODE2_CTRLB (0x40002402) /**< \brief (RTC) MODE2 Control B */ -#define REG_RTC_MODE2_EVCTRL (0x40002404) /**< \brief (RTC) MODE2 Event Control */ -#define REG_RTC_MODE2_INTENCLR (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ -#define REG_RTC_MODE2_INTENSET (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */ -#define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */ -#define REG_RTC_MODE2_CLOCK (0x40002418) /**< \brief (RTC) MODE2 Clock Value */ -#define REG_RTC_MODE2_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE2 Timestamp */ -#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ -#define REG_RTC_MODE2_ALARM_MASK0 (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ -#else -#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */ -#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */ -#define REG_RTC_GP0 (*(RwReg *)0x40002440UL) /**< \brief (RTC) General Purpose 0 */ -#define REG_RTC_GP1 (*(RwReg *)0x40002444UL) /**< \brief (RTC) General Purpose 1 */ -#define REG_RTC_TAMPCTRL (*(RwReg *)0x40002460UL) /**< \brief (RTC) Tamper Control */ -#define REG_RTC_TAMPID (*(RwReg *)0x40002468UL) /**< \brief (RTC) Tamper ID */ -#define REG_RTC_BKUP0 (*(RwReg *)0x40002480UL) /**< \brief (RTC) Backup 0 */ -#define REG_RTC_BKUP1 (*(RwReg *)0x40002484UL) /**< \brief (RTC) Backup 1 */ -#define REG_RTC_BKUP2 (*(RwReg *)0x40002488UL) /**< \brief (RTC) Backup 2 */ -#define REG_RTC_BKUP3 (*(RwReg *)0x4000248CUL) /**< \brief (RTC) Backup 3 */ -#define REG_RTC_BKUP4 (*(RwReg *)0x40002490UL) /**< \brief (RTC) Backup 4 */ -#define REG_RTC_BKUP5 (*(RwReg *)0x40002494UL) /**< \brief (RTC) Backup 5 */ -#define REG_RTC_BKUP6 (*(RwReg *)0x40002498UL) /**< \brief (RTC) Backup 6 */ -#define REG_RTC_BKUP7 (*(RwReg *)0x4000249CUL) /**< \brief (RTC) Backup 7 */ -#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */ -#define REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE0 Control B */ -#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */ -#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ -#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */ -#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */ -#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */ -#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */ -#define REG_RTC_MODE0_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE0 Timestamp */ -#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */ -#define REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE1 Control B */ -#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */ -#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ -#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */ -#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */ -#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */ -#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */ -#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */ -#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */ -#define REG_RTC_MODE1_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE1 Timestamp */ -#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */ -#define REG_RTC_MODE2_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE2 Control B */ -#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */ -#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ -#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */ -#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */ -#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */ -#define REG_RTC_MODE2_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE2 Timestamp */ -#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ -#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for RTC peripheral ========== */ -#define RTC_ALARM_NUM 1 // Number of Alarms -#define RTC_BKUP_NUM 8 // Number of Backup Registers -#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators -#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators -#define RTC_DMAC_ID_TIMESTAMP 1 // DMA RTC timestamp trigger -#define RTC_GPR_NUM 2 // Number of General-Purpose Registers -#define RTC_PER_NUM 8 // Number of Periodic Intervals -#define RTC_TAMPER_NUM 5 // Number of Tamper Inputs - -#endif /* _SAML22_RTC_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom0.h b/watch-library/include/instance/sercom0.h deleted file mode 100644 index 7160d497..00000000 --- a/watch-library/include/instance/sercom0.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM0 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM0_INSTANCE_ -#define _SAML22_SERCOM0_INSTANCE_ - -/* ========== Register definition for SERCOM0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM0_I2CM_CTRLA (0x42000400) /**< \brief (SERCOM0) I2CM Control A */ -#define REG_SERCOM0_I2CM_CTRLB (0x42000404) /**< \brief (SERCOM0) I2CM Control B */ -#define REG_SERCOM0_I2CM_BAUD (0x4200040C) /**< \brief (SERCOM0) I2CM Baud Rate */ -#define REG_SERCOM0_I2CM_INTENCLR (0x42000414) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ -#define REG_SERCOM0_I2CM_INTENSET (0x42000416) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ -#define REG_SERCOM0_I2CM_INTFLAG (0x42000418) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CM_STATUS (0x4200041A) /**< \brief (SERCOM0) I2CM Status */ -#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) I2CM Synchronization Busy */ -#define REG_SERCOM0_I2CM_ADDR (0x42000424) /**< \brief (SERCOM0) I2CM Address */ -#define REG_SERCOM0_I2CM_DATA (0x42000428) /**< \brief (SERCOM0) I2CM Data */ -#define REG_SERCOM0_I2CM_DBGCTRL (0x42000430) /**< \brief (SERCOM0) I2CM Debug Control */ -#define REG_SERCOM0_I2CS_CTRLA (0x42000400) /**< \brief (SERCOM0) I2CS Control A */ -#define REG_SERCOM0_I2CS_CTRLB (0x42000404) /**< \brief (SERCOM0) I2CS Control B */ -#define REG_SERCOM0_I2CS_INTENCLR (0x42000414) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ -#define REG_SERCOM0_I2CS_INTENSET (0x42000416) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ -#define REG_SERCOM0_I2CS_INTFLAG (0x42000418) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CS_STATUS (0x4200041A) /**< \brief (SERCOM0) I2CS Status */ -#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) I2CS Synchronization Busy */ -#define REG_SERCOM0_I2CS_ADDR (0x42000424) /**< \brief (SERCOM0) I2CS Address */ -#define REG_SERCOM0_I2CS_DATA (0x42000428) /**< \brief (SERCOM0) I2CS Data */ -#define REG_SERCOM0_SPI_CTRLA (0x42000400) /**< \brief (SERCOM0) SPI Control A */ -#define REG_SERCOM0_SPI_CTRLB (0x42000404) /**< \brief (SERCOM0) SPI Control B */ -#define REG_SERCOM0_SPI_BAUD (0x4200040C) /**< \brief (SERCOM0) SPI Baud Rate */ -#define REG_SERCOM0_SPI_INTENCLR (0x42000414) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ -#define REG_SERCOM0_SPI_INTENSET (0x42000416) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ -#define REG_SERCOM0_SPI_INTFLAG (0x42000418) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM0_SPI_STATUS (0x4200041A) /**< \brief (SERCOM0) SPI Status */ -#define REG_SERCOM0_SPI_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) SPI Synchronization Busy */ -#define REG_SERCOM0_SPI_ADDR (0x42000424) /**< \brief (SERCOM0) SPI Address */ -#define REG_SERCOM0_SPI_DATA (0x42000428) /**< \brief (SERCOM0) SPI Data */ -#define REG_SERCOM0_SPI_DBGCTRL (0x42000430) /**< \brief (SERCOM0) SPI Debug Control */ -#define REG_SERCOM0_USART_CTRLA (0x42000400) /**< \brief (SERCOM0) USART Control A */ -#define REG_SERCOM0_USART_CTRLB (0x42000404) /**< \brief (SERCOM0) USART Control B */ -#define REG_SERCOM0_USART_CTRLC (0x42000408) /**< \brief (SERCOM0) USART Control C */ -#define REG_SERCOM0_USART_BAUD (0x4200040C) /**< \brief (SERCOM0) USART Baud Rate */ -#define REG_SERCOM0_USART_RXPL (0x4200040E) /**< \brief (SERCOM0) USART Receive Pulse Length */ -#define REG_SERCOM0_USART_INTENCLR (0x42000414) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ -#define REG_SERCOM0_USART_INTENSET (0x42000416) /**< \brief (SERCOM0) USART Interrupt Enable Set */ -#define REG_SERCOM0_USART_INTFLAG (0x42000418) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM0_USART_STATUS (0x4200041A) /**< \brief (SERCOM0) USART Status */ -#define REG_SERCOM0_USART_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) USART Synchronization Busy */ -#define REG_SERCOM0_USART_RXERRCNT (0x42000420) /**< \brief (SERCOM0) USART Receive Error Count */ -#define REG_SERCOM0_USART_DATA (0x42000428) /**< \brief (SERCOM0) USART Data */ -#define REG_SERCOM0_USART_DBGCTRL (0x42000430) /**< \brief (SERCOM0) USART Debug Control */ -#else -#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) I2CM Control A */ -#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) I2CM Control B */ -#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200040CUL) /**< \brief (SERCOM0) I2CM Baud Rate */ -#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ -#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ -#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) I2CM Status */ -#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) I2CM Synchronization Busy */ -#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) I2CM Address */ -#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM0) I2CM Data */ -#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) I2CM Debug Control */ -#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) I2CS Control A */ -#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) I2CS Control B */ -#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ -#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ -#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) I2CS Status */ -#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) I2CS Synchronization Busy */ -#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) I2CS Address */ -#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM0) I2CS Data */ -#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) SPI Control A */ -#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) SPI Control B */ -#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200040CUL) /**< \brief (SERCOM0) SPI Baud Rate */ -#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ -#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ -#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) SPI Status */ -#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) SPI Synchronization Busy */ -#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) SPI Address */ -#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000428UL) /**< \brief (SERCOM0) SPI Data */ -#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) SPI Debug Control */ -#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) USART Control A */ -#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) USART Control B */ -#define REG_SERCOM0_USART_CTRLC (*(RwReg *)0x42000408UL) /**< \brief (SERCOM0) USART Control C */ -#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200040CUL) /**< \brief (SERCOM0) USART Baud Rate */ -#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200040EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */ -#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ -#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */ -#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) USART Status */ -#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) USART Synchronization Busy */ -#define REG_SERCOM0_USART_RXERRCNT (*(RoReg8 *)0x42000420UL) /**< \brief (SERCOM0) USART Receive Error Count */ -#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000428UL) /**< \brief (SERCOM0) USART Data */ -#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM0 peripheral ========== */ -#define SERCOM0_DMAC_ID_RX 2 // Index of DMA RX trigger -#define SERCOM0_DMAC_ID_TX 3 // Index of DMA TX trigger -#define SERCOM0_GCLK_ID_CORE 16 -#define SERCOM0_GCLK_ID_SLOW 15 -#define SERCOM0_INT_MSB 6 -#define SERCOM0_PMSB 3 -#define SERCOM0_SPI 1 // SPI mode implemented? -#define SERCOM0_TWIM 0 // TWI Master mode implemented? -#define SERCOM0_TWIS 0 // TWI Slave mode implemented? -#define SERCOM0_TWI_HSMODE 0 // TWI HighSpeed mode implemented? -#define SERCOM0_USART 1 // USART mode implemented? -#define SERCOM0_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM0_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM0_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM0_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom1.h b/watch-library/include/instance/sercom1.h deleted file mode 100644 index 1c0176ef..00000000 --- a/watch-library/include/instance/sercom1.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM1 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM1_INSTANCE_ -#define _SAML22_SERCOM1_INSTANCE_ - -/* ========== Register definition for SERCOM1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM1_I2CM_CTRLA (0x42000800) /**< \brief (SERCOM1) I2CM Control A */ -#define REG_SERCOM1_I2CM_CTRLB (0x42000804) /**< \brief (SERCOM1) I2CM Control B */ -#define REG_SERCOM1_I2CM_BAUD (0x4200080C) /**< \brief (SERCOM1) I2CM Baud Rate */ -#define REG_SERCOM1_I2CM_INTENCLR (0x42000814) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ -#define REG_SERCOM1_I2CM_INTENSET (0x42000816) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ -#define REG_SERCOM1_I2CM_INTFLAG (0x42000818) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CM_STATUS (0x4200081A) /**< \brief (SERCOM1) I2CM Status */ -#define REG_SERCOM1_I2CM_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) I2CM Synchronization Busy */ -#define REG_SERCOM1_I2CM_ADDR (0x42000824) /**< \brief (SERCOM1) I2CM Address */ -#define REG_SERCOM1_I2CM_DATA (0x42000828) /**< \brief (SERCOM1) I2CM Data */ -#define REG_SERCOM1_I2CM_DBGCTRL (0x42000830) /**< \brief (SERCOM1) I2CM Debug Control */ -#define REG_SERCOM1_I2CS_CTRLA (0x42000800) /**< \brief (SERCOM1) I2CS Control A */ -#define REG_SERCOM1_I2CS_CTRLB (0x42000804) /**< \brief (SERCOM1) I2CS Control B */ -#define REG_SERCOM1_I2CS_INTENCLR (0x42000814) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ -#define REG_SERCOM1_I2CS_INTENSET (0x42000816) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ -#define REG_SERCOM1_I2CS_INTFLAG (0x42000818) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CS_STATUS (0x4200081A) /**< \brief (SERCOM1) I2CS Status */ -#define REG_SERCOM1_I2CS_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) I2CS Synchronization Busy */ -#define REG_SERCOM1_I2CS_ADDR (0x42000824) /**< \brief (SERCOM1) I2CS Address */ -#define REG_SERCOM1_I2CS_DATA (0x42000828) /**< \brief (SERCOM1) I2CS Data */ -#define REG_SERCOM1_SPI_CTRLA (0x42000800) /**< \brief (SERCOM1) SPI Control A */ -#define REG_SERCOM1_SPI_CTRLB (0x42000804) /**< \brief (SERCOM1) SPI Control B */ -#define REG_SERCOM1_SPI_BAUD (0x4200080C) /**< \brief (SERCOM1) SPI Baud Rate */ -#define REG_SERCOM1_SPI_INTENCLR (0x42000814) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ -#define REG_SERCOM1_SPI_INTENSET (0x42000816) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ -#define REG_SERCOM1_SPI_INTFLAG (0x42000818) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM1_SPI_STATUS (0x4200081A) /**< \brief (SERCOM1) SPI Status */ -#define REG_SERCOM1_SPI_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) SPI Synchronization Busy */ -#define REG_SERCOM1_SPI_ADDR (0x42000824) /**< \brief (SERCOM1) SPI Address */ -#define REG_SERCOM1_SPI_DATA (0x42000828) /**< \brief (SERCOM1) SPI Data */ -#define REG_SERCOM1_SPI_DBGCTRL (0x42000830) /**< \brief (SERCOM1) SPI Debug Control */ -#define REG_SERCOM1_USART_CTRLA (0x42000800) /**< \brief (SERCOM1) USART Control A */ -#define REG_SERCOM1_USART_CTRLB (0x42000804) /**< \brief (SERCOM1) USART Control B */ -#define REG_SERCOM1_USART_CTRLC (0x42000808) /**< \brief (SERCOM1) USART Control C */ -#define REG_SERCOM1_USART_BAUD (0x4200080C) /**< \brief (SERCOM1) USART Baud Rate */ -#define REG_SERCOM1_USART_RXPL (0x4200080E) /**< \brief (SERCOM1) USART Receive Pulse Length */ -#define REG_SERCOM1_USART_INTENCLR (0x42000814) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ -#define REG_SERCOM1_USART_INTENSET (0x42000816) /**< \brief (SERCOM1) USART Interrupt Enable Set */ -#define REG_SERCOM1_USART_INTFLAG (0x42000818) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM1_USART_STATUS (0x4200081A) /**< \brief (SERCOM1) USART Status */ -#define REG_SERCOM1_USART_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) USART Synchronization Busy */ -#define REG_SERCOM1_USART_RXERRCNT (0x42000820) /**< \brief (SERCOM1) USART Receive Error Count */ -#define REG_SERCOM1_USART_DATA (0x42000828) /**< \brief (SERCOM1) USART Data */ -#define REG_SERCOM1_USART_DBGCTRL (0x42000830) /**< \brief (SERCOM1) USART Debug Control */ -#else -#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) I2CM Control A */ -#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) I2CM Control B */ -#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4200080CUL) /**< \brief (SERCOM1) I2CM Baud Rate */ -#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ -#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ -#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) I2CM Status */ -#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) I2CM Synchronization Busy */ -#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) I2CM Address */ -#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM1) I2CM Data */ -#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) I2CM Debug Control */ -#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) I2CS Control A */ -#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) I2CS Control B */ -#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ -#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ -#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) I2CS Status */ -#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) I2CS Synchronization Busy */ -#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) I2CS Address */ -#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM1) I2CS Data */ -#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) SPI Control A */ -#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) SPI Control B */ -#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM1) SPI Baud Rate */ -#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ -#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ -#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) SPI Status */ -#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) SPI Synchronization Busy */ -#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) SPI Address */ -#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000828UL) /**< \brief (SERCOM1) SPI Data */ -#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) SPI Debug Control */ -#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) USART Control A */ -#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) USART Control B */ -#define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x42000808UL) /**< \brief (SERCOM1) USART Control C */ -#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4200080CUL) /**< \brief (SERCOM1) USART Baud Rate */ -#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */ -#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ -#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */ -#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) USART Status */ -#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) USART Synchronization Busy */ -#define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x42000820UL) /**< \brief (SERCOM1) USART Receive Error Count */ -#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000828UL) /**< \brief (SERCOM1) USART Data */ -#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM1 peripheral ========== */ -#define SERCOM1_DMAC_ID_RX 4 // Index of DMA RX trigger -#define SERCOM1_DMAC_ID_TX 5 // Index of DMA TX trigger -#define SERCOM1_GCLK_ID_CORE 17 -#define SERCOM1_GCLK_ID_SLOW 15 -#define SERCOM1_INT_MSB 6 -#define SERCOM1_PMSB 3 -#define SERCOM1_SPI 1 // SPI mode implemented? -#define SERCOM1_TWIM 1 // TWI Master mode implemented? -#define SERCOM1_TWIS 1 // TWI Slave mode implemented? -#define SERCOM1_TWI_HSMODE 1 // TWI HighSpeed mode implemented? -#define SERCOM1_USART 1 // USART mode implemented? -#define SERCOM1_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM1_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM1_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM1_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom2.h b/watch-library/include/instance/sercom2.h deleted file mode 100644 index 6c8458cc..00000000 --- a/watch-library/include/instance/sercom2.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM2 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM2_INSTANCE_ -#define _SAML22_SERCOM2_INSTANCE_ - -/* ========== Register definition for SERCOM2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM2_I2CM_CTRLA (0x42000C00) /**< \brief (SERCOM2) I2CM Control A */ -#define REG_SERCOM2_I2CM_CTRLB (0x42000C04) /**< \brief (SERCOM2) I2CM Control B */ -#define REG_SERCOM2_I2CM_BAUD (0x42000C0C) /**< \brief (SERCOM2) I2CM Baud Rate */ -#define REG_SERCOM2_I2CM_INTENCLR (0x42000C14) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ -#define REG_SERCOM2_I2CM_INTENSET (0x42000C16) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ -#define REG_SERCOM2_I2CM_INTFLAG (0x42000C18) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CM_STATUS (0x42000C1A) /**< \brief (SERCOM2) I2CM Status */ -#define REG_SERCOM2_I2CM_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) I2CM Synchronization Busy */ -#define REG_SERCOM2_I2CM_ADDR (0x42000C24) /**< \brief (SERCOM2) I2CM Address */ -#define REG_SERCOM2_I2CM_DATA (0x42000C28) /**< \brief (SERCOM2) I2CM Data */ -#define REG_SERCOM2_I2CM_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) I2CM Debug Control */ -#define REG_SERCOM2_I2CS_CTRLA (0x42000C00) /**< \brief (SERCOM2) I2CS Control A */ -#define REG_SERCOM2_I2CS_CTRLB (0x42000C04) /**< \brief (SERCOM2) I2CS Control B */ -#define REG_SERCOM2_I2CS_INTENCLR (0x42000C14) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ -#define REG_SERCOM2_I2CS_INTENSET (0x42000C16) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ -#define REG_SERCOM2_I2CS_INTFLAG (0x42000C18) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CS_STATUS (0x42000C1A) /**< \brief (SERCOM2) I2CS Status */ -#define REG_SERCOM2_I2CS_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) I2CS Synchronization Busy */ -#define REG_SERCOM2_I2CS_ADDR (0x42000C24) /**< \brief (SERCOM2) I2CS Address */ -#define REG_SERCOM2_I2CS_DATA (0x42000C28) /**< \brief (SERCOM2) I2CS Data */ -#define REG_SERCOM2_SPI_CTRLA (0x42000C00) /**< \brief (SERCOM2) SPI Control A */ -#define REG_SERCOM2_SPI_CTRLB (0x42000C04) /**< \brief (SERCOM2) SPI Control B */ -#define REG_SERCOM2_SPI_BAUD (0x42000C0C) /**< \brief (SERCOM2) SPI Baud Rate */ -#define REG_SERCOM2_SPI_INTENCLR (0x42000C14) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ -#define REG_SERCOM2_SPI_INTENSET (0x42000C16) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ -#define REG_SERCOM2_SPI_INTFLAG (0x42000C18) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM2_SPI_STATUS (0x42000C1A) /**< \brief (SERCOM2) SPI Status */ -#define REG_SERCOM2_SPI_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) SPI Synchronization Busy */ -#define REG_SERCOM2_SPI_ADDR (0x42000C24) /**< \brief (SERCOM2) SPI Address */ -#define REG_SERCOM2_SPI_DATA (0x42000C28) /**< \brief (SERCOM2) SPI Data */ -#define REG_SERCOM2_SPI_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) SPI Debug Control */ -#define REG_SERCOM2_USART_CTRLA (0x42000C00) /**< \brief (SERCOM2) USART Control A */ -#define REG_SERCOM2_USART_CTRLB (0x42000C04) /**< \brief (SERCOM2) USART Control B */ -#define REG_SERCOM2_USART_CTRLC (0x42000C08) /**< \brief (SERCOM2) USART Control C */ -#define REG_SERCOM2_USART_BAUD (0x42000C0C) /**< \brief (SERCOM2) USART Baud Rate */ -#define REG_SERCOM2_USART_RXPL (0x42000C0E) /**< \brief (SERCOM2) USART Receive Pulse Length */ -#define REG_SERCOM2_USART_INTENCLR (0x42000C14) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ -#define REG_SERCOM2_USART_INTENSET (0x42000C16) /**< \brief (SERCOM2) USART Interrupt Enable Set */ -#define REG_SERCOM2_USART_INTFLAG (0x42000C18) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM2_USART_STATUS (0x42000C1A) /**< \brief (SERCOM2) USART Status */ -#define REG_SERCOM2_USART_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) USART Synchronization Busy */ -#define REG_SERCOM2_USART_RXERRCNT (0x42000C20) /**< \brief (SERCOM2) USART Receive Error Count */ -#define REG_SERCOM2_USART_DATA (0x42000C28) /**< \brief (SERCOM2) USART Data */ -#define REG_SERCOM2_USART_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) USART Debug Control */ -#else -#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) I2CM Control A */ -#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) I2CM Control B */ -#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x42000C0CUL) /**< \brief (SERCOM2) I2CM Baud Rate */ -#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ -#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ -#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) I2CM Status */ -#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) I2CM Synchronization Busy */ -#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) I2CM Address */ -#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM2) I2CM Data */ -#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) I2CM Debug Control */ -#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) I2CS Control A */ -#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) I2CS Control B */ -#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ -#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ -#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) I2CS Status */ -#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) I2CS Synchronization Busy */ -#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) I2CS Address */ -#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM2) I2CS Data */ -#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) SPI Control A */ -#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) SPI Control B */ -#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM2) SPI Baud Rate */ -#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ -#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ -#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) SPI Status */ -#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) SPI Synchronization Busy */ -#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) SPI Address */ -#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42000C28UL) /**< \brief (SERCOM2) SPI Data */ -#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) SPI Debug Control */ -#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) USART Control A */ -#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) USART Control B */ -#define REG_SERCOM2_USART_CTRLC (*(RwReg *)0x42000C08UL) /**< \brief (SERCOM2) USART Control C */ -#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x42000C0CUL) /**< \brief (SERCOM2) USART Baud Rate */ -#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */ -#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ -#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */ -#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) USART Status */ -#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) USART Synchronization Busy */ -#define REG_SERCOM2_USART_RXERRCNT (*(RoReg8 *)0x42000C20UL) /**< \brief (SERCOM2) USART Receive Error Count */ -#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42000C28UL) /**< \brief (SERCOM2) USART Data */ -#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM2 peripheral ========== */ -#define SERCOM2_DMAC_ID_RX 6 // Index of DMA RX trigger -#define SERCOM2_DMAC_ID_TX 7 // Index of DMA TX trigger -#define SERCOM2_GCLK_ID_CORE 18 -#define SERCOM2_GCLK_ID_SLOW 15 -#define SERCOM2_INT_MSB 6 -#define SERCOM2_PMSB 3 -#define SERCOM2_SPI 1 // SPI mode implemented? -#define SERCOM2_TWIM 1 // TWI Master mode implemented? -#define SERCOM2_TWIS 1 // TWI Slave mode implemented? -#define SERCOM2_TWI_HSMODE 0 // TWI HighSpeed mode implemented? -#define SERCOM2_USART 1 // USART mode implemented? -#define SERCOM2_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM2_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM2_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM2_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom3.h b/watch-library/include/instance/sercom3.h deleted file mode 100644 index f7256e22..00000000 --- a/watch-library/include/instance/sercom3.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM3 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM3_INSTANCE_ -#define _SAML22_SERCOM3_INSTANCE_ - -/* ========== Register definition for SERCOM3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM3_I2CM_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (0x4200100C) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CM Synchronization Busy */ -#define REG_SERCOM3_I2CM_ADDR (0x42001024) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (0x42001028) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (0x42001030) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CS Synchronization Busy */ -#define REG_SERCOM3_I2CS_ADDR (0x42001024) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (0x42001028) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (0x42001000) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (0x42001004) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (0x4200100C) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (0x42001014) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (0x42001016) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (0x42001018) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (0x4200101A) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) SPI Synchronization Busy */ -#define REG_SERCOM3_SPI_ADDR (0x42001024) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (0x42001028) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (0x42001030) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (0x42001000) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (0x42001004) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_CTRLC (0x42001008) /**< \brief (SERCOM3) USART Control C */ -#define REG_SERCOM3_USART_BAUD (0x4200100C) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (0x4200100E) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (0x42001014) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (0x42001016) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (0x42001018) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (0x4200101A) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) USART Synchronization Busy */ -#define REG_SERCOM3_USART_RXERRCNT (0x42001020) /**< \brief (SERCOM3) USART Receive Error Count */ -#define REG_SERCOM3_USART_DATA (0x42001028) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (0x42001030) /**< \brief (SERCOM3) USART Debug Control */ -#else -#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200100CUL) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CM Synchronization Busy */ -#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CS Synchronization Busy */ -#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) SPI Synchronization Busy */ -#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001028UL) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_CTRLC (*(RwReg *)0x42001008UL) /**< \brief (SERCOM3) USART Control C */ -#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200100CUL) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) USART Synchronization Busy */ -#define REG_SERCOM3_USART_RXERRCNT (*(RoReg8 *)0x42001020UL) /**< \brief (SERCOM3) USART Receive Error Count */ -#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001028UL) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM3 peripheral ========== */ -#define SERCOM3_DMAC_ID_RX 8 // Index of DMA RX trigger -#define SERCOM3_DMAC_ID_TX 9 // Index of DMA TX trigger -#define SERCOM3_GCLK_ID_CORE 19 -#define SERCOM3_GCLK_ID_SLOW 15 -#define SERCOM3_INT_MSB 6 -#define SERCOM3_PMSB 3 -#define SERCOM3_SPI 1 // SPI mode implemented? -#define SERCOM3_TWIM 1 // TWI Master mode implemented? -#define SERCOM3_TWIS 1 // TWI Slave mode implemented? -#define SERCOM3_TWI_HSMODE 0 // TWI HighSpeed mode implemented? -#define SERCOM3_USART 1 // USART mode implemented? -#define SERCOM3_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM3_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM3_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM3_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom4.h b/watch-library/include/instance/sercom4.h deleted file mode 100644 index d5f5d736..00000000 --- a/watch-library/include/instance/sercom4.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM4 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM4_INSTANCE_ -#define _SAML22_SERCOM4_INSTANCE_ - -/* ========== Register definition for SERCOM4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM4_I2CM_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CM Control A */ -#define REG_SERCOM4_I2CM_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CM Control B */ -#define REG_SERCOM4_I2CM_BAUD (0x4200140C) /**< \brief (SERCOM4) I2CM Baud Rate */ -#define REG_SERCOM4_I2CM_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ -#define REG_SERCOM4_I2CM_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ -#define REG_SERCOM4_I2CM_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CM_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CM Status */ -#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CM Synchronization Busy */ -#define REG_SERCOM4_I2CM_ADDR (0x42001424) /**< \brief (SERCOM4) I2CM Address */ -#define REG_SERCOM4_I2CM_DATA (0x42001428) /**< \brief (SERCOM4) I2CM Data */ -#define REG_SERCOM4_I2CM_DBGCTRL (0x42001430) /**< \brief (SERCOM4) I2CM Debug Control */ -#define REG_SERCOM4_I2CS_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CS Control A */ -#define REG_SERCOM4_I2CS_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CS Control B */ -#define REG_SERCOM4_I2CS_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ -#define REG_SERCOM4_I2CS_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ -#define REG_SERCOM4_I2CS_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CS_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CS Status */ -#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CS Synchronization Busy */ -#define REG_SERCOM4_I2CS_ADDR (0x42001424) /**< \brief (SERCOM4) I2CS Address */ -#define REG_SERCOM4_I2CS_DATA (0x42001428) /**< \brief (SERCOM4) I2CS Data */ -#define REG_SERCOM4_SPI_CTRLA (0x42001400) /**< \brief (SERCOM4) SPI Control A */ -#define REG_SERCOM4_SPI_CTRLB (0x42001404) /**< \brief (SERCOM4) SPI Control B */ -#define REG_SERCOM4_SPI_BAUD (0x4200140C) /**< \brief (SERCOM4) SPI Baud Rate */ -#define REG_SERCOM4_SPI_INTENCLR (0x42001414) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ -#define REG_SERCOM4_SPI_INTENSET (0x42001416) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ -#define REG_SERCOM4_SPI_INTFLAG (0x42001418) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM4_SPI_STATUS (0x4200141A) /**< \brief (SERCOM4) SPI Status */ -#define REG_SERCOM4_SPI_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) SPI Synchronization Busy */ -#define REG_SERCOM4_SPI_ADDR (0x42001424) /**< \brief (SERCOM4) SPI Address */ -#define REG_SERCOM4_SPI_DATA (0x42001428) /**< \brief (SERCOM4) SPI Data */ -#define REG_SERCOM4_SPI_DBGCTRL (0x42001430) /**< \brief (SERCOM4) SPI Debug Control */ -#define REG_SERCOM4_USART_CTRLA (0x42001400) /**< \brief (SERCOM4) USART Control A */ -#define REG_SERCOM4_USART_CTRLB (0x42001404) /**< \brief (SERCOM4) USART Control B */ -#define REG_SERCOM4_USART_CTRLC (0x42001408) /**< \brief (SERCOM4) USART Control C */ -#define REG_SERCOM4_USART_BAUD (0x4200140C) /**< \brief (SERCOM4) USART Baud Rate */ -#define REG_SERCOM4_USART_RXPL (0x4200140E) /**< \brief (SERCOM4) USART Receive Pulse Length */ -#define REG_SERCOM4_USART_INTENCLR (0x42001414) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ -#define REG_SERCOM4_USART_INTENSET (0x42001416) /**< \brief (SERCOM4) USART Interrupt Enable Set */ -#define REG_SERCOM4_USART_INTFLAG (0x42001418) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM4_USART_STATUS (0x4200141A) /**< \brief (SERCOM4) USART Status */ -#define REG_SERCOM4_USART_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) USART Synchronization Busy */ -#define REG_SERCOM4_USART_RXERRCNT (0x42001420) /**< \brief (SERCOM4) USART Receive Error Count */ -#define REG_SERCOM4_USART_DATA (0x42001428) /**< \brief (SERCOM4) USART Data */ -#define REG_SERCOM4_USART_DBGCTRL (0x42001430) /**< \brief (SERCOM4) USART Debug Control */ -#else -#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CM Control A */ -#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CM Control B */ -#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200140CUL) /**< \brief (SERCOM4) I2CM Baud Rate */ -#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ -#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ -#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CM Status */ -#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CM Synchronization Busy */ -#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CM Address */ -#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CM Data */ -#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) I2CM Debug Control */ -#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CS Control A */ -#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CS Control B */ -#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ -#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ -#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CS Status */ -#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CS Synchronization Busy */ -#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CS Address */ -#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CS Data */ -#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) SPI Control A */ -#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) SPI Control B */ -#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM4) SPI Baud Rate */ -#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ -#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ -#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) SPI Status */ -#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) SPI Synchronization Busy */ -#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) SPI Address */ -#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001428UL) /**< \brief (SERCOM4) SPI Data */ -#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) SPI Debug Control */ -#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) USART Control A */ -#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) USART Control B */ -#define REG_SERCOM4_USART_CTRLC (*(RwReg *)0x42001408UL) /**< \brief (SERCOM4) USART Control C */ -#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200140CUL) /**< \brief (SERCOM4) USART Baud Rate */ -#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */ -#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ -#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */ -#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) USART Status */ -#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) USART Synchronization Busy */ -#define REG_SERCOM4_USART_RXERRCNT (*(RoReg8 *)0x42001420UL) /**< \brief (SERCOM4) USART Receive Error Count */ -#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001428UL) /**< \brief (SERCOM4) USART Data */ -#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM4 peripheral ========== */ -#define SERCOM4_DMAC_ID_RX 10 // Index of DMA RX trigger -#define SERCOM4_DMAC_ID_TX 11 // Index of DMA TX trigger -#define SERCOM4_GCLK_ID_CORE 20 -#define SERCOM4_GCLK_ID_SLOW 15 -#define SERCOM4_INT_MSB 6 -#define SERCOM4_PMSB 3 -#define SERCOM4_SPI 1 // SPI mode implemented? -#define SERCOM4_TWIM 1 // TWI Master mode implemented? -#define SERCOM4_TWIS 1 // TWI Slave mode implemented? -#define SERCOM4_TWI_HSMODE 0 // TWI HighSpeed mode implemented? -#define SERCOM4_USART 1 // USART mode implemented? -#define SERCOM4_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM4_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM4_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM4_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom5.h b/watch-library/include/instance/sercom5.h deleted file mode 100644 index 93214cf3..00000000 --- a/watch-library/include/instance/sercom5.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM5 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM5_INSTANCE_ -#define _SAML22_SERCOM5_INSTANCE_ - -/* ========== Register definition for SERCOM5 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM5_I2CM_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CM Control A */ -#define REG_SERCOM5_I2CM_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CM Control B */ -#define REG_SERCOM5_I2CM_BAUD (0x4200180C) /**< \brief (SERCOM5) I2CM Baud Rate */ -#define REG_SERCOM5_I2CM_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ -#define REG_SERCOM5_I2CM_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ -#define REG_SERCOM5_I2CM_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CM_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CM Status */ -#define REG_SERCOM5_I2CM_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CM Synchronization Busy */ -#define REG_SERCOM5_I2CM_ADDR (0x42001824) /**< \brief (SERCOM5) I2CM Address */ -#define REG_SERCOM5_I2CM_DATA (0x42001828) /**< \brief (SERCOM5) I2CM Data */ -#define REG_SERCOM5_I2CM_DBGCTRL (0x42001830) /**< \brief (SERCOM5) I2CM Debug Control */ -#define REG_SERCOM5_I2CS_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CS Control A */ -#define REG_SERCOM5_I2CS_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CS Control B */ -#define REG_SERCOM5_I2CS_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ -#define REG_SERCOM5_I2CS_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ -#define REG_SERCOM5_I2CS_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CS_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CS Status */ -#define REG_SERCOM5_I2CS_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CS Synchronization Busy */ -#define REG_SERCOM5_I2CS_ADDR (0x42001824) /**< \brief (SERCOM5) I2CS Address */ -#define REG_SERCOM5_I2CS_DATA (0x42001828) /**< \brief (SERCOM5) I2CS Data */ -#define REG_SERCOM5_SPI_CTRLA (0x42001800) /**< \brief (SERCOM5) SPI Control A */ -#define REG_SERCOM5_SPI_CTRLB (0x42001804) /**< \brief (SERCOM5) SPI Control B */ -#define REG_SERCOM5_SPI_BAUD (0x4200180C) /**< \brief (SERCOM5) SPI Baud Rate */ -#define REG_SERCOM5_SPI_INTENCLR (0x42001814) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ -#define REG_SERCOM5_SPI_INTENSET (0x42001816) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ -#define REG_SERCOM5_SPI_INTFLAG (0x42001818) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM5_SPI_STATUS (0x4200181A) /**< \brief (SERCOM5) SPI Status */ -#define REG_SERCOM5_SPI_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) SPI Synchronization Busy */ -#define REG_SERCOM5_SPI_ADDR (0x42001824) /**< \brief (SERCOM5) SPI Address */ -#define REG_SERCOM5_SPI_DATA (0x42001828) /**< \brief (SERCOM5) SPI Data */ -#define REG_SERCOM5_SPI_DBGCTRL (0x42001830) /**< \brief (SERCOM5) SPI Debug Control */ -#define REG_SERCOM5_USART_CTRLA (0x42001800) /**< \brief (SERCOM5) USART Control A */ -#define REG_SERCOM5_USART_CTRLB (0x42001804) /**< \brief (SERCOM5) USART Control B */ -#define REG_SERCOM5_USART_CTRLC (0x42001808) /**< \brief (SERCOM5) USART Control C */ -#define REG_SERCOM5_USART_BAUD (0x4200180C) /**< \brief (SERCOM5) USART Baud Rate */ -#define REG_SERCOM5_USART_RXPL (0x4200180E) /**< \brief (SERCOM5) USART Receive Pulse Length */ -#define REG_SERCOM5_USART_INTENCLR (0x42001814) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ -#define REG_SERCOM5_USART_INTENSET (0x42001816) /**< \brief (SERCOM5) USART Interrupt Enable Set */ -#define REG_SERCOM5_USART_INTFLAG (0x42001818) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM5_USART_STATUS (0x4200181A) /**< \brief (SERCOM5) USART Status */ -#define REG_SERCOM5_USART_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) USART Synchronization Busy */ -#define REG_SERCOM5_USART_RXERRCNT (0x42001820) /**< \brief (SERCOM5) USART Receive Error Count */ -#define REG_SERCOM5_USART_DATA (0x42001828) /**< \brief (SERCOM5) USART Data */ -#define REG_SERCOM5_USART_DBGCTRL (0x42001830) /**< \brief (SERCOM5) USART Debug Control */ -#else -#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CM Control A */ -#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CM Control B */ -#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4200180CUL) /**< \brief (SERCOM5) I2CM Baud Rate */ -#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ -#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ -#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CM Status */ -#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CM Synchronization Busy */ -#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CM Address */ -#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CM Data */ -#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) I2CM Debug Control */ -#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CS Control A */ -#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CS Control B */ -#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ -#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ -#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CS Status */ -#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CS Synchronization Busy */ -#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CS Address */ -#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CS Data */ -#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) SPI Control A */ -#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) SPI Control B */ -#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM5) SPI Baud Rate */ -#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ -#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ -#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) SPI Status */ -#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) SPI Synchronization Busy */ -#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) SPI Address */ -#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001828UL) /**< \brief (SERCOM5) SPI Data */ -#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) SPI Debug Control */ -#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) USART Control A */ -#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) USART Control B */ -#define REG_SERCOM5_USART_CTRLC (*(RwReg *)0x42001808UL) /**< \brief (SERCOM5) USART Control C */ -#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4200180CUL) /**< \brief (SERCOM5) USART Baud Rate */ -#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */ -#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ -#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */ -#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) USART Status */ -#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) USART Synchronization Busy */ -#define REG_SERCOM5_USART_RXERRCNT (*(RoReg8 *)0x42001820UL) /**< \brief (SERCOM5) USART Receive Error Count */ -#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001828UL) /**< \brief (SERCOM5) USART Data */ -#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM5 peripheral ========== */ -#define SERCOM5_DMAC_ID_RX 12 // Index of DMA RX trigger -#define SERCOM5_DMAC_ID_TX 13 // Index of DMA TX trigger -#define SERCOM5_GCLK_ID_CORE 21 -#define SERCOM5_GCLK_ID_SLOW 15 -#define SERCOM5_INT_MSB 3 -#define SERCOM5_PMSB 3 -#define SERCOM5_SPI 1 // SPI mode implemented? -#define SERCOM5_TWIM 1 // TWI Master mode implemented? -#define SERCOM5_TWIS 1 // TWI Slave mode implemented? -#define SERCOM5_TWI_HSMODE 1 // TWI HighSpeed mode implemented? -#define SERCOM5_USART 1 // USART mode implemented? -#define SERCOM5_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM5_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM5_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM5_INSTANCE_ */ diff --git a/watch-library/include/instance/slcd.h b/watch-library/include/instance/slcd.h deleted file mode 100644 index c4785831..00000000 --- a/watch-library/include/instance/slcd.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief Instance description for SLCD - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SLCD_INSTANCE_ -#define _SAML22_SLCD_INSTANCE_ - -/* ========== Register definition for SLCD peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SLCD_CTRLA (0x42003C00) /**< \brief (SLCD) Control A */ -#define REG_SLCD_CTRLB (0x42003C04) /**< \brief (SLCD) Control B */ -#define REG_SLCD_CTRLC (0x42003C06) /**< \brief (SLCD) Control C */ -#define REG_SLCD_CTRLD (0x42003C08) /**< \brief (SLCD) Control D */ -#define REG_SLCD_EVCTRL (0x42003C0C) /**< \brief (SLCD) Event Control */ -#define REG_SLCD_INTENCLR (0x42003C0D) /**< \brief (SLCD) Interrupt Enable Clear */ -#define REG_SLCD_INTENSET (0x42003C0E) /**< \brief (SLCD) Interrupt Enable Set */ -#define REG_SLCD_INTFLAG (0x42003C0F) /**< \brief (SLCD) Interrupt Flag Status and Clear */ -#define REG_SLCD_STATUS (0x42003C10) /**< \brief (SLCD) Status */ -#define REG_SLCD_SYNCBUSY (0x42003C14) /**< \brief (SLCD) Synchronization Busy */ -#define REG_SLCD_FC0 (0x42003C18) /**< \brief (SLCD) Frame Counter 0 Configuration */ -#define REG_SLCD_FC1 (0x42003C19) /**< \brief (SLCD) Frame Counter 1 Configuration */ -#define REG_SLCD_FC2 (0x42003C1A) /**< \brief (SLCD) Frame Counter 2 Configuration */ -#define REG_SLCD_LPENL (0x42003C1C) /**< \brief (SLCD) LCD Pin Enable Low */ -#define REG_SLCD_LPENH (0x42003C20) /**< \brief (SLCD) LCD Pin Enable High */ -#define REG_SLCD_SDATAL0 (0x42003C24) /**< \brief (SLCD) Segments Data Low for COM0 Line */ -#define REG_SLCD_SDATAH0 (0x42003C28) /**< \brief (SLCD) Segments Data High for COM0 Line */ -#define REG_SLCD_SDATAL1 (0x42003C2C) /**< \brief (SLCD) Segments Data Low for COM1 Line */ -#define REG_SLCD_SDATAH1 (0x42003C30) /**< \brief (SLCD) Segments Data High for COM1 Line */ -#define REG_SLCD_SDATAL2 (0x42003C34) /**< \brief (SLCD) Segments Data Low for COM2 Line */ -#define REG_SLCD_SDATAH2 (0x42003C38) /**< \brief (SLCD) Segments Data High for COM2 Line */ -#define REG_SLCD_SDATAL3 (0x42003C3C) /**< \brief (SLCD) Segments Data Low for COM3 Line */ -#define REG_SLCD_SDATAH3 (0x42003C40) /**< \brief (SLCD) Segments Data High for COM3 Line */ -#define REG_SLCD_SDATAL4 (0x42003C44) /**< \brief (SLCD) Segments Data Low for COM4 Line */ -#define REG_SLCD_SDATAH4 (0x42003C48) /**< \brief (SLCD) Segments Data High for COM4 Line */ -#define REG_SLCD_SDATAL5 (0x42003C4C) /**< \brief (SLCD) Segments Data Low for COM5 Line */ -#define REG_SLCD_SDATAH5 (0x42003C50) /**< \brief (SLCD) Segments Data High for COM5 Line */ -#define REG_SLCD_SDATAL6 (0x42003C54) /**< \brief (SLCD) Segments Data Low for COM6 Line */ -#define REG_SLCD_SDATAH6 (0x42003C58) /**< \brief (SLCD) Segments Data High for COM6 Line */ -#define REG_SLCD_SDATAL7 (0x42003C5C) /**< \brief (SLCD) Segments Data Low for COM7 Line */ -#define REG_SLCD_SDATAH7 (0x42003C60) /**< \brief (SLCD) Segments Data High for COM7 Line */ -#define REG_SLCD_ISDATA (0x42003C64) /**< \brief (SLCD) Indirect Segments Data Access */ -#define REG_SLCD_BCFG (0x42003C68) /**< \brief (SLCD) Blink Configuration */ -#define REG_SLCD_CSRCFG (0x42003C6C) /**< \brief (SLCD) Circular Shift Register Configuration */ -#define REG_SLCD_CMCFG (0x42003C70) /**< \brief (SLCD) Character Mapping Configuration */ -#define REG_SLCD_ACMCFG (0x42003C74) /**< \brief (SLCD) Automated Character Mapping Configuration */ -#define REG_SLCD_ABMCFG (0x42003C78) /**< \brief (SLCD) Automated Bit Mapping Configuration */ -#define REG_SLCD_CMDATA (0x42003C7C) /**< \brief (SLCD) Character Mapping Segments Data */ -#define REG_SLCD_CMDMASK (0x42003C80) /**< \brief (SLCD) Character Mapping Segments Data Mask */ -#define REG_SLCD_CMINDEX (0x42003C84) /**< \brief (SLCD) Character Mapping SEG/COM Index */ -#else -#define REG_SLCD_CTRLA (*(RwReg *)0x42003C00UL) /**< \brief (SLCD) Control A */ -#define REG_SLCD_CTRLB (*(RwReg16*)0x42003C04UL) /**< \brief (SLCD) Control B */ -#define REG_SLCD_CTRLC (*(RwReg16*)0x42003C06UL) /**< \brief (SLCD) Control C */ -#define REG_SLCD_CTRLD (*(RwReg8 *)0x42003C08UL) /**< \brief (SLCD) Control D */ -#define REG_SLCD_EVCTRL (*(RwReg8 *)0x42003C0CUL) /**< \brief (SLCD) Event Control */ -#define REG_SLCD_INTENCLR (*(RwReg8 *)0x42003C0DUL) /**< \brief (SLCD) Interrupt Enable Clear */ -#define REG_SLCD_INTENSET (*(RwReg8 *)0x42003C0EUL) /**< \brief (SLCD) Interrupt Enable Set */ -#define REG_SLCD_INTFLAG (*(RwReg8 *)0x42003C0FUL) /**< \brief (SLCD) Interrupt Flag Status and Clear */ -#define REG_SLCD_STATUS (*(RoReg8 *)0x42003C10UL) /**< \brief (SLCD) Status */ -#define REG_SLCD_SYNCBUSY (*(RoReg *)0x42003C14UL) /**< \brief (SLCD) Synchronization Busy */ -#define REG_SLCD_FC0 (*(RwReg8 *)0x42003C18UL) /**< \brief (SLCD) Frame Counter 0 Configuration */ -#define REG_SLCD_FC1 (*(RwReg8 *)0x42003C19UL) /**< \brief (SLCD) Frame Counter 1 Configuration */ -#define REG_SLCD_FC2 (*(RwReg8 *)0x42003C1AUL) /**< \brief (SLCD) Frame Counter 2 Configuration */ -#define REG_SLCD_LPENL (*(RwReg *)0x42003C1CUL) /**< \brief (SLCD) LCD Pin Enable Low */ -#define REG_SLCD_LPENH (*(RwReg *)0x42003C20UL) /**< \brief (SLCD) LCD Pin Enable High */ -#define REG_SLCD_SDATAL0 (*(RwReg *)0x42003C24UL) /**< \brief (SLCD) Segments Data Low for COM0 Line */ -#define REG_SLCD_SDATAH0 (*(RwReg *)0x42003C28UL) /**< \brief (SLCD) Segments Data High for COM0 Line */ -#define REG_SLCD_SDATAL1 (*(RwReg *)0x42003C2CUL) /**< \brief (SLCD) Segments Data Low for COM1 Line */ -#define REG_SLCD_SDATAH1 (*(RwReg *)0x42003C30UL) /**< \brief (SLCD) Segments Data High for COM1 Line */ -#define REG_SLCD_SDATAL2 (*(RwReg *)0x42003C34UL) /**< \brief (SLCD) Segments Data Low for COM2 Line */ -#define REG_SLCD_SDATAH2 (*(RwReg *)0x42003C38UL) /**< \brief (SLCD) Segments Data High for COM2 Line */ -#define REG_SLCD_SDATAL3 (*(RwReg *)0x42003C3CUL) /**< \brief (SLCD) Segments Data Low for COM3 Line */ -#define REG_SLCD_SDATAH3 (*(RwReg *)0x42003C40UL) /**< \brief (SLCD) Segments Data High for COM3 Line */ -#define REG_SLCD_SDATAL4 (*(RwReg *)0x42003C44UL) /**< \brief (SLCD) Segments Data Low for COM4 Line */ -#define REG_SLCD_SDATAH4 (*(RwReg *)0x42003C48UL) /**< \brief (SLCD) Segments Data High for COM4 Line */ -#define REG_SLCD_SDATAL5 (*(RwReg *)0x42003C4CUL) /**< \brief (SLCD) Segments Data Low for COM5 Line */ -#define REG_SLCD_SDATAH5 (*(RwReg *)0x42003C50UL) /**< \brief (SLCD) Segments Data High for COM5 Line */ -#define REG_SLCD_SDATAL6 (*(RwReg *)0x42003C54UL) /**< \brief (SLCD) Segments Data Low for COM6 Line */ -#define REG_SLCD_SDATAH6 (*(RwReg *)0x42003C58UL) /**< \brief (SLCD) Segments Data High for COM6 Line */ -#define REG_SLCD_SDATAL7 (*(RwReg *)0x42003C5CUL) /**< \brief (SLCD) Segments Data Low for COM7 Line */ -#define REG_SLCD_SDATAH7 (*(RwReg *)0x42003C60UL) /**< \brief (SLCD) Segments Data High for COM7 Line */ -#define REG_SLCD_ISDATA (*(WoReg *)0x42003C64UL) /**< \brief (SLCD) Indirect Segments Data Access */ -#define REG_SLCD_BCFG (*(RwReg *)0x42003C68UL) /**< \brief (SLCD) Blink Configuration */ -#define REG_SLCD_CSRCFG (*(RwReg *)0x42003C6CUL) /**< \brief (SLCD) Circular Shift Register Configuration */ -#define REG_SLCD_CMCFG (*(RwReg8 *)0x42003C70UL) /**< \brief (SLCD) Character Mapping Configuration */ -#define REG_SLCD_ACMCFG (*(RwReg *)0x42003C74UL) /**< \brief (SLCD) Automated Character Mapping Configuration */ -#define REG_SLCD_ABMCFG (*(RwReg8 *)0x42003C78UL) /**< \brief (SLCD) Automated Bit Mapping Configuration */ -#define REG_SLCD_CMDATA (*(WoReg *)0x42003C7CUL) /**< \brief (SLCD) Character Mapping Segments Data */ -#define REG_SLCD_CMDMASK (*(RwReg *)0x42003C80UL) /**< \brief (SLCD) Character Mapping Segments Data Mask */ -#define REG_SLCD_CMINDEX (*(RwReg16*)0x42003C84UL) /**< \brief (SLCD) Character Mapping SEG/COM Index */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SLCD peripheral ========== */ -#define SLCD_DMAC_ID_ABMDRDY 34 -#define SLCD_DMAC_ID_ACMDRDY 33 -#define SLCD_DMAC_ID_DMU 32 -#define SLCD_MAX_COM 8 // Max number of COM lines (4 or 8) -#define SLCD_MAX_SEG 44 // Max number of SEG lines (24 or 44) -#define SLCD_NB_LP 52 // Number of LCD pins ([28..64] or [48..64]) - -#endif /* _SAML22_SLCD_INSTANCE_ */ diff --git a/watch-library/include/instance/supc.h b/watch-library/include/instance/supc.h deleted file mode 100644 index 0800c5f3..00000000 --- a/watch-library/include/instance/supc.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * \file - * - * \brief Instance description for SUPC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SUPC_INSTANCE_ -#define _SAML22_SUPC_INSTANCE_ - -/* ========== Register definition for SUPC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SUPC_INTENCLR (0x40001800) /**< \brief (SUPC) Interrupt Enable Clear */ -#define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ -#define REG_SUPC_INTFLAG (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */ -#define REG_SUPC_STATUS (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */ -#define REG_SUPC_BOD33 (0x40001810) /**< \brief (SUPC) BOD33 Control */ -#define REG_SUPC_BOD12 (0x40001814) /**< \brief (SUPC) BOD12 Control */ -#define REG_SUPC_VREG (0x40001818) /**< \brief (SUPC) VREG Control */ -#define REG_SUPC_VREF (0x4000181C) /**< \brief (SUPC) VREF Control */ -#define REG_SUPC_BBPS (0x40001820) /**< \brief (SUPC) Battery Backup Power Switch */ -#define REG_SUPC_BKOUT (0x40001824) /**< \brief (SUPC) Backup Output Control */ -#define REG_SUPC_BKIN (0x40001828) /**< \brief (SUPC) Backup Input Control */ -#else -#define REG_SUPC_INTENCLR (*(RwReg *)0x40001800UL) /**< \brief (SUPC) Interrupt Enable Clear */ -#define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Set */ -#define REG_SUPC_INTFLAG (*(RwReg *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */ -#define REG_SUPC_STATUS (*(RoReg *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */ -#define REG_SUPC_BOD33 (*(RwReg *)0x40001810UL) /**< \brief (SUPC) BOD33 Control */ -#define REG_SUPC_BOD12 (*(RwReg *)0x40001814UL) /**< \brief (SUPC) BOD12 Control */ -#define REG_SUPC_VREG (*(RwReg *)0x40001818UL) /**< \brief (SUPC) VREG Control */ -#define REG_SUPC_VREF (*(RwReg *)0x4000181CUL) /**< \brief (SUPC) VREF Control */ -#define REG_SUPC_BBPS (*(RwReg *)0x40001820UL) /**< \brief (SUPC) Battery Backup Power Switch */ -#define REG_SUPC_BKOUT (*(RwReg *)0x40001824UL) /**< \brief (SUPC) Backup Output Control */ -#define REG_SUPC_BKIN (*(RoReg *)0x40001828UL) /**< \brief (SUPC) Backup Input Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SUPC peripheral ========== */ -#define SUPC_BOD12_CALIB_MSB 5 -#define SUPC_BOD33_CALIB_MSB 5 -#define SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number - -#endif /* _SAML22_SUPC_INSTANCE_ */ diff --git a/watch-library/include/instance/tc0.h b/watch-library/include/instance/tc0.h deleted file mode 100644 index a50b87e9..00000000 --- a/watch-library/include/instance/tc0.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC0 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TC0_INSTANCE_ -#define _SAML22_TC0_INSTANCE_ - -/* ========== Register definition for TC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC0_CTRLA (0x42002000) /**< \brief (TC0) Control A */ -#define REG_TC0_CTRLBCLR (0x42002004) /**< \brief (TC0) Control B Clear */ -#define REG_TC0_CTRLBSET (0x42002005) /**< \brief (TC0) Control B Set */ -#define REG_TC0_EVCTRL (0x42002006) /**< \brief (TC0) Event Control */ -#define REG_TC0_INTENCLR (0x42002008) /**< \brief (TC0) Interrupt Enable Clear */ -#define REG_TC0_INTENSET (0x42002009) /**< \brief (TC0) Interrupt Enable Set */ -#define REG_TC0_INTFLAG (0x4200200A) /**< \brief (TC0) Interrupt Flag Status and Clear */ -#define REG_TC0_STATUS (0x4200200B) /**< \brief (TC0) Status */ -#define REG_TC0_WAVE (0x4200200C) /**< \brief (TC0) Waveform Generation Control */ -#define REG_TC0_DRVCTRL (0x4200200D) /**< \brief (TC0) Control C */ -#define REG_TC0_DBGCTRL (0x4200200F) /**< \brief (TC0) Debug Control */ -#define REG_TC0_SYNCBUSY (0x42002010) /**< \brief (TC0) Synchronization Status */ -#define REG_TC0_COUNT16_COUNT (0x42002014) /**< \brief (TC0) COUNT16 Count */ -#define REG_TC0_COUNT16_CC0 (0x4200201C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ -#define REG_TC0_COUNT16_CC1 (0x4200201E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ -#define REG_TC0_COUNT16_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT16_CCBUF1 (0x42002032) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT32_COUNT (0x42002014) /**< \brief (TC0) COUNT32 Count */ -#define REG_TC0_COUNT32_CC0 (0x4200201C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ -#define REG_TC0_COUNT32_CC1 (0x42002020) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ -#define REG_TC0_COUNT32_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT32_CCBUF1 (0x42002034) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT8_COUNT (0x42002014) /**< \brief (TC0) COUNT8 Count */ -#define REG_TC0_COUNT8_PER (0x4200201B) /**< \brief (TC0) COUNT8 Period */ -#define REG_TC0_COUNT8_CC0 (0x4200201C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ -#define REG_TC0_COUNT8_CC1 (0x4200201D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ -#define REG_TC0_COUNT8_PERBUF (0x4200202F) /**< \brief (TC0) COUNT8 Period Buffer */ -#define REG_TC0_COUNT8_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT8_CCBUF1 (0x42002031) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC0_CTRLA (*(RwReg *)0x42002000UL) /**< \brief (TC0) Control A */ -#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004UL) /**< \brief (TC0) Control B Clear */ -#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005UL) /**< \brief (TC0) Control B Set */ -#define REG_TC0_EVCTRL (*(RwReg16*)0x42002006UL) /**< \brief (TC0) Event Control */ -#define REG_TC0_INTENCLR (*(RwReg8 *)0x42002008UL) /**< \brief (TC0) Interrupt Enable Clear */ -#define REG_TC0_INTENSET (*(RwReg8 *)0x42002009UL) /**< \brief (TC0) Interrupt Enable Set */ -#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */ -#define REG_TC0_STATUS (*(RwReg8 *)0x4200200BUL) /**< \brief (TC0) Status */ -#define REG_TC0_WAVE (*(RwReg8 *)0x4200200CUL) /**< \brief (TC0) Waveform Generation Control */ -#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200200DUL) /**< \brief (TC0) Control C */ -#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200200FUL) /**< \brief (TC0) Debug Control */ -#define REG_TC0_SYNCBUSY (*(RoReg *)0x42002010UL) /**< \brief (TC0) Synchronization Status */ -#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002014UL) /**< \brief (TC0) COUNT16 Count */ -#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4200201CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ -#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ -#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x42002030UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x42002032UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002014UL) /**< \brief (TC0) COUNT32 Count */ -#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200201CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ -#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42002020UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ -#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42002030UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42002034UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002014UL) /**< \brief (TC0) COUNT8 Count */ -#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4200201BUL) /**< \brief (TC0) COUNT8 Period */ -#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4200201CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ -#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4200201DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ -#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4200202FUL) /**< \brief (TC0) COUNT8 Period Buffer */ -#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x42002030UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x42002031UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC0 peripheral ========== */ -#define TC0_CC_NUM 2 -#define TC0_DMAC_ID_MC_0 20 -#define TC0_DMAC_ID_MC_1 21 -#define TC0_DMAC_ID_MC_LSB 20 -#define TC0_DMAC_ID_MC_MSB 21 -#define TC0_DMAC_ID_MC_SIZE 2 -#define TC0_DMAC_ID_OVF 19 // Indexes of DMA Overflow trigger -#define TC0_EXT 0 -#define TC0_GCLK_ID 23 -#define TC0_MASTER 1 -#define TC0_OW_NUM 2 - -#endif /* _SAML22_TC0_INSTANCE_ */ diff --git a/watch-library/include/instance/tc1.h b/watch-library/include/instance/tc1.h deleted file mode 100644 index 9acada8a..00000000 --- a/watch-library/include/instance/tc1.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC1 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TC1_INSTANCE_ -#define _SAML22_TC1_INSTANCE_ - -/* ========== Register definition for TC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC1_CTRLA (0x42002400) /**< \brief (TC1) Control A */ -#define REG_TC1_CTRLBCLR (0x42002404) /**< \brief (TC1) Control B Clear */ -#define REG_TC1_CTRLBSET (0x42002405) /**< \brief (TC1) Control B Set */ -#define REG_TC1_EVCTRL (0x42002406) /**< \brief (TC1) Event Control */ -#define REG_TC1_INTENCLR (0x42002408) /**< \brief (TC1) Interrupt Enable Clear */ -#define REG_TC1_INTENSET (0x42002409) /**< \brief (TC1) Interrupt Enable Set */ -#define REG_TC1_INTFLAG (0x4200240A) /**< \brief (TC1) Interrupt Flag Status and Clear */ -#define REG_TC1_STATUS (0x4200240B) /**< \brief (TC1) Status */ -#define REG_TC1_WAVE (0x4200240C) /**< \brief (TC1) Waveform Generation Control */ -#define REG_TC1_DRVCTRL (0x4200240D) /**< \brief (TC1) Control C */ -#define REG_TC1_DBGCTRL (0x4200240F) /**< \brief (TC1) Debug Control */ -#define REG_TC1_SYNCBUSY (0x42002410) /**< \brief (TC1) Synchronization Status */ -#define REG_TC1_COUNT16_COUNT (0x42002414) /**< \brief (TC1) COUNT16 Count */ -#define REG_TC1_COUNT16_CC0 (0x4200241C) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ -#define REG_TC1_COUNT16_CC1 (0x4200241E) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ -#define REG_TC1_COUNT16_CCBUF0 (0x42002430) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT16_CCBUF1 (0x42002432) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT32_COUNT (0x42002414) /**< \brief (TC1) COUNT32 Count */ -#define REG_TC1_COUNT32_CC0 (0x4200241C) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ -#define REG_TC1_COUNT32_CC1 (0x42002420) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ -#define REG_TC1_COUNT32_CCBUF0 (0x42002430) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT32_CCBUF1 (0x42002434) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT8_COUNT (0x42002414) /**< \brief (TC1) COUNT8 Count */ -#define REG_TC1_COUNT8_PER (0x4200241B) /**< \brief (TC1) COUNT8 Period */ -#define REG_TC1_COUNT8_CC0 (0x4200241C) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ -#define REG_TC1_COUNT8_CC1 (0x4200241D) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ -#define REG_TC1_COUNT8_PERBUF (0x4200242F) /**< \brief (TC1) COUNT8 Period Buffer */ -#define REG_TC1_COUNT8_CCBUF0 (0x42002430) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT8_CCBUF1 (0x42002431) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC1_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (TC1) Control A */ -#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42002404UL) /**< \brief (TC1) Control B Clear */ -#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42002405UL) /**< \brief (TC1) Control B Set */ -#define REG_TC1_EVCTRL (*(RwReg16*)0x42002406UL) /**< \brief (TC1) Event Control */ -#define REG_TC1_INTENCLR (*(RwReg8 *)0x42002408UL) /**< \brief (TC1) Interrupt Enable Clear */ -#define REG_TC1_INTENSET (*(RwReg8 *)0x42002409UL) /**< \brief (TC1) Interrupt Enable Set */ -#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200240AUL) /**< \brief (TC1) Interrupt Flag Status and Clear */ -#define REG_TC1_STATUS (*(RwReg8 *)0x4200240BUL) /**< \brief (TC1) Status */ -#define REG_TC1_WAVE (*(RwReg8 *)0x4200240CUL) /**< \brief (TC1) Waveform Generation Control */ -#define REG_TC1_DRVCTRL (*(RwReg8 *)0x4200240DUL) /**< \brief (TC1) Control C */ -#define REG_TC1_DBGCTRL (*(RwReg8 *)0x4200240FUL) /**< \brief (TC1) Debug Control */ -#define REG_TC1_SYNCBUSY (*(RoReg *)0x42002410UL) /**< \brief (TC1) Synchronization Status */ -#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42002414UL) /**< \brief (TC1) COUNT16 Count */ -#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x4200241CUL) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ -#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200241EUL) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ -#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x42002430UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x42002432UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42002414UL) /**< \brief (TC1) COUNT32 Count */ -#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x4200241CUL) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ -#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x42002420UL) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ -#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x42002430UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x42002434UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42002414UL) /**< \brief (TC1) COUNT8 Count */ -#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x4200241BUL) /**< \brief (TC1) COUNT8 Period */ -#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x4200241CUL) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ -#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x4200241DUL) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ -#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x4200242FUL) /**< \brief (TC1) COUNT8 Period Buffer */ -#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x42002430UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x42002431UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC1 peripheral ========== */ -#define TC1_CC_NUM 2 -#define TC1_DMAC_ID_MC_0 23 -#define TC1_DMAC_ID_MC_1 24 -#define TC1_DMAC_ID_MC_LSB 23 -#define TC1_DMAC_ID_MC_MSB 24 -#define TC1_DMAC_ID_MC_SIZE 2 -#define TC1_DMAC_ID_OVF 22 // Indexes of DMA Overflow trigger -#define TC1_EXT 0 -#define TC1_GCLK_ID 23 -#define TC1_MASTER 0 -#define TC1_OW_NUM 2 - -#endif /* _SAML22_TC1_INSTANCE_ */ diff --git a/watch-library/include/instance/tc2.h b/watch-library/include/instance/tc2.h deleted file mode 100644 index 13b8fb2a..00000000 --- a/watch-library/include/instance/tc2.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC2 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TC2_INSTANCE_ -#define _SAML22_TC2_INSTANCE_ - -/* ========== Register definition for TC2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC2_CTRLA (0x42002800) /**< \brief (TC2) Control A */ -#define REG_TC2_CTRLBCLR (0x42002804) /**< \brief (TC2) Control B Clear */ -#define REG_TC2_CTRLBSET (0x42002805) /**< \brief (TC2) Control B Set */ -#define REG_TC2_EVCTRL (0x42002806) /**< \brief (TC2) Event Control */ -#define REG_TC2_INTENCLR (0x42002808) /**< \brief (TC2) Interrupt Enable Clear */ -#define REG_TC2_INTENSET (0x42002809) /**< \brief (TC2) Interrupt Enable Set */ -#define REG_TC2_INTFLAG (0x4200280A) /**< \brief (TC2) Interrupt Flag Status and Clear */ -#define REG_TC2_STATUS (0x4200280B) /**< \brief (TC2) Status */ -#define REG_TC2_WAVE (0x4200280C) /**< \brief (TC2) Waveform Generation Control */ -#define REG_TC2_DRVCTRL (0x4200280D) /**< \brief (TC2) Control C */ -#define REG_TC2_DBGCTRL (0x4200280F) /**< \brief (TC2) Debug Control */ -#define REG_TC2_SYNCBUSY (0x42002810) /**< \brief (TC2) Synchronization Status */ -#define REG_TC2_COUNT16_COUNT (0x42002814) /**< \brief (TC2) COUNT16 Count */ -#define REG_TC2_COUNT16_CC0 (0x4200281C) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ -#define REG_TC2_COUNT16_CC1 (0x4200281E) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ -#define REG_TC2_COUNT16_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT16_CCBUF1 (0x42002832) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT32_COUNT (0x42002814) /**< \brief (TC2) COUNT32 Count */ -#define REG_TC2_COUNT32_CC0 (0x4200281C) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ -#define REG_TC2_COUNT32_CC1 (0x42002820) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ -#define REG_TC2_COUNT32_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT32_CCBUF1 (0x42002834) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT8_COUNT (0x42002814) /**< \brief (TC2) COUNT8 Count */ -#define REG_TC2_COUNT8_PER (0x4200281B) /**< \brief (TC2) COUNT8 Period */ -#define REG_TC2_COUNT8_CC0 (0x4200281C) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ -#define REG_TC2_COUNT8_CC1 (0x4200281D) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ -#define REG_TC2_COUNT8_PERBUF (0x4200282F) /**< \brief (TC2) COUNT8 Period Buffer */ -#define REG_TC2_COUNT8_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT8_CCBUF1 (0x42002831) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC2_CTRLA (*(RwReg *)0x42002800UL) /**< \brief (TC2) Control A */ -#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804UL) /**< \brief (TC2) Control B Clear */ -#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805UL) /**< \brief (TC2) Control B Set */ -#define REG_TC2_EVCTRL (*(RwReg16*)0x42002806UL) /**< \brief (TC2) Event Control */ -#define REG_TC2_INTENCLR (*(RwReg8 *)0x42002808UL) /**< \brief (TC2) Interrupt Enable Clear */ -#define REG_TC2_INTENSET (*(RwReg8 *)0x42002809UL) /**< \brief (TC2) Interrupt Enable Set */ -#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280AUL) /**< \brief (TC2) Interrupt Flag Status and Clear */ -#define REG_TC2_STATUS (*(RwReg8 *)0x4200280BUL) /**< \brief (TC2) Status */ -#define REG_TC2_WAVE (*(RwReg8 *)0x4200280CUL) /**< \brief (TC2) Waveform Generation Control */ -#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200280DUL) /**< \brief (TC2) Control C */ -#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200280FUL) /**< \brief (TC2) Debug Control */ -#define REG_TC2_SYNCBUSY (*(RoReg *)0x42002810UL) /**< \brief (TC2) Synchronization Status */ -#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42002814UL) /**< \brief (TC2) COUNT16 Count */ -#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4200281CUL) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ -#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200281EUL) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ -#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x42002830UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x42002832UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42002814UL) /**< \brief (TC2) COUNT32 Count */ -#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4200281CUL) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ -#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42002820UL) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ -#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x42002830UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x42002834UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002814UL) /**< \brief (TC2) COUNT8 Count */ -#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4200281BUL) /**< \brief (TC2) COUNT8 Period */ -#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4200281CUL) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ -#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4200281DUL) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ -#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4200282FUL) /**< \brief (TC2) COUNT8 Period Buffer */ -#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x42002830UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x42002831UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC2 peripheral ========== */ -#define TC2_CC_NUM 2 -#define TC2_DMAC_ID_MC_0 26 -#define TC2_DMAC_ID_MC_1 27 -#define TC2_DMAC_ID_MC_LSB 26 -#define TC2_DMAC_ID_MC_MSB 27 -#define TC2_DMAC_ID_MC_SIZE 2 -#define TC2_DMAC_ID_OVF 25 // Indexes of DMA Overflow trigger -#define TC2_EXT 0 -#define TC2_GCLK_ID 24 -#define TC2_MASTER 1 -#define TC2_OW_NUM 2 - -#endif /* _SAML22_TC2_INSTANCE_ */ diff --git a/watch-library/include/instance/tc3.h b/watch-library/include/instance/tc3.h deleted file mode 100644 index 7555903a..00000000 --- a/watch-library/include/instance/tc3.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC3 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TC3_INSTANCE_ -#define _SAML22_TC3_INSTANCE_ - -/* ========== Register definition for TC3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC3_CTRLA (0x42002C00) /**< \brief (TC3) Control A */ -#define REG_TC3_CTRLBCLR (0x42002C04) /**< \brief (TC3) Control B Clear */ -#define REG_TC3_CTRLBSET (0x42002C05) /**< \brief (TC3) Control B Set */ -#define REG_TC3_EVCTRL (0x42002C06) /**< \brief (TC3) Event Control */ -#define REG_TC3_INTENCLR (0x42002C08) /**< \brief (TC3) Interrupt Enable Clear */ -#define REG_TC3_INTENSET (0x42002C09) /**< \brief (TC3) Interrupt Enable Set */ -#define REG_TC3_INTFLAG (0x42002C0A) /**< \brief (TC3) Interrupt Flag Status and Clear */ -#define REG_TC3_STATUS (0x42002C0B) /**< \brief (TC3) Status */ -#define REG_TC3_WAVE (0x42002C0C) /**< \brief (TC3) Waveform Generation Control */ -#define REG_TC3_DRVCTRL (0x42002C0D) /**< \brief (TC3) Control C */ -#define REG_TC3_DBGCTRL (0x42002C0F) /**< \brief (TC3) Debug Control */ -#define REG_TC3_SYNCBUSY (0x42002C10) /**< \brief (TC3) Synchronization Status */ -#define REG_TC3_COUNT16_COUNT (0x42002C14) /**< \brief (TC3) COUNT16 Count */ -#define REG_TC3_COUNT16_CC0 (0x42002C1C) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ -#define REG_TC3_COUNT16_CC1 (0x42002C1E) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ -#define REG_TC3_COUNT16_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT16_CCBUF1 (0x42002C32) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT32_COUNT (0x42002C14) /**< \brief (TC3) COUNT32 Count */ -#define REG_TC3_COUNT32_CC0 (0x42002C1C) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ -#define REG_TC3_COUNT32_CC1 (0x42002C20) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ -#define REG_TC3_COUNT32_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT32_CCBUF1 (0x42002C34) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT8_COUNT (0x42002C14) /**< \brief (TC3) COUNT8 Count */ -#define REG_TC3_COUNT8_PER (0x42002C1B) /**< \brief (TC3) COUNT8 Period */ -#define REG_TC3_COUNT8_CC0 (0x42002C1C) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ -#define REG_TC3_COUNT8_CC1 (0x42002C1D) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ -#define REG_TC3_COUNT8_PERBUF (0x42002C2F) /**< \brief (TC3) COUNT8 Period Buffer */ -#define REG_TC3_COUNT8_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT8_CCBUF1 (0x42002C31) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC3_CTRLA (*(RwReg *)0x42002C00UL) /**< \brief (TC3) Control A */ -#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TC3) Control B Clear */ -#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TC3) Control B Set */ -#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C06UL) /**< \brief (TC3) Event Control */ -#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C08UL) /**< \brief (TC3) Interrupt Enable Clear */ -#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C09UL) /**< \brief (TC3) Interrupt Enable Set */ -#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0AUL) /**< \brief (TC3) Interrupt Flag Status and Clear */ -#define REG_TC3_STATUS (*(RwReg8 *)0x42002C0BUL) /**< \brief (TC3) Status */ -#define REG_TC3_WAVE (*(RwReg8 *)0x42002C0CUL) /**< \brief (TC3) Waveform Generation Control */ -#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42002C0DUL) /**< \brief (TC3) Control C */ -#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C0FUL) /**< \brief (TC3) Debug Control */ -#define REG_TC3_SYNCBUSY (*(RoReg *)0x42002C10UL) /**< \brief (TC3) Synchronization Status */ -#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C14UL) /**< \brief (TC3) COUNT16 Count */ -#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C1CUL) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ -#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1EUL) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ -#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42002C30UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42002C32UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C14UL) /**< \brief (TC3) COUNT32 Count */ -#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C1CUL) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ -#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C20UL) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ -#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42002C30UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42002C34UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C14UL) /**< \brief (TC3) COUNT8 Count */ -#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C1BUL) /**< \brief (TC3) COUNT8 Period */ -#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C1CUL) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ -#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C1DUL) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ -#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42002C2FUL) /**< \brief (TC3) COUNT8 Period Buffer */ -#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42002C30UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42002C31UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC3 peripheral ========== */ -#define TC3_CC_NUM 2 -#define TC3_DMAC_ID_MC_0 29 -#define TC3_DMAC_ID_MC_1 30 -#define TC3_DMAC_ID_MC_LSB 29 -#define TC3_DMAC_ID_MC_MSB 30 -#define TC3_DMAC_ID_MC_SIZE 2 -#define TC3_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger -#define TC3_EXT 0 -#define TC3_GCLK_ID 24 -#define TC3_MASTER 0 -#define TC3_OW_NUM 2 - -#endif /* _SAML22_TC3_INSTANCE_ */ diff --git a/watch-library/include/instance/tcc0.h b/watch-library/include/instance/tcc0.h deleted file mode 100644 index e5567d45..00000000 --- a/watch-library/include/instance/tcc0.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Instance description for TCC0 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TCC0_INSTANCE_ -#define _SAML22_TCC0_INSTANCE_ - -/* ========== Register definition for TCC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TCC0_CTRLA (0x42001C00) /**< \brief (TCC0) Control A */ -#define REG_TCC0_CTRLBCLR (0x42001C04) /**< \brief (TCC0) Control B Clear */ -#define REG_TCC0_CTRLBSET (0x42001C05) /**< \brief (TCC0) Control B Set */ -#define REG_TCC0_SYNCBUSY (0x42001C08) /**< \brief (TCC0) Synchronization Busy */ -#define REG_TCC0_FCTRLA (0x42001C0C) /**< \brief (TCC0) Recoverable Fault A Configuration */ -#define REG_TCC0_FCTRLB (0x42001C10) /**< \brief (TCC0) Recoverable Fault B Configuration */ -#define REG_TCC0_WEXCTRL (0x42001C14) /**< \brief (TCC0) Waveform Extension Configuration */ -#define REG_TCC0_DRVCTRL (0x42001C18) /**< \brief (TCC0) Driver Control */ -#define REG_TCC0_DBGCTRL (0x42001C1E) /**< \brief (TCC0) Debug Control */ -#define REG_TCC0_EVCTRL (0x42001C20) /**< \brief (TCC0) Event Control */ -#define REG_TCC0_INTENCLR (0x42001C24) /**< \brief (TCC0) Interrupt Enable Clear */ -#define REG_TCC0_INTENSET (0x42001C28) /**< \brief (TCC0) Interrupt Enable Set */ -#define REG_TCC0_INTFLAG (0x42001C2C) /**< \brief (TCC0) Interrupt Flag Status and Clear */ -#define REG_TCC0_STATUS (0x42001C30) /**< \brief (TCC0) Status */ -#define REG_TCC0_COUNT (0x42001C34) /**< \brief (TCC0) Count */ -#define REG_TCC0_PATT (0x42001C38) /**< \brief (TCC0) Pattern */ -#define REG_TCC0_WAVE (0x42001C3C) /**< \brief (TCC0) Waveform Control */ -#define REG_TCC0_PER (0x42001C40) /**< \brief (TCC0) Period */ -#define REG_TCC0_CC0 (0x42001C44) /**< \brief (TCC0) Compare and Capture 0 */ -#define REG_TCC0_CC1 (0x42001C48) /**< \brief (TCC0) Compare and Capture 1 */ -#define REG_TCC0_CC2 (0x42001C4C) /**< \brief (TCC0) Compare and Capture 2 */ -#define REG_TCC0_CC3 (0x42001C50) /**< \brief (TCC0) Compare and Capture 3 */ -#define REG_TCC0_PATTBUF (0x42001C64) /**< \brief (TCC0) Pattern Buffer */ -#define REG_TCC0_PERBUF (0x42001C6C) /**< \brief (TCC0) Period Buffer */ -#define REG_TCC0_CCBUF0 (0x42001C70) /**< \brief (TCC0) Compare and Capture Buffer 0 */ -#define REG_TCC0_CCBUF1 (0x42001C74) /**< \brief (TCC0) Compare and Capture Buffer 1 */ -#define REG_TCC0_CCBUF2 (0x42001C78) /**< \brief (TCC0) Compare and Capture Buffer 2 */ -#define REG_TCC0_CCBUF3 (0x42001C7C) /**< \brief (TCC0) Compare and Capture Buffer 3 */ -#else -#define REG_TCC0_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (TCC0) Control A */ -#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42001C04UL) /**< \brief (TCC0) Control B Clear */ -#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42001C05UL) /**< \brief (TCC0) Control B Set */ -#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42001C08UL) /**< \brief (TCC0) Synchronization Busy */ -#define REG_TCC0_FCTRLA (*(RwReg *)0x42001C0CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */ -#define REG_TCC0_FCTRLB (*(RwReg *)0x42001C10UL) /**< \brief (TCC0) Recoverable Fault B Configuration */ -#define REG_TCC0_WEXCTRL (*(RwReg *)0x42001C14UL) /**< \brief (TCC0) Waveform Extension Configuration */ -#define REG_TCC0_DRVCTRL (*(RwReg *)0x42001C18UL) /**< \brief (TCC0) Driver Control */ -#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x42001C1EUL) /**< \brief (TCC0) Debug Control */ -#define REG_TCC0_EVCTRL (*(RwReg *)0x42001C20UL) /**< \brief (TCC0) Event Control */ -#define REG_TCC0_INTENCLR (*(RwReg *)0x42001C24UL) /**< \brief (TCC0) Interrupt Enable Clear */ -#define REG_TCC0_INTENSET (*(RwReg *)0x42001C28UL) /**< \brief (TCC0) Interrupt Enable Set */ -#define REG_TCC0_INTFLAG (*(RwReg *)0x42001C2CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */ -#define REG_TCC0_STATUS (*(RwReg *)0x42001C30UL) /**< \brief (TCC0) Status */ -#define REG_TCC0_COUNT (*(RwReg *)0x42001C34UL) /**< \brief (TCC0) Count */ -#define REG_TCC0_PATT (*(RwReg16*)0x42001C38UL) /**< \brief (TCC0) Pattern */ -#define REG_TCC0_WAVE (*(RwReg *)0x42001C3CUL) /**< \brief (TCC0) Waveform Control */ -#define REG_TCC0_PER (*(RwReg *)0x42001C40UL) /**< \brief (TCC0) Period */ -#define REG_TCC0_CC0 (*(RwReg *)0x42001C44UL) /**< \brief (TCC0) Compare and Capture 0 */ -#define REG_TCC0_CC1 (*(RwReg *)0x42001C48UL) /**< \brief (TCC0) Compare and Capture 1 */ -#define REG_TCC0_CC2 (*(RwReg *)0x42001C4CUL) /**< \brief (TCC0) Compare and Capture 2 */ -#define REG_TCC0_CC3 (*(RwReg *)0x42001C50UL) /**< \brief (TCC0) Compare and Capture 3 */ -#define REG_TCC0_PATTBUF (*(RwReg16*)0x42001C64UL) /**< \brief (TCC0) Pattern Buffer */ -#define REG_TCC0_PERBUF (*(RwReg *)0x42001C6CUL) /**< \brief (TCC0) Period Buffer */ -#define REG_TCC0_CCBUF0 (*(RwReg *)0x42001C70UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */ -#define REG_TCC0_CCBUF1 (*(RwReg *)0x42001C74UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */ -#define REG_TCC0_CCBUF2 (*(RwReg *)0x42001C78UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */ -#define REG_TCC0_CCBUF3 (*(RwReg *)0x42001C7CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TCC0 peripheral ========== */ -#define TCC0_CC_NUM 4 // Number of Compare/Capture units -#define TCC0_DITHERING 1 // Dithering feature implemented -#define TCC0_DMAC_ID_MC_0 15 -#define TCC0_DMAC_ID_MC_1 16 -#define TCC0_DMAC_ID_MC_2 17 -#define TCC0_DMAC_ID_MC_3 18 -#define TCC0_DMAC_ID_MC_LSB 15 -#define TCC0_DMAC_ID_MC_MSB 18 -#define TCC0_DMAC_ID_MC_SIZE 4 -#define TCC0_DMAC_ID_OVF 14 // DMA overflow/underflow/retrigger trigger -#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented -#define TCC0_EXT 31 // Coding of implemented extended features -#define TCC0_GCLK_ID 22 // Index of Generic Clock -#define TCC0_OTMX 1 // Output Matrix feature implemented -#define TCC0_OW_NUM 8 // Number of Output Waveforms -#define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 -#define TCC0_SWAP 1 // DTI outputs swap feature implemented -#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave - -#endif /* _SAML22_TCC0_INSTANCE_ */ diff --git a/watch-library/include/instance/trng.h b/watch-library/include/instance/trng.h deleted file mode 100644 index 0f80f00a..00000000 --- a/watch-library/include/instance/trng.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief Instance description for TRNG - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TRNG_INSTANCE_ -#define _SAML22_TRNG_INSTANCE_ - -/* ========== Register definition for TRNG peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TRNG_CTRLA (0x42004400) /**< \brief (TRNG) Control A */ -#define REG_TRNG_EVCTRL (0x42004404) /**< \brief (TRNG) Event Control */ -#define REG_TRNG_INTENCLR (0x42004408) /**< \brief (TRNG) Interrupt Enable Clear */ -#define REG_TRNG_INTENSET (0x42004409) /**< \brief (TRNG) Interrupt Enable Set */ -#define REG_TRNG_INTFLAG (0x4200440A) /**< \brief (TRNG) Interrupt Flag Status and Clear */ -#define REG_TRNG_DATA (0x42004420) /**< \brief (TRNG) Output Data */ -#else -#define REG_TRNG_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (TRNG) Control A */ -#define REG_TRNG_EVCTRL (*(RwReg8 *)0x42004404UL) /**< \brief (TRNG) Event Control */ -#define REG_TRNG_INTENCLR (*(RwReg8 *)0x42004408UL) /**< \brief (TRNG) Interrupt Enable Clear */ -#define REG_TRNG_INTENSET (*(RwReg8 *)0x42004409UL) /**< \brief (TRNG) Interrupt Enable Set */ -#define REG_TRNG_INTFLAG (*(RwReg8 *)0x4200440AUL) /**< \brief (TRNG) Interrupt Flag Status and Clear */ -#define REG_TRNG_DATA (*(RoReg *)0x42004420UL) /**< \brief (TRNG) Output Data */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAML22_TRNG_INSTANCE_ */ diff --git a/watch-library/include/instance/usb.h b/watch-library/include/instance/usb.h deleted file mode 100644 index 9060d62e..00000000 --- a/watch-library/include/instance/usb.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - * \file - * - * \brief Instance description for USB - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_USB_INSTANCE_ -#define _SAML22_USB_INSTANCE_ - -/* ========== Register definition for USB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USB_CTRLA (0x41000000) /**< \brief (USB) Control A */ -#define REG_USB_SYNCBUSY (0x41000002) /**< \brief (USB) Synchronization Busy */ -#define REG_USB_QOSCTRL (0x41000003) /**< \brief (USB) USB Quality Of Service */ -#define REG_USB_FSMSTATUS (0x4100000D) /**< \brief (USB) Finite State Machine Status */ -#define REG_USB_DESCADD (0x41000024) /**< \brief (USB) Descriptor Address */ -#define REG_USB_PADCAL (0x41000028) /**< \brief (USB) USB PAD Calibration */ -#define REG_USB_DEVICE_CTRLB (0x41000008) /**< \brief (USB) DEVICE Control B */ -#define REG_USB_DEVICE_DADD (0x4100000A) /**< \brief (USB) DEVICE Device Address */ -#define REG_USB_DEVICE_STATUS (0x4100000C) /**< \brief (USB) DEVICE Status */ -#define REG_USB_DEVICE_FNUM (0x41000010) /**< \brief (USB) DEVICE Device Frame Number */ -#define REG_USB_DEVICE_INTENCLR (0x41000014) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ -#define REG_USB_DEVICE_INTENSET (0x41000018) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ -#define REG_USB_DEVICE_INTFLAG (0x4100001C) /**< \brief (USB) DEVICE Device Interrupt Flag */ -#define REG_USB_DEVICE_EPINTSMRY (0x41000020) /**< \brief (USB) DEVICE End Point Interrupt Summary */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41000100) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41000104) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41000105) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41000106) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41000107) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41000108) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41000109) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41000120) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41000124) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41000125) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41000126) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41000127) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41000128) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41000129) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41000140) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41000144) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41000145) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41000146) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41000147) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41000148) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41000149) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41000160) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41000164) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41000165) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41000166) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41000167) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41000168) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41000169) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41000180) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41000184) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41000185) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41000186) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41000187) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41000188) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41000189) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410001A0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410001A4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410001A5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410001A6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410001A7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410001A8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410001A9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410001C0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410001C4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410001C5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410001C6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410001C7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410001C8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410001C9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410001E0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410001E4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410001E5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410001E6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410001E7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410001E8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410001E9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ -#else -#define REG_USB_CTRLA (*(RwReg8 *)0x41000000UL) /**< \brief (USB) Control A */ -#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41000002UL) /**< \brief (USB) Synchronization Busy */ -#define REG_USB_QOSCTRL (*(RwReg8 *)0x41000003UL) /**< \brief (USB) USB Quality Of Service */ -#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100000DUL) /**< \brief (USB) Finite State Machine Status */ -#define REG_USB_DESCADD (*(RwReg *)0x41000024UL) /**< \brief (USB) Descriptor Address */ -#define REG_USB_PADCAL (*(RwReg16*)0x41000028UL) /**< \brief (USB) USB PAD Calibration */ -#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41000008UL) /**< \brief (USB) DEVICE Control B */ -#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) DEVICE Device Address */ -#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100000CUL) /**< \brief (USB) DEVICE Status */ -#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41000010UL) /**< \brief (USB) DEVICE Device Frame Number */ -#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41000014UL) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ -#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41000018UL) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ -#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100001CUL) /**< \brief (USB) DEVICE Device Interrupt Flag */ -#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41000020UL) /**< \brief (USB) DEVICE End Point Interrupt Summary */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41000104UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41000105UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41000124UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41000125UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41000129UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41000140UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41000144UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41000145UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41000147UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41000148UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41000149UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41000160UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41000164UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41000165UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41000167UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41000168UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41000169UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41000180UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41000184UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41000185UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41000187UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41000188UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41000189UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410001A0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410001A4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410001A5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410001A7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410001A8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410001A9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410001C0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410001C4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410001C5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410001C7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410001C8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410001C9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410001E0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410001E4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410001E5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410001E6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410001E7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410001E8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410001E9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for USB peripheral ========== */ -#define USB_EPT_NBR 8 // Number of USB end points (obsolete) -#define USB_EPT_NUM 8 // Number of USB end points -#define USB_GCLK_ID 6 // Index of Generic Clock -#define USB_PIPE_NUM 0 // Number of USB pipes - -#endif /* _SAML22_USB_INSTANCE_ */ diff --git a/watch-library/include/instance/wdt.h b/watch-library/include/instance/wdt.h deleted file mode 100644 index 2bb1d1ba..00000000 --- a/watch-library/include/instance/wdt.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief Instance description for WDT - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_WDT_INSTANCE_ -#define _SAML22_WDT_INSTANCE_ - -/* ========== Register definition for WDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ -#else -#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAML22_WDT_INSTANCE_ */ diff --git a/watch-library/include/pio/saml22g16a.h b/watch-library/include/pio/saml22g16a.h deleted file mode 100644 index 2c4d2ee5..00000000 --- a/watch-library/include/pio/saml22g16a.h +++ /dev/null @@ -1,947 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML22G16A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22G16A_PIO_ -#define _SAML22G16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 _L_(7) -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) -#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT _L_(7) -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 _L_(7) -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 _L_(7) -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 _L_(7) -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) -#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 _L_(7) -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 _L_(7) -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 _L_(7) -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 _L_(7) -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 _L_(7) -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 _L_(7) -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 _L_(7) -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) -/* ========== PORT definition for RTC peripheral ========== */ -#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ -#define MUX_PB02G_RTC_IN1 _L_(6) -#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) -#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) -#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ -#define MUX_PA02G_RTC_IN2 _L_(6) -#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) -#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM _L_(6) -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (_UL_(1) << 24) -#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP _L_(6) -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (_UL_(1) << 25) -#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ -#define MUX_PB22G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) -#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ -#define MUX_PA20C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) -#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ -#define MUX_PA21C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) -#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ -#define MUX_PA22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) -#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) -#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ -#define MUX_PA23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) -#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) -#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) -#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) -#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) -#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) -#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) -#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) -#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) -#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) -#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) -#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) -#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) -#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) -#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) -#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) -#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) -#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) -#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) -#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ -#define MUX_PB02C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) -#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) -#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) -#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) -#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) -#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ -#define MUX_PB03C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) -#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) -#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) -#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) -#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) -#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ -#define MUX_PA24F_TCC0_WO0 _L_(5) -#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) -#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 _L_(4) -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 _L_(4) -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ -#define MUX_PA25F_TCC0_WO1 _L_(5) -#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) -#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 _L_(4) -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 _L_(4) -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 _L_(5) -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ -#define MUX_PB22F_TCC0_WO2 _L_(5) -#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) -#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 _L_(5) -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ -#define MUX_PB23F_TCC0_WO3 _L_(5) -#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) -#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 _L_(5) -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) -#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 _L_(5) -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 _L_(5) -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 _L_(5) -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) -#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ -#define MUX_PA27F_TCC0_WO5 _L_(5) -#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) -#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 _L_(5) -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) -#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 _L_(5) -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 _L_(5) -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) -#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 _L_(5) -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 _L_(4) -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 _L_(4) -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 _L_(4) -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 _L_(4) -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 _L_(4) -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) -#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 _L_(4) -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 _L_(4) -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 _L_(4) -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) -#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 _L_(4) -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 _L_(4) -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) -#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 _L_(4) -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 _L_(4) -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) -#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 _L_(4) -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 _L_(1) -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 _L_(1) -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 _L_(1) -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 _L_(1) -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 _L_(1) -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 _L_(1) -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 _L_(1) -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 _L_(1) -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) -#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 _L_(1) -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) -#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 _L_(1) -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) -#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ -#define MUX_PA03B_ADC_VREFA _L_(1) -#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) -#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) -#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ -#define MUX_PA02B_ADC_VREFB _L_(1) -#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) -#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_AC_AIN0 _L_(1) -#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) -#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_AC_AIN1 _L_(1) -#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) -#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) -#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 _L_(7) -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 _L_(7) -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 _L_(7) -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 _L_(7) -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for SLCD peripheral ========== */ -#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ -#define MUX_PB08B_SLCD_LP2 _L_(1) -#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) -#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) -#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ -#define MUX_PB09B_SLCD_LP3 _L_(1) -#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) -#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) -#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ -#define MUX_PA04B_SLCD_LP4 _L_(1) -#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) -#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) -#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ -#define MUX_PA05B_SLCD_LP5 _L_(1) -#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) -#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) -#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ -#define MUX_PA06B_SLCD_LP6 _L_(1) -#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) -#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) -#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ -#define MUX_PA07B_SLCD_LP7 _L_(1) -#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) -#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) -#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ -#define MUX_PA08B_SLCD_LP11 _L_(1) -#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) -#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) -#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ -#define MUX_PA09B_SLCD_LP12 _L_(1) -#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) -#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) -#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ -#define MUX_PA10B_SLCD_LP13 _L_(1) -#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) -#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) -#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ -#define MUX_PA11B_SLCD_LP14 _L_(1) -#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) -#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) -#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ -#define MUX_PB11B_SLCD_LP21 _L_(1) -#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) -#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) -#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ -#define MUX_PA12B_SLCD_LP28 _L_(1) -#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) -#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) -#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ -#define MUX_PA13B_SLCD_LP29 _L_(1) -#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) -#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) -#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ -#define MUX_PA14B_SLCD_LP30 _L_(1) -#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) -#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) -#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ -#define MUX_PA15B_SLCD_LP31 _L_(1) -#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) -#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) -#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ -#define MUX_PA16B_SLCD_LP32 _L_(1) -#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) -#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) -#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ -#define MUX_PA17B_SLCD_LP33 _L_(1) -#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) -#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) -#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ -#define MUX_PA18B_SLCD_LP34 _L_(1) -#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) -#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) -#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ -#define MUX_PA19B_SLCD_LP35 _L_(1) -#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) -#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) -#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ -#define MUX_PA20B_SLCD_LP48 _L_(1) -#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) -#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) -#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ -#define MUX_PA21B_SLCD_LP49 _L_(1) -#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) -#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) -#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ -#define MUX_PA22B_SLCD_LP50 _L_(1) -#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) -#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) -#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ -#define MUX_PA23B_SLCD_LP51 _L_(1) -#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) -#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 _L_(8) -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 _L_(8) -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 _L_(8) -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 _L_(8) -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 _L_(8) -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) -#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 _L_(8) -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 _L_(8) -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) -#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 _L_(8) -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 _L_(8) -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 _L_(8) -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 _L_(8) -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 _L_(8) -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) -#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 _L_(8) -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) -#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 _L_(8) -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 _L_(8) -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) -#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 _L_(8) -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 _L_(8) -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 _L_(8) -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 _L_(8) -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 _L_(8) -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 _L_(8) -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 _L_(8) -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 _L_(8) -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 _L_(8) -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) - -#endif /* _SAML22G16A_PIO_ */ diff --git a/watch-library/include/pio/saml22g17a.h b/watch-library/include/pio/saml22g17a.h deleted file mode 100644 index 582cf91f..00000000 --- a/watch-library/include/pio/saml22g17a.h +++ /dev/null @@ -1,947 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML22G17A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22G17A_PIO_ -#define _SAML22G17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 _L_(7) -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) -#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT _L_(7) -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 _L_(7) -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 _L_(7) -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 _L_(7) -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) -#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 _L_(7) -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 _L_(7) -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 _L_(7) -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 _L_(7) -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 _L_(7) -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 _L_(7) -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 _L_(7) -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) -/* ========== PORT definition for RTC peripheral ========== */ -#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ -#define MUX_PB02G_RTC_IN1 _L_(6) -#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) -#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) -#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ -#define MUX_PA02G_RTC_IN2 _L_(6) -#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) -#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM _L_(6) -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (_UL_(1) << 24) -#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP _L_(6) -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (_UL_(1) << 25) -#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ -#define MUX_PB22G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) -#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ -#define MUX_PA20C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) -#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ -#define MUX_PA21C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) -#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ -#define MUX_PA22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) -#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) -#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ -#define MUX_PA23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) -#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) -#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) -#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) -#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) -#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) -#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) -#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) -#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) -#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) -#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) -#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) -#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) -#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) -#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) -#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) -#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) -#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) -#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) -#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ -#define MUX_PB02C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) -#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) -#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) -#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) -#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) -#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ -#define MUX_PB03C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) -#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) -#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) -#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) -#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) -#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ -#define MUX_PA24F_TCC0_WO0 _L_(5) -#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) -#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 _L_(4) -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 _L_(4) -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ -#define MUX_PA25F_TCC0_WO1 _L_(5) -#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) -#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 _L_(4) -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 _L_(4) -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 _L_(5) -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ -#define MUX_PB22F_TCC0_WO2 _L_(5) -#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) -#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 _L_(5) -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ -#define MUX_PB23F_TCC0_WO3 _L_(5) -#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) -#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 _L_(5) -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) -#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 _L_(5) -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 _L_(5) -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 _L_(5) -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) -#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ -#define MUX_PA27F_TCC0_WO5 _L_(5) -#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) -#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 _L_(5) -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) -#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 _L_(5) -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 _L_(5) -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) -#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 _L_(5) -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 _L_(4) -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 _L_(4) -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 _L_(4) -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 _L_(4) -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 _L_(4) -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) -#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 _L_(4) -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 _L_(4) -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 _L_(4) -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) -#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 _L_(4) -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 _L_(4) -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) -#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 _L_(4) -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 _L_(4) -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) -#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 _L_(4) -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 _L_(1) -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 _L_(1) -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 _L_(1) -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 _L_(1) -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 _L_(1) -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 _L_(1) -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 _L_(1) -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 _L_(1) -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) -#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 _L_(1) -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) -#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 _L_(1) -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) -#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ -#define MUX_PA03B_ADC_VREFA _L_(1) -#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) -#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) -#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ -#define MUX_PA02B_ADC_VREFB _L_(1) -#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) -#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_AC_AIN0 _L_(1) -#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) -#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_AC_AIN1 _L_(1) -#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) -#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) -#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 _L_(7) -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 _L_(7) -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 _L_(7) -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 _L_(7) -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for SLCD peripheral ========== */ -#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ -#define MUX_PB08B_SLCD_LP2 _L_(1) -#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) -#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) -#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ -#define MUX_PB09B_SLCD_LP3 _L_(1) -#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) -#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) -#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ -#define MUX_PA04B_SLCD_LP4 _L_(1) -#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) -#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) -#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ -#define MUX_PA05B_SLCD_LP5 _L_(1) -#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) -#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) -#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ -#define MUX_PA06B_SLCD_LP6 _L_(1) -#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) -#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) -#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ -#define MUX_PA07B_SLCD_LP7 _L_(1) -#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) -#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) -#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ -#define MUX_PA08B_SLCD_LP11 _L_(1) -#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) -#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) -#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ -#define MUX_PA09B_SLCD_LP12 _L_(1) -#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) -#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) -#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ -#define MUX_PA10B_SLCD_LP13 _L_(1) -#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) -#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) -#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ -#define MUX_PA11B_SLCD_LP14 _L_(1) -#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) -#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) -#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ -#define MUX_PB11B_SLCD_LP21 _L_(1) -#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) -#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) -#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ -#define MUX_PA12B_SLCD_LP28 _L_(1) -#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) -#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) -#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ -#define MUX_PA13B_SLCD_LP29 _L_(1) -#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) -#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) -#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ -#define MUX_PA14B_SLCD_LP30 _L_(1) -#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) -#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) -#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ -#define MUX_PA15B_SLCD_LP31 _L_(1) -#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) -#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) -#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ -#define MUX_PA16B_SLCD_LP32 _L_(1) -#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) -#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) -#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ -#define MUX_PA17B_SLCD_LP33 _L_(1) -#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) -#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) -#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ -#define MUX_PA18B_SLCD_LP34 _L_(1) -#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) -#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) -#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ -#define MUX_PA19B_SLCD_LP35 _L_(1) -#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) -#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) -#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ -#define MUX_PA20B_SLCD_LP48 _L_(1) -#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) -#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) -#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ -#define MUX_PA21B_SLCD_LP49 _L_(1) -#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) -#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) -#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ -#define MUX_PA22B_SLCD_LP50 _L_(1) -#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) -#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) -#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ -#define MUX_PA23B_SLCD_LP51 _L_(1) -#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) -#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 _L_(8) -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 _L_(8) -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 _L_(8) -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 _L_(8) -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 _L_(8) -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) -#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 _L_(8) -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 _L_(8) -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) -#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 _L_(8) -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 _L_(8) -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 _L_(8) -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 _L_(8) -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 _L_(8) -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) -#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 _L_(8) -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) -#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 _L_(8) -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 _L_(8) -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) -#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 _L_(8) -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 _L_(8) -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 _L_(8) -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 _L_(8) -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 _L_(8) -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 _L_(8) -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 _L_(8) -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 _L_(8) -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 _L_(8) -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) - -#endif /* _SAML22G17A_PIO_ */ diff --git a/watch-library/include/pio/saml22g18a.h b/watch-library/include/pio/saml22g18a.h deleted file mode 100644 index 3570da86..00000000 --- a/watch-library/include/pio/saml22g18a.h +++ /dev/null @@ -1,947 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML22G18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22G18A_PIO_ -#define _SAML22G18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 _L_(7) -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) -#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT _L_(7) -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 _L_(7) -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 _L_(7) -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 _L_(7) -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) -#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 _L_(7) -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 _L_(7) -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 _L_(7) -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 _L_(7) -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 _L_(7) -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 _L_(7) -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 _L_(7) -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) -/* ========== PORT definition for RTC peripheral ========== */ -#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ -#define MUX_PB02G_RTC_IN1 _L_(6) -#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) -#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) -#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ -#define MUX_PA02G_RTC_IN2 _L_(6) -#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) -#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM _L_(6) -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (_UL_(1) << 24) -#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP _L_(6) -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (_UL_(1) << 25) -#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ -#define MUX_PB22G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) -#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ -#define MUX_PA20C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) -#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ -#define MUX_PA21C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) -#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ -#define MUX_PA22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) -#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) -#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ -#define MUX_PA23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) -#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) -#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) -#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) -#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) -#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) -#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) -#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) -#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) -#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) -#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) -#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) -#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) -#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) -#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) -#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) -#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) -#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) -#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) -#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ -#define MUX_PB02C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) -#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) -#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) -#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) -#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) -#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ -#define MUX_PB03C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) -#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) -#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) -#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) -#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) -#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ -#define MUX_PA24F_TCC0_WO0 _L_(5) -#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) -#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 _L_(4) -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 _L_(4) -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ -#define MUX_PA25F_TCC0_WO1 _L_(5) -#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) -#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 _L_(4) -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 _L_(4) -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 _L_(5) -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ -#define MUX_PB22F_TCC0_WO2 _L_(5) -#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) -#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 _L_(5) -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ -#define MUX_PB23F_TCC0_WO3 _L_(5) -#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) -#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 _L_(5) -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) -#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 _L_(5) -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 _L_(5) -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 _L_(5) -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) -#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ -#define MUX_PA27F_TCC0_WO5 _L_(5) -#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) -#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 _L_(5) -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) -#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 _L_(5) -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 _L_(5) -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) -#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 _L_(5) -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 _L_(4) -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 _L_(4) -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 _L_(4) -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 _L_(4) -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 _L_(4) -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) -#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 _L_(4) -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 _L_(4) -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 _L_(4) -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) -#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 _L_(4) -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 _L_(4) -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) -#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 _L_(4) -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 _L_(4) -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) -#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 _L_(4) -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 _L_(1) -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 _L_(1) -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 _L_(1) -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 _L_(1) -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 _L_(1) -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 _L_(1) -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 _L_(1) -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 _L_(1) -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) -#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 _L_(1) -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) -#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 _L_(1) -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) -#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ -#define MUX_PA03B_ADC_VREFA _L_(1) -#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) -#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) -#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ -#define MUX_PA02B_ADC_VREFB _L_(1) -#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) -#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_AC_AIN0 _L_(1) -#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) -#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_AC_AIN1 _L_(1) -#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) -#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) -#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 _L_(7) -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 _L_(7) -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 _L_(7) -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 _L_(7) -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for SLCD peripheral ========== */ -#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ -#define MUX_PB08B_SLCD_LP2 _L_(1) -#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) -#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) -#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ -#define MUX_PB09B_SLCD_LP3 _L_(1) -#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) -#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) -#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ -#define MUX_PA04B_SLCD_LP4 _L_(1) -#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) -#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) -#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ -#define MUX_PA05B_SLCD_LP5 _L_(1) -#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) -#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) -#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ -#define MUX_PA06B_SLCD_LP6 _L_(1) -#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) -#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) -#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ -#define MUX_PA07B_SLCD_LP7 _L_(1) -#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) -#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) -#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ -#define MUX_PA08B_SLCD_LP11 _L_(1) -#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) -#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) -#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ -#define MUX_PA09B_SLCD_LP12 _L_(1) -#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) -#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) -#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ -#define MUX_PA10B_SLCD_LP13 _L_(1) -#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) -#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) -#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ -#define MUX_PA11B_SLCD_LP14 _L_(1) -#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) -#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) -#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ -#define MUX_PB11B_SLCD_LP21 _L_(1) -#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) -#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) -#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ -#define MUX_PA12B_SLCD_LP28 _L_(1) -#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) -#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) -#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ -#define MUX_PA13B_SLCD_LP29 _L_(1) -#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) -#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) -#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ -#define MUX_PA14B_SLCD_LP30 _L_(1) -#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) -#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) -#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ -#define MUX_PA15B_SLCD_LP31 _L_(1) -#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) -#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) -#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ -#define MUX_PA16B_SLCD_LP32 _L_(1) -#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) -#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) -#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ -#define MUX_PA17B_SLCD_LP33 _L_(1) -#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) -#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) -#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ -#define MUX_PA18B_SLCD_LP34 _L_(1) -#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) -#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) -#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ -#define MUX_PA19B_SLCD_LP35 _L_(1) -#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) -#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) -#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ -#define MUX_PA20B_SLCD_LP48 _L_(1) -#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) -#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) -#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ -#define MUX_PA21B_SLCD_LP49 _L_(1) -#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) -#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) -#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ -#define MUX_PA22B_SLCD_LP50 _L_(1) -#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) -#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) -#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ -#define MUX_PA23B_SLCD_LP51 _L_(1) -#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) -#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 _L_(8) -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 _L_(8) -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 _L_(8) -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 _L_(8) -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 _L_(8) -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) -#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 _L_(8) -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 _L_(8) -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) -#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 _L_(8) -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 _L_(8) -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 _L_(8) -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 _L_(8) -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 _L_(8) -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) -#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 _L_(8) -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) -#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 _L_(8) -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 _L_(8) -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) -#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 _L_(8) -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 _L_(8) -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 _L_(8) -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 _L_(8) -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 _L_(8) -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 _L_(8) -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 _L_(8) -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 _L_(8) -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 _L_(8) -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) - -#endif /* _SAML22G18A_PIO_ */ diff --git a/watch-library/include/pio/saml22j16a.h b/watch-library/include/pio/saml22j16a.h deleted file mode 100644 index 055a2b55..00000000 --- a/watch-library/include/pio/saml22j16a.h +++ /dev/null @@ -1,1265 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML22J16A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22J16A_PIO_ -#define _SAML22J16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ -#define MUX_PB01H_SUPC_OUT0 _L_(7) -#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) -#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) -#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 _L_(7) -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) -#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ -#define MUX_PB00H_SUPC_PSOK _L_(7) -#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) -#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) -#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT _L_(7) -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 _L_(7) -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 _L_(7) -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 _L_(7) -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 _L_(7) -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) -#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 _L_(7) -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 _L_(7) -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 _L_(7) -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 _L_(7) -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 _L_(7) -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 _L_(7) -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 _L_(7) -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 _L_(7) -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 _L_(7) -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 _L_(7) -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) -/* ========== PORT definition for RTC peripheral ========== */ -#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ -#define MUX_PB00G_RTC_IN0 _L_(6) -#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) -#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) -#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ -#define MUX_PB02G_RTC_IN1 _L_(6) -#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) -#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) -#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ -#define MUX_PA02G_RTC_IN2 _L_(6) -#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) -#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) -#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ -#define MUX_PB01F_RTC_IN2 _L_(5) -#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) -#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) -#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ -#define MUX_PB01G_RTC_OUT _L_(6) -#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) -#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM _L_(6) -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (_UL_(1) << 24) -#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP _L_(6) -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (_UL_(1) << 25) -#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ -#define MUX_PB22G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) -#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ -#define MUX_PA20C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) -#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ -#define MUX_PA21C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) -#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ -#define MUX_PA22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) -#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) -#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ -#define MUX_PA23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) -#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) -#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) -#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) -#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) -#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) -#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) -#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) -#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) -#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) -#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) -#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) -#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) -#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) -#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) -#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) -#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) -#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) -#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) -#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) -#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) -#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) -#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ -#define MUX_PB02C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) -#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) -#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) -#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) -#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) -#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) -#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ -#define MUX_PB03C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) -#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) -#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) -#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) -#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ -#define MUX_PB00C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) -#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) -#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) -#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) -#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) -#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) -#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ -#define MUX_PB01C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) -#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ -#define MUX_PA24F_TCC0_WO0 _L_(5) -#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) -#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 _L_(4) -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 _L_(4) -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 _L_(4) -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) -#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ -#define MUX_PA25F_TCC0_WO1 _L_(5) -#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) -#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 _L_(4) -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 _L_(4) -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 _L_(4) -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 _L_(5) -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ -#define MUX_PB22F_TCC0_WO2 _L_(5) -#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) -#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 _L_(5) -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ -#define MUX_PB23F_TCC0_WO3 _L_(5) -#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) -#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 _L_(5) -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) -#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 _L_(5) -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 _L_(5) -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 _L_(5) -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 _L_(5) -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) -#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ -#define MUX_PA27F_TCC0_WO5 _L_(5) -#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) -#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 _L_(5) -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 _L_(5) -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) -#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 _L_(5) -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) -#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 _L_(5) -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 _L_(5) -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) -#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 _L_(5) -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) -#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 _L_(5) -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 _L_(4) -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 _L_(4) -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC0_WO0 _L_(4) -#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) -#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 _L_(4) -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 _L_(4) -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC0_WO1 _L_(4) -#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) -#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 _L_(4) -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) -#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC1_WO0 _L_(4) -#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) -#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 _L_(4) -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 _L_(4) -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC1_WO1 _L_(4) -#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) -#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 _L_(4) -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC2_WO0 _L_(4) -#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) -#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 _L_(4) -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC2_WO1 _L_(4) -#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) -#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 _L_(4) -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC3_WO0 _L_(4) -#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) -#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 _L_(4) -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 _L_(4) -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC3_WO1 _L_(4) -#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) -#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 _L_(4) -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 _L_(1) -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 _L_(1) -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 _L_(1) -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 _L_(1) -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 _L_(1) -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 _L_(1) -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 _L_(1) -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 _L_(1) -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) -#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 _L_(1) -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) -#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 _L_(1) -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) -#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 _L_(1) -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) -#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 _L_(1) -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) -#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 _L_(1) -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) -#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 _L_(1) -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) -#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 _L_(1) -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) -#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 _L_(1) -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) -#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ -#define MUX_PA03B_ADC_VREFA _L_(1) -#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) -#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) -#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ -#define MUX_PA02B_ADC_VREFB _L_(1) -#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) -#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_AC_AIN0 _L_(1) -#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) -#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_AC_AIN1 _L_(1) -#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) -#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) -#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ -#define MUX_PB04B_AC_AIN2 _L_(1) -#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) -#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) -#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ -#define MUX_PB05B_AC_AIN3 _L_(1) -#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) -#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) -#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 _L_(7) -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 _L_(7) -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 _L_(7) -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 _L_(7) -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for SLCD peripheral ========== */ -#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ -#define MUX_PB06B_SLCD_LP0 _L_(1) -#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) -#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) -#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ -#define MUX_PB07B_SLCD_LP1 _L_(1) -#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) -#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) -#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ -#define MUX_PB08B_SLCD_LP2 _L_(1) -#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) -#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) -#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ -#define MUX_PB09B_SLCD_LP3 _L_(1) -#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) -#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) -#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ -#define MUX_PA04B_SLCD_LP4 _L_(1) -#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) -#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) -#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ -#define MUX_PA05B_SLCD_LP5 _L_(1) -#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) -#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) -#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ -#define MUX_PA06B_SLCD_LP6 _L_(1) -#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) -#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) -#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ -#define MUX_PA07B_SLCD_LP7 _L_(1) -#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) -#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) -#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ -#define MUX_PA08B_SLCD_LP11 _L_(1) -#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) -#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) -#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ -#define MUX_PA09B_SLCD_LP12 _L_(1) -#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) -#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) -#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ -#define MUX_PA10B_SLCD_LP13 _L_(1) -#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) -#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) -#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ -#define MUX_PA11B_SLCD_LP14 _L_(1) -#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) -#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) -#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ -#define MUX_PB11B_SLCD_LP21 _L_(1) -#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) -#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) -#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ -#define MUX_PB12B_SLCD_LP22 _L_(1) -#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) -#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) -#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ -#define MUX_PB13B_SLCD_LP23 _L_(1) -#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) -#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) -#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ -#define MUX_PB14B_SLCD_LP24 _L_(1) -#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) -#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) -#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ -#define MUX_PB15B_SLCD_LP25 _L_(1) -#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) -#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) -#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ -#define MUX_PA12B_SLCD_LP28 _L_(1) -#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) -#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) -#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ -#define MUX_PA13B_SLCD_LP29 _L_(1) -#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) -#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) -#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ -#define MUX_PA14B_SLCD_LP30 _L_(1) -#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) -#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) -#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ -#define MUX_PA15B_SLCD_LP31 _L_(1) -#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) -#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) -#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ -#define MUX_PA16B_SLCD_LP32 _L_(1) -#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) -#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) -#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ -#define MUX_PA17B_SLCD_LP33 _L_(1) -#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) -#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) -#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ -#define MUX_PA18B_SLCD_LP34 _L_(1) -#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) -#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) -#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ -#define MUX_PA19B_SLCD_LP35 _L_(1) -#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) -#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) -#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ -#define MUX_PB16B_SLCD_LP42 _L_(1) -#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) -#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) -#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ -#define MUX_PB17B_SLCD_LP43 _L_(1) -#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) -#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) -#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ -#define MUX_PA20B_SLCD_LP48 _L_(1) -#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) -#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) -#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ -#define MUX_PA21B_SLCD_LP49 _L_(1) -#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) -#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) -#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ -#define MUX_PA22B_SLCD_LP50 _L_(1) -#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) -#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) -#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ -#define MUX_PA23B_SLCD_LP51 _L_(1) -#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) -#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 _L_(8) -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 _L_(8) -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 _L_(8) -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 _L_(8) -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 _L_(8) -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ -#define MUX_PB00I_CCL_IN1 _L_(8) -#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) -#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 _L_(8) -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 _L_(8) -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ -#define MUX_PB01I_CCL_IN2 _L_(8) -#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) -#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 _L_(8) -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 _L_(8) -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 _L_(8) -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 _L_(8) -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 _L_(8) -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ -#define MUX_PB06I_CCL_IN6 _L_(8) -#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) -#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 _L_(8) -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ -#define MUX_PB07I_CCL_IN7 _L_(8) -#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) -#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 _L_(8) -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 _L_(8) -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ -#define MUX_PB14I_CCL_IN9 _L_(8) -#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) -#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) -#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ -#define MUX_PB15I_CCL_IN10 _L_(8) -#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) -#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) -#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ -#define MUX_PB16I_CCL_IN11 _L_(8) -#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) -#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 _L_(8) -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 _L_(8) -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 _L_(8) -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 _L_(8) -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 _L_(8) -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 _L_(8) -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 _L_(8) -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 _L_(8) -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 _L_(8) -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ -#define MUX_PB17I_CCL_OUT3 _L_(8) -#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) -#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) - -#endif /* _SAML22J16A_PIO_ */ diff --git a/watch-library/include/pio/saml22j17a.h b/watch-library/include/pio/saml22j17a.h deleted file mode 100644 index 9dae1d93..00000000 --- a/watch-library/include/pio/saml22j17a.h +++ /dev/null @@ -1,1265 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML22J17A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22J17A_PIO_ -#define _SAML22J17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ -#define MUX_PB01H_SUPC_OUT0 _L_(7) -#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) -#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) -#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 _L_(7) -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) -#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ -#define MUX_PB00H_SUPC_PSOK _L_(7) -#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) -#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) -#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT _L_(7) -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 _L_(7) -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 _L_(7) -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 _L_(7) -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 _L_(7) -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) -#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 _L_(7) -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 _L_(7) -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 _L_(7) -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 _L_(7) -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 _L_(7) -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 _L_(7) -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 _L_(7) -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 _L_(7) -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 _L_(7) -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 _L_(7) -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) -/* ========== PORT definition for RTC peripheral ========== */ -#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ -#define MUX_PB00G_RTC_IN0 _L_(6) -#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) -#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) -#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ -#define MUX_PB02G_RTC_IN1 _L_(6) -#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) -#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) -#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ -#define MUX_PA02G_RTC_IN2 _L_(6) -#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) -#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) -#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ -#define MUX_PB01F_RTC_IN2 _L_(5) -#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) -#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) -#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ -#define MUX_PB01G_RTC_OUT _L_(6) -#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) -#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM _L_(6) -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (_UL_(1) << 24) -#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP _L_(6) -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (_UL_(1) << 25) -#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ -#define MUX_PB22G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) -#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ -#define MUX_PA20C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) -#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ -#define MUX_PA21C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) -#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ -#define MUX_PA22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) -#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) -#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ -#define MUX_PA23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) -#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) -#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) -#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) -#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) -#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) -#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) -#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) -#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) -#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) -#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) -#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) -#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) -#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) -#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) -#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) -#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) -#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) -#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) -#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) -#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) -#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) -#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ -#define MUX_PB02C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) -#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) -#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) -#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) -#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) -#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) -#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ -#define MUX_PB03C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) -#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) -#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) -#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) -#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ -#define MUX_PB00C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) -#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) -#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) -#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) -#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) -#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) -#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ -#define MUX_PB01C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) -#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ -#define MUX_PA24F_TCC0_WO0 _L_(5) -#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) -#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 _L_(4) -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 _L_(4) -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 _L_(4) -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) -#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ -#define MUX_PA25F_TCC0_WO1 _L_(5) -#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) -#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 _L_(4) -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 _L_(4) -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 _L_(4) -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 _L_(5) -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ -#define MUX_PB22F_TCC0_WO2 _L_(5) -#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) -#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 _L_(5) -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ -#define MUX_PB23F_TCC0_WO3 _L_(5) -#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) -#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 _L_(5) -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) -#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 _L_(5) -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 _L_(5) -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 _L_(5) -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 _L_(5) -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) -#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ -#define MUX_PA27F_TCC0_WO5 _L_(5) -#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) -#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 _L_(5) -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 _L_(5) -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) -#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 _L_(5) -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) -#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 _L_(5) -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 _L_(5) -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) -#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 _L_(5) -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) -#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 _L_(5) -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 _L_(4) -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 _L_(4) -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC0_WO0 _L_(4) -#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) -#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 _L_(4) -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 _L_(4) -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC0_WO1 _L_(4) -#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) -#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 _L_(4) -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) -#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC1_WO0 _L_(4) -#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) -#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 _L_(4) -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 _L_(4) -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC1_WO1 _L_(4) -#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) -#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 _L_(4) -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC2_WO0 _L_(4) -#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) -#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 _L_(4) -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC2_WO1 _L_(4) -#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) -#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 _L_(4) -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC3_WO0 _L_(4) -#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) -#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 _L_(4) -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 _L_(4) -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC3_WO1 _L_(4) -#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) -#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 _L_(4) -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 _L_(1) -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 _L_(1) -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 _L_(1) -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 _L_(1) -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 _L_(1) -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 _L_(1) -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 _L_(1) -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 _L_(1) -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) -#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 _L_(1) -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) -#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 _L_(1) -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) -#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 _L_(1) -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) -#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 _L_(1) -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) -#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 _L_(1) -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) -#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 _L_(1) -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) -#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 _L_(1) -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) -#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 _L_(1) -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) -#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ -#define MUX_PA03B_ADC_VREFA _L_(1) -#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) -#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) -#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ -#define MUX_PA02B_ADC_VREFB _L_(1) -#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) -#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_AC_AIN0 _L_(1) -#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) -#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_AC_AIN1 _L_(1) -#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) -#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) -#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ -#define MUX_PB04B_AC_AIN2 _L_(1) -#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) -#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) -#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ -#define MUX_PB05B_AC_AIN3 _L_(1) -#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) -#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) -#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 _L_(7) -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 _L_(7) -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 _L_(7) -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 _L_(7) -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for SLCD peripheral ========== */ -#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ -#define MUX_PB06B_SLCD_LP0 _L_(1) -#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) -#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) -#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ -#define MUX_PB07B_SLCD_LP1 _L_(1) -#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) -#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) -#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ -#define MUX_PB08B_SLCD_LP2 _L_(1) -#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) -#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) -#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ -#define MUX_PB09B_SLCD_LP3 _L_(1) -#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) -#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) -#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ -#define MUX_PA04B_SLCD_LP4 _L_(1) -#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) -#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) -#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ -#define MUX_PA05B_SLCD_LP5 _L_(1) -#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) -#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) -#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ -#define MUX_PA06B_SLCD_LP6 _L_(1) -#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) -#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) -#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ -#define MUX_PA07B_SLCD_LP7 _L_(1) -#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) -#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) -#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ -#define MUX_PA08B_SLCD_LP11 _L_(1) -#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) -#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) -#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ -#define MUX_PA09B_SLCD_LP12 _L_(1) -#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) -#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) -#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ -#define MUX_PA10B_SLCD_LP13 _L_(1) -#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) -#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) -#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ -#define MUX_PA11B_SLCD_LP14 _L_(1) -#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) -#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) -#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ -#define MUX_PB11B_SLCD_LP21 _L_(1) -#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) -#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) -#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ -#define MUX_PB12B_SLCD_LP22 _L_(1) -#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) -#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) -#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ -#define MUX_PB13B_SLCD_LP23 _L_(1) -#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) -#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) -#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ -#define MUX_PB14B_SLCD_LP24 _L_(1) -#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) -#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) -#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ -#define MUX_PB15B_SLCD_LP25 _L_(1) -#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) -#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) -#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ -#define MUX_PA12B_SLCD_LP28 _L_(1) -#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) -#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) -#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ -#define MUX_PA13B_SLCD_LP29 _L_(1) -#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) -#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) -#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ -#define MUX_PA14B_SLCD_LP30 _L_(1) -#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) -#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) -#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ -#define MUX_PA15B_SLCD_LP31 _L_(1) -#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) -#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) -#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ -#define MUX_PA16B_SLCD_LP32 _L_(1) -#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) -#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) -#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ -#define MUX_PA17B_SLCD_LP33 _L_(1) -#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) -#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) -#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ -#define MUX_PA18B_SLCD_LP34 _L_(1) -#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) -#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) -#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ -#define MUX_PA19B_SLCD_LP35 _L_(1) -#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) -#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) -#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ -#define MUX_PB16B_SLCD_LP42 _L_(1) -#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) -#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) -#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ -#define MUX_PB17B_SLCD_LP43 _L_(1) -#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) -#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) -#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ -#define MUX_PA20B_SLCD_LP48 _L_(1) -#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) -#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) -#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ -#define MUX_PA21B_SLCD_LP49 _L_(1) -#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) -#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) -#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ -#define MUX_PA22B_SLCD_LP50 _L_(1) -#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) -#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) -#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ -#define MUX_PA23B_SLCD_LP51 _L_(1) -#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) -#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 _L_(8) -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 _L_(8) -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 _L_(8) -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 _L_(8) -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 _L_(8) -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ -#define MUX_PB00I_CCL_IN1 _L_(8) -#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) -#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 _L_(8) -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 _L_(8) -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ -#define MUX_PB01I_CCL_IN2 _L_(8) -#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) -#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 _L_(8) -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 _L_(8) -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 _L_(8) -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 _L_(8) -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 _L_(8) -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ -#define MUX_PB06I_CCL_IN6 _L_(8) -#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) -#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 _L_(8) -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ -#define MUX_PB07I_CCL_IN7 _L_(8) -#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) -#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 _L_(8) -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 _L_(8) -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ -#define MUX_PB14I_CCL_IN9 _L_(8) -#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) -#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) -#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ -#define MUX_PB15I_CCL_IN10 _L_(8) -#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) -#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) -#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ -#define MUX_PB16I_CCL_IN11 _L_(8) -#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) -#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 _L_(8) -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 _L_(8) -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 _L_(8) -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 _L_(8) -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 _L_(8) -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 _L_(8) -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 _L_(8) -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 _L_(8) -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 _L_(8) -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ -#define MUX_PB17I_CCL_OUT3 _L_(8) -#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) -#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) - -#endif /* _SAML22J17A_PIO_ */ diff --git a/watch-library/include/pio/saml22j18a.h b/watch-library/include/pio/saml22j18a.h deleted file mode 100644 index d2c8c3c7..00000000 --- a/watch-library/include/pio/saml22j18a.h +++ /dev/null @@ -1,1265 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML22J18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22J18A_PIO_ -#define _SAML22J18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ -#define MUX_PB01H_SUPC_OUT0 _L_(7) -#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) -#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) -#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 _L_(7) -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) -#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ -#define MUX_PB00H_SUPC_PSOK _L_(7) -#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) -#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) -#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT _L_(7) -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 _L_(7) -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 _L_(7) -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 _L_(7) -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 _L_(7) -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) -#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 _L_(7) -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 _L_(7) -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 _L_(7) -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 _L_(7) -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 _L_(7) -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 _L_(7) -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 _L_(7) -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 _L_(7) -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 _L_(7) -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 _L_(7) -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) -/* ========== PORT definition for RTC peripheral ========== */ -#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ -#define MUX_PB00G_RTC_IN0 _L_(6) -#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) -#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) -#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ -#define MUX_PB02G_RTC_IN1 _L_(6) -#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) -#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) -#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ -#define MUX_PA02G_RTC_IN2 _L_(6) -#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) -#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) -#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ -#define MUX_PB01F_RTC_IN2 _L_(5) -#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) -#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) -#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ -#define MUX_PB01G_RTC_OUT _L_(6) -#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) -#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM _L_(6) -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (_UL_(1) << 24) -#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP _L_(6) -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (_UL_(1) << 25) -#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ -#define MUX_PB22G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) -#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ -#define MUX_PA20C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) -#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ -#define MUX_PA21C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) -#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ -#define MUX_PA22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) -#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) -#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ -#define MUX_PA23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) -#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) -#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) -#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) -#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) -#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) -#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) -#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) -#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) -#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) -#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) -#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) -#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) -#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) -#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) -#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) -#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) -#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) -#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) -#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) -#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) -#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) -#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ -#define MUX_PB02C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) -#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) -#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) -#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) -#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) -#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) -#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ -#define MUX_PB03C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) -#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) -#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) -#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) -#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ -#define MUX_PB00C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) -#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) -#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) -#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) -#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) -#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) -#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ -#define MUX_PB01C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) -#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ -#define MUX_PA24F_TCC0_WO0 _L_(5) -#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) -#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 _L_(4) -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 _L_(4) -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 _L_(4) -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) -#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ -#define MUX_PA25F_TCC0_WO1 _L_(5) -#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) -#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 _L_(4) -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 _L_(4) -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 _L_(4) -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 _L_(5) -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ -#define MUX_PB22F_TCC0_WO2 _L_(5) -#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) -#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 _L_(5) -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ -#define MUX_PB23F_TCC0_WO3 _L_(5) -#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) -#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 _L_(5) -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) -#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 _L_(5) -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 _L_(5) -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 _L_(5) -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 _L_(5) -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) -#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ -#define MUX_PA27F_TCC0_WO5 _L_(5) -#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) -#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 _L_(5) -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 _L_(5) -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) -#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 _L_(5) -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) -#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 _L_(5) -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 _L_(5) -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) -#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 _L_(5) -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) -#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 _L_(5) -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 _L_(4) -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 _L_(4) -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC0_WO0 _L_(4) -#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) -#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 _L_(4) -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 _L_(4) -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC0_WO1 _L_(4) -#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) -#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 _L_(4) -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) -#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC1_WO0 _L_(4) -#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) -#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 _L_(4) -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 _L_(4) -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC1_WO1 _L_(4) -#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) -#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 _L_(4) -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC2_WO0 _L_(4) -#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) -#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 _L_(4) -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC2_WO1 _L_(4) -#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) -#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 _L_(4) -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC3_WO0 _L_(4) -#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) -#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 _L_(4) -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 _L_(4) -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC3_WO1 _L_(4) -#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) -#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 _L_(4) -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 _L_(1) -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 _L_(1) -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 _L_(1) -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 _L_(1) -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 _L_(1) -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 _L_(1) -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 _L_(1) -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 _L_(1) -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) -#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 _L_(1) -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) -#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 _L_(1) -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) -#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 _L_(1) -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) -#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 _L_(1) -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) -#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 _L_(1) -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) -#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 _L_(1) -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) -#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 _L_(1) -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) -#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 _L_(1) -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) -#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ -#define MUX_PA03B_ADC_VREFA _L_(1) -#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) -#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) -#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ -#define MUX_PA02B_ADC_VREFB _L_(1) -#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) -#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_AC_AIN0 _L_(1) -#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) -#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_AC_AIN1 _L_(1) -#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) -#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) -#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ -#define MUX_PB04B_AC_AIN2 _L_(1) -#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) -#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) -#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ -#define MUX_PB05B_AC_AIN3 _L_(1) -#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) -#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) -#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 _L_(7) -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 _L_(7) -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 _L_(7) -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 _L_(7) -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for SLCD peripheral ========== */ -#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ -#define MUX_PB06B_SLCD_LP0 _L_(1) -#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) -#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) -#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ -#define MUX_PB07B_SLCD_LP1 _L_(1) -#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) -#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) -#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ -#define MUX_PB08B_SLCD_LP2 _L_(1) -#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) -#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) -#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ -#define MUX_PB09B_SLCD_LP3 _L_(1) -#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) -#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) -#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ -#define MUX_PA04B_SLCD_LP4 _L_(1) -#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) -#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) -#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ -#define MUX_PA05B_SLCD_LP5 _L_(1) -#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) -#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) -#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ -#define MUX_PA06B_SLCD_LP6 _L_(1) -#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) -#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) -#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ -#define MUX_PA07B_SLCD_LP7 _L_(1) -#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) -#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) -#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ -#define MUX_PA08B_SLCD_LP11 _L_(1) -#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) -#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) -#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ -#define MUX_PA09B_SLCD_LP12 _L_(1) -#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) -#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) -#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ -#define MUX_PA10B_SLCD_LP13 _L_(1) -#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) -#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) -#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ -#define MUX_PA11B_SLCD_LP14 _L_(1) -#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) -#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) -#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ -#define MUX_PB11B_SLCD_LP21 _L_(1) -#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) -#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) -#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ -#define MUX_PB12B_SLCD_LP22 _L_(1) -#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) -#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) -#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ -#define MUX_PB13B_SLCD_LP23 _L_(1) -#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) -#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) -#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ -#define MUX_PB14B_SLCD_LP24 _L_(1) -#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) -#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) -#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ -#define MUX_PB15B_SLCD_LP25 _L_(1) -#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) -#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) -#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ -#define MUX_PA12B_SLCD_LP28 _L_(1) -#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) -#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) -#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ -#define MUX_PA13B_SLCD_LP29 _L_(1) -#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) -#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) -#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ -#define MUX_PA14B_SLCD_LP30 _L_(1) -#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) -#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) -#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ -#define MUX_PA15B_SLCD_LP31 _L_(1) -#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) -#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) -#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ -#define MUX_PA16B_SLCD_LP32 _L_(1) -#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) -#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) -#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ -#define MUX_PA17B_SLCD_LP33 _L_(1) -#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) -#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) -#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ -#define MUX_PA18B_SLCD_LP34 _L_(1) -#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) -#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) -#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ -#define MUX_PA19B_SLCD_LP35 _L_(1) -#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) -#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) -#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ -#define MUX_PB16B_SLCD_LP42 _L_(1) -#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) -#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) -#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ -#define MUX_PB17B_SLCD_LP43 _L_(1) -#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) -#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) -#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ -#define MUX_PA20B_SLCD_LP48 _L_(1) -#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) -#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) -#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ -#define MUX_PA21B_SLCD_LP49 _L_(1) -#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) -#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) -#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ -#define MUX_PA22B_SLCD_LP50 _L_(1) -#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) -#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) -#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ -#define MUX_PA23B_SLCD_LP51 _L_(1) -#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) -#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 _L_(8) -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 _L_(8) -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 _L_(8) -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 _L_(8) -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 _L_(8) -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ -#define MUX_PB00I_CCL_IN1 _L_(8) -#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) -#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 _L_(8) -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 _L_(8) -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ -#define MUX_PB01I_CCL_IN2 _L_(8) -#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) -#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 _L_(8) -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 _L_(8) -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 _L_(8) -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 _L_(8) -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 _L_(8) -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ -#define MUX_PB06I_CCL_IN6 _L_(8) -#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) -#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 _L_(8) -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ -#define MUX_PB07I_CCL_IN7 _L_(8) -#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) -#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 _L_(8) -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 _L_(8) -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ -#define MUX_PB14I_CCL_IN9 _L_(8) -#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) -#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) -#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ -#define MUX_PB15I_CCL_IN10 _L_(8) -#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) -#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) -#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ -#define MUX_PB16I_CCL_IN11 _L_(8) -#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) -#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 _L_(8) -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 _L_(8) -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 _L_(8) -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 _L_(8) -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 _L_(8) -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 _L_(8) -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 _L_(8) -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 _L_(8) -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 _L_(8) -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ -#define MUX_PB17I_CCL_OUT3 _L_(8) -#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) -#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) - -#endif /* _SAML22J18A_PIO_ */ diff --git a/watch-library/include/pio/saml22n16a.h b/watch-library/include/pio/saml22n16a.h deleted file mode 100644 index bd4c515f..00000000 --- a/watch-library/include/pio/saml22n16a.h +++ /dev/null @@ -1,1851 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML22N16A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22N16A_PIO_ -#define _SAML22N16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC08 72 /**< \brief Pin Number for PC08 */ -#define PORT_PC08 (_UL_(1) << 8) /**< \brief PORT Mask for PC08 */ -#define PIN_PC09 73 /**< \brief Pin Number for PC09 */ -#define PORT_PC09 (_UL_(1) << 9) /**< \brief PORT Mask for PC09 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ -#define MUX_PB01H_SUPC_OUT0 _L_(7) -#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) -#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) -#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 _L_(7) -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) -#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ -#define MUX_PB00H_SUPC_PSOK _L_(7) -#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) -#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) -#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT _L_(7) -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 _L_(7) -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 _L_(7) -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 _L_(7) -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 _L_(7) -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) -#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 _L_(7) -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 _L_(7) -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 _L_(7) -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 _L_(7) -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 _L_(7) -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 _L_(7) -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 _L_(7) -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 _L_(7) -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 _L_(7) -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 _L_(7) -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) -/* ========== PORT definition for RTC peripheral ========== */ -#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ -#define MUX_PB00G_RTC_IN0 _L_(6) -#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) -#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) -#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ -#define MUX_PB02G_RTC_IN1 _L_(6) -#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) -#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) -#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ -#define MUX_PA02G_RTC_IN2 _L_(6) -#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) -#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) -#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ -#define MUX_PB01F_RTC_IN2 _L_(5) -#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) -#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) -#define PIN_PC00G_RTC_IN3 _L_(64) /**< \brief RTC signal: IN3 on PC00 mux G */ -#define MUX_PC00G_RTC_IN3 _L_(6) -#define PINMUX_PC00G_RTC_IN3 ((PIN_PC00G_RTC_IN3 << 16) | MUX_PC00G_RTC_IN3) -#define PORT_PC00G_RTC_IN3 (_UL_(1) << 0) -#define PIN_PC01G_RTC_IN4 _L_(65) /**< \brief RTC signal: IN4 on PC01 mux G */ -#define MUX_PC01G_RTC_IN4 _L_(6) -#define PINMUX_PC01G_RTC_IN4 ((PIN_PC01G_RTC_IN4 << 16) | MUX_PC01G_RTC_IN4) -#define PORT_PC01G_RTC_IN4 (_UL_(1) << 1) -#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ -#define MUX_PB01G_RTC_OUT _L_(6) -#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) -#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC08A_EIC_EXTINT0 _L_(72) /**< \brief EIC signal: EXTINT0 on PC08 mux A */ -#define MUX_PC08A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC08A_EIC_EXTINT0 ((PIN_PC08A_EIC_EXTINT0 << 16) | MUX_PC08A_EIC_EXTINT0) -#define PORT_PC08A_EIC_EXTINT0 (_UL_(1) << 8) -#define PIN_PC08A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC08 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT0 _L_(88) /**< \brief EIC signal: EXTINT0 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT0 ((PIN_PC24A_EIC_EXTINT0 << 16) | MUX_PC24A_EIC_EXTINT0) -#define PORT_PC24A_EIC_EXTINT0 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC09A_EIC_EXTINT1 _L_(73) /**< \brief EIC signal: EXTINT1 on PC09 mux A */ -#define MUX_PC09A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC09A_EIC_EXTINT1 ((PIN_PC09A_EIC_EXTINT1 << 16) | MUX_PC09A_EIC_EXTINT1) -#define PORT_PC09A_EIC_EXTINT1 (_UL_(1) << 9) -#define PIN_PC09A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC09 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT1 _L_(89) /**< \brief EIC signal: EXTINT1 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT1 ((PIN_PC25A_EIC_EXTINT1 << 16) | MUX_PC25A_EIC_EXTINT1) -#define PORT_PC25A_EIC_EXTINT1 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT2 _L_(74) /**< \brief EIC signal: EXTINT2 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT2 ((PIN_PC10A_EIC_EXTINT2 << 16) | MUX_PC10A_EIC_EXTINT2) -#define PORT_PC10A_EIC_EXTINT2 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT2 _L_(90) /**< \brief EIC signal: EXTINT2 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT2 ((PIN_PC26A_EIC_EXTINT2 << 16) | MUX_PC26A_EIC_EXTINT2) -#define PORT_PC26A_EIC_EXTINT2 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT3 _L_(75) /**< \brief EIC signal: EXTINT3 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT3 ((PIN_PC11A_EIC_EXTINT3 << 16) | MUX_PC11A_EIC_EXTINT3) -#define PORT_PC11A_EIC_EXTINT3 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT3 _L_(91) /**< \brief EIC signal: EXTINT3 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT3 ((PIN_PC27A_EIC_EXTINT3 << 16) | MUX_PC27A_EIC_EXTINT3) -#define PORT_PC27A_EIC_EXTINT3 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT4 _L_(76) /**< \brief EIC signal: EXTINT4 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT4 ((PIN_PC12A_EIC_EXTINT4 << 16) | MUX_PC12A_EIC_EXTINT4) -#define PORT_PC12A_EIC_EXTINT4 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT4 _L_(92) /**< \brief EIC signal: EXTINT4 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT4 ((PIN_PC28A_EIC_EXTINT4 << 16) | MUX_PC28A_EIC_EXTINT4) -#define PORT_PC28A_EIC_EXTINT4 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT5 _L_(77) /**< \brief EIC signal: EXTINT5 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT5 ((PIN_PC13A_EIC_EXTINT5 << 16) | MUX_PC13A_EIC_EXTINT5) -#define PORT_PC13A_EIC_EXTINT5 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT6 _L_(78) /**< \brief EIC signal: EXTINT6 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT6 ((PIN_PC14A_EIC_EXTINT6 << 16) | MUX_PC14A_EIC_EXTINT6) -#define PORT_PC14A_EIC_EXTINT6 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT7 _L_(79) /**< \brief EIC signal: EXTINT7 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT7 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT7 ((PIN_PC15A_EIC_EXTINT7 << 16) | MUX_PC15A_EIC_EXTINT7) -#define PORT_PC15A_EIC_EXTINT7 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT8 _L_(64) /**< \brief EIC signal: EXTINT8 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT8 ((PIN_PC00A_EIC_EXTINT8 << 16) | MUX_PC00A_EIC_EXTINT8) -#define PORT_PC00A_EIC_EXTINT8 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT8 _L_(80) /**< \brief EIC signal: EXTINT8 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT8 ((PIN_PC16A_EIC_EXTINT8 << 16) | MUX_PC16A_EIC_EXTINT8) -#define PORT_PC16A_EIC_EXTINT8 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT9 _L_(65) /**< \brief EIC signal: EXTINT9 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT9 ((PIN_PC01A_EIC_EXTINT9 << 16) | MUX_PC01A_EIC_EXTINT9) -#define PORT_PC01A_EIC_EXTINT9 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT9 _L_(81) /**< \brief EIC signal: EXTINT9 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT9 ((PIN_PC17A_EIC_EXTINT9 << 16) | MUX_PC17A_EIC_EXTINT9) -#define PORT_PC17A_EIC_EXTINT9 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT10 _L_(66) /**< \brief EIC signal: EXTINT10 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT10 ((PIN_PC02A_EIC_EXTINT10 << 16) | MUX_PC02A_EIC_EXTINT10) -#define PORT_PC02A_EIC_EXTINT10 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT10 _L_(82) /**< \brief EIC signal: EXTINT10 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT10 ((PIN_PC18A_EIC_EXTINT10 << 16) | MUX_PC18A_EIC_EXTINT10) -#define PORT_PC18A_EIC_EXTINT10 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT11 _L_(67) /**< \brief EIC signal: EXTINT11 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT11 ((PIN_PC03A_EIC_EXTINT11 << 16) | MUX_PC03A_EIC_EXTINT11) -#define PORT_PC03A_EIC_EXTINT11 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT11 _L_(83) /**< \brief EIC signal: EXTINT11 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT11 ((PIN_PC19A_EIC_EXTINT11 << 16) | MUX_PC19A_EIC_EXTINT11) -#define PORT_PC19A_EIC_EXTINT11 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT12 _L_(84) /**< \brief EIC signal: EXTINT12 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT12 ((PIN_PC20A_EIC_EXTINT12 << 16) | MUX_PC20A_EIC_EXTINT12) -#define PORT_PC20A_EIC_EXTINT12 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT13 _L_(69) /**< \brief EIC signal: EXTINT13 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT13 ((PIN_PC05A_EIC_EXTINT13 << 16) | MUX_PC05A_EIC_EXTINT13) -#define PORT_PC05A_EIC_EXTINT13 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT13 _L_(85) /**< \brief EIC signal: EXTINT13 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT13 ((PIN_PC21A_EIC_EXTINT13 << 16) | MUX_PC21A_EIC_EXTINT13) -#define PORT_PC21A_EIC_EXTINT13 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT14 _L_(70) /**< \brief EIC signal: EXTINT14 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT14 ((PIN_PC06A_EIC_EXTINT14 << 16) | MUX_PC06A_EIC_EXTINT14) -#define PORT_PC06A_EIC_EXTINT14 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT15 _L_(71) /**< \brief EIC signal: EXTINT15 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT15 ((PIN_PC07A_EIC_EXTINT15 << 16) | MUX_PC07A_EIC_EXTINT15) -#define PORT_PC07A_EIC_EXTINT15 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM _L_(6) -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (_UL_(1) << 24) -#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP _L_(6) -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (_UL_(1) << 25) -#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ -#define MUX_PB22G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) -#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ -#define MUX_PA20C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) -#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ -#define MUX_PA21C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) -#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ -#define MUX_PA22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) -#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) -#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ -#define MUX_PA23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) -#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) -#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) -#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PC27D_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux D */ -#define MUX_PC27D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PC27D_SERCOM1_PAD0 ((PIN_PC27D_SERCOM1_PAD0 << 16) | MUX_PC27D_SERCOM1_PAD0) -#define PORT_PC27D_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC12C_SERCOM1_PAD0 _L_(76) /**< \brief SERCOM1 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM1_PAD0 ((PIN_PC12C_SERCOM1_PAD0 << 16) | MUX_PC12C_SERCOM1_PAD0) -#define PORT_PC12C_SERCOM1_PAD0 (_UL_(1) << 12) -#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) -#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PC28D_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux D */ -#define MUX_PC28D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PC28D_SERCOM1_PAD1 ((PIN_PC28D_SERCOM1_PAD1 << 16) | MUX_PC28D_SERCOM1_PAD1) -#define PORT_PC28D_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC13C_SERCOM1_PAD1 _L_(77) /**< \brief SERCOM1 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM1_PAD1 ((PIN_PC13C_SERCOM1_PAD1 << 16) | MUX_PC13C_SERCOM1_PAD1) -#define PORT_PC13C_SERCOM1_PAD1 (_UL_(1) << 13) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PC10C_SERCOM1_PAD2 _L_(74) /**< \brief SERCOM1 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM1_PAD2 ((PIN_PC10C_SERCOM1_PAD2 << 16) | MUX_PC10C_SERCOM1_PAD2) -#define PORT_PC10C_SERCOM1_PAD2 (_UL_(1) << 10) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PC11C_SERCOM1_PAD3 _L_(75) /**< \brief SERCOM1 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM1_PAD3 ((PIN_PC11C_SERCOM1_PAD3 << 16) | MUX_PC11C_SERCOM1_PAD3) -#define PORT_PC11C_SERCOM1_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) -#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) -#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) -#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) -#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) -#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) -#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) -#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) -#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) -#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) -#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) -#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) -#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) -#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) -#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) -#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) -#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) -#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ -#define MUX_PB02C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) -#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) -#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) -#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) -#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) -#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ -#define MUX_PB03C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) -#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) -#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) -#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PB18D_SERCOM3_PAD2 _L_(50) /**< \brief SERCOM3 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM3_PAD2 ((PIN_PB18D_SERCOM3_PAD2 << 16) | MUX_PB18D_SERCOM3_PAD2) -#define PORT_PB18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ -#define MUX_PB00C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) -#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) -#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) -#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) -#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) -#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) -#define PIN_PB19D_SERCOM3_PAD3 _L_(51) /**< \brief SERCOM3 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM3_PAD3 ((PIN_PB19D_SERCOM3_PAD3 << 16) | MUX_PB19D_SERCOM3_PAD3) -#define PORT_PB19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ -#define MUX_PB01C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) -#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA08D_SERCOM4_PAD0 _L_(8) /**< \brief SERCOM4 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA08D_SERCOM4_PAD0 ((PIN_PA08D_SERCOM4_PAD0 << 16) | MUX_PA08D_SERCOM4_PAD0) -#define PORT_PA08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM4_PAD0 _L_(56) /**< \brief SERCOM4 signal: PAD0 on PB24 mux D */ -#define MUX_PB24D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB24D_SERCOM4_PAD0 ((PIN_PB24D_SERCOM4_PAD0 << 16) | MUX_PB24D_SERCOM4_PAD0) -#define PORT_PB24D_SERCOM4_PAD0 (_UL_(1) << 24) -#define PIN_PA12C_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM4_PAD0 ((PIN_PA12C_SERCOM4_PAD0 << 16) | MUX_PA12C_SERCOM4_PAD0) -#define PORT_PA12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA09D_SERCOM4_PAD1 _L_(9) /**< \brief SERCOM4 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA09D_SERCOM4_PAD1 ((PIN_PA09D_SERCOM4_PAD1 << 16) | MUX_PA09D_SERCOM4_PAD1) -#define PORT_PA09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM4_PAD1 _L_(57) /**< \brief SERCOM4 signal: PAD1 on PB25 mux D */ -#define MUX_PB25D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB25D_SERCOM4_PAD1 ((PIN_PB25D_SERCOM4_PAD1 << 16) | MUX_PB25D_SERCOM4_PAD1) -#define PORT_PB25D_SERCOM4_PAD1 (_UL_(1) << 25) -#define PIN_PA13C_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM4_PAD1 ((PIN_PA13C_SERCOM4_PAD1 << 16) | MUX_PA13C_SERCOM4_PAD1) -#define PORT_PA13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM4_PAD2 _L_(10) /**< \brief SERCOM4 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM4_PAD2 ((PIN_PA10D_SERCOM4_PAD2 << 16) | MUX_PA10D_SERCOM4_PAD2) -#define PORT_PA10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM4_PAD2 _L_(88) /**< \brief SERCOM4 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM4_PAD2 ((PIN_PC24D_SERCOM4_PAD2 << 16) | MUX_PC24D_SERCOM4_PAD2) -#define PORT_PC24D_SERCOM4_PAD2 (_UL_(1) << 24) -#define PIN_PA14C_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM4_PAD2 ((PIN_PA14C_SERCOM4_PAD2 << 16) | MUX_PA14C_SERCOM4_PAD2) -#define PORT_PA14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM4_PAD3 _L_(11) /**< \brief SERCOM4 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM4_PAD3 ((PIN_PA11D_SERCOM4_PAD3 << 16) | MUX_PA11D_SERCOM4_PAD3) -#define PORT_PA11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM4_PAD3 _L_(89) /**< \brief SERCOM4 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM4_PAD3 ((PIN_PC25D_SERCOM4_PAD3 << 16) | MUX_PC25D_SERCOM4_PAD3) -#define PORT_PC25D_SERCOM4_PAD3 (_UL_(1) << 25) -#define PIN_PA15C_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM4_PAD3 ((PIN_PA15C_SERCOM4_PAD3 << 16) | MUX_PA15C_SERCOM4_PAD3) -#define PORT_PA15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) -#define PIN_PA24D_SERCOM5_PAD0 _L_(24) /**< \brief SERCOM5 signal: PAD0 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD0 ((PIN_PA24D_SERCOM5_PAD0 << 16) | MUX_PA24D_SERCOM5_PAD0) -#define PORT_PA24D_SERCOM5_PAD0 (_UL_(1) << 24) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB20D_SERCOM5_PAD0 _L_(52) /**< \brief SERCOM5 signal: PAD0 on PB20 mux D */ -#define MUX_PB20D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB20D_SERCOM5_PAD0 ((PIN_PB20D_SERCOM5_PAD0 << 16) | MUX_PB20D_SERCOM5_PAD0) -#define PORT_PB20D_SERCOM5_PAD0 (_UL_(1) << 20) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) -#define PIN_PA25D_SERCOM5_PAD1 _L_(25) /**< \brief SERCOM5 signal: PAD1 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD1 ((PIN_PA25D_SERCOM5_PAD1 << 16) | MUX_PA25D_SERCOM5_PAD1) -#define PORT_PA25D_SERCOM5_PAD1 (_UL_(1) << 25) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB21D_SERCOM5_PAD1 _L_(53) /**< \brief SERCOM5 signal: PAD1 on PB21 mux D */ -#define MUX_PB21D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB21D_SERCOM5_PAD1 ((PIN_PB21D_SERCOM5_PAD1 << 16) | MUX_PB21D_SERCOM5_PAD1) -#define PORT_PB21D_SERCOM5_PAD1 (_UL_(1) << 21) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ -#define MUX_PA24F_TCC0_WO0 _L_(5) -#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) -#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PB18F_TCC0_WO0 _L_(50) /**< \brief TCC0 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC0_WO0 _L_(5) -#define PINMUX_PB18F_TCC0_WO0 ((PIN_PB18F_TCC0_WO0 << 16) | MUX_PB18F_TCC0_WO0) -#define PORT_PB18F_TCC0_WO0 (_UL_(1) << 18) -#define PIN_PC24F_TCC0_WO0 _L_(88) /**< \brief TCC0 signal: WO0 on PC24 mux F */ -#define MUX_PC24F_TCC0_WO0 _L_(5) -#define PINMUX_PC24F_TCC0_WO0 ((PIN_PC24F_TCC0_WO0 << 16) | MUX_PC24F_TCC0_WO0) -#define PORT_PC24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 _L_(4) -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 _L_(4) -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 _L_(4) -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) -#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ -#define MUX_PA25F_TCC0_WO1 _L_(5) -#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) -#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PB19F_TCC0_WO1 _L_(51) /**< \brief TCC0 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC0_WO1 _L_(5) -#define PINMUX_PB19F_TCC0_WO1 ((PIN_PB19F_TCC0_WO1 << 16) | MUX_PB19F_TCC0_WO1) -#define PORT_PB19F_TCC0_WO1 (_UL_(1) << 19) -#define PIN_PC25F_TCC0_WO1 _L_(89) /**< \brief TCC0 signal: WO1 on PC25 mux F */ -#define MUX_PC25F_TCC0_WO1 _L_(5) -#define PINMUX_PC25F_TCC0_WO1 ((PIN_PC25F_TCC0_WO1 << 16) | MUX_PC25F_TCC0_WO1) -#define PORT_PC25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 _L_(4) -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 _L_(4) -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 _L_(4) -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 _L_(5) -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC0_WO2 _L_(52) /**< \brief TCC0 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC0_WO2 _L_(5) -#define PINMUX_PB20F_TCC0_WO2 ((PIN_PB20F_TCC0_WO2 << 16) | MUX_PB20F_TCC0_WO2) -#define PORT_PB20F_TCC0_WO2 (_UL_(1) << 20) -#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ -#define MUX_PB22F_TCC0_WO2 _L_(5) -#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) -#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PC26F_TCC0_WO2 _L_(90) /**< \brief TCC0 signal: WO2 on PC26 mux F */ -#define MUX_PC26F_TCC0_WO2 _L_(5) -#define PINMUX_PC26F_TCC0_WO2 ((PIN_PC26F_TCC0_WO2 << 16) | MUX_PC26F_TCC0_WO2) -#define PORT_PC26F_TCC0_WO2 (_UL_(1) << 26) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 _L_(5) -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC0_WO3 _L_(53) /**< \brief TCC0 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC0_WO3 _L_(5) -#define PINMUX_PB21F_TCC0_WO3 ((PIN_PB21F_TCC0_WO3 << 16) | MUX_PB21F_TCC0_WO3) -#define PORT_PB21F_TCC0_WO3 (_UL_(1) << 21) -#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ -#define MUX_PB23F_TCC0_WO3 _L_(5) -#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) -#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PC27F_TCC0_WO3 _L_(91) /**< \brief TCC0 signal: WO3 on PC27 mux F */ -#define MUX_PC27F_TCC0_WO3 _L_(5) -#define PINMUX_PC27F_TCC0_WO3 ((PIN_PC27F_TCC0_WO3 << 16) | MUX_PC27F_TCC0_WO3) -#define PORT_PC27F_TCC0_WO3 (_UL_(1) << 27) -#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 _L_(5) -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) -#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 _L_(5) -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PC28F_TCC0_WO4 _L_(92) /**< \brief TCC0 signal: WO4 on PC28 mux F */ -#define MUX_PC28F_TCC0_WO4 _L_(5) -#define PINMUX_PC28F_TCC0_WO4 ((PIN_PC28F_TCC0_WO4 << 16) | MUX_PC28F_TCC0_WO4) -#define PORT_PC28F_TCC0_WO4 (_UL_(1) << 28) -#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 _L_(5) -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 _L_(5) -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 _L_(5) -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) -#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ -#define MUX_PA27F_TCC0_WO5 _L_(5) -#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) -#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 _L_(5) -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 _L_(5) -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) -#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 _L_(5) -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) -#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 _L_(5) -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PB24F_TCC0_WO6 _L_(56) /**< \brief TCC0 signal: WO6 on PB24 mux F */ -#define MUX_PB24F_TCC0_WO6 _L_(5) -#define PINMUX_PB24F_TCC0_WO6 ((PIN_PB24F_TCC0_WO6 << 16) | MUX_PB24F_TCC0_WO6) -#define PORT_PB24F_TCC0_WO6 (_UL_(1) << 24) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 _L_(5) -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) -#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 _L_(5) -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) -#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 _L_(5) -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PB25F_TCC0_WO7 _L_(57) /**< \brief TCC0 signal: WO7 on PB25 mux F */ -#define MUX_PB25F_TCC0_WO7 _L_(5) -#define PINMUX_PB25F_TCC0_WO7 ((PIN_PB25F_TCC0_WO7 << 16) | MUX_PB25F_TCC0_WO7) -#define PORT_PB25F_TCC0_WO7 (_UL_(1) << 25) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 _L_(4) -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 _L_(4) -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC0_WO0 _L_(4) -#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) -#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 _L_(4) -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 _L_(4) -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC0_WO1 _L_(4) -#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) -#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 _L_(4) -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) -#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC1_WO0 _L_(4) -#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) -#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 _L_(4) -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 _L_(4) -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC1_WO1 _L_(4) -#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) -#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 _L_(4) -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC2_WO0 _L_(4) -#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) -#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PC24E_TC2_WO0 _L_(88) /**< \brief TC2 signal: WO0 on PC24 mux E */ -#define MUX_PC24E_TC2_WO0 _L_(4) -#define PINMUX_PC24E_TC2_WO0 ((PIN_PC24E_TC2_WO0 << 16) | MUX_PC24E_TC2_WO0) -#define PORT_PC24E_TC2_WO0 (_UL_(1) << 24) -#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 _L_(4) -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC2_WO1 _L_(4) -#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) -#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) -#define PIN_PC25E_TC2_WO1 _L_(89) /**< \brief TC2 signal: WO1 on PC25 mux E */ -#define MUX_PC25E_TC2_WO1 _L_(4) -#define PINMUX_PC25E_TC2_WO1 ((PIN_PC25E_TC2_WO1 << 16) | MUX_PC25E_TC2_WO1) -#define PORT_PC25E_TC2_WO1 (_UL_(1) << 25) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 _L_(4) -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC3_WO0 _L_(4) -#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) -#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 _L_(4) -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) -#define PIN_PC26E_TC3_WO0 _L_(90) /**< \brief TC3 signal: WO0 on PC26 mux E */ -#define MUX_PC26E_TC3_WO0 _L_(4) -#define PINMUX_PC26E_TC3_WO0 ((PIN_PC26E_TC3_WO0 << 16) | MUX_PC26E_TC3_WO0) -#define PORT_PC26E_TC3_WO0 (_UL_(1) << 26) -#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 _L_(4) -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC3_WO1 _L_(4) -#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) -#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 _L_(4) -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) -#define PIN_PC27E_TC3_WO1 _L_(91) /**< \brief TC3 signal: WO1 on PC27 mux E */ -#define MUX_PC27E_TC3_WO1 _L_(4) -#define PINMUX_PC27E_TC3_WO1 ((PIN_PC27E_TC3_WO1 << 16) | MUX_PC27E_TC3_WO1) -#define PORT_PC27E_TC3_WO1 (_UL_(1) << 27) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 _L_(1) -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 _L_(1) -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 _L_(1) -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 _L_(1) -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 _L_(1) -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 _L_(1) -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 _L_(1) -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 _L_(1) -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) -#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 _L_(1) -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) -#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 _L_(1) -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) -#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 _L_(1) -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) -#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 _L_(1) -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) -#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 _L_(1) -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) -#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 _L_(1) -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) -#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 _L_(1) -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) -#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 _L_(1) -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) -#define PIN_PC00B_ADC_AIN16 _L_(64) /**< \brief ADC signal: AIN16 on PC00 mux B */ -#define MUX_PC00B_ADC_AIN16 _L_(1) -#define PINMUX_PC00B_ADC_AIN16 ((PIN_PC00B_ADC_AIN16 << 16) | MUX_PC00B_ADC_AIN16) -#define PORT_PC00B_ADC_AIN16 (_UL_(1) << 0) -#define PIN_PC01B_ADC_AIN17 _L_(65) /**< \brief ADC signal: AIN17 on PC01 mux B */ -#define MUX_PC01B_ADC_AIN17 _L_(1) -#define PINMUX_PC01B_ADC_AIN17 ((PIN_PC01B_ADC_AIN17 << 16) | MUX_PC01B_ADC_AIN17) -#define PORT_PC01B_ADC_AIN17 (_UL_(1) << 1) -#define PIN_PC02B_ADC_AIN18 _L_(66) /**< \brief ADC signal: AIN18 on PC02 mux B */ -#define MUX_PC02B_ADC_AIN18 _L_(1) -#define PINMUX_PC02B_ADC_AIN18 ((PIN_PC02B_ADC_AIN18 << 16) | MUX_PC02B_ADC_AIN18) -#define PORT_PC02B_ADC_AIN18 (_UL_(1) << 2) -#define PIN_PC03B_ADC_AIN19 _L_(67) /**< \brief ADC signal: AIN19 on PC03 mux B */ -#define MUX_PC03B_ADC_AIN19 _L_(1) -#define PINMUX_PC03B_ADC_AIN19 ((PIN_PC03B_ADC_AIN19 << 16) | MUX_PC03B_ADC_AIN19) -#define PORT_PC03B_ADC_AIN19 (_UL_(1) << 3) -#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ -#define MUX_PA03B_ADC_VREFA _L_(1) -#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) -#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) -#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ -#define MUX_PA02B_ADC_VREFB _L_(1) -#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) -#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_AC_AIN0 _L_(1) -#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) -#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_AC_AIN1 _L_(1) -#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) -#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) -#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ -#define MUX_PB04B_AC_AIN2 _L_(1) -#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) -#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) -#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ -#define MUX_PB05B_AC_AIN3 _L_(1) -#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) -#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) -#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 _L_(7) -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 _L_(7) -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24H_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux H */ -#define MUX_PB24H_AC_CMP0 _L_(7) -#define PINMUX_PB24H_AC_CMP0 ((PIN_PB24H_AC_CMP0 << 16) | MUX_PB24H_AC_CMP0) -#define PORT_PB24H_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 _L_(7) -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 _L_(7) -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25H_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux H */ -#define MUX_PB25H_AC_CMP1 _L_(7) -#define PINMUX_PB25H_AC_CMP1 ((PIN_PB25H_AC_CMP1 << 16) | MUX_PB25H_AC_CMP1) -#define PORT_PB25H_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for SLCD peripheral ========== */ -#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ -#define MUX_PB06B_SLCD_LP0 _L_(1) -#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) -#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) -#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ -#define MUX_PB07B_SLCD_LP1 _L_(1) -#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) -#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) -#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ -#define MUX_PB08B_SLCD_LP2 _L_(1) -#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) -#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) -#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ -#define MUX_PB09B_SLCD_LP3 _L_(1) -#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) -#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) -#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ -#define MUX_PA04B_SLCD_LP4 _L_(1) -#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) -#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) -#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ -#define MUX_PA05B_SLCD_LP5 _L_(1) -#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) -#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) -#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ -#define MUX_PA06B_SLCD_LP6 _L_(1) -#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) -#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) -#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ -#define MUX_PA07B_SLCD_LP7 _L_(1) -#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) -#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) -#define PIN_PC05B_SLCD_LP8 _L_(69) /**< \brief SLCD signal: LP8 on PC05 mux B */ -#define MUX_PC05B_SLCD_LP8 _L_(1) -#define PINMUX_PC05B_SLCD_LP8 ((PIN_PC05B_SLCD_LP8 << 16) | MUX_PC05B_SLCD_LP8) -#define PORT_PC05B_SLCD_LP8 (_UL_(1) << 5) -#define PIN_PC06B_SLCD_LP9 _L_(70) /**< \brief SLCD signal: LP9 on PC06 mux B */ -#define MUX_PC06B_SLCD_LP9 _L_(1) -#define PINMUX_PC06B_SLCD_LP9 ((PIN_PC06B_SLCD_LP9 << 16) | MUX_PC06B_SLCD_LP9) -#define PORT_PC06B_SLCD_LP9 (_UL_(1) << 6) -#define PIN_PC07B_SLCD_LP10 _L_(71) /**< \brief SLCD signal: LP10 on PC07 mux B */ -#define MUX_PC07B_SLCD_LP10 _L_(1) -#define PINMUX_PC07B_SLCD_LP10 ((PIN_PC07B_SLCD_LP10 << 16) | MUX_PC07B_SLCD_LP10) -#define PORT_PC07B_SLCD_LP10 (_UL_(1) << 7) -#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ -#define MUX_PA08B_SLCD_LP11 _L_(1) -#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) -#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) -#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ -#define MUX_PA09B_SLCD_LP12 _L_(1) -#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) -#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) -#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ -#define MUX_PA10B_SLCD_LP13 _L_(1) -#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) -#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) -#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ -#define MUX_PA11B_SLCD_LP14 _L_(1) -#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) -#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) -#define PIN_PC08B_SLCD_LP15 _L_(72) /**< \brief SLCD signal: LP15 on PC08 mux B */ -#define MUX_PC08B_SLCD_LP15 _L_(1) -#define PINMUX_PC08B_SLCD_LP15 ((PIN_PC08B_SLCD_LP15 << 16) | MUX_PC08B_SLCD_LP15) -#define PORT_PC08B_SLCD_LP15 (_UL_(1) << 8) -#define PIN_PC09B_SLCD_LP16 _L_(73) /**< \brief SLCD signal: LP16 on PC09 mux B */ -#define MUX_PC09B_SLCD_LP16 _L_(1) -#define PINMUX_PC09B_SLCD_LP16 ((PIN_PC09B_SLCD_LP16 << 16) | MUX_PC09B_SLCD_LP16) -#define PORT_PC09B_SLCD_LP16 (_UL_(1) << 9) -#define PIN_PC10B_SLCD_LP17 _L_(74) /**< \brief SLCD signal: LP17 on PC10 mux B */ -#define MUX_PC10B_SLCD_LP17 _L_(1) -#define PINMUX_PC10B_SLCD_LP17 ((PIN_PC10B_SLCD_LP17 << 16) | MUX_PC10B_SLCD_LP17) -#define PORT_PC10B_SLCD_LP17 (_UL_(1) << 10) -#define PIN_PC11B_SLCD_LP18 _L_(75) /**< \brief SLCD signal: LP18 on PC11 mux B */ -#define MUX_PC11B_SLCD_LP18 _L_(1) -#define PINMUX_PC11B_SLCD_LP18 ((PIN_PC11B_SLCD_LP18 << 16) | MUX_PC11B_SLCD_LP18) -#define PORT_PC11B_SLCD_LP18 (_UL_(1) << 11) -#define PIN_PC12B_SLCD_LP19 _L_(76) /**< \brief SLCD signal: LP19 on PC12 mux B */ -#define MUX_PC12B_SLCD_LP19 _L_(1) -#define PINMUX_PC12B_SLCD_LP19 ((PIN_PC12B_SLCD_LP19 << 16) | MUX_PC12B_SLCD_LP19) -#define PORT_PC12B_SLCD_LP19 (_UL_(1) << 12) -#define PIN_PC13B_SLCD_LP20 _L_(77) /**< \brief SLCD signal: LP20 on PC13 mux B */ -#define MUX_PC13B_SLCD_LP20 _L_(1) -#define PINMUX_PC13B_SLCD_LP20 ((PIN_PC13B_SLCD_LP20 << 16) | MUX_PC13B_SLCD_LP20) -#define PORT_PC13B_SLCD_LP20 (_UL_(1) << 13) -#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ -#define MUX_PB11B_SLCD_LP21 _L_(1) -#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) -#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) -#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ -#define MUX_PB12B_SLCD_LP22 _L_(1) -#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) -#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) -#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ -#define MUX_PB13B_SLCD_LP23 _L_(1) -#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) -#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) -#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ -#define MUX_PB14B_SLCD_LP24 _L_(1) -#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) -#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) -#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ -#define MUX_PB15B_SLCD_LP25 _L_(1) -#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) -#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) -#define PIN_PC14B_SLCD_LP26 _L_(78) /**< \brief SLCD signal: LP26 on PC14 mux B */ -#define MUX_PC14B_SLCD_LP26 _L_(1) -#define PINMUX_PC14B_SLCD_LP26 ((PIN_PC14B_SLCD_LP26 << 16) | MUX_PC14B_SLCD_LP26) -#define PORT_PC14B_SLCD_LP26 (_UL_(1) << 14) -#define PIN_PC15B_SLCD_LP27 _L_(79) /**< \brief SLCD signal: LP27 on PC15 mux B */ -#define MUX_PC15B_SLCD_LP27 _L_(1) -#define PINMUX_PC15B_SLCD_LP27 ((PIN_PC15B_SLCD_LP27 << 16) | MUX_PC15B_SLCD_LP27) -#define PORT_PC15B_SLCD_LP27 (_UL_(1) << 15) -#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ -#define MUX_PA12B_SLCD_LP28 _L_(1) -#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) -#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) -#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ -#define MUX_PA13B_SLCD_LP29 _L_(1) -#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) -#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) -#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ -#define MUX_PA14B_SLCD_LP30 _L_(1) -#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) -#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) -#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ -#define MUX_PA15B_SLCD_LP31 _L_(1) -#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) -#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) -#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ -#define MUX_PA16B_SLCD_LP32 _L_(1) -#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) -#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) -#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ -#define MUX_PA17B_SLCD_LP33 _L_(1) -#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) -#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) -#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ -#define MUX_PA18B_SLCD_LP34 _L_(1) -#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) -#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) -#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ -#define MUX_PA19B_SLCD_LP35 _L_(1) -#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) -#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) -#define PIN_PC16B_SLCD_LP36 _L_(80) /**< \brief SLCD signal: LP36 on PC16 mux B */ -#define MUX_PC16B_SLCD_LP36 _L_(1) -#define PINMUX_PC16B_SLCD_LP36 ((PIN_PC16B_SLCD_LP36 << 16) | MUX_PC16B_SLCD_LP36) -#define PORT_PC16B_SLCD_LP36 (_UL_(1) << 16) -#define PIN_PC17B_SLCD_LP37 _L_(81) /**< \brief SLCD signal: LP37 on PC17 mux B */ -#define MUX_PC17B_SLCD_LP37 _L_(1) -#define PINMUX_PC17B_SLCD_LP37 ((PIN_PC17B_SLCD_LP37 << 16) | MUX_PC17B_SLCD_LP37) -#define PORT_PC17B_SLCD_LP37 (_UL_(1) << 17) -#define PIN_PC18B_SLCD_LP38 _L_(82) /**< \brief SLCD signal: LP38 on PC18 mux B */ -#define MUX_PC18B_SLCD_LP38 _L_(1) -#define PINMUX_PC18B_SLCD_LP38 ((PIN_PC18B_SLCD_LP38 << 16) | MUX_PC18B_SLCD_LP38) -#define PORT_PC18B_SLCD_LP38 (_UL_(1) << 18) -#define PIN_PC19B_SLCD_LP39 _L_(83) /**< \brief SLCD signal: LP39 on PC19 mux B */ -#define MUX_PC19B_SLCD_LP39 _L_(1) -#define PINMUX_PC19B_SLCD_LP39 ((PIN_PC19B_SLCD_LP39 << 16) | MUX_PC19B_SLCD_LP39) -#define PORT_PC19B_SLCD_LP39 (_UL_(1) << 19) -#define PIN_PC20B_SLCD_LP40 _L_(84) /**< \brief SLCD signal: LP40 on PC20 mux B */ -#define MUX_PC20B_SLCD_LP40 _L_(1) -#define PINMUX_PC20B_SLCD_LP40 ((PIN_PC20B_SLCD_LP40 << 16) | MUX_PC20B_SLCD_LP40) -#define PORT_PC20B_SLCD_LP40 (_UL_(1) << 20) -#define PIN_PC21B_SLCD_LP41 _L_(85) /**< \brief SLCD signal: LP41 on PC21 mux B */ -#define MUX_PC21B_SLCD_LP41 _L_(1) -#define PINMUX_PC21B_SLCD_LP41 ((PIN_PC21B_SLCD_LP41 << 16) | MUX_PC21B_SLCD_LP41) -#define PORT_PC21B_SLCD_LP41 (_UL_(1) << 21) -#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ -#define MUX_PB16B_SLCD_LP42 _L_(1) -#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) -#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) -#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ -#define MUX_PB17B_SLCD_LP43 _L_(1) -#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) -#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) -#define PIN_PB18B_SLCD_LP44 _L_(50) /**< \brief SLCD signal: LP44 on PB18 mux B */ -#define MUX_PB18B_SLCD_LP44 _L_(1) -#define PINMUX_PB18B_SLCD_LP44 ((PIN_PB18B_SLCD_LP44 << 16) | MUX_PB18B_SLCD_LP44) -#define PORT_PB18B_SLCD_LP44 (_UL_(1) << 18) -#define PIN_PB19B_SLCD_LP45 _L_(51) /**< \brief SLCD signal: LP45 on PB19 mux B */ -#define MUX_PB19B_SLCD_LP45 _L_(1) -#define PINMUX_PB19B_SLCD_LP45 ((PIN_PB19B_SLCD_LP45 << 16) | MUX_PB19B_SLCD_LP45) -#define PORT_PB19B_SLCD_LP45 (_UL_(1) << 19) -#define PIN_PB20B_SLCD_LP46 _L_(52) /**< \brief SLCD signal: LP46 on PB20 mux B */ -#define MUX_PB20B_SLCD_LP46 _L_(1) -#define PINMUX_PB20B_SLCD_LP46 ((PIN_PB20B_SLCD_LP46 << 16) | MUX_PB20B_SLCD_LP46) -#define PORT_PB20B_SLCD_LP46 (_UL_(1) << 20) -#define PIN_PB21B_SLCD_LP47 _L_(53) /**< \brief SLCD signal: LP47 on PB21 mux B */ -#define MUX_PB21B_SLCD_LP47 _L_(1) -#define PINMUX_PB21B_SLCD_LP47 ((PIN_PB21B_SLCD_LP47 << 16) | MUX_PB21B_SLCD_LP47) -#define PORT_PB21B_SLCD_LP47 (_UL_(1) << 21) -#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ -#define MUX_PA20B_SLCD_LP48 _L_(1) -#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) -#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) -#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ -#define MUX_PA21B_SLCD_LP49 _L_(1) -#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) -#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) -#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ -#define MUX_PA22B_SLCD_LP50 _L_(1) -#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) -#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) -#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ -#define MUX_PA23B_SLCD_LP51 _L_(1) -#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) -#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 _L_(8) -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 _L_(8) -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 _L_(8) -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 _L_(8) -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 _L_(8) -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ -#define MUX_PB00I_CCL_IN1 _L_(8) -#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) -#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 _L_(8) -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 _L_(8) -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ -#define MUX_PB01I_CCL_IN2 _L_(8) -#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) -#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 _L_(8) -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 _L_(8) -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 _L_(8) -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27I_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux I */ -#define MUX_PC27I_CCL_IN4 _L_(8) -#define PINMUX_PC27I_CCL_IN4 ((PIN_PC27I_CCL_IN4 << 16) | MUX_PC27I_CCL_IN4) -#define PORT_PC27I_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 _L_(8) -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28I_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux I */ -#define MUX_PC28I_CCL_IN5 _L_(8) -#define PINMUX_PC28I_CCL_IN5 ((PIN_PC28I_CCL_IN5 << 16) | MUX_PC28I_CCL_IN5) -#define PORT_PC28I_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 _L_(8) -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ -#define MUX_PB06I_CCL_IN6 _L_(8) -#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) -#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 _L_(8) -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ -#define MUX_PB07I_CCL_IN7 _L_(8) -#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) -#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 _L_(8) -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 _L_(8) -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ -#define MUX_PB14I_CCL_IN9 _L_(8) -#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) -#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20I_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux I */ -#define MUX_PC20I_CCL_IN9 _L_(8) -#define PINMUX_PC20I_CCL_IN9 ((PIN_PC20I_CCL_IN9 << 16) | MUX_PC20I_CCL_IN9) -#define PORT_PC20I_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ -#define MUX_PB15I_CCL_IN10 _L_(8) -#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) -#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21I_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux I */ -#define MUX_PC21I_CCL_IN10 _L_(8) -#define PINMUX_PC21I_CCL_IN10 ((PIN_PC21I_CCL_IN10 << 16) | MUX_PC21I_CCL_IN10) -#define PORT_PC21I_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ -#define MUX_PB16I_CCL_IN11 _L_(8) -#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) -#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 _L_(8) -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 _L_(8) -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 _L_(8) -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 _L_(8) -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 _L_(8) -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 _L_(8) -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 _L_(8) -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 _L_(8) -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 _L_(8) -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ -#define MUX_PB17I_CCL_OUT3 _L_(8) -#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) -#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) - -#endif /* _SAML22N16A_PIO_ */ diff --git a/watch-library/include/pio/saml22n17a.h b/watch-library/include/pio/saml22n17a.h deleted file mode 100644 index b7c98cd0..00000000 --- a/watch-library/include/pio/saml22n17a.h +++ /dev/null @@ -1,1851 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML22N17A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22N17A_PIO_ -#define _SAML22N17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC08 72 /**< \brief Pin Number for PC08 */ -#define PORT_PC08 (_UL_(1) << 8) /**< \brief PORT Mask for PC08 */ -#define PIN_PC09 73 /**< \brief Pin Number for PC09 */ -#define PORT_PC09 (_UL_(1) << 9) /**< \brief PORT Mask for PC09 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ -#define MUX_PB01H_SUPC_OUT0 _L_(7) -#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) -#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) -#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 _L_(7) -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) -#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ -#define MUX_PB00H_SUPC_PSOK _L_(7) -#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) -#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) -#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT _L_(7) -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 _L_(7) -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 _L_(7) -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 _L_(7) -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 _L_(7) -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) -#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 _L_(7) -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 _L_(7) -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 _L_(7) -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 _L_(7) -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 _L_(7) -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 _L_(7) -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 _L_(7) -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 _L_(7) -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 _L_(7) -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 _L_(7) -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) -/* ========== PORT definition for RTC peripheral ========== */ -#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ -#define MUX_PB00G_RTC_IN0 _L_(6) -#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) -#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) -#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ -#define MUX_PB02G_RTC_IN1 _L_(6) -#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) -#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) -#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ -#define MUX_PA02G_RTC_IN2 _L_(6) -#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) -#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) -#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ -#define MUX_PB01F_RTC_IN2 _L_(5) -#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) -#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) -#define PIN_PC00G_RTC_IN3 _L_(64) /**< \brief RTC signal: IN3 on PC00 mux G */ -#define MUX_PC00G_RTC_IN3 _L_(6) -#define PINMUX_PC00G_RTC_IN3 ((PIN_PC00G_RTC_IN3 << 16) | MUX_PC00G_RTC_IN3) -#define PORT_PC00G_RTC_IN3 (_UL_(1) << 0) -#define PIN_PC01G_RTC_IN4 _L_(65) /**< \brief RTC signal: IN4 on PC01 mux G */ -#define MUX_PC01G_RTC_IN4 _L_(6) -#define PINMUX_PC01G_RTC_IN4 ((PIN_PC01G_RTC_IN4 << 16) | MUX_PC01G_RTC_IN4) -#define PORT_PC01G_RTC_IN4 (_UL_(1) << 1) -#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ -#define MUX_PB01G_RTC_OUT _L_(6) -#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) -#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC08A_EIC_EXTINT0 _L_(72) /**< \brief EIC signal: EXTINT0 on PC08 mux A */ -#define MUX_PC08A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC08A_EIC_EXTINT0 ((PIN_PC08A_EIC_EXTINT0 << 16) | MUX_PC08A_EIC_EXTINT0) -#define PORT_PC08A_EIC_EXTINT0 (_UL_(1) << 8) -#define PIN_PC08A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC08 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT0 _L_(88) /**< \brief EIC signal: EXTINT0 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT0 ((PIN_PC24A_EIC_EXTINT0 << 16) | MUX_PC24A_EIC_EXTINT0) -#define PORT_PC24A_EIC_EXTINT0 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC09A_EIC_EXTINT1 _L_(73) /**< \brief EIC signal: EXTINT1 on PC09 mux A */ -#define MUX_PC09A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC09A_EIC_EXTINT1 ((PIN_PC09A_EIC_EXTINT1 << 16) | MUX_PC09A_EIC_EXTINT1) -#define PORT_PC09A_EIC_EXTINT1 (_UL_(1) << 9) -#define PIN_PC09A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC09 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT1 _L_(89) /**< \brief EIC signal: EXTINT1 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT1 ((PIN_PC25A_EIC_EXTINT1 << 16) | MUX_PC25A_EIC_EXTINT1) -#define PORT_PC25A_EIC_EXTINT1 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT2 _L_(74) /**< \brief EIC signal: EXTINT2 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT2 ((PIN_PC10A_EIC_EXTINT2 << 16) | MUX_PC10A_EIC_EXTINT2) -#define PORT_PC10A_EIC_EXTINT2 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT2 _L_(90) /**< \brief EIC signal: EXTINT2 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT2 ((PIN_PC26A_EIC_EXTINT2 << 16) | MUX_PC26A_EIC_EXTINT2) -#define PORT_PC26A_EIC_EXTINT2 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT3 _L_(75) /**< \brief EIC signal: EXTINT3 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT3 ((PIN_PC11A_EIC_EXTINT3 << 16) | MUX_PC11A_EIC_EXTINT3) -#define PORT_PC11A_EIC_EXTINT3 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT3 _L_(91) /**< \brief EIC signal: EXTINT3 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT3 ((PIN_PC27A_EIC_EXTINT3 << 16) | MUX_PC27A_EIC_EXTINT3) -#define PORT_PC27A_EIC_EXTINT3 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT4 _L_(76) /**< \brief EIC signal: EXTINT4 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT4 ((PIN_PC12A_EIC_EXTINT4 << 16) | MUX_PC12A_EIC_EXTINT4) -#define PORT_PC12A_EIC_EXTINT4 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT4 _L_(92) /**< \brief EIC signal: EXTINT4 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT4 ((PIN_PC28A_EIC_EXTINT4 << 16) | MUX_PC28A_EIC_EXTINT4) -#define PORT_PC28A_EIC_EXTINT4 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT5 _L_(77) /**< \brief EIC signal: EXTINT5 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT5 ((PIN_PC13A_EIC_EXTINT5 << 16) | MUX_PC13A_EIC_EXTINT5) -#define PORT_PC13A_EIC_EXTINT5 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT6 _L_(78) /**< \brief EIC signal: EXTINT6 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT6 ((PIN_PC14A_EIC_EXTINT6 << 16) | MUX_PC14A_EIC_EXTINT6) -#define PORT_PC14A_EIC_EXTINT6 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT7 _L_(79) /**< \brief EIC signal: EXTINT7 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT7 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT7 ((PIN_PC15A_EIC_EXTINT7 << 16) | MUX_PC15A_EIC_EXTINT7) -#define PORT_PC15A_EIC_EXTINT7 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT8 _L_(64) /**< \brief EIC signal: EXTINT8 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT8 ((PIN_PC00A_EIC_EXTINT8 << 16) | MUX_PC00A_EIC_EXTINT8) -#define PORT_PC00A_EIC_EXTINT8 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT8 _L_(80) /**< \brief EIC signal: EXTINT8 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT8 ((PIN_PC16A_EIC_EXTINT8 << 16) | MUX_PC16A_EIC_EXTINT8) -#define PORT_PC16A_EIC_EXTINT8 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT9 _L_(65) /**< \brief EIC signal: EXTINT9 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT9 ((PIN_PC01A_EIC_EXTINT9 << 16) | MUX_PC01A_EIC_EXTINT9) -#define PORT_PC01A_EIC_EXTINT9 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT9 _L_(81) /**< \brief EIC signal: EXTINT9 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT9 ((PIN_PC17A_EIC_EXTINT9 << 16) | MUX_PC17A_EIC_EXTINT9) -#define PORT_PC17A_EIC_EXTINT9 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT10 _L_(66) /**< \brief EIC signal: EXTINT10 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT10 ((PIN_PC02A_EIC_EXTINT10 << 16) | MUX_PC02A_EIC_EXTINT10) -#define PORT_PC02A_EIC_EXTINT10 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT10 _L_(82) /**< \brief EIC signal: EXTINT10 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT10 ((PIN_PC18A_EIC_EXTINT10 << 16) | MUX_PC18A_EIC_EXTINT10) -#define PORT_PC18A_EIC_EXTINT10 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT11 _L_(67) /**< \brief EIC signal: EXTINT11 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT11 ((PIN_PC03A_EIC_EXTINT11 << 16) | MUX_PC03A_EIC_EXTINT11) -#define PORT_PC03A_EIC_EXTINT11 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT11 _L_(83) /**< \brief EIC signal: EXTINT11 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT11 ((PIN_PC19A_EIC_EXTINT11 << 16) | MUX_PC19A_EIC_EXTINT11) -#define PORT_PC19A_EIC_EXTINT11 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT12 _L_(84) /**< \brief EIC signal: EXTINT12 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT12 ((PIN_PC20A_EIC_EXTINT12 << 16) | MUX_PC20A_EIC_EXTINT12) -#define PORT_PC20A_EIC_EXTINT12 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT13 _L_(69) /**< \brief EIC signal: EXTINT13 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT13 ((PIN_PC05A_EIC_EXTINT13 << 16) | MUX_PC05A_EIC_EXTINT13) -#define PORT_PC05A_EIC_EXTINT13 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT13 _L_(85) /**< \brief EIC signal: EXTINT13 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT13 ((PIN_PC21A_EIC_EXTINT13 << 16) | MUX_PC21A_EIC_EXTINT13) -#define PORT_PC21A_EIC_EXTINT13 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT14 _L_(70) /**< \brief EIC signal: EXTINT14 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT14 ((PIN_PC06A_EIC_EXTINT14 << 16) | MUX_PC06A_EIC_EXTINT14) -#define PORT_PC06A_EIC_EXTINT14 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT15 _L_(71) /**< \brief EIC signal: EXTINT15 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT15 ((PIN_PC07A_EIC_EXTINT15 << 16) | MUX_PC07A_EIC_EXTINT15) -#define PORT_PC07A_EIC_EXTINT15 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM _L_(6) -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (_UL_(1) << 24) -#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP _L_(6) -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (_UL_(1) << 25) -#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ -#define MUX_PB22G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) -#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ -#define MUX_PA20C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) -#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ -#define MUX_PA21C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) -#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ -#define MUX_PA22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) -#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) -#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ -#define MUX_PA23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) -#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) -#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) -#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PC27D_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux D */ -#define MUX_PC27D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PC27D_SERCOM1_PAD0 ((PIN_PC27D_SERCOM1_PAD0 << 16) | MUX_PC27D_SERCOM1_PAD0) -#define PORT_PC27D_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC12C_SERCOM1_PAD0 _L_(76) /**< \brief SERCOM1 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM1_PAD0 ((PIN_PC12C_SERCOM1_PAD0 << 16) | MUX_PC12C_SERCOM1_PAD0) -#define PORT_PC12C_SERCOM1_PAD0 (_UL_(1) << 12) -#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) -#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PC28D_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux D */ -#define MUX_PC28D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PC28D_SERCOM1_PAD1 ((PIN_PC28D_SERCOM1_PAD1 << 16) | MUX_PC28D_SERCOM1_PAD1) -#define PORT_PC28D_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC13C_SERCOM1_PAD1 _L_(77) /**< \brief SERCOM1 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM1_PAD1 ((PIN_PC13C_SERCOM1_PAD1 << 16) | MUX_PC13C_SERCOM1_PAD1) -#define PORT_PC13C_SERCOM1_PAD1 (_UL_(1) << 13) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PC10C_SERCOM1_PAD2 _L_(74) /**< \brief SERCOM1 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM1_PAD2 ((PIN_PC10C_SERCOM1_PAD2 << 16) | MUX_PC10C_SERCOM1_PAD2) -#define PORT_PC10C_SERCOM1_PAD2 (_UL_(1) << 10) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PC11C_SERCOM1_PAD3 _L_(75) /**< \brief SERCOM1 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM1_PAD3 ((PIN_PC11C_SERCOM1_PAD3 << 16) | MUX_PC11C_SERCOM1_PAD3) -#define PORT_PC11C_SERCOM1_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) -#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) -#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) -#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) -#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) -#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) -#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) -#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) -#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) -#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) -#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) -#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) -#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) -#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) -#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) -#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) -#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) -#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ -#define MUX_PB02C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) -#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) -#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) -#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) -#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) -#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ -#define MUX_PB03C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) -#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) -#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) -#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PB18D_SERCOM3_PAD2 _L_(50) /**< \brief SERCOM3 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM3_PAD2 ((PIN_PB18D_SERCOM3_PAD2 << 16) | MUX_PB18D_SERCOM3_PAD2) -#define PORT_PB18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ -#define MUX_PB00C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) -#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) -#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) -#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) -#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) -#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) -#define PIN_PB19D_SERCOM3_PAD3 _L_(51) /**< \brief SERCOM3 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM3_PAD3 ((PIN_PB19D_SERCOM3_PAD3 << 16) | MUX_PB19D_SERCOM3_PAD3) -#define PORT_PB19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ -#define MUX_PB01C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) -#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA08D_SERCOM4_PAD0 _L_(8) /**< \brief SERCOM4 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA08D_SERCOM4_PAD0 ((PIN_PA08D_SERCOM4_PAD0 << 16) | MUX_PA08D_SERCOM4_PAD0) -#define PORT_PA08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM4_PAD0 _L_(56) /**< \brief SERCOM4 signal: PAD0 on PB24 mux D */ -#define MUX_PB24D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB24D_SERCOM4_PAD0 ((PIN_PB24D_SERCOM4_PAD0 << 16) | MUX_PB24D_SERCOM4_PAD0) -#define PORT_PB24D_SERCOM4_PAD0 (_UL_(1) << 24) -#define PIN_PA12C_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM4_PAD0 ((PIN_PA12C_SERCOM4_PAD0 << 16) | MUX_PA12C_SERCOM4_PAD0) -#define PORT_PA12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA09D_SERCOM4_PAD1 _L_(9) /**< \brief SERCOM4 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA09D_SERCOM4_PAD1 ((PIN_PA09D_SERCOM4_PAD1 << 16) | MUX_PA09D_SERCOM4_PAD1) -#define PORT_PA09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM4_PAD1 _L_(57) /**< \brief SERCOM4 signal: PAD1 on PB25 mux D */ -#define MUX_PB25D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB25D_SERCOM4_PAD1 ((PIN_PB25D_SERCOM4_PAD1 << 16) | MUX_PB25D_SERCOM4_PAD1) -#define PORT_PB25D_SERCOM4_PAD1 (_UL_(1) << 25) -#define PIN_PA13C_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM4_PAD1 ((PIN_PA13C_SERCOM4_PAD1 << 16) | MUX_PA13C_SERCOM4_PAD1) -#define PORT_PA13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM4_PAD2 _L_(10) /**< \brief SERCOM4 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM4_PAD2 ((PIN_PA10D_SERCOM4_PAD2 << 16) | MUX_PA10D_SERCOM4_PAD2) -#define PORT_PA10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM4_PAD2 _L_(88) /**< \brief SERCOM4 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM4_PAD2 ((PIN_PC24D_SERCOM4_PAD2 << 16) | MUX_PC24D_SERCOM4_PAD2) -#define PORT_PC24D_SERCOM4_PAD2 (_UL_(1) << 24) -#define PIN_PA14C_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM4_PAD2 ((PIN_PA14C_SERCOM4_PAD2 << 16) | MUX_PA14C_SERCOM4_PAD2) -#define PORT_PA14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM4_PAD3 _L_(11) /**< \brief SERCOM4 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM4_PAD3 ((PIN_PA11D_SERCOM4_PAD3 << 16) | MUX_PA11D_SERCOM4_PAD3) -#define PORT_PA11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM4_PAD3 _L_(89) /**< \brief SERCOM4 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM4_PAD3 ((PIN_PC25D_SERCOM4_PAD3 << 16) | MUX_PC25D_SERCOM4_PAD3) -#define PORT_PC25D_SERCOM4_PAD3 (_UL_(1) << 25) -#define PIN_PA15C_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM4_PAD3 ((PIN_PA15C_SERCOM4_PAD3 << 16) | MUX_PA15C_SERCOM4_PAD3) -#define PORT_PA15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) -#define PIN_PA24D_SERCOM5_PAD0 _L_(24) /**< \brief SERCOM5 signal: PAD0 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD0 ((PIN_PA24D_SERCOM5_PAD0 << 16) | MUX_PA24D_SERCOM5_PAD0) -#define PORT_PA24D_SERCOM5_PAD0 (_UL_(1) << 24) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB20D_SERCOM5_PAD0 _L_(52) /**< \brief SERCOM5 signal: PAD0 on PB20 mux D */ -#define MUX_PB20D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB20D_SERCOM5_PAD0 ((PIN_PB20D_SERCOM5_PAD0 << 16) | MUX_PB20D_SERCOM5_PAD0) -#define PORT_PB20D_SERCOM5_PAD0 (_UL_(1) << 20) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) -#define PIN_PA25D_SERCOM5_PAD1 _L_(25) /**< \brief SERCOM5 signal: PAD1 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD1 ((PIN_PA25D_SERCOM5_PAD1 << 16) | MUX_PA25D_SERCOM5_PAD1) -#define PORT_PA25D_SERCOM5_PAD1 (_UL_(1) << 25) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB21D_SERCOM5_PAD1 _L_(53) /**< \brief SERCOM5 signal: PAD1 on PB21 mux D */ -#define MUX_PB21D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB21D_SERCOM5_PAD1 ((PIN_PB21D_SERCOM5_PAD1 << 16) | MUX_PB21D_SERCOM5_PAD1) -#define PORT_PB21D_SERCOM5_PAD1 (_UL_(1) << 21) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ -#define MUX_PA24F_TCC0_WO0 _L_(5) -#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) -#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PB18F_TCC0_WO0 _L_(50) /**< \brief TCC0 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC0_WO0 _L_(5) -#define PINMUX_PB18F_TCC0_WO0 ((PIN_PB18F_TCC0_WO0 << 16) | MUX_PB18F_TCC0_WO0) -#define PORT_PB18F_TCC0_WO0 (_UL_(1) << 18) -#define PIN_PC24F_TCC0_WO0 _L_(88) /**< \brief TCC0 signal: WO0 on PC24 mux F */ -#define MUX_PC24F_TCC0_WO0 _L_(5) -#define PINMUX_PC24F_TCC0_WO0 ((PIN_PC24F_TCC0_WO0 << 16) | MUX_PC24F_TCC0_WO0) -#define PORT_PC24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 _L_(4) -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 _L_(4) -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 _L_(4) -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) -#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ -#define MUX_PA25F_TCC0_WO1 _L_(5) -#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) -#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PB19F_TCC0_WO1 _L_(51) /**< \brief TCC0 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC0_WO1 _L_(5) -#define PINMUX_PB19F_TCC0_WO1 ((PIN_PB19F_TCC0_WO1 << 16) | MUX_PB19F_TCC0_WO1) -#define PORT_PB19F_TCC0_WO1 (_UL_(1) << 19) -#define PIN_PC25F_TCC0_WO1 _L_(89) /**< \brief TCC0 signal: WO1 on PC25 mux F */ -#define MUX_PC25F_TCC0_WO1 _L_(5) -#define PINMUX_PC25F_TCC0_WO1 ((PIN_PC25F_TCC0_WO1 << 16) | MUX_PC25F_TCC0_WO1) -#define PORT_PC25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 _L_(4) -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 _L_(4) -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 _L_(4) -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 _L_(5) -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC0_WO2 _L_(52) /**< \brief TCC0 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC0_WO2 _L_(5) -#define PINMUX_PB20F_TCC0_WO2 ((PIN_PB20F_TCC0_WO2 << 16) | MUX_PB20F_TCC0_WO2) -#define PORT_PB20F_TCC0_WO2 (_UL_(1) << 20) -#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ -#define MUX_PB22F_TCC0_WO2 _L_(5) -#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) -#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PC26F_TCC0_WO2 _L_(90) /**< \brief TCC0 signal: WO2 on PC26 mux F */ -#define MUX_PC26F_TCC0_WO2 _L_(5) -#define PINMUX_PC26F_TCC0_WO2 ((PIN_PC26F_TCC0_WO2 << 16) | MUX_PC26F_TCC0_WO2) -#define PORT_PC26F_TCC0_WO2 (_UL_(1) << 26) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 _L_(5) -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC0_WO3 _L_(53) /**< \brief TCC0 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC0_WO3 _L_(5) -#define PINMUX_PB21F_TCC0_WO3 ((PIN_PB21F_TCC0_WO3 << 16) | MUX_PB21F_TCC0_WO3) -#define PORT_PB21F_TCC0_WO3 (_UL_(1) << 21) -#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ -#define MUX_PB23F_TCC0_WO3 _L_(5) -#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) -#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PC27F_TCC0_WO3 _L_(91) /**< \brief TCC0 signal: WO3 on PC27 mux F */ -#define MUX_PC27F_TCC0_WO3 _L_(5) -#define PINMUX_PC27F_TCC0_WO3 ((PIN_PC27F_TCC0_WO3 << 16) | MUX_PC27F_TCC0_WO3) -#define PORT_PC27F_TCC0_WO3 (_UL_(1) << 27) -#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 _L_(5) -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) -#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 _L_(5) -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PC28F_TCC0_WO4 _L_(92) /**< \brief TCC0 signal: WO4 on PC28 mux F */ -#define MUX_PC28F_TCC0_WO4 _L_(5) -#define PINMUX_PC28F_TCC0_WO4 ((PIN_PC28F_TCC0_WO4 << 16) | MUX_PC28F_TCC0_WO4) -#define PORT_PC28F_TCC0_WO4 (_UL_(1) << 28) -#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 _L_(5) -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 _L_(5) -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 _L_(5) -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) -#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ -#define MUX_PA27F_TCC0_WO5 _L_(5) -#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) -#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 _L_(5) -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 _L_(5) -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) -#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 _L_(5) -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) -#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 _L_(5) -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PB24F_TCC0_WO6 _L_(56) /**< \brief TCC0 signal: WO6 on PB24 mux F */ -#define MUX_PB24F_TCC0_WO6 _L_(5) -#define PINMUX_PB24F_TCC0_WO6 ((PIN_PB24F_TCC0_WO6 << 16) | MUX_PB24F_TCC0_WO6) -#define PORT_PB24F_TCC0_WO6 (_UL_(1) << 24) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 _L_(5) -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) -#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 _L_(5) -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) -#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 _L_(5) -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PB25F_TCC0_WO7 _L_(57) /**< \brief TCC0 signal: WO7 on PB25 mux F */ -#define MUX_PB25F_TCC0_WO7 _L_(5) -#define PINMUX_PB25F_TCC0_WO7 ((PIN_PB25F_TCC0_WO7 << 16) | MUX_PB25F_TCC0_WO7) -#define PORT_PB25F_TCC0_WO7 (_UL_(1) << 25) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 _L_(4) -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 _L_(4) -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC0_WO0 _L_(4) -#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) -#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 _L_(4) -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 _L_(4) -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC0_WO1 _L_(4) -#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) -#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 _L_(4) -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) -#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC1_WO0 _L_(4) -#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) -#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 _L_(4) -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 _L_(4) -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC1_WO1 _L_(4) -#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) -#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 _L_(4) -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC2_WO0 _L_(4) -#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) -#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PC24E_TC2_WO0 _L_(88) /**< \brief TC2 signal: WO0 on PC24 mux E */ -#define MUX_PC24E_TC2_WO0 _L_(4) -#define PINMUX_PC24E_TC2_WO0 ((PIN_PC24E_TC2_WO0 << 16) | MUX_PC24E_TC2_WO0) -#define PORT_PC24E_TC2_WO0 (_UL_(1) << 24) -#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 _L_(4) -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC2_WO1 _L_(4) -#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) -#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) -#define PIN_PC25E_TC2_WO1 _L_(89) /**< \brief TC2 signal: WO1 on PC25 mux E */ -#define MUX_PC25E_TC2_WO1 _L_(4) -#define PINMUX_PC25E_TC2_WO1 ((PIN_PC25E_TC2_WO1 << 16) | MUX_PC25E_TC2_WO1) -#define PORT_PC25E_TC2_WO1 (_UL_(1) << 25) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 _L_(4) -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC3_WO0 _L_(4) -#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) -#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 _L_(4) -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) -#define PIN_PC26E_TC3_WO0 _L_(90) /**< \brief TC3 signal: WO0 on PC26 mux E */ -#define MUX_PC26E_TC3_WO0 _L_(4) -#define PINMUX_PC26E_TC3_WO0 ((PIN_PC26E_TC3_WO0 << 16) | MUX_PC26E_TC3_WO0) -#define PORT_PC26E_TC3_WO0 (_UL_(1) << 26) -#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 _L_(4) -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC3_WO1 _L_(4) -#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) -#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 _L_(4) -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) -#define PIN_PC27E_TC3_WO1 _L_(91) /**< \brief TC3 signal: WO1 on PC27 mux E */ -#define MUX_PC27E_TC3_WO1 _L_(4) -#define PINMUX_PC27E_TC3_WO1 ((PIN_PC27E_TC3_WO1 << 16) | MUX_PC27E_TC3_WO1) -#define PORT_PC27E_TC3_WO1 (_UL_(1) << 27) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 _L_(1) -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 _L_(1) -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 _L_(1) -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 _L_(1) -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 _L_(1) -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 _L_(1) -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 _L_(1) -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 _L_(1) -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) -#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 _L_(1) -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) -#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 _L_(1) -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) -#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 _L_(1) -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) -#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 _L_(1) -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) -#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 _L_(1) -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) -#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 _L_(1) -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) -#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 _L_(1) -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) -#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 _L_(1) -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) -#define PIN_PC00B_ADC_AIN16 _L_(64) /**< \brief ADC signal: AIN16 on PC00 mux B */ -#define MUX_PC00B_ADC_AIN16 _L_(1) -#define PINMUX_PC00B_ADC_AIN16 ((PIN_PC00B_ADC_AIN16 << 16) | MUX_PC00B_ADC_AIN16) -#define PORT_PC00B_ADC_AIN16 (_UL_(1) << 0) -#define PIN_PC01B_ADC_AIN17 _L_(65) /**< \brief ADC signal: AIN17 on PC01 mux B */ -#define MUX_PC01B_ADC_AIN17 _L_(1) -#define PINMUX_PC01B_ADC_AIN17 ((PIN_PC01B_ADC_AIN17 << 16) | MUX_PC01B_ADC_AIN17) -#define PORT_PC01B_ADC_AIN17 (_UL_(1) << 1) -#define PIN_PC02B_ADC_AIN18 _L_(66) /**< \brief ADC signal: AIN18 on PC02 mux B */ -#define MUX_PC02B_ADC_AIN18 _L_(1) -#define PINMUX_PC02B_ADC_AIN18 ((PIN_PC02B_ADC_AIN18 << 16) | MUX_PC02B_ADC_AIN18) -#define PORT_PC02B_ADC_AIN18 (_UL_(1) << 2) -#define PIN_PC03B_ADC_AIN19 _L_(67) /**< \brief ADC signal: AIN19 on PC03 mux B */ -#define MUX_PC03B_ADC_AIN19 _L_(1) -#define PINMUX_PC03B_ADC_AIN19 ((PIN_PC03B_ADC_AIN19 << 16) | MUX_PC03B_ADC_AIN19) -#define PORT_PC03B_ADC_AIN19 (_UL_(1) << 3) -#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ -#define MUX_PA03B_ADC_VREFA _L_(1) -#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) -#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) -#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ -#define MUX_PA02B_ADC_VREFB _L_(1) -#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) -#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_AC_AIN0 _L_(1) -#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) -#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_AC_AIN1 _L_(1) -#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) -#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) -#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ -#define MUX_PB04B_AC_AIN2 _L_(1) -#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) -#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) -#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ -#define MUX_PB05B_AC_AIN3 _L_(1) -#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) -#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) -#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 _L_(7) -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 _L_(7) -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24H_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux H */ -#define MUX_PB24H_AC_CMP0 _L_(7) -#define PINMUX_PB24H_AC_CMP0 ((PIN_PB24H_AC_CMP0 << 16) | MUX_PB24H_AC_CMP0) -#define PORT_PB24H_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 _L_(7) -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 _L_(7) -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25H_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux H */ -#define MUX_PB25H_AC_CMP1 _L_(7) -#define PINMUX_PB25H_AC_CMP1 ((PIN_PB25H_AC_CMP1 << 16) | MUX_PB25H_AC_CMP1) -#define PORT_PB25H_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for SLCD peripheral ========== */ -#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ -#define MUX_PB06B_SLCD_LP0 _L_(1) -#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) -#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) -#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ -#define MUX_PB07B_SLCD_LP1 _L_(1) -#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) -#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) -#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ -#define MUX_PB08B_SLCD_LP2 _L_(1) -#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) -#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) -#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ -#define MUX_PB09B_SLCD_LP3 _L_(1) -#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) -#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) -#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ -#define MUX_PA04B_SLCD_LP4 _L_(1) -#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) -#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) -#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ -#define MUX_PA05B_SLCD_LP5 _L_(1) -#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) -#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) -#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ -#define MUX_PA06B_SLCD_LP6 _L_(1) -#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) -#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) -#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ -#define MUX_PA07B_SLCD_LP7 _L_(1) -#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) -#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) -#define PIN_PC05B_SLCD_LP8 _L_(69) /**< \brief SLCD signal: LP8 on PC05 mux B */ -#define MUX_PC05B_SLCD_LP8 _L_(1) -#define PINMUX_PC05B_SLCD_LP8 ((PIN_PC05B_SLCD_LP8 << 16) | MUX_PC05B_SLCD_LP8) -#define PORT_PC05B_SLCD_LP8 (_UL_(1) << 5) -#define PIN_PC06B_SLCD_LP9 _L_(70) /**< \brief SLCD signal: LP9 on PC06 mux B */ -#define MUX_PC06B_SLCD_LP9 _L_(1) -#define PINMUX_PC06B_SLCD_LP9 ((PIN_PC06B_SLCD_LP9 << 16) | MUX_PC06B_SLCD_LP9) -#define PORT_PC06B_SLCD_LP9 (_UL_(1) << 6) -#define PIN_PC07B_SLCD_LP10 _L_(71) /**< \brief SLCD signal: LP10 on PC07 mux B */ -#define MUX_PC07B_SLCD_LP10 _L_(1) -#define PINMUX_PC07B_SLCD_LP10 ((PIN_PC07B_SLCD_LP10 << 16) | MUX_PC07B_SLCD_LP10) -#define PORT_PC07B_SLCD_LP10 (_UL_(1) << 7) -#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ -#define MUX_PA08B_SLCD_LP11 _L_(1) -#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) -#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) -#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ -#define MUX_PA09B_SLCD_LP12 _L_(1) -#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) -#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) -#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ -#define MUX_PA10B_SLCD_LP13 _L_(1) -#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) -#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) -#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ -#define MUX_PA11B_SLCD_LP14 _L_(1) -#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) -#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) -#define PIN_PC08B_SLCD_LP15 _L_(72) /**< \brief SLCD signal: LP15 on PC08 mux B */ -#define MUX_PC08B_SLCD_LP15 _L_(1) -#define PINMUX_PC08B_SLCD_LP15 ((PIN_PC08B_SLCD_LP15 << 16) | MUX_PC08B_SLCD_LP15) -#define PORT_PC08B_SLCD_LP15 (_UL_(1) << 8) -#define PIN_PC09B_SLCD_LP16 _L_(73) /**< \brief SLCD signal: LP16 on PC09 mux B */ -#define MUX_PC09B_SLCD_LP16 _L_(1) -#define PINMUX_PC09B_SLCD_LP16 ((PIN_PC09B_SLCD_LP16 << 16) | MUX_PC09B_SLCD_LP16) -#define PORT_PC09B_SLCD_LP16 (_UL_(1) << 9) -#define PIN_PC10B_SLCD_LP17 _L_(74) /**< \brief SLCD signal: LP17 on PC10 mux B */ -#define MUX_PC10B_SLCD_LP17 _L_(1) -#define PINMUX_PC10B_SLCD_LP17 ((PIN_PC10B_SLCD_LP17 << 16) | MUX_PC10B_SLCD_LP17) -#define PORT_PC10B_SLCD_LP17 (_UL_(1) << 10) -#define PIN_PC11B_SLCD_LP18 _L_(75) /**< \brief SLCD signal: LP18 on PC11 mux B */ -#define MUX_PC11B_SLCD_LP18 _L_(1) -#define PINMUX_PC11B_SLCD_LP18 ((PIN_PC11B_SLCD_LP18 << 16) | MUX_PC11B_SLCD_LP18) -#define PORT_PC11B_SLCD_LP18 (_UL_(1) << 11) -#define PIN_PC12B_SLCD_LP19 _L_(76) /**< \brief SLCD signal: LP19 on PC12 mux B */ -#define MUX_PC12B_SLCD_LP19 _L_(1) -#define PINMUX_PC12B_SLCD_LP19 ((PIN_PC12B_SLCD_LP19 << 16) | MUX_PC12B_SLCD_LP19) -#define PORT_PC12B_SLCD_LP19 (_UL_(1) << 12) -#define PIN_PC13B_SLCD_LP20 _L_(77) /**< \brief SLCD signal: LP20 on PC13 mux B */ -#define MUX_PC13B_SLCD_LP20 _L_(1) -#define PINMUX_PC13B_SLCD_LP20 ((PIN_PC13B_SLCD_LP20 << 16) | MUX_PC13B_SLCD_LP20) -#define PORT_PC13B_SLCD_LP20 (_UL_(1) << 13) -#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ -#define MUX_PB11B_SLCD_LP21 _L_(1) -#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) -#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) -#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ -#define MUX_PB12B_SLCD_LP22 _L_(1) -#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) -#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) -#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ -#define MUX_PB13B_SLCD_LP23 _L_(1) -#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) -#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) -#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ -#define MUX_PB14B_SLCD_LP24 _L_(1) -#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) -#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) -#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ -#define MUX_PB15B_SLCD_LP25 _L_(1) -#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) -#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) -#define PIN_PC14B_SLCD_LP26 _L_(78) /**< \brief SLCD signal: LP26 on PC14 mux B */ -#define MUX_PC14B_SLCD_LP26 _L_(1) -#define PINMUX_PC14B_SLCD_LP26 ((PIN_PC14B_SLCD_LP26 << 16) | MUX_PC14B_SLCD_LP26) -#define PORT_PC14B_SLCD_LP26 (_UL_(1) << 14) -#define PIN_PC15B_SLCD_LP27 _L_(79) /**< \brief SLCD signal: LP27 on PC15 mux B */ -#define MUX_PC15B_SLCD_LP27 _L_(1) -#define PINMUX_PC15B_SLCD_LP27 ((PIN_PC15B_SLCD_LP27 << 16) | MUX_PC15B_SLCD_LP27) -#define PORT_PC15B_SLCD_LP27 (_UL_(1) << 15) -#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ -#define MUX_PA12B_SLCD_LP28 _L_(1) -#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) -#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) -#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ -#define MUX_PA13B_SLCD_LP29 _L_(1) -#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) -#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) -#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ -#define MUX_PA14B_SLCD_LP30 _L_(1) -#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) -#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) -#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ -#define MUX_PA15B_SLCD_LP31 _L_(1) -#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) -#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) -#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ -#define MUX_PA16B_SLCD_LP32 _L_(1) -#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) -#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) -#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ -#define MUX_PA17B_SLCD_LP33 _L_(1) -#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) -#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) -#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ -#define MUX_PA18B_SLCD_LP34 _L_(1) -#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) -#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) -#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ -#define MUX_PA19B_SLCD_LP35 _L_(1) -#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) -#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) -#define PIN_PC16B_SLCD_LP36 _L_(80) /**< \brief SLCD signal: LP36 on PC16 mux B */ -#define MUX_PC16B_SLCD_LP36 _L_(1) -#define PINMUX_PC16B_SLCD_LP36 ((PIN_PC16B_SLCD_LP36 << 16) | MUX_PC16B_SLCD_LP36) -#define PORT_PC16B_SLCD_LP36 (_UL_(1) << 16) -#define PIN_PC17B_SLCD_LP37 _L_(81) /**< \brief SLCD signal: LP37 on PC17 mux B */ -#define MUX_PC17B_SLCD_LP37 _L_(1) -#define PINMUX_PC17B_SLCD_LP37 ((PIN_PC17B_SLCD_LP37 << 16) | MUX_PC17B_SLCD_LP37) -#define PORT_PC17B_SLCD_LP37 (_UL_(1) << 17) -#define PIN_PC18B_SLCD_LP38 _L_(82) /**< \brief SLCD signal: LP38 on PC18 mux B */ -#define MUX_PC18B_SLCD_LP38 _L_(1) -#define PINMUX_PC18B_SLCD_LP38 ((PIN_PC18B_SLCD_LP38 << 16) | MUX_PC18B_SLCD_LP38) -#define PORT_PC18B_SLCD_LP38 (_UL_(1) << 18) -#define PIN_PC19B_SLCD_LP39 _L_(83) /**< \brief SLCD signal: LP39 on PC19 mux B */ -#define MUX_PC19B_SLCD_LP39 _L_(1) -#define PINMUX_PC19B_SLCD_LP39 ((PIN_PC19B_SLCD_LP39 << 16) | MUX_PC19B_SLCD_LP39) -#define PORT_PC19B_SLCD_LP39 (_UL_(1) << 19) -#define PIN_PC20B_SLCD_LP40 _L_(84) /**< \brief SLCD signal: LP40 on PC20 mux B */ -#define MUX_PC20B_SLCD_LP40 _L_(1) -#define PINMUX_PC20B_SLCD_LP40 ((PIN_PC20B_SLCD_LP40 << 16) | MUX_PC20B_SLCD_LP40) -#define PORT_PC20B_SLCD_LP40 (_UL_(1) << 20) -#define PIN_PC21B_SLCD_LP41 _L_(85) /**< \brief SLCD signal: LP41 on PC21 mux B */ -#define MUX_PC21B_SLCD_LP41 _L_(1) -#define PINMUX_PC21B_SLCD_LP41 ((PIN_PC21B_SLCD_LP41 << 16) | MUX_PC21B_SLCD_LP41) -#define PORT_PC21B_SLCD_LP41 (_UL_(1) << 21) -#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ -#define MUX_PB16B_SLCD_LP42 _L_(1) -#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) -#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) -#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ -#define MUX_PB17B_SLCD_LP43 _L_(1) -#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) -#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) -#define PIN_PB18B_SLCD_LP44 _L_(50) /**< \brief SLCD signal: LP44 on PB18 mux B */ -#define MUX_PB18B_SLCD_LP44 _L_(1) -#define PINMUX_PB18B_SLCD_LP44 ((PIN_PB18B_SLCD_LP44 << 16) | MUX_PB18B_SLCD_LP44) -#define PORT_PB18B_SLCD_LP44 (_UL_(1) << 18) -#define PIN_PB19B_SLCD_LP45 _L_(51) /**< \brief SLCD signal: LP45 on PB19 mux B */ -#define MUX_PB19B_SLCD_LP45 _L_(1) -#define PINMUX_PB19B_SLCD_LP45 ((PIN_PB19B_SLCD_LP45 << 16) | MUX_PB19B_SLCD_LP45) -#define PORT_PB19B_SLCD_LP45 (_UL_(1) << 19) -#define PIN_PB20B_SLCD_LP46 _L_(52) /**< \brief SLCD signal: LP46 on PB20 mux B */ -#define MUX_PB20B_SLCD_LP46 _L_(1) -#define PINMUX_PB20B_SLCD_LP46 ((PIN_PB20B_SLCD_LP46 << 16) | MUX_PB20B_SLCD_LP46) -#define PORT_PB20B_SLCD_LP46 (_UL_(1) << 20) -#define PIN_PB21B_SLCD_LP47 _L_(53) /**< \brief SLCD signal: LP47 on PB21 mux B */ -#define MUX_PB21B_SLCD_LP47 _L_(1) -#define PINMUX_PB21B_SLCD_LP47 ((PIN_PB21B_SLCD_LP47 << 16) | MUX_PB21B_SLCD_LP47) -#define PORT_PB21B_SLCD_LP47 (_UL_(1) << 21) -#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ -#define MUX_PA20B_SLCD_LP48 _L_(1) -#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) -#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) -#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ -#define MUX_PA21B_SLCD_LP49 _L_(1) -#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) -#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) -#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ -#define MUX_PA22B_SLCD_LP50 _L_(1) -#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) -#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) -#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ -#define MUX_PA23B_SLCD_LP51 _L_(1) -#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) -#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 _L_(8) -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 _L_(8) -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 _L_(8) -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 _L_(8) -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 _L_(8) -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ -#define MUX_PB00I_CCL_IN1 _L_(8) -#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) -#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 _L_(8) -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 _L_(8) -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ -#define MUX_PB01I_CCL_IN2 _L_(8) -#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) -#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 _L_(8) -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 _L_(8) -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 _L_(8) -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27I_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux I */ -#define MUX_PC27I_CCL_IN4 _L_(8) -#define PINMUX_PC27I_CCL_IN4 ((PIN_PC27I_CCL_IN4 << 16) | MUX_PC27I_CCL_IN4) -#define PORT_PC27I_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 _L_(8) -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28I_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux I */ -#define MUX_PC28I_CCL_IN5 _L_(8) -#define PINMUX_PC28I_CCL_IN5 ((PIN_PC28I_CCL_IN5 << 16) | MUX_PC28I_CCL_IN5) -#define PORT_PC28I_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 _L_(8) -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ -#define MUX_PB06I_CCL_IN6 _L_(8) -#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) -#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 _L_(8) -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ -#define MUX_PB07I_CCL_IN7 _L_(8) -#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) -#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 _L_(8) -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 _L_(8) -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ -#define MUX_PB14I_CCL_IN9 _L_(8) -#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) -#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20I_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux I */ -#define MUX_PC20I_CCL_IN9 _L_(8) -#define PINMUX_PC20I_CCL_IN9 ((PIN_PC20I_CCL_IN9 << 16) | MUX_PC20I_CCL_IN9) -#define PORT_PC20I_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ -#define MUX_PB15I_CCL_IN10 _L_(8) -#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) -#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21I_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux I */ -#define MUX_PC21I_CCL_IN10 _L_(8) -#define PINMUX_PC21I_CCL_IN10 ((PIN_PC21I_CCL_IN10 << 16) | MUX_PC21I_CCL_IN10) -#define PORT_PC21I_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ -#define MUX_PB16I_CCL_IN11 _L_(8) -#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) -#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 _L_(8) -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 _L_(8) -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 _L_(8) -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 _L_(8) -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 _L_(8) -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 _L_(8) -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 _L_(8) -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 _L_(8) -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 _L_(8) -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ -#define MUX_PB17I_CCL_OUT3 _L_(8) -#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) -#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) - -#endif /* _SAML22N17A_PIO_ */ diff --git a/watch-library/include/pio/saml22n18a.h b/watch-library/include/pio/saml22n18a.h deleted file mode 100644 index ad683b1d..00000000 --- a/watch-library/include/pio/saml22n18a.h +++ /dev/null @@ -1,1851 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAML22N18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22N18A_PIO_ -#define _SAML22N18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC08 72 /**< \brief Pin Number for PC08 */ -#define PORT_PC08 (_UL_(1) << 8) /**< \brief PORT Mask for PC08 */ -#define PIN_PC09 73 /**< \brief Pin Number for PC09 */ -#define PORT_PC09 (_UL_(1) << 9) /**< \brief PORT Mask for PC09 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -/* ========== PORT definition for SUPC peripheral ========== */ -#define PIN_PB01H_SUPC_OUT0 _L_(33) /**< \brief SUPC signal: OUT0 on PB01 mux H */ -#define MUX_PB01H_SUPC_OUT0 _L_(7) -#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) -#define PORT_PB01H_SUPC_OUT0 (_UL_(1) << 1) -#define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ -#define MUX_PB02H_SUPC_OUT1 _L_(7) -#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) -#define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) -#define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ -#define MUX_PB00H_SUPC_PSOK _L_(7) -#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) -#define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) -#define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ -#define MUX_PB03H_SUPC_VBAT _L_(7) -#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) -#define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 _L_(7) -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 _L_(7) -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 _L_(7) -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 _L_(7) -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) -#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 _L_(7) -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 _L_(7) -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 _L_(7) -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 _L_(7) -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 _L_(7) -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 _L_(7) -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 _L_(7) -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 _L_(7) -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 _L_(7) -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 _L_(7) -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) -/* ========== PORT definition for RTC peripheral ========== */ -#define PIN_PB00G_RTC_IN0 _L_(32) /**< \brief RTC signal: IN0 on PB00 mux G */ -#define MUX_PB00G_RTC_IN0 _L_(6) -#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0) -#define PORT_PB00G_RTC_IN0 (_UL_(1) << 0) -#define PIN_PB02G_RTC_IN1 _L_(34) /**< \brief RTC signal: IN1 on PB02 mux G */ -#define MUX_PB02G_RTC_IN1 _L_(6) -#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1) -#define PORT_PB02G_RTC_IN1 (_UL_(1) << 2) -#define PIN_PA02G_RTC_IN2 _L_(2) /**< \brief RTC signal: IN2 on PA02 mux G */ -#define MUX_PA02G_RTC_IN2 _L_(6) -#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2) -#define PORT_PA02G_RTC_IN2 (_UL_(1) << 2) -#define PIN_PB01F_RTC_IN2 _L_(33) /**< \brief RTC signal: IN2 on PB01 mux F */ -#define MUX_PB01F_RTC_IN2 _L_(5) -#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2) -#define PORT_PB01F_RTC_IN2 (_UL_(1) << 1) -#define PIN_PC00G_RTC_IN3 _L_(64) /**< \brief RTC signal: IN3 on PC00 mux G */ -#define MUX_PC00G_RTC_IN3 _L_(6) -#define PINMUX_PC00G_RTC_IN3 ((PIN_PC00G_RTC_IN3 << 16) | MUX_PC00G_RTC_IN3) -#define PORT_PC00G_RTC_IN3 (_UL_(1) << 0) -#define PIN_PC01G_RTC_IN4 _L_(65) /**< \brief RTC signal: IN4 on PC01 mux G */ -#define MUX_PC01G_RTC_IN4 _L_(6) -#define PINMUX_PC01G_RTC_IN4 ((PIN_PC01G_RTC_IN4 << 16) | MUX_PC01G_RTC_IN4) -#define PORT_PC01G_RTC_IN4 (_UL_(1) << 1) -#define PIN_PB01G_RTC_OUT _L_(33) /**< \brief RTC signal: OUT on PB01 mux G */ -#define MUX_PB01G_RTC_OUT _L_(6) -#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT) -#define PORT_PB01G_RTC_OUT (_UL_(1) << 1) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC08A_EIC_EXTINT0 _L_(72) /**< \brief EIC signal: EXTINT0 on PC08 mux A */ -#define MUX_PC08A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC08A_EIC_EXTINT0 ((PIN_PC08A_EIC_EXTINT0 << 16) | MUX_PC08A_EIC_EXTINT0) -#define PORT_PC08A_EIC_EXTINT0 (_UL_(1) << 8) -#define PIN_PC08A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC08 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT0 _L_(88) /**< \brief EIC signal: EXTINT0 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT0 ((PIN_PC24A_EIC_EXTINT0 << 16) | MUX_PC24A_EIC_EXTINT0) -#define PORT_PC24A_EIC_EXTINT0 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC09A_EIC_EXTINT1 _L_(73) /**< \brief EIC signal: EXTINT1 on PC09 mux A */ -#define MUX_PC09A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC09A_EIC_EXTINT1 ((PIN_PC09A_EIC_EXTINT1 << 16) | MUX_PC09A_EIC_EXTINT1) -#define PORT_PC09A_EIC_EXTINT1 (_UL_(1) << 9) -#define PIN_PC09A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC09 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT1 _L_(89) /**< \brief EIC signal: EXTINT1 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT1 ((PIN_PC25A_EIC_EXTINT1 << 16) | MUX_PC25A_EIC_EXTINT1) -#define PORT_PC25A_EIC_EXTINT1 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT2 _L_(74) /**< \brief EIC signal: EXTINT2 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT2 ((PIN_PC10A_EIC_EXTINT2 << 16) | MUX_PC10A_EIC_EXTINT2) -#define PORT_PC10A_EIC_EXTINT2 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT2 _L_(90) /**< \brief EIC signal: EXTINT2 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT2 ((PIN_PC26A_EIC_EXTINT2 << 16) | MUX_PC26A_EIC_EXTINT2) -#define PORT_PC26A_EIC_EXTINT2 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT3 _L_(75) /**< \brief EIC signal: EXTINT3 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT3 ((PIN_PC11A_EIC_EXTINT3 << 16) | MUX_PC11A_EIC_EXTINT3) -#define PORT_PC11A_EIC_EXTINT3 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT3 _L_(91) /**< \brief EIC signal: EXTINT3 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT3 ((PIN_PC27A_EIC_EXTINT3 << 16) | MUX_PC27A_EIC_EXTINT3) -#define PORT_PC27A_EIC_EXTINT3 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT4 _L_(76) /**< \brief EIC signal: EXTINT4 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT4 ((PIN_PC12A_EIC_EXTINT4 << 16) | MUX_PC12A_EIC_EXTINT4) -#define PORT_PC12A_EIC_EXTINT4 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT4 _L_(92) /**< \brief EIC signal: EXTINT4 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT4 ((PIN_PC28A_EIC_EXTINT4 << 16) | MUX_PC28A_EIC_EXTINT4) -#define PORT_PC28A_EIC_EXTINT4 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT5 _L_(77) /**< \brief EIC signal: EXTINT5 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT5 ((PIN_PC13A_EIC_EXTINT5 << 16) | MUX_PC13A_EIC_EXTINT5) -#define PORT_PC13A_EIC_EXTINT5 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT6 _L_(78) /**< \brief EIC signal: EXTINT6 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT6 ((PIN_PC14A_EIC_EXTINT6 << 16) | MUX_PC14A_EIC_EXTINT6) -#define PORT_PC14A_EIC_EXTINT6 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT7 _L_(79) /**< \brief EIC signal: EXTINT7 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT7 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT7 ((PIN_PC15A_EIC_EXTINT7 << 16) | MUX_PC15A_EIC_EXTINT7) -#define PORT_PC15A_EIC_EXTINT7 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT8 _L_(64) /**< \brief EIC signal: EXTINT8 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT8 ((PIN_PC00A_EIC_EXTINT8 << 16) | MUX_PC00A_EIC_EXTINT8) -#define PORT_PC00A_EIC_EXTINT8 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT8 _L_(80) /**< \brief EIC signal: EXTINT8 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT8 ((PIN_PC16A_EIC_EXTINT8 << 16) | MUX_PC16A_EIC_EXTINT8) -#define PORT_PC16A_EIC_EXTINT8 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT9 _L_(65) /**< \brief EIC signal: EXTINT9 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT9 ((PIN_PC01A_EIC_EXTINT9 << 16) | MUX_PC01A_EIC_EXTINT9) -#define PORT_PC01A_EIC_EXTINT9 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT9 _L_(81) /**< \brief EIC signal: EXTINT9 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT9 ((PIN_PC17A_EIC_EXTINT9 << 16) | MUX_PC17A_EIC_EXTINT9) -#define PORT_PC17A_EIC_EXTINT9 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT10 _L_(66) /**< \brief EIC signal: EXTINT10 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT10 ((PIN_PC02A_EIC_EXTINT10 << 16) | MUX_PC02A_EIC_EXTINT10) -#define PORT_PC02A_EIC_EXTINT10 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT10 _L_(82) /**< \brief EIC signal: EXTINT10 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT10 ((PIN_PC18A_EIC_EXTINT10 << 16) | MUX_PC18A_EIC_EXTINT10) -#define PORT_PC18A_EIC_EXTINT10 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT11 _L_(67) /**< \brief EIC signal: EXTINT11 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT11 ((PIN_PC03A_EIC_EXTINT11 << 16) | MUX_PC03A_EIC_EXTINT11) -#define PORT_PC03A_EIC_EXTINT11 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT11 _L_(83) /**< \brief EIC signal: EXTINT11 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT11 ((PIN_PC19A_EIC_EXTINT11 << 16) | MUX_PC19A_EIC_EXTINT11) -#define PORT_PC19A_EIC_EXTINT11 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT12 _L_(84) /**< \brief EIC signal: EXTINT12 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT12 ((PIN_PC20A_EIC_EXTINT12 << 16) | MUX_PC20A_EIC_EXTINT12) -#define PORT_PC20A_EIC_EXTINT12 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT13 _L_(69) /**< \brief EIC signal: EXTINT13 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT13 ((PIN_PC05A_EIC_EXTINT13 << 16) | MUX_PC05A_EIC_EXTINT13) -#define PORT_PC05A_EIC_EXTINT13 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT13 _L_(85) /**< \brief EIC signal: EXTINT13 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT13 ((PIN_PC21A_EIC_EXTINT13 << 16) | MUX_PC21A_EIC_EXTINT13) -#define PORT_PC21A_EIC_EXTINT13 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT14 _L_(70) /**< \brief EIC signal: EXTINT14 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT14 ((PIN_PC06A_EIC_EXTINT14 << 16) | MUX_PC06A_EIC_EXTINT14) -#define PORT_PC06A_EIC_EXTINT14 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT15 _L_(71) /**< \brief EIC signal: EXTINT15 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT15 ((PIN_PC07A_EIC_EXTINT15 << 16) | MUX_PC07A_EIC_EXTINT15) -#define PORT_PC07A_EIC_EXTINT15 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM _L_(6) -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (_UL_(1) << 24) -#define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP _L_(6) -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (_UL_(1) << 25) -#define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22G_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux G */ -#define MUX_PB22G_USB_SOF_1KHZ _L_(6) -#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ) -#define PORT_PB22G_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA20C_SERCOM0_PAD0 _L_(20) /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */ -#define MUX_PA20C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0) -#define PORT_PA20C_SERCOM0_PAD0 (_UL_(1) << 20) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA21C_SERCOM0_PAD1 _L_(21) /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */ -#define MUX_PA21C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1) -#define PORT_PA21C_SERCOM0_PAD1 (_UL_(1) << 21) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA22C_SERCOM0_PAD2 _L_(22) /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */ -#define MUX_PA22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2) -#define PORT_PA22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PB22C_SERCOM0_PAD2 _L_(54) /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2) -#define PORT_PB22C_SERCOM0_PAD2 (_UL_(1) << 22) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PA23C_SERCOM0_PAD3 _L_(23) /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */ -#define MUX_PA23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3) -#define PORT_PA23C_SERCOM0_PAD3 (_UL_(1) << 23) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -#define PIN_PB23C_SERCOM0_PAD3 _L_(55) /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3) -#define PORT_PB23C_SERCOM0_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PB30C_SERCOM1_PAD0 _L_(62) /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0) -#define PORT_PB30C_SERCOM1_PAD0 (_UL_(1) << 30) -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PC27D_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux D */ -#define MUX_PC27D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PC27D_SERCOM1_PAD0 ((PIN_PC27D_SERCOM1_PAD0 << 16) | MUX_PC27D_SERCOM1_PAD0) -#define PORT_PC27D_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC12C_SERCOM1_PAD0 _L_(76) /**< \brief SERCOM1 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM1_PAD0 ((PIN_PC12C_SERCOM1_PAD0 << 16) | MUX_PC12C_SERCOM1_PAD0) -#define PORT_PC12C_SERCOM1_PAD0 (_UL_(1) << 12) -#define PIN_PB31C_SERCOM1_PAD1 _L_(63) /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1) -#define PORT_PB31C_SERCOM1_PAD1 (_UL_(1) << 31) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PC28D_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux D */ -#define MUX_PC28D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PC28D_SERCOM1_PAD1 ((PIN_PC28D_SERCOM1_PAD1 << 16) | MUX_PC28D_SERCOM1_PAD1) -#define PORT_PC28D_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC13C_SERCOM1_PAD1 _L_(77) /**< \brief SERCOM1 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM1_PAD1 ((PIN_PC13C_SERCOM1_PAD1 << 16) | MUX_PC13C_SERCOM1_PAD1) -#define PORT_PC13C_SERCOM1_PAD1 (_UL_(1) << 13) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PC10C_SERCOM1_PAD2 _L_(74) /**< \brief SERCOM1 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM1_PAD2 ((PIN_PC10C_SERCOM1_PAD2 << 16) | MUX_PC10C_SERCOM1_PAD2) -#define PORT_PC10C_SERCOM1_PAD2 (_UL_(1) << 10) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PC11C_SERCOM1_PAD3 _L_(75) /**< \brief SERCOM1 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM1_PAD3 ((PIN_PC11C_SERCOM1_PAD3 << 16) | MUX_PC11C_SERCOM1_PAD3) -#define PORT_PC11C_SERCOM1_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA22D_SERCOM2_PAD0 _L_(22) /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0) -#define PORT_PA22D_SERCOM2_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM2_PAD0 _L_(16) /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0) -#define PORT_PA16D_SERCOM2_PAD0 (_UL_(1) << 16) -#define PIN_PA23D_SERCOM2_PAD1 _L_(23) /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1) -#define PORT_PA23D_SERCOM2_PAD1 (_UL_(1) << 23) -#define PIN_PA17D_SERCOM2_PAD1 _L_(17) /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1) -#define PORT_PA17D_SERCOM2_PAD1 (_UL_(1) << 17) -#define PIN_PA18D_SERCOM2_PAD2 _L_(18) /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2) -#define PORT_PA18D_SERCOM2_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM2_PAD2 _L_(20) /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2) -#define PORT_PA20D_SERCOM2_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM2_PAD2 _L_(24) /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2) -#define PORT_PA24C_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM2_PAD3 _L_(19) /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3) -#define PORT_PA19D_SERCOM2_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM2_PAD3 _L_(21) /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3) -#define PORT_PA21D_SERCOM2_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM2_PAD3 _L_(25) /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3) -#define PORT_PA25C_SERCOM2_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PB12C_SERCOM3_PAD0 _L_(44) /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0) -#define PORT_PB12C_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM3_PAD0 _L_(12) /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0) -#define PORT_PA12D_SERCOM3_PAD0 (_UL_(1) << 12) -#define PIN_PB08D_SERCOM3_PAD0 _L_(40) /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0) -#define PORT_PB08D_SERCOM3_PAD0 (_UL_(1) << 8) -#define PIN_PB02C_SERCOM3_PAD0 _L_(34) /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */ -#define MUX_PB02C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0) -#define PORT_PB02C_SERCOM3_PAD0 (_UL_(1) << 2) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PB13C_SERCOM3_PAD1 _L_(45) /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1) -#define PORT_PB13C_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PA13D_SERCOM3_PAD1 _L_(13) /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1) -#define PORT_PA13D_SERCOM3_PAD1 (_UL_(1) << 13) -#define PIN_PB09D_SERCOM3_PAD1 _L_(41) /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1) -#define PORT_PB09D_SERCOM3_PAD1 (_UL_(1) << 9) -#define PIN_PB03C_SERCOM3_PAD1 _L_(35) /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */ -#define MUX_PB03C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1) -#define PORT_PB03C_SERCOM3_PAD1 (_UL_(1) << 3) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PB14C_SERCOM3_PAD2 _L_(46) /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2) -#define PORT_PB14C_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PA14D_SERCOM3_PAD2 _L_(14) /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2) -#define PORT_PA14D_SERCOM3_PAD2 (_UL_(1) << 14) -#define PIN_PB18D_SERCOM3_PAD2 _L_(50) /**< \brief SERCOM3 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM3_PAD2 ((PIN_PB18D_SERCOM3_PAD2 << 16) | MUX_PB18D_SERCOM3_PAD2) -#define PORT_PB18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PB00C_SERCOM3_PAD2 _L_(32) /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */ -#define MUX_PB00C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2) -#define PORT_PB00C_SERCOM3_PAD2 (_UL_(1) << 0) -#define PIN_PB15C_SERCOM3_PAD3 _L_(47) /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3) -#define PORT_PB15C_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PA15D_SERCOM3_PAD3 _L_(15) /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3) -#define PORT_PA15D_SERCOM3_PAD3 (_UL_(1) << 15) -#define PIN_PB11D_SERCOM3_PAD3 _L_(43) /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3) -#define PORT_PB11D_SERCOM3_PAD3 (_UL_(1) << 11) -#define PIN_PB19D_SERCOM3_PAD3 _L_(51) /**< \brief SERCOM3 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM3_PAD3 ((PIN_PB19D_SERCOM3_PAD3 << 16) | MUX_PB19D_SERCOM3_PAD3) -#define PORT_PB19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PB01C_SERCOM3_PAD3 _L_(33) /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */ -#define MUX_PB01C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3) -#define PORT_PB01C_SERCOM3_PAD3 (_UL_(1) << 1) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA08D_SERCOM4_PAD0 _L_(8) /**< \brief SERCOM4 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA08D_SERCOM4_PAD0 ((PIN_PA08D_SERCOM4_PAD0 << 16) | MUX_PA08D_SERCOM4_PAD0) -#define PORT_PA08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM4_PAD0 _L_(56) /**< \brief SERCOM4 signal: PAD0 on PB24 mux D */ -#define MUX_PB24D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB24D_SERCOM4_PAD0 ((PIN_PB24D_SERCOM4_PAD0 << 16) | MUX_PB24D_SERCOM4_PAD0) -#define PORT_PB24D_SERCOM4_PAD0 (_UL_(1) << 24) -#define PIN_PA12C_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM4_PAD0 ((PIN_PA12C_SERCOM4_PAD0 << 16) | MUX_PA12C_SERCOM4_PAD0) -#define PORT_PA12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA09D_SERCOM4_PAD1 _L_(9) /**< \brief SERCOM4 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA09D_SERCOM4_PAD1 ((PIN_PA09D_SERCOM4_PAD1 << 16) | MUX_PA09D_SERCOM4_PAD1) -#define PORT_PA09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM4_PAD1 _L_(57) /**< \brief SERCOM4 signal: PAD1 on PB25 mux D */ -#define MUX_PB25D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB25D_SERCOM4_PAD1 ((PIN_PB25D_SERCOM4_PAD1 << 16) | MUX_PB25D_SERCOM4_PAD1) -#define PORT_PB25D_SERCOM4_PAD1 (_UL_(1) << 25) -#define PIN_PA13C_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM4_PAD1 ((PIN_PA13C_SERCOM4_PAD1 << 16) | MUX_PA13C_SERCOM4_PAD1) -#define PORT_PA13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM4_PAD2 _L_(10) /**< \brief SERCOM4 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM4_PAD2 ((PIN_PA10D_SERCOM4_PAD2 << 16) | MUX_PA10D_SERCOM4_PAD2) -#define PORT_PA10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM4_PAD2 _L_(88) /**< \brief SERCOM4 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM4_PAD2 ((PIN_PC24D_SERCOM4_PAD2 << 16) | MUX_PC24D_SERCOM4_PAD2) -#define PORT_PC24D_SERCOM4_PAD2 (_UL_(1) << 24) -#define PIN_PA14C_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM4_PAD2 ((PIN_PA14C_SERCOM4_PAD2 << 16) | MUX_PA14C_SERCOM4_PAD2) -#define PORT_PA14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM4_PAD3 _L_(11) /**< \brief SERCOM4 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM4_PAD3 ((PIN_PA11D_SERCOM4_PAD3 << 16) | MUX_PA11D_SERCOM4_PAD3) -#define PORT_PA11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM4_PAD3 _L_(89) /**< \brief SERCOM4 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM4_PAD3 ((PIN_PC25D_SERCOM4_PAD3 << 16) | MUX_PC25D_SERCOM4_PAD3) -#define PORT_PC25D_SERCOM4_PAD3 (_UL_(1) << 25) -#define PIN_PA15C_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM4_PAD3 ((PIN_PA15C_SERCOM4_PAD3 << 16) | MUX_PA15C_SERCOM4_PAD3) -#define PORT_PA15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) -#define PIN_PA24D_SERCOM5_PAD0 _L_(24) /**< \brief SERCOM5 signal: PAD0 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD0 ((PIN_PA24D_SERCOM5_PAD0 << 16) | MUX_PA24D_SERCOM5_PAD0) -#define PORT_PA24D_SERCOM5_PAD0 (_UL_(1) << 24) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB20D_SERCOM5_PAD0 _L_(52) /**< \brief SERCOM5 signal: PAD0 on PB20 mux D */ -#define MUX_PB20D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB20D_SERCOM5_PAD0 ((PIN_PB20D_SERCOM5_PAD0 << 16) | MUX_PB20D_SERCOM5_PAD0) -#define PORT_PB20D_SERCOM5_PAD0 (_UL_(1) << 20) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) -#define PIN_PA25D_SERCOM5_PAD1 _L_(25) /**< \brief SERCOM5 signal: PAD1 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD1 ((PIN_PA25D_SERCOM5_PAD1 << 16) | MUX_PA25D_SERCOM5_PAD1) -#define PORT_PA25D_SERCOM5_PAD1 (_UL_(1) << 25) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB21D_SERCOM5_PAD1 _L_(53) /**< \brief SERCOM5 signal: PAD1 on PB21 mux D */ -#define MUX_PB21D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB21D_SERCOM5_PAD1 ((PIN_PB21D_SERCOM5_PAD1 << 16) | MUX_PB21D_SERCOM5_PAD1) -#define PORT_PB21D_SERCOM5_PAD1 (_UL_(1) << 21) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA24F_TCC0_WO0 _L_(24) /**< \brief TCC0 signal: WO0 on PA24 mux F */ -#define MUX_PA24F_TCC0_WO0 _L_(5) -#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0) -#define PORT_PA24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PB18F_TCC0_WO0 _L_(50) /**< \brief TCC0 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC0_WO0 _L_(5) -#define PINMUX_PB18F_TCC0_WO0 ((PIN_PB18F_TCC0_WO0 << 16) | MUX_PB18F_TCC0_WO0) -#define PORT_PB18F_TCC0_WO0 (_UL_(1) << 18) -#define PIN_PC24F_TCC0_WO0 _L_(88) /**< \brief TCC0 signal: WO0 on PC24 mux F */ -#define MUX_PC24F_TCC0_WO0 _L_(5) -#define PINMUX_PC24F_TCC0_WO0 ((PIN_PC24F_TCC0_WO0 << 16) | MUX_PC24F_TCC0_WO0) -#define PORT_PC24F_TCC0_WO0 (_UL_(1) << 24) -#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 _L_(4) -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 _L_(4) -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 _L_(4) -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) -#define PIN_PA25F_TCC0_WO1 _L_(25) /**< \brief TCC0 signal: WO1 on PA25 mux F */ -#define MUX_PA25F_TCC0_WO1 _L_(5) -#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1) -#define PORT_PA25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PB19F_TCC0_WO1 _L_(51) /**< \brief TCC0 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC0_WO1 _L_(5) -#define PINMUX_PB19F_TCC0_WO1 ((PIN_PB19F_TCC0_WO1 << 16) | MUX_PB19F_TCC0_WO1) -#define PORT_PB19F_TCC0_WO1 (_UL_(1) << 19) -#define PIN_PC25F_TCC0_WO1 _L_(89) /**< \brief TCC0 signal: WO1 on PC25 mux F */ -#define MUX_PC25F_TCC0_WO1 _L_(5) -#define PINMUX_PC25F_TCC0_WO1 ((PIN_PC25F_TCC0_WO1 << 16) | MUX_PC25F_TCC0_WO1) -#define PORT_PC25F_TCC0_WO1 (_UL_(1) << 25) -#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 _L_(4) -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 _L_(4) -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 _L_(4) -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 _L_(5) -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC0_WO2 _L_(52) /**< \brief TCC0 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC0_WO2 _L_(5) -#define PINMUX_PB20F_TCC0_WO2 ((PIN_PB20F_TCC0_WO2 << 16) | MUX_PB20F_TCC0_WO2) -#define PORT_PB20F_TCC0_WO2 (_UL_(1) << 20) -#define PIN_PB22F_TCC0_WO2 _L_(54) /**< \brief TCC0 signal: WO2 on PB22 mux F */ -#define MUX_PB22F_TCC0_WO2 _L_(5) -#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2) -#define PORT_PB22F_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PC26F_TCC0_WO2 _L_(90) /**< \brief TCC0 signal: WO2 on PC26 mux F */ -#define MUX_PC26F_TCC0_WO2 _L_(5) -#define PINMUX_PC26F_TCC0_WO2 ((PIN_PC26F_TCC0_WO2 << 16) | MUX_PC26F_TCC0_WO2) -#define PORT_PC26F_TCC0_WO2 (_UL_(1) << 26) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 _L_(5) -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC0_WO3 _L_(53) /**< \brief TCC0 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC0_WO3 _L_(5) -#define PINMUX_PB21F_TCC0_WO3 ((PIN_PB21F_TCC0_WO3 << 16) | MUX_PB21F_TCC0_WO3) -#define PORT_PB21F_TCC0_WO3 (_UL_(1) << 21) -#define PIN_PB23F_TCC0_WO3 _L_(55) /**< \brief TCC0 signal: WO3 on PB23 mux F */ -#define MUX_PB23F_TCC0_WO3 _L_(5) -#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3) -#define PORT_PB23F_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PC27F_TCC0_WO3 _L_(91) /**< \brief TCC0 signal: WO3 on PC27 mux F */ -#define MUX_PC27F_TCC0_WO3 _L_(5) -#define PINMUX_PC27F_TCC0_WO3 ((PIN_PC27F_TCC0_WO3 << 16) | MUX_PC27F_TCC0_WO3) -#define PORT_PC27F_TCC0_WO3 (_UL_(1) << 27) -#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 _L_(5) -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) -#define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 _L_(5) -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PC28F_TCC0_WO4 _L_(92) /**< \brief TCC0 signal: WO4 on PC28 mux F */ -#define MUX_PC28F_TCC0_WO4 _L_(5) -#define PINMUX_PC28F_TCC0_WO4 ((PIN_PC28F_TCC0_WO4 << 16) | MUX_PC28F_TCC0_WO4) -#define PORT_PC28F_TCC0_WO4 (_UL_(1) << 28) -#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 _L_(5) -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 _L_(5) -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 _L_(5) -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) -#define PIN_PA27F_TCC0_WO5 _L_(27) /**< \brief TCC0 signal: WO5 on PA27 mux F */ -#define MUX_PA27F_TCC0_WO5 _L_(5) -#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5) -#define PORT_PA27F_TCC0_WO5 (_UL_(1) << 27) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 _L_(5) -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 _L_(5) -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) -#define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 _L_(5) -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) -#define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 _L_(5) -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PB24F_TCC0_WO6 _L_(56) /**< \brief TCC0 signal: WO6 on PB24 mux F */ -#define MUX_PB24F_TCC0_WO6 _L_(5) -#define PINMUX_PB24F_TCC0_WO6 ((PIN_PB24F_TCC0_WO6 << 16) | MUX_PB24F_TCC0_WO6) -#define PORT_PB24F_TCC0_WO6 (_UL_(1) << 24) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 _L_(5) -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) -#define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 _L_(5) -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) -#define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 _L_(5) -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PB25F_TCC0_WO7 _L_(57) /**< \brief TCC0 signal: WO7 on PB25 mux F */ -#define MUX_PB25F_TCC0_WO7 _L_(5) -#define PINMUX_PB25F_TCC0_WO7 ((PIN_PB25F_TCC0_WO7 << 16) | MUX_PB25F_TCC0_WO7) -#define PORT_PB25F_TCC0_WO7 (_UL_(1) << 25) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC0_WO0 _L_(4) -#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) -#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC0_WO0 _L_(4) -#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) -#define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC0_WO0 _L_(4) -#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) -#define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC0_WO1 _L_(4) -#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) -#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC0_WO1 _L_(4) -#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) -#define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC0_WO1 _L_(4) -#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) -#define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC1_WO0 _L_(4) -#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) -#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) -#define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC1_WO0 _L_(4) -#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) -#define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC1_WO1 _L_(4) -#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) -#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC1_WO1 _L_(4) -#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) -#define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC1_WO1 _L_(4) -#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) -#define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC2_WO0 _L_(4) -#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) -#define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC2_WO0 _L_(4) -#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) -#define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PC24E_TC2_WO0 _L_(88) /**< \brief TC2 signal: WO0 on PC24 mux E */ -#define MUX_PC24E_TC2_WO0 _L_(4) -#define PINMUX_PC24E_TC2_WO0 ((PIN_PC24E_TC2_WO0 << 16) | MUX_PC24E_TC2_WO0) -#define PORT_PC24E_TC2_WO0 (_UL_(1) << 24) -#define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC2_WO1 _L_(4) -#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) -#define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC2_WO1 _L_(4) -#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) -#define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) -#define PIN_PC25E_TC2_WO1 _L_(89) /**< \brief TC2 signal: WO1 on PC25 mux E */ -#define MUX_PC25E_TC2_WO1 _L_(4) -#define PINMUX_PC25E_TC2_WO1 ((PIN_PC25E_TC2_WO1 << 16) | MUX_PC25E_TC2_WO1) -#define PORT_PC25E_TC2_WO1 (_UL_(1) << 25) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC3_WO0 _L_(4) -#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) -#define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC3_WO0 _L_(4) -#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) -#define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC3_WO0 _L_(4) -#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) -#define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) -#define PIN_PC26E_TC3_WO0 _L_(90) /**< \brief TC3 signal: WO0 on PC26 mux E */ -#define MUX_PC26E_TC3_WO0 _L_(4) -#define PINMUX_PC26E_TC3_WO0 ((PIN_PC26E_TC3_WO0 << 16) | MUX_PC26E_TC3_WO0) -#define PORT_PC26E_TC3_WO0 (_UL_(1) << 26) -#define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC3_WO1 _L_(4) -#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) -#define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC3_WO1 _L_(4) -#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) -#define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC3_WO1 _L_(4) -#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) -#define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) -#define PIN_PC27E_TC3_WO1 _L_(91) /**< \brief TC3 signal: WO1 on PC27 mux E */ -#define MUX_PC27E_TC3_WO1 _L_(4) -#define PINMUX_PC27E_TC3_WO1 ((PIN_PC27E_TC3_WO1 << 16) | MUX_PC27E_TC3_WO1) -#define PORT_PC27E_TC3_WO1 (_UL_(1) << 27) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 _L_(1) -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 _L_(1) -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 _L_(1) -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 _L_(1) -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 _L_(1) -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 _L_(1) -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 _L_(1) -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 _L_(1) -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) -#define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 _L_(1) -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) -#define PIN_PB01B_ADC_AIN9 _L_(33) /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 _L_(1) -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (_UL_(1) << 1) -#define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 _L_(1) -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) -#define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 _L_(1) -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) -#define PIN_PB04B_ADC_AIN12 _L_(36) /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 _L_(1) -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (_UL_(1) << 4) -#define PIN_PB05B_ADC_AIN13 _L_(37) /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 _L_(1) -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (_UL_(1) << 5) -#define PIN_PB06B_ADC_AIN14 _L_(38) /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 _L_(1) -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (_UL_(1) << 6) -#define PIN_PB07B_ADC_AIN15 _L_(39) /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 _L_(1) -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (_UL_(1) << 7) -#define PIN_PC00B_ADC_AIN16 _L_(64) /**< \brief ADC signal: AIN16 on PC00 mux B */ -#define MUX_PC00B_ADC_AIN16 _L_(1) -#define PINMUX_PC00B_ADC_AIN16 ((PIN_PC00B_ADC_AIN16 << 16) | MUX_PC00B_ADC_AIN16) -#define PORT_PC00B_ADC_AIN16 (_UL_(1) << 0) -#define PIN_PC01B_ADC_AIN17 _L_(65) /**< \brief ADC signal: AIN17 on PC01 mux B */ -#define MUX_PC01B_ADC_AIN17 _L_(1) -#define PINMUX_PC01B_ADC_AIN17 ((PIN_PC01B_ADC_AIN17 << 16) | MUX_PC01B_ADC_AIN17) -#define PORT_PC01B_ADC_AIN17 (_UL_(1) << 1) -#define PIN_PC02B_ADC_AIN18 _L_(66) /**< \brief ADC signal: AIN18 on PC02 mux B */ -#define MUX_PC02B_ADC_AIN18 _L_(1) -#define PINMUX_PC02B_ADC_AIN18 ((PIN_PC02B_ADC_AIN18 << 16) | MUX_PC02B_ADC_AIN18) -#define PORT_PC02B_ADC_AIN18 (_UL_(1) << 2) -#define PIN_PC03B_ADC_AIN19 _L_(67) /**< \brief ADC signal: AIN19 on PC03 mux B */ -#define MUX_PC03B_ADC_AIN19 _L_(1) -#define PINMUX_PC03B_ADC_AIN19 ((PIN_PC03B_ADC_AIN19 << 16) | MUX_PC03B_ADC_AIN19) -#define PORT_PC03B_ADC_AIN19 (_UL_(1) << 3) -#define PIN_PA03B_ADC_VREFA _L_(3) /**< \brief ADC signal: VREFA on PA03 mux B */ -#define MUX_PA03B_ADC_VREFA _L_(1) -#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA) -#define PORT_PA03B_ADC_VREFA (_UL_(1) << 3) -#define PIN_PA02B_ADC_VREFB _L_(2) /**< \brief ADC signal: VREFB on PA02 mux B */ -#define MUX_PA02B_ADC_VREFB _L_(1) -#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB) -#define PORT_PA02B_ADC_VREFB (_UL_(1) << 2) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA02B_AC_AIN0 _L_(2) /**< \brief AC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_AC_AIN0 _L_(1) -#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0) -#define PORT_PA02B_AC_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_AC_AIN1 _L_(3) /**< \brief AC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_AC_AIN1 _L_(1) -#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1) -#define PORT_PA03B_AC_AIN1 (_UL_(1) << 3) -#define PIN_PB04B_AC_AIN2 _L_(36) /**< \brief AC signal: AIN2 on PB04 mux B */ -#define MUX_PB04B_AC_AIN2 _L_(1) -#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2) -#define PORT_PB04B_AC_AIN2 (_UL_(1) << 4) -#define PIN_PB05B_AC_AIN3 _L_(37) /**< \brief AC signal: AIN3 on PB05 mux B */ -#define MUX_PB05B_AC_AIN3 _L_(1) -#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3) -#define PORT_PB05B_AC_AIN3 (_UL_(1) << 5) -#define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 _L_(7) -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 _L_(7) -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24H_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux H */ -#define MUX_PB24H_AC_CMP0 _L_(7) -#define PINMUX_PB24H_AC_CMP0 ((PIN_PB24H_AC_CMP0 << 16) | MUX_PB24H_AC_CMP0) -#define PORT_PB24H_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 _L_(7) -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 _L_(7) -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25H_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux H */ -#define MUX_PB25H_AC_CMP1 _L_(7) -#define PINMUX_PB25H_AC_CMP1 ((PIN_PB25H_AC_CMP1 << 16) | MUX_PB25H_AC_CMP1) -#define PORT_PB25H_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for SLCD peripheral ========== */ -#define PIN_PB06B_SLCD_LP0 _L_(38) /**< \brief SLCD signal: LP0 on PB06 mux B */ -#define MUX_PB06B_SLCD_LP0 _L_(1) -#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0) -#define PORT_PB06B_SLCD_LP0 (_UL_(1) << 6) -#define PIN_PB07B_SLCD_LP1 _L_(39) /**< \brief SLCD signal: LP1 on PB07 mux B */ -#define MUX_PB07B_SLCD_LP1 _L_(1) -#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1) -#define PORT_PB07B_SLCD_LP1 (_UL_(1) << 7) -#define PIN_PB08B_SLCD_LP2 _L_(40) /**< \brief SLCD signal: LP2 on PB08 mux B */ -#define MUX_PB08B_SLCD_LP2 _L_(1) -#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2) -#define PORT_PB08B_SLCD_LP2 (_UL_(1) << 8) -#define PIN_PB09B_SLCD_LP3 _L_(41) /**< \brief SLCD signal: LP3 on PB09 mux B */ -#define MUX_PB09B_SLCD_LP3 _L_(1) -#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3) -#define PORT_PB09B_SLCD_LP3 (_UL_(1) << 9) -#define PIN_PA04B_SLCD_LP4 _L_(4) /**< \brief SLCD signal: LP4 on PA04 mux B */ -#define MUX_PA04B_SLCD_LP4 _L_(1) -#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4) -#define PORT_PA04B_SLCD_LP4 (_UL_(1) << 4) -#define PIN_PA05B_SLCD_LP5 _L_(5) /**< \brief SLCD signal: LP5 on PA05 mux B */ -#define MUX_PA05B_SLCD_LP5 _L_(1) -#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5) -#define PORT_PA05B_SLCD_LP5 (_UL_(1) << 5) -#define PIN_PA06B_SLCD_LP6 _L_(6) /**< \brief SLCD signal: LP6 on PA06 mux B */ -#define MUX_PA06B_SLCD_LP6 _L_(1) -#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6) -#define PORT_PA06B_SLCD_LP6 (_UL_(1) << 6) -#define PIN_PA07B_SLCD_LP7 _L_(7) /**< \brief SLCD signal: LP7 on PA07 mux B */ -#define MUX_PA07B_SLCD_LP7 _L_(1) -#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7) -#define PORT_PA07B_SLCD_LP7 (_UL_(1) << 7) -#define PIN_PC05B_SLCD_LP8 _L_(69) /**< \brief SLCD signal: LP8 on PC05 mux B */ -#define MUX_PC05B_SLCD_LP8 _L_(1) -#define PINMUX_PC05B_SLCD_LP8 ((PIN_PC05B_SLCD_LP8 << 16) | MUX_PC05B_SLCD_LP8) -#define PORT_PC05B_SLCD_LP8 (_UL_(1) << 5) -#define PIN_PC06B_SLCD_LP9 _L_(70) /**< \brief SLCD signal: LP9 on PC06 mux B */ -#define MUX_PC06B_SLCD_LP9 _L_(1) -#define PINMUX_PC06B_SLCD_LP9 ((PIN_PC06B_SLCD_LP9 << 16) | MUX_PC06B_SLCD_LP9) -#define PORT_PC06B_SLCD_LP9 (_UL_(1) << 6) -#define PIN_PC07B_SLCD_LP10 _L_(71) /**< \brief SLCD signal: LP10 on PC07 mux B */ -#define MUX_PC07B_SLCD_LP10 _L_(1) -#define PINMUX_PC07B_SLCD_LP10 ((PIN_PC07B_SLCD_LP10 << 16) | MUX_PC07B_SLCD_LP10) -#define PORT_PC07B_SLCD_LP10 (_UL_(1) << 7) -#define PIN_PA08B_SLCD_LP11 _L_(8) /**< \brief SLCD signal: LP11 on PA08 mux B */ -#define MUX_PA08B_SLCD_LP11 _L_(1) -#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11) -#define PORT_PA08B_SLCD_LP11 (_UL_(1) << 8) -#define PIN_PA09B_SLCD_LP12 _L_(9) /**< \brief SLCD signal: LP12 on PA09 mux B */ -#define MUX_PA09B_SLCD_LP12 _L_(1) -#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12) -#define PORT_PA09B_SLCD_LP12 (_UL_(1) << 9) -#define PIN_PA10B_SLCD_LP13 _L_(10) /**< \brief SLCD signal: LP13 on PA10 mux B */ -#define MUX_PA10B_SLCD_LP13 _L_(1) -#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13) -#define PORT_PA10B_SLCD_LP13 (_UL_(1) << 10) -#define PIN_PA11B_SLCD_LP14 _L_(11) /**< \brief SLCD signal: LP14 on PA11 mux B */ -#define MUX_PA11B_SLCD_LP14 _L_(1) -#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14) -#define PORT_PA11B_SLCD_LP14 (_UL_(1) << 11) -#define PIN_PC08B_SLCD_LP15 _L_(72) /**< \brief SLCD signal: LP15 on PC08 mux B */ -#define MUX_PC08B_SLCD_LP15 _L_(1) -#define PINMUX_PC08B_SLCD_LP15 ((PIN_PC08B_SLCD_LP15 << 16) | MUX_PC08B_SLCD_LP15) -#define PORT_PC08B_SLCD_LP15 (_UL_(1) << 8) -#define PIN_PC09B_SLCD_LP16 _L_(73) /**< \brief SLCD signal: LP16 on PC09 mux B */ -#define MUX_PC09B_SLCD_LP16 _L_(1) -#define PINMUX_PC09B_SLCD_LP16 ((PIN_PC09B_SLCD_LP16 << 16) | MUX_PC09B_SLCD_LP16) -#define PORT_PC09B_SLCD_LP16 (_UL_(1) << 9) -#define PIN_PC10B_SLCD_LP17 _L_(74) /**< \brief SLCD signal: LP17 on PC10 mux B */ -#define MUX_PC10B_SLCD_LP17 _L_(1) -#define PINMUX_PC10B_SLCD_LP17 ((PIN_PC10B_SLCD_LP17 << 16) | MUX_PC10B_SLCD_LP17) -#define PORT_PC10B_SLCD_LP17 (_UL_(1) << 10) -#define PIN_PC11B_SLCD_LP18 _L_(75) /**< \brief SLCD signal: LP18 on PC11 mux B */ -#define MUX_PC11B_SLCD_LP18 _L_(1) -#define PINMUX_PC11B_SLCD_LP18 ((PIN_PC11B_SLCD_LP18 << 16) | MUX_PC11B_SLCD_LP18) -#define PORT_PC11B_SLCD_LP18 (_UL_(1) << 11) -#define PIN_PC12B_SLCD_LP19 _L_(76) /**< \brief SLCD signal: LP19 on PC12 mux B */ -#define MUX_PC12B_SLCD_LP19 _L_(1) -#define PINMUX_PC12B_SLCD_LP19 ((PIN_PC12B_SLCD_LP19 << 16) | MUX_PC12B_SLCD_LP19) -#define PORT_PC12B_SLCD_LP19 (_UL_(1) << 12) -#define PIN_PC13B_SLCD_LP20 _L_(77) /**< \brief SLCD signal: LP20 on PC13 mux B */ -#define MUX_PC13B_SLCD_LP20 _L_(1) -#define PINMUX_PC13B_SLCD_LP20 ((PIN_PC13B_SLCD_LP20 << 16) | MUX_PC13B_SLCD_LP20) -#define PORT_PC13B_SLCD_LP20 (_UL_(1) << 13) -#define PIN_PB11B_SLCD_LP21 _L_(43) /**< \brief SLCD signal: LP21 on PB11 mux B */ -#define MUX_PB11B_SLCD_LP21 _L_(1) -#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21) -#define PORT_PB11B_SLCD_LP21 (_UL_(1) << 11) -#define PIN_PB12B_SLCD_LP22 _L_(44) /**< \brief SLCD signal: LP22 on PB12 mux B */ -#define MUX_PB12B_SLCD_LP22 _L_(1) -#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22) -#define PORT_PB12B_SLCD_LP22 (_UL_(1) << 12) -#define PIN_PB13B_SLCD_LP23 _L_(45) /**< \brief SLCD signal: LP23 on PB13 mux B */ -#define MUX_PB13B_SLCD_LP23 _L_(1) -#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23) -#define PORT_PB13B_SLCD_LP23 (_UL_(1) << 13) -#define PIN_PB14B_SLCD_LP24 _L_(46) /**< \brief SLCD signal: LP24 on PB14 mux B */ -#define MUX_PB14B_SLCD_LP24 _L_(1) -#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24) -#define PORT_PB14B_SLCD_LP24 (_UL_(1) << 14) -#define PIN_PB15B_SLCD_LP25 _L_(47) /**< \brief SLCD signal: LP25 on PB15 mux B */ -#define MUX_PB15B_SLCD_LP25 _L_(1) -#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25) -#define PORT_PB15B_SLCD_LP25 (_UL_(1) << 15) -#define PIN_PC14B_SLCD_LP26 _L_(78) /**< \brief SLCD signal: LP26 on PC14 mux B */ -#define MUX_PC14B_SLCD_LP26 _L_(1) -#define PINMUX_PC14B_SLCD_LP26 ((PIN_PC14B_SLCD_LP26 << 16) | MUX_PC14B_SLCD_LP26) -#define PORT_PC14B_SLCD_LP26 (_UL_(1) << 14) -#define PIN_PC15B_SLCD_LP27 _L_(79) /**< \brief SLCD signal: LP27 on PC15 mux B */ -#define MUX_PC15B_SLCD_LP27 _L_(1) -#define PINMUX_PC15B_SLCD_LP27 ((PIN_PC15B_SLCD_LP27 << 16) | MUX_PC15B_SLCD_LP27) -#define PORT_PC15B_SLCD_LP27 (_UL_(1) << 15) -#define PIN_PA12B_SLCD_LP28 _L_(12) /**< \brief SLCD signal: LP28 on PA12 mux B */ -#define MUX_PA12B_SLCD_LP28 _L_(1) -#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28) -#define PORT_PA12B_SLCD_LP28 (_UL_(1) << 12) -#define PIN_PA13B_SLCD_LP29 _L_(13) /**< \brief SLCD signal: LP29 on PA13 mux B */ -#define MUX_PA13B_SLCD_LP29 _L_(1) -#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29) -#define PORT_PA13B_SLCD_LP29 (_UL_(1) << 13) -#define PIN_PA14B_SLCD_LP30 _L_(14) /**< \brief SLCD signal: LP30 on PA14 mux B */ -#define MUX_PA14B_SLCD_LP30 _L_(1) -#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30) -#define PORT_PA14B_SLCD_LP30 (_UL_(1) << 14) -#define PIN_PA15B_SLCD_LP31 _L_(15) /**< \brief SLCD signal: LP31 on PA15 mux B */ -#define MUX_PA15B_SLCD_LP31 _L_(1) -#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31) -#define PORT_PA15B_SLCD_LP31 (_UL_(1) << 15) -#define PIN_PA16B_SLCD_LP32 _L_(16) /**< \brief SLCD signal: LP32 on PA16 mux B */ -#define MUX_PA16B_SLCD_LP32 _L_(1) -#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32) -#define PORT_PA16B_SLCD_LP32 (_UL_(1) << 16) -#define PIN_PA17B_SLCD_LP33 _L_(17) /**< \brief SLCD signal: LP33 on PA17 mux B */ -#define MUX_PA17B_SLCD_LP33 _L_(1) -#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33) -#define PORT_PA17B_SLCD_LP33 (_UL_(1) << 17) -#define PIN_PA18B_SLCD_LP34 _L_(18) /**< \brief SLCD signal: LP34 on PA18 mux B */ -#define MUX_PA18B_SLCD_LP34 _L_(1) -#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34) -#define PORT_PA18B_SLCD_LP34 (_UL_(1) << 18) -#define PIN_PA19B_SLCD_LP35 _L_(19) /**< \brief SLCD signal: LP35 on PA19 mux B */ -#define MUX_PA19B_SLCD_LP35 _L_(1) -#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35) -#define PORT_PA19B_SLCD_LP35 (_UL_(1) << 19) -#define PIN_PC16B_SLCD_LP36 _L_(80) /**< \brief SLCD signal: LP36 on PC16 mux B */ -#define MUX_PC16B_SLCD_LP36 _L_(1) -#define PINMUX_PC16B_SLCD_LP36 ((PIN_PC16B_SLCD_LP36 << 16) | MUX_PC16B_SLCD_LP36) -#define PORT_PC16B_SLCD_LP36 (_UL_(1) << 16) -#define PIN_PC17B_SLCD_LP37 _L_(81) /**< \brief SLCD signal: LP37 on PC17 mux B */ -#define MUX_PC17B_SLCD_LP37 _L_(1) -#define PINMUX_PC17B_SLCD_LP37 ((PIN_PC17B_SLCD_LP37 << 16) | MUX_PC17B_SLCD_LP37) -#define PORT_PC17B_SLCD_LP37 (_UL_(1) << 17) -#define PIN_PC18B_SLCD_LP38 _L_(82) /**< \brief SLCD signal: LP38 on PC18 mux B */ -#define MUX_PC18B_SLCD_LP38 _L_(1) -#define PINMUX_PC18B_SLCD_LP38 ((PIN_PC18B_SLCD_LP38 << 16) | MUX_PC18B_SLCD_LP38) -#define PORT_PC18B_SLCD_LP38 (_UL_(1) << 18) -#define PIN_PC19B_SLCD_LP39 _L_(83) /**< \brief SLCD signal: LP39 on PC19 mux B */ -#define MUX_PC19B_SLCD_LP39 _L_(1) -#define PINMUX_PC19B_SLCD_LP39 ((PIN_PC19B_SLCD_LP39 << 16) | MUX_PC19B_SLCD_LP39) -#define PORT_PC19B_SLCD_LP39 (_UL_(1) << 19) -#define PIN_PC20B_SLCD_LP40 _L_(84) /**< \brief SLCD signal: LP40 on PC20 mux B */ -#define MUX_PC20B_SLCD_LP40 _L_(1) -#define PINMUX_PC20B_SLCD_LP40 ((PIN_PC20B_SLCD_LP40 << 16) | MUX_PC20B_SLCD_LP40) -#define PORT_PC20B_SLCD_LP40 (_UL_(1) << 20) -#define PIN_PC21B_SLCD_LP41 _L_(85) /**< \brief SLCD signal: LP41 on PC21 mux B */ -#define MUX_PC21B_SLCD_LP41 _L_(1) -#define PINMUX_PC21B_SLCD_LP41 ((PIN_PC21B_SLCD_LP41 << 16) | MUX_PC21B_SLCD_LP41) -#define PORT_PC21B_SLCD_LP41 (_UL_(1) << 21) -#define PIN_PB16B_SLCD_LP42 _L_(48) /**< \brief SLCD signal: LP42 on PB16 mux B */ -#define MUX_PB16B_SLCD_LP42 _L_(1) -#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42) -#define PORT_PB16B_SLCD_LP42 (_UL_(1) << 16) -#define PIN_PB17B_SLCD_LP43 _L_(49) /**< \brief SLCD signal: LP43 on PB17 mux B */ -#define MUX_PB17B_SLCD_LP43 _L_(1) -#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43) -#define PORT_PB17B_SLCD_LP43 (_UL_(1) << 17) -#define PIN_PB18B_SLCD_LP44 _L_(50) /**< \brief SLCD signal: LP44 on PB18 mux B */ -#define MUX_PB18B_SLCD_LP44 _L_(1) -#define PINMUX_PB18B_SLCD_LP44 ((PIN_PB18B_SLCD_LP44 << 16) | MUX_PB18B_SLCD_LP44) -#define PORT_PB18B_SLCD_LP44 (_UL_(1) << 18) -#define PIN_PB19B_SLCD_LP45 _L_(51) /**< \brief SLCD signal: LP45 on PB19 mux B */ -#define MUX_PB19B_SLCD_LP45 _L_(1) -#define PINMUX_PB19B_SLCD_LP45 ((PIN_PB19B_SLCD_LP45 << 16) | MUX_PB19B_SLCD_LP45) -#define PORT_PB19B_SLCD_LP45 (_UL_(1) << 19) -#define PIN_PB20B_SLCD_LP46 _L_(52) /**< \brief SLCD signal: LP46 on PB20 mux B */ -#define MUX_PB20B_SLCD_LP46 _L_(1) -#define PINMUX_PB20B_SLCD_LP46 ((PIN_PB20B_SLCD_LP46 << 16) | MUX_PB20B_SLCD_LP46) -#define PORT_PB20B_SLCD_LP46 (_UL_(1) << 20) -#define PIN_PB21B_SLCD_LP47 _L_(53) /**< \brief SLCD signal: LP47 on PB21 mux B */ -#define MUX_PB21B_SLCD_LP47 _L_(1) -#define PINMUX_PB21B_SLCD_LP47 ((PIN_PB21B_SLCD_LP47 << 16) | MUX_PB21B_SLCD_LP47) -#define PORT_PB21B_SLCD_LP47 (_UL_(1) << 21) -#define PIN_PA20B_SLCD_LP48 _L_(20) /**< \brief SLCD signal: LP48 on PA20 mux B */ -#define MUX_PA20B_SLCD_LP48 _L_(1) -#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48) -#define PORT_PA20B_SLCD_LP48 (_UL_(1) << 20) -#define PIN_PA21B_SLCD_LP49 _L_(21) /**< \brief SLCD signal: LP49 on PA21 mux B */ -#define MUX_PA21B_SLCD_LP49 _L_(1) -#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49) -#define PORT_PA21B_SLCD_LP49 (_UL_(1) << 21) -#define PIN_PA22B_SLCD_LP50 _L_(22) /**< \brief SLCD signal: LP50 on PA22 mux B */ -#define MUX_PA22B_SLCD_LP50 _L_(1) -#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50) -#define PORT_PA22B_SLCD_LP50 (_UL_(1) << 22) -#define PIN_PA23B_SLCD_LP51 _L_(23) /**< \brief SLCD signal: LP51 on PA23 mux B */ -#define MUX_PA23B_SLCD_LP51 _L_(1) -#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51) -#define PORT_PA23B_SLCD_LP51 (_UL_(1) << 23) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ -#define MUX_PA04I_CCL_IN0 _L_(8) -#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) -#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ -#define MUX_PA16I_CCL_IN0 _L_(8) -#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) -#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ -#define MUX_PB22I_CCL_IN0 _L_(8) -#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) -#define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ -#define MUX_PA05I_CCL_IN1 _L_(8) -#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) -#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ -#define MUX_PA17I_CCL_IN1 _L_(8) -#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) -#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ -#define MUX_PB00I_CCL_IN1 _L_(8) -#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) -#define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ -#define MUX_PA06I_CCL_IN2 _L_(8) -#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) -#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ -#define MUX_PA18I_CCL_IN2 _L_(8) -#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) -#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ -#define MUX_PB01I_CCL_IN2 _L_(8) -#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) -#define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ -#define MUX_PA08I_CCL_IN3 _L_(8) -#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) -#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ -#define MUX_PA30I_CCL_IN3 _L_(8) -#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) -#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ -#define MUX_PA09I_CCL_IN4 _L_(8) -#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) -#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27I_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux I */ -#define MUX_PC27I_CCL_IN4 _L_(8) -#define PINMUX_PC27I_CCL_IN4 ((PIN_PC27I_CCL_IN4 << 16) | MUX_PC27I_CCL_IN4) -#define PORT_PC27I_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ -#define MUX_PA10I_CCL_IN5 _L_(8) -#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) -#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28I_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux I */ -#define MUX_PC28I_CCL_IN5 _L_(8) -#define PINMUX_PC28I_CCL_IN5 ((PIN_PC28I_CCL_IN5 << 16) | MUX_PC28I_CCL_IN5) -#define PORT_PC28I_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ -#define MUX_PA22I_CCL_IN6 _L_(8) -#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) -#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ -#define MUX_PB06I_CCL_IN6 _L_(8) -#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) -#define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ -#define MUX_PA23I_CCL_IN7 _L_(8) -#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) -#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ -#define MUX_PB07I_CCL_IN7 _L_(8) -#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) -#define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ -#define MUX_PA24I_CCL_IN8 _L_(8) -#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) -#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ -#define MUX_PB08I_CCL_IN8 _L_(8) -#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) -#define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ -#define MUX_PB14I_CCL_IN9 _L_(8) -#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) -#define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20I_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux I */ -#define MUX_PC20I_CCL_IN9 _L_(8) -#define PINMUX_PC20I_CCL_IN9 ((PIN_PC20I_CCL_IN9 << 16) | MUX_PC20I_CCL_IN9) -#define PORT_PC20I_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ -#define MUX_PB15I_CCL_IN10 _L_(8) -#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) -#define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21I_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux I */ -#define MUX_PC21I_CCL_IN10 _L_(8) -#define PINMUX_PC21I_CCL_IN10 ((PIN_PC21I_CCL_IN10 << 16) | MUX_PC21I_CCL_IN10) -#define PORT_PC21I_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ -#define MUX_PB16I_CCL_IN11 _L_(8) -#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) -#define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ -#define MUX_PA07I_CCL_OUT0 _L_(8) -#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) -#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ -#define MUX_PA19I_CCL_OUT0 _L_(8) -#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) -#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ -#define MUX_PB02I_CCL_OUT0 _L_(8) -#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) -#define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ -#define MUX_PB23I_CCL_OUT0 _L_(8) -#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) -#define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ -#define MUX_PA11I_CCL_OUT1 _L_(8) -#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) -#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ -#define MUX_PA31I_CCL_OUT1 _L_(8) -#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) -#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ -#define MUX_PB11I_CCL_OUT1 _L_(8) -#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) -#define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ -#define MUX_PA25I_CCL_OUT2 _L_(8) -#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) -#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ -#define MUX_PB09I_CCL_OUT2 _L_(8) -#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) -#define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ -#define MUX_PB17I_CCL_OUT3 _L_(8) -#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) -#define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) - -#endif /* _SAML22N18A_PIO_ */ diff --git a/watch-library/include/sam.h b/watch-library/include/sam.h deleted file mode 100644 index c5702205..00000000 --- a/watch-library/include/sam.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief Top level header file - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _SAM_ -#define _SAM_ - -#if defined(__SAML22G16A__) || defined(__ATSAML22G16A__) -#include "saml22g16a.h" -#elif defined(__SAML22G17A__) || defined(__ATSAML22G17A__) -#include "saml22g17a.h" -#elif defined(__SAML22G18A__) || defined(__ATSAML22G18A__) -#include "saml22g18a.h" -#elif defined(__SAML22J16A__) || defined(__ATSAML22J16A__) -#include "saml22j16a.h" -#elif defined(__SAML22J17A__) || defined(__ATSAML22J17A__) -#include "saml22j17a.h" -#elif defined(__SAML22J18A__) || defined(__ATSAML22J18A__) -#include "saml22j18a.h" -#elif defined(__SAML22N16A__) || defined(__ATSAML22N16A__) -#include "saml22n16a.h" -#elif defined(__SAML22N17A__) || defined(__ATSAML22N17A__) -#include "saml22n17a.h" -#elif defined(__SAML22N18A__) || defined(__ATSAML22N18A__) -#include "saml22n18a.h" -#else -#error Library does not support the specified device -#endif - -#endif /* _SAM_ */ diff --git a/watch-library/include/saml22.h b/watch-library/include/saml22.h deleted file mode 100644 index d1a84287..00000000 --- a/watch-library/include/saml22.h +++ /dev/null @@ -1,60 +0,0 @@ -/** - * \file - * - * \brief Top header file for SAML22 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_ -#define _SAML22_ - -/** - * \defgroup SAML22_definitions SAML22 Device Definitions - * \brief SAML22 CMSIS Definitions. - */ - -#if defined(__SAML22G16A__) || defined(__ATSAML22G16A__) - #include "saml22g16a.h" -#elif defined(__SAML22G17A__) || defined(__ATSAML22G17A__) - #include "saml22g17a.h" -#elif defined(__SAML22G18A__) || defined(__ATSAML22G18A__) - #include "saml22g18a.h" -#elif defined(__SAML22J16A__) || defined(__ATSAML22J16A__) - #include "saml22j16a.h" -#elif defined(__SAML22J17A__) || defined(__ATSAML22J17A__) - #include "saml22j17a.h" -#elif defined(__SAML22J18A__) || defined(__ATSAML22J18A__) - #include "saml22j18a.h" -#elif defined(__SAML22N16A__) || defined(__ATSAML22N16A__) - #include "saml22n16a.h" -#elif defined(__SAML22N17A__) || defined(__ATSAML22N17A__) - #include "saml22n17a.h" -#elif defined(__SAML22N18A__) || defined(__ATSAML22N18A__) - #include "saml22n18a.h" -#else - #error Library does not support the specified device. -#endif - -#endif /* _SAML22_ */ diff --git a/watch-library/include/saml22g16a.h b/watch-library/include/saml22g16a.h deleted file mode 100644 index d2690bd4..00000000 --- a/watch-library/include/saml22g16a.h +++ /dev/null @@ -1,596 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML22G16A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22G16A_ -#define _SAML22G16A_ - -/** - * \ingroup SAML22_definitions - * \addtogroup SAML22G16A_definitions SAML22G16A definitions - * This file defines all structures and symbols for SAML22G16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML22G16A */ -/* ************************************************************************** */ -/** \defgroup SAML22G16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAML22G16A-specific Interrupt Numbers *********************/ - SYSTEM_IRQn = 0, /**< 0 SAML22G16A System Interrupts */ - WDT_IRQn = 1, /**< 1 SAML22G16A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML22G16A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML22G16A External Interrupt Controller (EIC) */ - FREQM_IRQn = 4, /**< 4 SAML22G16A Frequency Meter (FREQM) */ - USB_IRQn = 5, /**< 5 SAML22G16A Universal Serial Bus (USB) */ - NVMCTRL_IRQn = 6, /**< 6 SAML22G16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 7, /**< 7 SAML22G16A Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAML22G16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAML22G16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAML22G16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAML22G16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAML22G16A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAML22G16A Timer Counter Control (TCC0) */ - TC0_IRQn = 16, /**< 16 SAML22G16A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 17, /**< 17 SAML22G16A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 18, /**< 18 SAML22G16A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 19, /**< 19 SAML22G16A Basic Timer Counter 3 (TC3) */ - ADC_IRQn = 20, /**< 20 SAML22G16A Analog Digital Converter (ADC) */ - AC_IRQn = 21, /**< 21 SAML22G16A Analog Comparators (AC) */ - PTC_IRQn = 22, /**< 22 SAML22G16A Peripheral Touch Controller (PTC) */ - SLCD_IRQn = 23, /**< 23 SAML22G16A Segment Liquid Crystal Display Controller (SLCD) */ - AES_IRQn = 24, /**< 24 SAML22G16A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 25, /**< 25 SAML22G16A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnFREQM_Handler; /* 4 Frequency Meter */ - void* pfnUSB_Handler; /* 5 Universal Serial Bus */ - void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control */ - void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ - void* pfnADC_Handler; /* 20 Analog Digital Converter */ - void* pfnAC_Handler; /* 21 Analog Comparators */ - void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ - void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ - void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 25 True Random Generator */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void FREQM_Handler ( void ); -void USB_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void PTC_Handler ( void ); -void SLCD_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml22.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22G16A */ -/* ************************************************************************** */ -/** \defgroup SAML22G16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/slcd.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML22G16A */ -/* ************************************************************************** */ -/** \defgroup SAML22G16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/slcd.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML22G16A */ -/* ************************************************************************** */ -/** \defgroup SAML22G16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 77 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ -#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ -#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ - -#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML22G16A */ -/* ************************************************************************** */ -/** \defgroup SAML22G16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42003400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ -#define AES (0x42004000) /**< \brief (AES) APB Base Address */ -#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ -#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ -#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ -#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 27 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ -#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ -#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ -#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML22G16A */ -/* ************************************************************************** */ -/** \defgroup SAML22G16A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml22g16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML22G16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x1082010C) -#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML22G16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML22G16A_H */ diff --git a/watch-library/include/saml22g17a.h b/watch-library/include/saml22g17a.h deleted file mode 100644 index d3932fc0..00000000 --- a/watch-library/include/saml22g17a.h +++ /dev/null @@ -1,596 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML22G17A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22G17A_ -#define _SAML22G17A_ - -/** - * \ingroup SAML22_definitions - * \addtogroup SAML22G17A_definitions SAML22G17A definitions - * This file defines all structures and symbols for SAML22G17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML22G17A */ -/* ************************************************************************** */ -/** \defgroup SAML22G17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAML22G17A-specific Interrupt Numbers *********************/ - SYSTEM_IRQn = 0, /**< 0 SAML22G17A System Interrupts */ - WDT_IRQn = 1, /**< 1 SAML22G17A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML22G17A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML22G17A External Interrupt Controller (EIC) */ - FREQM_IRQn = 4, /**< 4 SAML22G17A Frequency Meter (FREQM) */ - USB_IRQn = 5, /**< 5 SAML22G17A Universal Serial Bus (USB) */ - NVMCTRL_IRQn = 6, /**< 6 SAML22G17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 7, /**< 7 SAML22G17A Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAML22G17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAML22G17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAML22G17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAML22G17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAML22G17A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAML22G17A Timer Counter Control (TCC0) */ - TC0_IRQn = 16, /**< 16 SAML22G17A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 17, /**< 17 SAML22G17A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 18, /**< 18 SAML22G17A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 19, /**< 19 SAML22G17A Basic Timer Counter 3 (TC3) */ - ADC_IRQn = 20, /**< 20 SAML22G17A Analog Digital Converter (ADC) */ - AC_IRQn = 21, /**< 21 SAML22G17A Analog Comparators (AC) */ - PTC_IRQn = 22, /**< 22 SAML22G17A Peripheral Touch Controller (PTC) */ - SLCD_IRQn = 23, /**< 23 SAML22G17A Segment Liquid Crystal Display Controller (SLCD) */ - AES_IRQn = 24, /**< 24 SAML22G17A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 25, /**< 25 SAML22G17A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnFREQM_Handler; /* 4 Frequency Meter */ - void* pfnUSB_Handler; /* 5 Universal Serial Bus */ - void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control */ - void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ - void* pfnADC_Handler; /* 20 Analog Digital Converter */ - void* pfnAC_Handler; /* 21 Analog Comparators */ - void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ - void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ - void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 25 True Random Generator */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void FREQM_Handler ( void ); -void USB_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void PTC_Handler ( void ); -void SLCD_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml22.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22G17A */ -/* ************************************************************************** */ -/** \defgroup SAML22G17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/slcd.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML22G17A */ -/* ************************************************************************** */ -/** \defgroup SAML22G17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/slcd.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML22G17A */ -/* ************************************************************************** */ -/** \defgroup SAML22G17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 77 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ -#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ -#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ - -#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML22G17A */ -/* ************************************************************************** */ -/** \defgroup SAML22G17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42003400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ -#define AES (0x42004000) /**< \brief (AES) APB Base Address */ -#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ -#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ -#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ -#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 27 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ -#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ -#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ -#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML22G17A */ -/* ************************************************************************** */ -/** \defgroup SAML22G17A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml22g17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML22G17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x1082010B) -#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML22G17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML22G17A_H */ diff --git a/watch-library/include/saml22g18a.h b/watch-library/include/saml22g18a.h deleted file mode 100644 index 588a3f1e..00000000 --- a/watch-library/include/saml22g18a.h +++ /dev/null @@ -1,596 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML22G18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22G18A_ -#define _SAML22G18A_ - -/** - * \ingroup SAML22_definitions - * \addtogroup SAML22G18A_definitions SAML22G18A definitions - * This file defines all structures and symbols for SAML22G18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML22G18A */ -/* ************************************************************************** */ -/** \defgroup SAML22G18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAML22G18A-specific Interrupt Numbers *********************/ - SYSTEM_IRQn = 0, /**< 0 SAML22G18A System Interrupts */ - WDT_IRQn = 1, /**< 1 SAML22G18A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML22G18A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML22G18A External Interrupt Controller (EIC) */ - FREQM_IRQn = 4, /**< 4 SAML22G18A Frequency Meter (FREQM) */ - USB_IRQn = 5, /**< 5 SAML22G18A Universal Serial Bus (USB) */ - NVMCTRL_IRQn = 6, /**< 6 SAML22G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 7, /**< 7 SAML22G18A Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAML22G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAML22G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAML22G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAML22G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAML22G18A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAML22G18A Timer Counter Control (TCC0) */ - TC0_IRQn = 16, /**< 16 SAML22G18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 17, /**< 17 SAML22G18A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 18, /**< 18 SAML22G18A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 19, /**< 19 SAML22G18A Basic Timer Counter 3 (TC3) */ - ADC_IRQn = 20, /**< 20 SAML22G18A Analog Digital Converter (ADC) */ - AC_IRQn = 21, /**< 21 SAML22G18A Analog Comparators (AC) */ - PTC_IRQn = 22, /**< 22 SAML22G18A Peripheral Touch Controller (PTC) */ - SLCD_IRQn = 23, /**< 23 SAML22G18A Segment Liquid Crystal Display Controller (SLCD) */ - AES_IRQn = 24, /**< 24 SAML22G18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 25, /**< 25 SAML22G18A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnFREQM_Handler; /* 4 Frequency Meter */ - void* pfnUSB_Handler; /* 5 Universal Serial Bus */ - void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control */ - void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ - void* pfnADC_Handler; /* 20 Analog Digital Converter */ - void* pfnAC_Handler; /* 21 Analog Comparators */ - void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ - void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ - void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 25 True Random Generator */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void FREQM_Handler ( void ); -void USB_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void PTC_Handler ( void ); -void SLCD_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml22.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22G18A */ -/* ************************************************************************** */ -/** \defgroup SAML22G18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/slcd.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML22G18A */ -/* ************************************************************************** */ -/** \defgroup SAML22G18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/slcd.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML22G18A */ -/* ************************************************************************** */ -/** \defgroup SAML22G18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 77 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ -#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ -#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ - -#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML22G18A */ -/* ************************************************************************** */ -/** \defgroup SAML22G18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42003400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ -#define AES (0x42004000) /**< \brief (AES) APB Base Address */ -#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ -#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ -#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ -#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 27 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ -#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ -#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ -#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML22G18A */ -/* ************************************************************************** */ -/** \defgroup SAML22G18A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml22g18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML22G18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x1082010A) -#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML22G18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML22G18A_H */ diff --git a/watch-library/include/saml22j16a.h b/watch-library/include/saml22j16a.h deleted file mode 100644 index 35d65a1c..00000000 --- a/watch-library/include/saml22j16a.h +++ /dev/null @@ -1,596 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML22J16A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22J16A_ -#define _SAML22J16A_ - -/** - * \ingroup SAML22_definitions - * \addtogroup SAML22J16A_definitions SAML22J16A definitions - * This file defines all structures and symbols for SAML22J16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML22J16A */ -/* ************************************************************************** */ -/** \defgroup SAML22J16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAML22J16A-specific Interrupt Numbers *********************/ - SYSTEM_IRQn = 0, /**< 0 SAML22J16A System Interrupts */ - WDT_IRQn = 1, /**< 1 SAML22J16A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML22J16A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML22J16A External Interrupt Controller (EIC) */ - FREQM_IRQn = 4, /**< 4 SAML22J16A Frequency Meter (FREQM) */ - USB_IRQn = 5, /**< 5 SAML22J16A Universal Serial Bus (USB) */ - NVMCTRL_IRQn = 6, /**< 6 SAML22J16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 7, /**< 7 SAML22J16A Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAML22J16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAML22J16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAML22J16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAML22J16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAML22J16A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAML22J16A Timer Counter Control (TCC0) */ - TC0_IRQn = 16, /**< 16 SAML22J16A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 17, /**< 17 SAML22J16A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 18, /**< 18 SAML22J16A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 19, /**< 19 SAML22J16A Basic Timer Counter 3 (TC3) */ - ADC_IRQn = 20, /**< 20 SAML22J16A Analog Digital Converter (ADC) */ - AC_IRQn = 21, /**< 21 SAML22J16A Analog Comparators (AC) */ - PTC_IRQn = 22, /**< 22 SAML22J16A Peripheral Touch Controller (PTC) */ - SLCD_IRQn = 23, /**< 23 SAML22J16A Segment Liquid Crystal Display Controller (SLCD) */ - AES_IRQn = 24, /**< 24 SAML22J16A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 25, /**< 25 SAML22J16A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnFREQM_Handler; /* 4 Frequency Meter */ - void* pfnUSB_Handler; /* 5 Universal Serial Bus */ - void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control */ - void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ - void* pfnADC_Handler; /* 20 Analog Digital Converter */ - void* pfnAC_Handler; /* 21 Analog Comparators */ - void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ - void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ - void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 25 True Random Generator */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void FREQM_Handler ( void ); -void USB_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void PTC_Handler ( void ); -void SLCD_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml22.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22J16A */ -/* ************************************************************************** */ -/** \defgroup SAML22J16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/slcd.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML22J16A */ -/* ************************************************************************** */ -/** \defgroup SAML22J16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/slcd.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML22J16A */ -/* ************************************************************************** */ -/** \defgroup SAML22J16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 77 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ -#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ -#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ - -#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML22J16A */ -/* ************************************************************************** */ -/** \defgroup SAML22J16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42003400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ -#define AES (0x42004000) /**< \brief (AES) APB Base Address */ -#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ -#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ -#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ -#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 27 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ -#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ -#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ -#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML22J16A */ -/* ************************************************************************** */ -/** \defgroup SAML22J16A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml22j16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML22J16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10820107) -#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML22J16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML22J16A_H */ diff --git a/watch-library/include/saml22j17a.h b/watch-library/include/saml22j17a.h deleted file mode 100644 index a1c95952..00000000 --- a/watch-library/include/saml22j17a.h +++ /dev/null @@ -1,596 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML22J17A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22J17A_ -#define _SAML22J17A_ - -/** - * \ingroup SAML22_definitions - * \addtogroup SAML22J17A_definitions SAML22J17A definitions - * This file defines all structures and symbols for SAML22J17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML22J17A */ -/* ************************************************************************** */ -/** \defgroup SAML22J17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAML22J17A-specific Interrupt Numbers *********************/ - SYSTEM_IRQn = 0, /**< 0 SAML22J17A System Interrupts */ - WDT_IRQn = 1, /**< 1 SAML22J17A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML22J17A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML22J17A External Interrupt Controller (EIC) */ - FREQM_IRQn = 4, /**< 4 SAML22J17A Frequency Meter (FREQM) */ - USB_IRQn = 5, /**< 5 SAML22J17A Universal Serial Bus (USB) */ - NVMCTRL_IRQn = 6, /**< 6 SAML22J17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 7, /**< 7 SAML22J17A Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAML22J17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAML22J17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAML22J17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAML22J17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAML22J17A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAML22J17A Timer Counter Control (TCC0) */ - TC0_IRQn = 16, /**< 16 SAML22J17A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 17, /**< 17 SAML22J17A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 18, /**< 18 SAML22J17A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 19, /**< 19 SAML22J17A Basic Timer Counter 3 (TC3) */ - ADC_IRQn = 20, /**< 20 SAML22J17A Analog Digital Converter (ADC) */ - AC_IRQn = 21, /**< 21 SAML22J17A Analog Comparators (AC) */ - PTC_IRQn = 22, /**< 22 SAML22J17A Peripheral Touch Controller (PTC) */ - SLCD_IRQn = 23, /**< 23 SAML22J17A Segment Liquid Crystal Display Controller (SLCD) */ - AES_IRQn = 24, /**< 24 SAML22J17A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 25, /**< 25 SAML22J17A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnFREQM_Handler; /* 4 Frequency Meter */ - void* pfnUSB_Handler; /* 5 Universal Serial Bus */ - void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control */ - void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ - void* pfnADC_Handler; /* 20 Analog Digital Converter */ - void* pfnAC_Handler; /* 21 Analog Comparators */ - void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ - void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ - void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 25 True Random Generator */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void FREQM_Handler ( void ); -void USB_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void PTC_Handler ( void ); -void SLCD_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml22.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22J17A */ -/* ************************************************************************** */ -/** \defgroup SAML22J17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/slcd.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML22J17A */ -/* ************************************************************************** */ -/** \defgroup SAML22J17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/slcd.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML22J17A */ -/* ************************************************************************** */ -/** \defgroup SAML22J17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 77 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ -#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ -#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ - -#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML22J17A */ -/* ************************************************************************** */ -/** \defgroup SAML22J17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42003400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ -#define AES (0x42004000) /**< \brief (AES) APB Base Address */ -#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ -#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ -#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ -#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 27 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ -#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ -#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ -#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML22J17A */ -/* ************************************************************************** */ -/** \defgroup SAML22J17A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml22j17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML22J17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10820106) -#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML22J17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML22J17A_H */ diff --git a/watch-library/include/saml22j18a.h b/watch-library/include/saml22j18a.h deleted file mode 100644 index 8286db88..00000000 --- a/watch-library/include/saml22j18a.h +++ /dev/null @@ -1,596 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML22J18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22J18A_ -#define _SAML22J18A_ - -/** - * \ingroup SAML22_definitions - * \addtogroup SAML22J18A_definitions SAML22J18A definitions - * This file defines all structures and symbols for SAML22J18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML22J18A */ -/* ************************************************************************** */ -/** \defgroup SAML22J18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAML22J18A-specific Interrupt Numbers *********************/ - SYSTEM_IRQn = 0, /**< 0 SAML22J18A System Interrupts */ - WDT_IRQn = 1, /**< 1 SAML22J18A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML22J18A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML22J18A External Interrupt Controller (EIC) */ - FREQM_IRQn = 4, /**< 4 SAML22J18A Frequency Meter (FREQM) */ - USB_IRQn = 5, /**< 5 SAML22J18A Universal Serial Bus (USB) */ - NVMCTRL_IRQn = 6, /**< 6 SAML22J18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 7, /**< 7 SAML22J18A Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAML22J18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAML22J18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAML22J18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAML22J18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAML22J18A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAML22J18A Timer Counter Control (TCC0) */ - TC0_IRQn = 16, /**< 16 SAML22J18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 17, /**< 17 SAML22J18A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 18, /**< 18 SAML22J18A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 19, /**< 19 SAML22J18A Basic Timer Counter 3 (TC3) */ - ADC_IRQn = 20, /**< 20 SAML22J18A Analog Digital Converter (ADC) */ - AC_IRQn = 21, /**< 21 SAML22J18A Analog Comparators (AC) */ - PTC_IRQn = 22, /**< 22 SAML22J18A Peripheral Touch Controller (PTC) */ - SLCD_IRQn = 23, /**< 23 SAML22J18A Segment Liquid Crystal Display Controller (SLCD) */ - AES_IRQn = 24, /**< 24 SAML22J18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 25, /**< 25 SAML22J18A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnFREQM_Handler; /* 4 Frequency Meter */ - void* pfnUSB_Handler; /* 5 Universal Serial Bus */ - void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control */ - void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ - void* pfnADC_Handler; /* 20 Analog Digital Converter */ - void* pfnAC_Handler; /* 21 Analog Comparators */ - void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ - void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ - void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 25 True Random Generator */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void FREQM_Handler ( void ); -void USB_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void PTC_Handler ( void ); -void SLCD_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml22.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22J18A */ -/* ************************************************************************** */ -/** \defgroup SAML22J18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/slcd.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML22J18A */ -/* ************************************************************************** */ -/** \defgroup SAML22J18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/slcd.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML22J18A */ -/* ************************************************************************** */ -/** \defgroup SAML22J18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 77 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ -#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ -#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ - -#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML22J18A */ -/* ************************************************************************** */ -/** \defgroup SAML22J18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42003400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ -#define AES (0x42004000) /**< \brief (AES) APB Base Address */ -#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ -#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ -#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ -#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 27 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ -#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ -#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ -#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML22J18A */ -/* ************************************************************************** */ -/** \defgroup SAML22J18A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml22j18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML22J18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10820105) -#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML22J18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML22J18A_H */ diff --git a/watch-library/include/saml22n16a.h b/watch-library/include/saml22n16a.h deleted file mode 100644 index 34ea155d..00000000 --- a/watch-library/include/saml22n16a.h +++ /dev/null @@ -1,608 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML22N16A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22N16A_ -#define _SAML22N16A_ - -/** - * \ingroup SAML22_definitions - * \addtogroup SAML22N16A_definitions SAML22N16A definitions - * This file defines all structures and symbols for SAML22N16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML22N16A */ -/* ************************************************************************** */ -/** \defgroup SAML22N16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAML22N16A-specific Interrupt Numbers *********************/ - SYSTEM_IRQn = 0, /**< 0 SAML22N16A System Interrupts */ - WDT_IRQn = 1, /**< 1 SAML22N16A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML22N16A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML22N16A External Interrupt Controller (EIC) */ - FREQM_IRQn = 4, /**< 4 SAML22N16A Frequency Meter (FREQM) */ - USB_IRQn = 5, /**< 5 SAML22N16A Universal Serial Bus (USB) */ - NVMCTRL_IRQn = 6, /**< 6 SAML22N16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 7, /**< 7 SAML22N16A Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAML22N16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAML22N16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAML22N16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAML22N16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAML22N16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAML22N16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAML22N16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAML22N16A Timer Counter Control (TCC0) */ - TC0_IRQn = 16, /**< 16 SAML22N16A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 17, /**< 17 SAML22N16A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 18, /**< 18 SAML22N16A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 19, /**< 19 SAML22N16A Basic Timer Counter 3 (TC3) */ - ADC_IRQn = 20, /**< 20 SAML22N16A Analog Digital Converter (ADC) */ - AC_IRQn = 21, /**< 21 SAML22N16A Analog Comparators (AC) */ - PTC_IRQn = 22, /**< 22 SAML22N16A Peripheral Touch Controller (PTC) */ - SLCD_IRQn = 23, /**< 23 SAML22N16A Segment Liquid Crystal Display Controller (SLCD) */ - AES_IRQn = 24, /**< 24 SAML22N16A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 25, /**< 25 SAML22N16A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnFREQM_Handler; /* 4 Frequency Meter */ - void* pfnUSB_Handler; /* 5 Universal Serial Bus */ - void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control */ - void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ - void* pfnADC_Handler; /* 20 Analog Digital Converter */ - void* pfnAC_Handler; /* 21 Analog Comparators */ - void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ - void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ - void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 25 True Random Generator */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void FREQM_Handler ( void ); -void USB_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void PTC_Handler ( void ); -void SLCD_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml22.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22N16A */ -/* ************************************************************************** */ -/** \defgroup SAML22N16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/slcd.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML22N16A */ -/* ************************************************************************** */ -/** \defgroup SAML22N16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/slcd.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML22N16A */ -/* ************************************************************************** */ -/** \defgroup SAML22N16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 77 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ -#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ -#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ - -#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML22N16A */ -/* ************************************************************************** */ -/** \defgroup SAML22N16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42003400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ -#define AES (0x42004000) /**< \brief (AES) APB Base Address */ -#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ -#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ -#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ -#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 27 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ -#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ -#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ -#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML22N16A */ -/* ************************************************************************** */ -/** \defgroup SAML22N16A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml22n16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML22N16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10820102) -#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ -#define PORT_GROUPS 3 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML22N16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML22N16A_H */ diff --git a/watch-library/include/saml22n17a.h b/watch-library/include/saml22n17a.h deleted file mode 100644 index 7b3cd85a..00000000 --- a/watch-library/include/saml22n17a.h +++ /dev/null @@ -1,608 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML22N17A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22N17A_ -#define _SAML22N17A_ - -/** - * \ingroup SAML22_definitions - * \addtogroup SAML22N17A_definitions SAML22N17A definitions - * This file defines all structures and symbols for SAML22N17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML22N17A */ -/* ************************************************************************** */ -/** \defgroup SAML22N17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAML22N17A-specific Interrupt Numbers *********************/ - SYSTEM_IRQn = 0, /**< 0 SAML22N17A System Interrupts */ - WDT_IRQn = 1, /**< 1 SAML22N17A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML22N17A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML22N17A External Interrupt Controller (EIC) */ - FREQM_IRQn = 4, /**< 4 SAML22N17A Frequency Meter (FREQM) */ - USB_IRQn = 5, /**< 5 SAML22N17A Universal Serial Bus (USB) */ - NVMCTRL_IRQn = 6, /**< 6 SAML22N17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 7, /**< 7 SAML22N17A Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAML22N17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAML22N17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAML22N17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAML22N17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAML22N17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAML22N17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAML22N17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAML22N17A Timer Counter Control (TCC0) */ - TC0_IRQn = 16, /**< 16 SAML22N17A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 17, /**< 17 SAML22N17A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 18, /**< 18 SAML22N17A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 19, /**< 19 SAML22N17A Basic Timer Counter 3 (TC3) */ - ADC_IRQn = 20, /**< 20 SAML22N17A Analog Digital Converter (ADC) */ - AC_IRQn = 21, /**< 21 SAML22N17A Analog Comparators (AC) */ - PTC_IRQn = 22, /**< 22 SAML22N17A Peripheral Touch Controller (PTC) */ - SLCD_IRQn = 23, /**< 23 SAML22N17A Segment Liquid Crystal Display Controller (SLCD) */ - AES_IRQn = 24, /**< 24 SAML22N17A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 25, /**< 25 SAML22N17A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnFREQM_Handler; /* 4 Frequency Meter */ - void* pfnUSB_Handler; /* 5 Universal Serial Bus */ - void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control */ - void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ - void* pfnADC_Handler; /* 20 Analog Digital Converter */ - void* pfnAC_Handler; /* 21 Analog Comparators */ - void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ - void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ - void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 25 True Random Generator */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void FREQM_Handler ( void ); -void USB_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void PTC_Handler ( void ); -void SLCD_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml22.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22N17A */ -/* ************************************************************************** */ -/** \defgroup SAML22N17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/slcd.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML22N17A */ -/* ************************************************************************** */ -/** \defgroup SAML22N17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/slcd.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML22N17A */ -/* ************************************************************************** */ -/** \defgroup SAML22N17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 77 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ -#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ -#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ - -#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML22N17A */ -/* ************************************************************************** */ -/** \defgroup SAML22N17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42003400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ -#define AES (0x42004000) /**< \brief (AES) APB Base Address */ -#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ -#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ -#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ -#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 27 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ -#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ -#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ -#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML22N17A */ -/* ************************************************************************** */ -/** \defgroup SAML22N17A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml22n17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML22N17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10820101) -#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ -#define PORT_GROUPS 3 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML22N17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML22N17A_H */ diff --git a/watch-library/include/saml22n18a.h b/watch-library/include/saml22n18a.h deleted file mode 100644 index de160b83..00000000 --- a/watch-library/include/saml22n18a.h +++ /dev/null @@ -1,608 +0,0 @@ -/** - * \file - * - * \brief Header file for SAML22N18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22N18A_ -#define _SAML22N18A_ - -/** - * \ingroup SAML22_definitions - * \addtogroup SAML22N18A_definitions SAML22N18A definitions - * This file defines all structures and symbols for SAML22N18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML22N18A */ -/* ************************************************************************** */ -/** \defgroup SAML22N18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAML22N18A-specific Interrupt Numbers *********************/ - SYSTEM_IRQn = 0, /**< 0 SAML22N18A System Interrupts */ - WDT_IRQn = 1, /**< 1 SAML22N18A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML22N18A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML22N18A External Interrupt Controller (EIC) */ - FREQM_IRQn = 4, /**< 4 SAML22N18A Frequency Meter (FREQM) */ - USB_IRQn = 5, /**< 5 SAML22N18A Universal Serial Bus (USB) */ - NVMCTRL_IRQn = 6, /**< 6 SAML22N18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 7, /**< 7 SAML22N18A Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAML22N18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAML22N18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAML22N18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAML22N18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAML22N18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAML22N18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAML22N18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAML22N18A Timer Counter Control (TCC0) */ - TC0_IRQn = 16, /**< 16 SAML22N18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 17, /**< 17 SAML22N18A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 18, /**< 18 SAML22N18A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 19, /**< 19 SAML22N18A Basic Timer Counter 3 (TC3) */ - ADC_IRQn = 20, /**< 20 SAML22N18A Analog Digital Converter (ADC) */ - AC_IRQn = 21, /**< 21 SAML22N18A Analog Comparators (AC) */ - PTC_IRQn = 22, /**< 22 SAML22N18A Peripheral Touch Controller (PTC) */ - SLCD_IRQn = 23, /**< 23 SAML22N18A Segment Liquid Crystal Display Controller (SLCD) */ - AES_IRQn = 24, /**< 24 SAML22N18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 25, /**< 25 SAML22N18A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 26 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnFREQM_Handler; /* 4 Frequency Meter */ - void* pfnUSB_Handler; /* 5 Universal Serial Bus */ - void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control */ - void* pfnTC0_Handler; /* 16 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 17 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 18 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 19 Basic Timer Counter 3 */ - void* pfnADC_Handler; /* 20 Analog Digital Converter */ - void* pfnAC_Handler; /* 21 Analog Comparators */ - void* pfnPTC_Handler; /* 22 Peripheral Touch Controller */ - void* pfnSLCD_Handler; /* 23 Segment Liquid Crystal Display Controller */ - void* pfnAES_Handler; /* 24 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 25 True Random Generator */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void FREQM_Handler ( void ); -void USB_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void PTC_Handler ( void ); -void SLCD_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml22.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML22N18A */ -/* ************************************************************************** */ -/** \defgroup SAML22N18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/slcd.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML22N18A */ -/* ************************************************************************** */ -/** \defgroup SAML22N18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/slcd.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML22N18A */ -/* ************************************************************************** */ -/** \defgroup SAML22N18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 37 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 71 /**< \brief Timer Counter Control (TCC0) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_ADC 76 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 77 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 78 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_SLCD 79 /**< \brief Segment Liquid Crystal Display Controller (SLCD) */ -#define ID_AES 80 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 81 /**< \brief True Random Generator (TRNG) */ -#define ID_CCL 82 /**< \brief Configurable Custom Logic (CCL) */ - -#define ID_PERIPH_COUNT 83 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML22N18A */ -/* ************************************************************************** */ -/** \defgroup SAML22N18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42003400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42003000) /**< \brief (ADC) APB Base Address */ -#define AES (0x42004000) /**< \brief (AES) APB Base Address */ -#define CCL (0x42004800) /**< \brief (CCL) APB Base Address */ -#define DMAC (0x41008000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x4100A000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41006000) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42003800) /**< \brief (PTC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ -#define SLCD (0x42003C00) /**< \brief (SLCD) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x42001C00) /**< \brief (TCC0) APB Base Address */ -#define TRNG (0x42004400) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42003400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42003000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42004000UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42004800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DMAC ((Dmac *)0x41008000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x4100A000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41006000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42003800UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 27 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SLCD ((Slcd *)0x42003C00UL) /**< \brief (SLCD) APB Base Address */ -#define SLCD_INST_NUM 1 /**< \brief (SLCD) Number of instances */ -#define SLCD_INSTS { SLCD } /**< \brief (SLCD) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001C00UL) /**< \brief (TCC0) APB Base Address */ -#define TCC_INST_NUM 1 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42004400UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML22N18A */ -/* ************************************************************************** */ -/** \defgroup SAML22N18A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml22n18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML22N18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10820100) -#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ -#define PORT_GROUPS 3 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML22N18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML22N18A_H */ diff --git a/watch-library/include/system_saml22.h b/watch-library/include/system_saml22.h deleted file mode 100644 index e41bb831..00000000 --- a/watch-library/include/system_saml22.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SYSTEM_SAML22_H_INCLUDED_ -#define _SYSTEM_SAML22_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAML22_H_INCLUDED */ diff --git a/watch-library/linker/saml22j18.ld b/watch-library/linker/saml22j18.ld deleted file mode 100755 index a9801509..00000000 --- a/watch-library/linker/saml22j18.ld +++ /dev/null @@ -1,145 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAML22J18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x2000, LENGTH = 0x00040000-0x2000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; - -ENTRY(Reset_Handler) - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/watch-library/main.c b/watch-library/main.c deleted file mode 100755 index 1fe751ef..00000000 --- a/watch-library/main.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2021 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -//----------------------------------------------------------------------------- -#include -#include -#include -#include -#include -#include "saml22.h" -#include "hal_init.h" -#include "pins.h" -#include "watch.h" -#include "tusb.h" - -int main(void) { - // ASF code. Initialize the MCU with configuration options from Atmel Studio. - init_mcu(); - - // check if we are plugged into USB power. - watch_enable_digital_input(VBUS_DET); - watch_enable_pull_down(VBUS_DET); - if (watch_get_pin_level(VBUS_DET)) { - // if so, enable USB functionality. - _watch_enable_usb(); - } - watch_disable_digital_input(VBUS_DET); - - // initialize the delay driver before any user code is called. - delay_driver_init(); - - // User code. Give the app a chance to initialize its data structures and state. - app_init(); - - // If the RTC is already enabled, we're either waking from BACKUP mode or a reset. - // Ideally we should check if the TAMPER or CMP0 (alarm) flags are set. - if (_watch_rtc_is_enabled()) { - // User code. Give the application a chance to restore state from backup registers. - app_wake_from_backup(); - - // disable the tamper interrupt and clear the tamper bit - hri_rtcmode0_clear_INTEN_TAMPER_bit(RTC); - hri_rtcmode0_clear_interrupt_TAMPER_bit(RTC); - } - - // Watch library code. Set initial parameters for the device and enable the RTC. - _watch_init(); - - // User code. Give the app a chance to enable and set up peripherals. - app_setup(); - - while (1) { - bool usb_enabled = hri_usbdevice_get_CTRLA_ENABLE_bit(USB); - bool can_sleep = app_loop(); - - if (can_sleep && !usb_enabled) { - app_prepare_for_standby(); - sleep(4); - app_wake_from_standby(); - } - } - - return 0; -} diff --git a/watch-library/shared/config/RTE_Components.h b/watch-library/shared/config/RTE_Components.h new file mode 100644 index 00000000..3ba6b1ba --- /dev/null +++ b/watch-library/shared/config/RTE_Components.h @@ -0,0 +1,54 @@ + /** + * \file + * + * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME) + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \acme_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \acme_license_stop + * + * Project: My Project + * Target: ATSAML22J18A + * + **/ + + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +#define ATMEL_START + +#endif /* RTE_COMPONENTS_H */ diff --git a/watch-library/shared/config/hpl_dmac_config.h b/watch-library/shared/config/hpl_dmac_config.h new file mode 100644 index 00000000..36adb88b --- /dev/null +++ b/watch-library/shared/config/hpl_dmac_config.h @@ -0,0 +1,3122 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 0 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif + +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 0 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif + +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 0 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif + +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 0 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif + +// Data Transfer Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the data transfer operation +// dmac_dqos +#ifndef CONF_DMAC_DQOS +#define CONF_DMAC_DQOS 0 +#endif + +// Fetch Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the fetch operation +// dmac_fqos +#ifndef CONF_DMAC_FQOS +#define CONF_DMAC_FQOS 0 +#endif + +// Write-Back Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the write-back operation +// dmac_wrbqos +#ifndef CONF_DMAC_WRBQOS +#define CONF_DMAC_WRBQOS 0 +#endif + +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 0 is enabled or not +// dmac_enable_0 +#ifndef CONF_DMAC_ENABLE_0 +#define CONF_DMAC_ENABLE_0 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 1 is enabled or not +// dmac_enable_1 +#ifndef CONF_DMAC_ENABLE_1 +#define CONF_DMAC_ENABLE_1 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 2 is enabled or not +// dmac_enable_2 +#ifndef CONF_DMAC_ENABLE_2 +#define CONF_DMAC_ENABLE_2 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 3 is enabled or not +// dmac_enable_3 +#ifndef CONF_DMAC_ENABLE_3 +#define CONF_DMAC_ENABLE_3 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 4 is enabled or not +// dmac_enable_4 +#ifndef CONF_DMAC_ENABLE_4 +#define CONF_DMAC_ENABLE_4 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 5 is enabled or not +// dmac_enable_5 +#ifndef CONF_DMAC_ENABLE_5 +#define CONF_DMAC_ENABLE_5 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 6 is enabled or not +// dmac_enable_6 +#ifndef CONF_DMAC_ENABLE_6 +#define CONF_DMAC_ENABLE_6 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 7 is enabled or not +// dmac_enable_7 +#ifndef CONF_DMAC_ENABLE_7 +#define CONF_DMAC_ENABLE_7 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 8 is enabled or not +// dmac_enable_8 +#ifndef CONF_DMAC_ENABLE_8 +#define CONF_DMAC_ENABLE_8 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 9 is enabled or not +// dmac_enable_9 +#ifndef CONF_DMAC_ENABLE_9 +#define CONF_DMAC_ENABLE_9 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 10 is enabled or not +// dmac_enable_10 +#ifndef CONF_DMAC_ENABLE_10 +#define CONF_DMAC_ENABLE_10 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 11 is enabled or not +// dmac_enable_11 +#ifndef CONF_DMAC_ENABLE_11 +#define CONF_DMAC_ENABLE_11 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 12 is enabled or not +// dmac_enable_12 +#ifndef CONF_DMAC_ENABLE_12 +#define CONF_DMAC_ENABLE_12 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 13 is enabled or not +// dmac_enable_13 +#ifndef CONF_DMAC_ENABLE_13 +#define CONF_DMAC_ENABLE_13 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 14 is enabled or not +// dmac_enable_14 +#ifndef CONF_DMAC_ENABLE_14 +#define CONF_DMAC_ENABLE_14 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 15 is enabled or not +// dmac_enable_15 +#ifndef CONF_DMAC_ENABLE_15 +#define CONF_DMAC_ENABLE_15 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Timestamp +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> TCC0 Overflow Trigger +// <0x0F=> TCC0 Match/Compare 0 Trigger +// <0x10=> TCC0 Match/Compare 1 Trigger +// <0x11=> TCC0 Match/Compare 2 Trigger +// <0x12=> TCC0 Match/Compare 3 Trigger +// <0x13=> TC0 Overflow Trigger +// <0x14=> TC0 Match/Compare 0 Trigger +// <0x15=> TC0 Match/Compare 1 Trigger +// <0x16=> TC1 Overflow Trigger +// <0x17=> TC1 Match/Compare 0 Trigger +// <0x18=> TC1 Match/Compare 1 Trigger +// <0x19=> TC2 Overflow Trigger +// <0x1A=> TC2 Match/Compare 0 Trigger +// <0x1B=> TC2 Match/Compare 1 Trigger +// <0x1C=> TC3 Overflow Trigger +// <0x1D=> TC3 Match/Compare 0 Trigger +// <0x1E=> TC3 Match/Compare 1 Trigger +// <0x1F=> ADC Result Ready Trigger +// <0x20=> SLCD Display Memory Update Trigger +// <0x21=> SLCD Automated Character Mapping Data Ready Trigger +// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger +// <0x23=> AES Write Trigger +// <0x24=> AES Read Trigger +// <0x25=> PTC End of Conversion Trigger +// <0x26=> PTC Sequence Trigger +// <0x27=> PTC Window Comparator Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/watch-library/shared/config/hpl_eic_config.h b/watch-library/shared/config/hpl_eic_config.h new file mode 100644 index 00000000..be54c2e1 --- /dev/null +++ b/watch-library/shared/config/hpl_eic_config.h @@ -0,0 +1,736 @@ +/* Auto-generated config file hpl_eic_config.h */ +#ifndef HPL_EIC_CONFIG_H +#define HPL_EIC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Settings +// Clock Selection +// Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or +// either by CLK_ULP32K when power consumption is the priority. +// <0x0=> Clocked by GCLK +// <0x1=> Clocked by ULPOSC32K +// eic_arch_cksel +#ifndef CONF_EIC_CKSEL +#define CONF_EIC_CKSEL 0 +#endif + +// + +// Non-Maskable Interrupt Control +// eic_arch_nmi_ctrl +#ifndef CONF_EIC_ENABLE_NMI_CTRL +#define CONF_EIC_ENABLE_NMI_CTRL 0 +#endif + +// Non-Maskable Interrupt Filter Enable +// Indicates whether the mon-maskable interrupt filter is enabled or not +// eic_arch_nmifilten +#ifndef CONF_EIC_NMIFILTEN +#define CONF_EIC_NMIFILTEN 0 +#endif + +// Non-Maskable Interrupt Sense +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines non-maskable interrupt sense +// eic_arch_nmisense +#ifndef CONF_EIC_NMISENSE +#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// Asynchronous Edge Detection Mode +// Indicates the interrupt detection mode operated synchronously or asynchronousl +// eic_arch_nmiasynch +#ifndef CONF_EIC_NMIASYNCH +#define CONF_EIC_NMIASYNCH 0 +#endif +// + +// Interrupt 0 Settings +// eic_arch_enable_irq_setting0 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING0 +#define CONF_EIC_ENABLE_IRQ_SETTING0 0 +#endif + +// External Interrupt 0 Filter Enable +// Indicates whether the external interrupt 0 filter is enabled or not +// eic_arch_filten0 +#ifndef CONF_EIC_FILTEN0 +#define CONF_EIC_FILTEN0 1 +#endif + +// External Interrupt 0 Event Output Enable +// Indicates whether the external interrupt 0 event output is enabled or not +// eic_arch_extinteo0 +#ifndef CONF_EIC_EXTINTEO0 +#define CONF_EIC_EXTINTEO0 0 +#endif + +// Input 0 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense0 +#ifndef CONF_EIC_SENSE0 +#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 0 Asynchronous Edge Detection Mode +// Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl +// eic_arch_asynch0 +#ifndef CONF_EIC_ASYNCH0 +#define CONF_EIC_ASYNCH0 0 +#endif + +// + +// Interrupt 1 Settings +// eic_arch_enable_irq_setting1 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING1 +#define CONF_EIC_ENABLE_IRQ_SETTING1 0 +#endif + +// External Interrupt 1 Filter Enable +// Indicates whether the external interrupt 1 filter is enabled or not +// eic_arch_filten1 +#ifndef CONF_EIC_FILTEN1 +#define CONF_EIC_FILTEN1 1 +#endif + +// External Interrupt 1 Event Output Enable +// Indicates whether the external interrupt 1 event output is enabled or not +// eic_arch_extinteo1 +#ifndef CONF_EIC_EXTINTEO1 +#define CONF_EIC_EXTINTEO1 0 +#endif + +// Input 1 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense1 +#ifndef CONF_EIC_SENSE1 +#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 1 Asynchronous Edge Detection Mode +// Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl +// eic_arch_asynch1 +#ifndef CONF_EIC_ASYNCH1 +#define CONF_EIC_ASYNCH1 0 +#endif + +// + +// Interrupt 2 Settings +// eic_arch_enable_irq_setting2 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING2 +#define CONF_EIC_ENABLE_IRQ_SETTING2 0 +#endif + +// External Interrupt 2 Filter Enable +// Indicates whether the external interrupt 2 filter is enabled or not +// eic_arch_filten2 +#ifndef CONF_EIC_FILTEN2 +#define CONF_EIC_FILTEN2 1 +#endif + +// External Interrupt 2 Event Output Enable +// Indicates whether the external interrupt 2 event output is enabled or not +// eic_arch_extinteo2 +#ifndef CONF_EIC_EXTINTEO2 +#define CONF_EIC_EXTINTEO2 0 +#endif + +// Input 2 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense2 +#ifndef CONF_EIC_SENSE2 +#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 2 Asynchronous Edge Detection Mode +// Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl +// eic_arch_asynch2 +#ifndef CONF_EIC_ASYNCH2 +#define CONF_EIC_ASYNCH2 0 +#endif + +// + +// Interrupt 3 Settings +// eic_arch_enable_irq_setting3 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING3 +#define CONF_EIC_ENABLE_IRQ_SETTING3 0 +#endif + +// External Interrupt 3 Filter Enable +// Indicates whether the external interrupt 3 filter is enabled or not +// eic_arch_filten3 +#ifndef CONF_EIC_FILTEN3 +#define CONF_EIC_FILTEN3 1 +#endif + +// External Interrupt 3 Event Output Enable +// Indicates whether the external interrupt 3 event output is enabled or not +// eic_arch_extinteo3 +#ifndef CONF_EIC_EXTINTEO3 +#define CONF_EIC_EXTINTEO3 0 +#endif + +// Input 3 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense3 +#ifndef CONF_EIC_SENSE3 +#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 3 Asynchronous Edge Detection Mode +// Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl +// eic_arch_asynch3 +#ifndef CONF_EIC_ASYNCH3 +#define CONF_EIC_ASYNCH3 0 +#endif + +// + +// Interrupt 4 Settings +// eic_arch_enable_irq_setting4 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING4 +#define CONF_EIC_ENABLE_IRQ_SETTING4 0 +#endif + +// External Interrupt 4 Filter Enable +// Indicates whether the external interrupt 4 filter is enabled or not +// eic_arch_filten4 +#ifndef CONF_EIC_FILTEN4 +#define CONF_EIC_FILTEN4 1 +#endif + +// External Interrupt 4 Event Output Enable +// Indicates whether the external interrupt 4 event output is enabled or not +// eic_arch_extinteo4 +#ifndef CONF_EIC_EXTINTEO4 +#define CONF_EIC_EXTINTEO4 0 +#endif + +// Input 4 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense4 +#ifndef CONF_EIC_SENSE4 +#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 4 Asynchronous Edge Detection Mode +// Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl +// eic_arch_asynch4 +#ifndef CONF_EIC_ASYNCH4 +#define CONF_EIC_ASYNCH4 0 +#endif + +// + +// Interrupt 5 Settings +// eic_arch_enable_irq_setting5 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING5 +#define CONF_EIC_ENABLE_IRQ_SETTING5 0 +#endif + +// External Interrupt 5 Filter Enable +// Indicates whether the external interrupt 5 filter is enabled or not +// eic_arch_filten5 +#ifndef CONF_EIC_FILTEN5 +#define CONF_EIC_FILTEN5 1 +#endif + +// External Interrupt 5 Event Output Enable +// Indicates whether the external interrupt 5 event output is enabled or not +// eic_arch_extinteo5 +#ifndef CONF_EIC_EXTINTEO5 +#define CONF_EIC_EXTINTEO5 0 +#endif + +// Input 5 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense5 +#ifndef CONF_EIC_SENSE5 +#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 5 Asynchronous Edge Detection Mode +// Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl +// eic_arch_asynch5 +#ifndef CONF_EIC_ASYNCH5 +#define CONF_EIC_ASYNCH5 0 +#endif + +// + +// Interrupt 6 Settings +// eic_arch_enable_irq_setting6 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING6 +#define CONF_EIC_ENABLE_IRQ_SETTING6 0 +#endif + +// External Interrupt 6 Filter Enable +// Indicates whether the external interrupt 6 filter is enabled or not +// eic_arch_filten6 +#ifndef CONF_EIC_FILTEN6 +#define CONF_EIC_FILTEN6 1 +#endif + +// External Interrupt 6 Event Output Enable +// Indicates whether the external interrupt 6 event output is enabled or not +// eic_arch_extinteo6 +#ifndef CONF_EIC_EXTINTEO6 +#define CONF_EIC_EXTINTEO6 0 +#endif + +// Input 6 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense6 +#ifndef CONF_EIC_SENSE6 +#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 6 Asynchronous Edge Detection Mode +// Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl +// eic_arch_asynch6 +#ifndef CONF_EIC_ASYNCH6 +#define CONF_EIC_ASYNCH6 0 +#endif + +// + +// Interrupt 7 Settings +// eic_arch_enable_irq_setting7 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING7 +#define CONF_EIC_ENABLE_IRQ_SETTING7 0 +#endif + +// External Interrupt 7 Filter Enable +// Indicates whether the external interrupt 7 filter is enabled or not +// eic_arch_filten7 +#ifndef CONF_EIC_FILTEN7 +#define CONF_EIC_FILTEN7 1 +#endif + +// External Interrupt 7 Event Output Enable +// Indicates whether the external interrupt 7 event output is enabled or not +// eic_arch_extinteo7 +#ifndef CONF_EIC_EXTINTEO7 +#define CONF_EIC_EXTINTEO7 0 +#endif + +// Input 7 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense7 +#ifndef CONF_EIC_SENSE7 +#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 7 Asynchronous Edge Detection Mode +// Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl +// eic_arch_asynch7 +#ifndef CONF_EIC_ASYNCH7 +#define CONF_EIC_ASYNCH7 0 +#endif + +// + +// Interrupt 8 Settings +// eic_arch_enable_irq_setting8 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING8 +#define CONF_EIC_ENABLE_IRQ_SETTING8 0 +#endif + +// External Interrupt 8 Filter Enable +// Indicates whether the external interrupt 8 filter is enabled or not +// eic_arch_filten8 +#ifndef CONF_EIC_FILTEN8 +#define CONF_EIC_FILTEN8 0 +#endif + +// External Interrupt 8 Event Output Enable +// Indicates whether the external interrupt 8 event output is enabled or not +// eic_arch_extinteo8 +#ifndef CONF_EIC_EXTINTEO8 +#define CONF_EIC_EXTINTEO8 0 +#endif + +// Input 8 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense8 +#ifndef CONF_EIC_SENSE8 +#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 8 Asynchronous Edge Detection Mode +// Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl +// eic_arch_asynch8 +#ifndef CONF_EIC_ASYNCH8 +#define CONF_EIC_ASYNCH8 0 +#endif + +// + +// Interrupt 9 Settings +// eic_arch_enable_irq_setting9 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING9 +#define CONF_EIC_ENABLE_IRQ_SETTING9 0 +#endif + +// External Interrupt 9 Filter Enable +// Indicates whether the external interrupt 9 filter is enabled or not +// eic_arch_filten9 +#ifndef CONF_EIC_FILTEN9 +#define CONF_EIC_FILTEN9 0 +#endif + +// External Interrupt 9 Event Output Enable +// Indicates whether the external interrupt 9 event output is enabled or not +// eic_arch_extinteo9 +#ifndef CONF_EIC_EXTINTEO9 +#define CONF_EIC_EXTINTEO9 0 +#endif + +// Input 9 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense9 +#ifndef CONF_EIC_SENSE9 +#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 9 Asynchronous Edge Detection Mode +// Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl +// eic_arch_asynch9 +#ifndef CONF_EIC_ASYNCH9 +#define CONF_EIC_ASYNCH9 0 +#endif + +// + +// Interrupt 10 Settings +// eic_arch_enable_irq_setting10 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING10 +#define CONF_EIC_ENABLE_IRQ_SETTING10 0 +#endif + +// External Interrupt 10 Filter Enable +// Indicates whether the external interrupt 10 filter is enabled or not +// eic_arch_filten10 +#ifndef CONF_EIC_FILTEN10 +#define CONF_EIC_FILTEN10 0 +#endif + +// External Interrupt 10 Event Output Enable +// Indicates whether the external interrupt 10 event output is enabled or not +// eic_arch_extinteo10 +#ifndef CONF_EIC_EXTINTEO10 +#define CONF_EIC_EXTINTEO10 0 +#endif + +// Input 10 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense10 +#ifndef CONF_EIC_SENSE10 +#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 10 Asynchronous Edge Detection Mode +// Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl +// eic_arch_asynch10 +#ifndef CONF_EIC_ASYNCH10 +#define CONF_EIC_ASYNCH10 0 +#endif + +// + +// Interrupt 11 Settings +// eic_arch_enable_irq_setting11 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING11 +#define CONF_EIC_ENABLE_IRQ_SETTING11 0 +#endif + +// External Interrupt 11 Filter Enable +// Indicates whether the external interrupt 11 filter is enabled or not +// eic_arch_filten11 +#ifndef CONF_EIC_FILTEN11 +#define CONF_EIC_FILTEN11 0 +#endif + +// External Interrupt 11 Event Output Enable +// Indicates whether the external interrupt 11 event output is enabled or not +// eic_arch_extinteo11 +#ifndef CONF_EIC_EXTINTEO11 +#define CONF_EIC_EXTINTEO11 0 +#endif + +// Input 11 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense11 +#ifndef CONF_EIC_SENSE11 +#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 11 Asynchronous Edge Detection Mode +// Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl +// eic_arch_asynch11 +#ifndef CONF_EIC_ASYNCH11 +#define CONF_EIC_ASYNCH11 0 +#endif + +// + +// Interrupt 12 Settings +// eic_arch_enable_irq_setting12 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING12 +#define CONF_EIC_ENABLE_IRQ_SETTING12 0 +#endif + +// External Interrupt 12 Filter Enable +// Indicates whether the external interrupt 12 filter is enabled or not +// eic_arch_filten12 +#ifndef CONF_EIC_FILTEN12 +#define CONF_EIC_FILTEN12 0 +#endif + +// External Interrupt 12 Event Output Enable +// Indicates whether the external interrupt 12 event output is enabled or not +// eic_arch_extinteo12 +#ifndef CONF_EIC_EXTINTEO12 +#define CONF_EIC_EXTINTEO12 0 +#endif + +// Input 12 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense12 +#ifndef CONF_EIC_SENSE12 +#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 12 Asynchronous Edge Detection Mode +// Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl +// eic_arch_asynch12 +#ifndef CONF_EIC_ASYNCH12 +#define CONF_EIC_ASYNCH12 0 +#endif + +// + +// Interrupt 13 Settings +// eic_arch_enable_irq_setting13 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING13 +#define CONF_EIC_ENABLE_IRQ_SETTING13 0 +#endif + +// External Interrupt 13 Filter Enable +// Indicates whether the external interrupt 13 filter is enabled or not +// eic_arch_filten13 +#ifndef CONF_EIC_FILTEN13 +#define CONF_EIC_FILTEN13 0 +#endif + +// External Interrupt 13 Event Output Enable +// Indicates whether the external interrupt 13 event output is enabled or not +// eic_arch_extinteo13 +#ifndef CONF_EIC_EXTINTEO13 +#define CONF_EIC_EXTINTEO13 0 +#endif + +// Input 13 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense13 +#ifndef CONF_EIC_SENSE13 +#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 13 Asynchronous Edge Detection Mode +// Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl +// eic_arch_asynch13 +#ifndef CONF_EIC_ASYNCH13 +#define CONF_EIC_ASYNCH13 0 +#endif + +// + +// Interrupt 14 Settings +// eic_arch_enable_irq_setting14 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING14 +#define CONF_EIC_ENABLE_IRQ_SETTING14 0 +#endif + +// External Interrupt 14 Filter Enable +// Indicates whether the external interrupt 14 filter is enabled or not +// eic_arch_filten14 +#ifndef CONF_EIC_FILTEN14 +#define CONF_EIC_FILTEN14 0 +#endif + +// External Interrupt 14 Event Output Enable +// Indicates whether the external interrupt 14 event output is enabled or not +// eic_arch_extinteo14 +#ifndef CONF_EIC_EXTINTEO14 +#define CONF_EIC_EXTINTEO14 0 +#endif + +// Input 14 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense14 +#ifndef CONF_EIC_SENSE14 +#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 14 Asynchronous Edge Detection Mode +// Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl +// eic_arch_asynch14 +#ifndef CONF_EIC_ASYNCH14 +#define CONF_EIC_ASYNCH14 0 +#endif + +// + +// Interrupt 15 Settings +// eic_arch_enable_irq_setting15 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING15 +#define CONF_EIC_ENABLE_IRQ_SETTING15 0 +#endif + +// External Interrupt 15 Filter Enable +// Indicates whether the external interrupt 15 filter is enabled or not +// eic_arch_filten15 +#ifndef CONF_EIC_FILTEN15 +#define CONF_EIC_FILTEN15 0 +#endif + +// External Interrupt 15 Event Output Enable +// Indicates whether the external interrupt 15 event output is enabled or not +// eic_arch_extinteo15 +#ifndef CONF_EIC_EXTINTEO15 +#define CONF_EIC_EXTINTEO15 0 +#endif + +// Input 15 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense15 +#ifndef CONF_EIC_SENSE15 +#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 15 Asynchronous Edge Detection Mode +// Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl +// eic_arch_asynch15 +#ifndef CONF_EIC_ASYNCH15 +#define CONF_EIC_ASYNCH15 0 +#endif + +// + +// this is still a hack: if the user wants to use PA02 (alarm button) as an RTC interrupt pin and PB02 (9-pin A2) on the EIC, we don't support that. +// TODO item: refactor out our reliance on the ASF external interrupt driver. - joey 11/30 +#ifdef CRYSTALLESS +#define CONFIG_EIC_EXTINT_MAP {0, PIN_PB00}, {1, PIN_PB01}, {2, PIN_PA02}, {3, PIN_PB03}, {5, PIN_PB05}, {7, PIN_PA07}, +#else +#define CONFIG_EIC_EXTINT_MAP {0, PIN_PB00}, {1, PIN_PB01}, {2, PIN_PA02}, {3, PIN_PB03}, {6, PIN_PA22}, {7, PIN_PA23}, +#endif + +// <<< end of configuration section >>> + +#endif // HPL_EIC_CONFIG_H diff --git a/watch-library/shared/config/hpl_gclk_config.h b/watch-library/shared/config/hpl_gclk_config.h new file mode 100644 index 00000000..ee7aace3 --- /dev/null +++ b/watch-library/shared/config/hpl_gclk_config.h @@ -0,0 +1,388 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#ifdef CRYSTALLESS +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_OSCULP32K +#else +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K +#endif + +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 1 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 1 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/watch-library/shared/config/hpl_mclk_config.h b/watch-library/shared/config/hpl_mclk_config.h new file mode 100644 index 00000000..3358edcf --- /dev/null +++ b/watch-library/shared/config/hpl_mclk_config.h @@ -0,0 +1,85 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val +#endif + +// Backup Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV1_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/watch-library/shared/config/hpl_nvmctrl_config.h b/watch-library/shared/config/hpl_nvmctrl_config.h new file mode 100755 index 00000000..76d49bac --- /dev/null +++ b/watch-library/shared/config/hpl_nvmctrl_config.h @@ -0,0 +1,38 @@ +/* Auto-generated config file hpl_nvmctrl_config.h */ +#ifndef HPL_NVMCTRL_CONFIG_H +#define HPL_NVMCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Settings + +// Read Mode Selection +// <0x00=> No Miss Penalty +// <0x01=> Low Power +// <0x02=> Deterministic +// nvm_arch_read_mode +#ifndef CONF_NVM_READ_MODE +#define CONF_NVM_READ_MODE 1 +#endif + +// Power Reduction Mode During Sleep +// <0x00=> Wake On Access +// <0x01=> Wake Up Instant +// <0x03=> Disabled +// nvm_arch_sleepprm +#ifndef CONF_NVM_SLEEPPRM +#define CONF_NVM_SLEEPPRM 0 +#endif + +// Cache Disable +// Indicate whether cache is disable or not +// nvm_arch_cache +#ifndef CONF_NVM_CACHE +#define CONF_NVM_CACHE 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_NVMCTRL_CONFIG_H diff --git a/watch-library/shared/config/hpl_osc32kctrl_config.h b/watch-library/shared/config/hpl_osc32kctrl_config.h new file mode 100644 index 00000000..540f1c60 --- /dev/null +++ b/watch-library/shared/config/hpl_osc32kctrl_config.h @@ -0,0 +1,177 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#ifdef CRYSTALLESS +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#else +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K +#endif +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ + +#define CONF_RTCCTRL_1KHZ 1 + +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// +// SLCD Source configuration +// enable_slcd_source +#ifndef CONF_SLCDCTRL_CONFIG +#define CONF_SLCDCTRL_CONFIG 0 +#endif + +// SLCD source control +// SLCD Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for SLCD +// slcd_source_oscillator +#ifndef CONF_SLCDCTRL_SRC +#define CONF_SLCDCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K +#endif + +// +// +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 1 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 1 +#endif + +// Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x3 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 1 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 1 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 1 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc32k_arch_swben +#ifndef CONF_XOSC32K_SWBEN +#define CONF_XOSC32K_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc32k_arch_cfden +#ifndef CONF_XOSC32K_CFDEN +#define CONF_XOSC32K_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc32k_arch_cfdeo +#ifndef CONF_XOSC32K_CFDEO +#define CONF_XOSC32K_CFDEO 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 1 +#endif + +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x1F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/watch-library/shared/config/hpl_oscctrl_config.h b/watch-library/shared/config/hpl_oscctrl_config.h new file mode 100644 index 00000000..ba2d42e6 --- /dev/null +++ b/watch-library/shared/config/hpl_oscctrl_config.h @@ -0,0 +1,483 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC is enabled or not +// enable_xosc +#ifndef CONF_XOSC_CONFIG +#define CONF_XOSC_CONFIG 0 +#endif + +// Frequency <400000-32000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC_FREQUENCY 400000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc_arch_enable +#ifndef CONF_XOSC_ENABLE +#define CONF_XOSC_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc_arch_startup +#ifndef CONF_XOSC_STARTUP +#define CONF_XOSC_STARTUP 0x0 +#endif + +// Automatic Amplitude Gain Control +// Indicates whether Automatic Amplitude Gain Control is enabled or not +// xosc_arch_ampgc +#ifndef CONF_XOSC_AMPGC +#define CONF_XOSC_AMPGC 0 +#endif + +// External Multipurpose Crystal Oscillator Gain +// <0x0=>2MHz +// <0x1=>4MHz +// <0x2=>8MHz +// <0x3=>16MHz +// <0x4=>30MHz +// xosc_arch_gain +#ifndef CONF_XOSC_GAIN +#define CONF_XOSC_GAIN 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc_arch_ondemand +#ifndef CONF_XOSC_ONDEMAND +#define CONF_XOSC_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc_arch_runstdby +#ifndef CONF_XOSC_RUNSTDBY +#define CONF_XOSC_RUNSTDBY 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc_arch_swben +#ifndef CONF_XOSC_SWBEN +#define CONF_XOSC_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc_arch_cfden +#ifndef CONF_XOSC_CFDEN +#define CONF_XOSC_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc_arch_cfdeo +#ifndef CONF_XOSC_CFDEO +#define CONF_XOSC_CFDEO 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc_arch_xtalen +#ifndef CONF_XOSC_XTALEN +#define CONF_XOSC_XTALEN 0 +#endif +// +// + +// 16MHz Internal Oscillator Configuration +// Indicates whether configuration for OSC8M is enabled or not +// enable_osc16m +#ifndef CONF_OSC16M_CONFIG +#define CONF_OSC16M_CONFIG 1 +#endif + +// 16MHz Internal Oscillator Control +// Enable +// Indicates whether 16MHz Internal Oscillator is enabled or not +// osc16m_arch_enable +#ifndef CONF_OSC16M_ENABLE +#define CONF_OSC16M_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// osc16m_arch_ondemand +#ifndef CONF_OSC16M_ONDEMAND +#define CONF_OSC16M_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// osc16m_arch_runstdby +#ifndef CONF_OSC16M_RUNSTDBY +#define CONF_OSC16M_RUNSTDBY 0 +#endif + +// Oscillator Frequency Selection(Mhz) +// 4 +// 8 +// 12 +// 16 +// This defines the oscillator frequency (Mhz) +// osc16m_freq +#ifndef CONF_OSC16M_FSEL +#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val +#endif + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osc16m_arch_calib_enable +#ifndef CONF_OSC16M_CALIB_ENABLE +#define CONF_OSC16M_CALIB_ENABLE 0 +#endif + +// 4MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_4m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_4M_FCAL 0 +#endif + +// 4MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_4m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_4M_TCAL 0 +#endif + +// 8MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_8m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_8M_FCAL 0 +#endif + +// 8MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_8m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_8M_TCAL 0 +#endif + +// 12MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_12m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_12M_FCAL 0 +#endif + +// 12MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_12m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_12M_TCAL 0 +#endif + +// 16MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_16M_FCAL 0 +#endif + +// 16MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_16m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_16M_TCAL 0 +#endif +// +// + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll48m +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// dfll48m_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// Digital Frequency Locked Loop Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll48m_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 0 +#endif + +// Wait Lock +// Indicates whether Wait Lock is enabled or not +// dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 0 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass Coarse Lock is enabled or not +// dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Indicates whether Quick Lock Disable is enabled or not +// dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Indicates whether Chill Cycle Disable is enabled or not +// dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// Indicates whether USB Clock Recovery Mode is enabled or not +// dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 0 +#endif + +// Lose Lock After Wake +// Indicates whether Lose Lock After Wake is enabled or not +// dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Indicates whether Stable DFLL Frequency is enabled or not +// dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// dfll48m_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0 +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 1 +#endif + +// Fine Maximum Step <0x0-0x3FF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 1 +#endif + +// DFLL Multiply Factor <0x0-0xFFFF> +// dfll48m_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// Fine Value <0x0-0x3FF> +// dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x200) +#endif + +// + +// + +// + +// DPLL Configuration +// Indicates whether configuration for DPLL is enabled or not +// enable_fdpll96m +#ifndef CONF_DPLL_CONFIG +#define CONF_DPLL_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// fdpll96m_ref_clock +#ifndef CONF_DPLL_GCLK +#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K + +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll96m_arch_enable +#ifndef CONF_DPLL_ENABLE +#define CONF_DPLL_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll96m_arch_ondemand +#ifndef CONF_DPLL_ONDEMAND +#define CONF_DPLL_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll96m_arch_runstdby +#ifndef CONF_DPLL_RUNSTDBY +#define CONF_DPLL_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0xF> +// fdpll96m_ldrfrac +#ifndef CONF_DPLL_LDRFRAC +#define CONF_DPLL_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0xFFF> +// fdpll96m_ldr +#ifndef CONF_DPLL_LDR +#define CONF_DPLL_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x3FF> +// fdpll96m_clock_div +#ifndef CONF_DPLL_DIV +#define CONF_DPLL_DIV 0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll96m_arch_lbypass +#ifndef CONF_DPLL_LBYPASS +#define CONF_DPLL_LBYPASS 0 +#endif + +// Lock Time +// <0=>No time-out, automatic lock +// <4=>The Time-out if no lock within 8 ms +// <5=>The Time-out if no lock within 9 ms +// <6=>The Time-out if no lock within 10 ms +// <7=>The Time-out if no lock within 11 ms +// fdpll96m_arch_ltime +#ifndef CONF_DPLL_LTIME +#define CONF_DPLL_LTIME 0 +#endif + +// Reference Clock Selection +// <0=>XOSC32K clock reference +// <1=>XOSC clock reference +// <2=>GCLK clock reference +// fdpll96m_arch_refclk +#ifndef CONF_DPLL_REFCLK +#define CONF_DPLL_REFCLK 0 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll96m_arch_wuf +#ifndef CONF_DPLL_WUF +#define CONF_DPLL_WUF 0 +#endif + +// Low-Power Enable +// Indicates whether Low-Power Enable is enabled or not +// fdpll96m_arch_lpen +#ifndef CONF_DPLL_LPEN +#define CONF_DPLL_LPEN 0 +#endif + +// Reference Clock Selection +// <0=>Default filter mode +// <1=>Low bandwidth filter +// <2=>High bandwidth filter +// <3=>High damping filter +// fdpll96m_arch_filter +#ifndef CONF_DPLL_FILTER +#define CONF_DPLL_FILTER 0 +#endif + +// Output Clock Prescaler +// 1 +// 2 +// 4 +// fdpll96m_presc +#ifndef CONF_DPLL_PRESC +#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/watch-library/shared/config/hpl_port_config.h b/watch-library/shared/config/hpl_port_config.h new file mode 100644 index 00000000..1efce33e --- /dev/null +++ b/watch-library/shared/config/hpl_port_config.h @@ -0,0 +1,284 @@ +/* Auto-generated config file hpl_port_config.h */ +#ifndef HPL_PORT_CONFIG_H +#define HPL_PORT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PORT Input Event 0 configuration +// enable_port_input_event_0 +#ifndef CONF_PORT_EVCTRL_PORT_0 +#define CONF_PORT_EVCTRL_PORT_0 0 +#endif + +// PORT Input Event 0 configuration on PORT A + +// PORTA Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled +// porta_input_event_enable_0 +#ifndef CONF_PORTA_EVCTRL_PORTEI_0 +#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTA Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_0 +#ifndef CONF_PORTA_EVCTRL_PID_0 +#define CONF_PORTA_EVCTRL_PID_0 0x0 +#endif + +// PORTA Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 0 +// porta_event_action_0 +#ifndef CONF_PORTA_EVCTRL_EVACT_0 +#define CONF_PORTA_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT B + +// PORTB Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled +// portb_input_event_enable_0 +#ifndef CONF_PORTB_EVCTRL_PORTEI_0 +#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTB Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_0 +#ifndef CONF_PORTB_EVCTRL_PID_0 +#define CONF_PORTB_EVCTRL_PID_0 0x0 +#endif + +// PORTB Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 0 +// portb_event_action_0 +#ifndef CONF_PORTB_EVCTRL_EVACT_0 +#define CONF_PORTB_EVCTRL_EVACT_0 0 +#endif + +// + +// + +// PORT Input Event 1 configuration +// enable_port_input_event_1 +#ifndef CONF_PORT_EVCTRL_PORT_1 +#define CONF_PORT_EVCTRL_PORT_1 0 +#endif + +// PORT Input Event 1 configuration on PORT A + +// PORTA Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled +// porta_input_event_enable_1 +#ifndef CONF_PORTA_EVCTRL_PORTEI_1 +#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTA Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_1 +#ifndef CONF_PORTA_EVCTRL_PID_1 +#define CONF_PORTA_EVCTRL_PID_1 0x0 +#endif + +// PORTA Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 1 +// porta_event_action_1 +#ifndef CONF_PORTA_EVCTRL_EVACT_1 +#define CONF_PORTA_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT B + +// PORTB Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled +// portb_input_event_enable_1 +#ifndef CONF_PORTB_EVCTRL_PORTEI_1 +#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTB Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_1 +#ifndef CONF_PORTB_EVCTRL_PID_1 +#define CONF_PORTB_EVCTRL_PID_1 0x0 +#endif + +// PORTB Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 1 +// portb_event_action_1 +#ifndef CONF_PORTB_EVCTRL_EVACT_1 +#define CONF_PORTB_EVCTRL_EVACT_1 0 +#endif + +// + +// + +// PORT Input Event 2 configuration +// enable_port_input_event_2 +#ifndef CONF_PORT_EVCTRL_PORT_2 +#define CONF_PORT_EVCTRL_PORT_2 0 +#endif + +// PORT Input Event 2 configuration on PORT A + +// PORTA Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled +// porta_input_event_enable_2 +#ifndef CONF_PORTA_EVCTRL_PORTEI_2 +#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTA Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_2 +#ifndef CONF_PORTA_EVCTRL_PID_2 +#define CONF_PORTA_EVCTRL_PID_2 0x0 +#endif + +// PORTA Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 2 +// porta_event_action_2 +#ifndef CONF_PORTA_EVCTRL_EVACT_2 +#define CONF_PORTA_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT B + +// PORTB Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled +// portb_input_event_enable_2 +#ifndef CONF_PORTB_EVCTRL_PORTEI_2 +#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTB Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_2 +#ifndef CONF_PORTB_EVCTRL_PID_2 +#define CONF_PORTB_EVCTRL_PID_2 0x0 +#endif + +// PORTB Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 2 +// portb_event_action_2 +#ifndef CONF_PORTB_EVCTRL_EVACT_2 +#define CONF_PORTB_EVCTRL_EVACT_2 0 +#endif + +// + +// + +// PORT Input Event 3 configuration +// enable_port_input_event_3 +#ifndef CONF_PORT_EVCTRL_PORT_3 +#define CONF_PORT_EVCTRL_PORT_3 0 +#endif + +// PORT Input Event 3 configuration on PORT A + +// PORTA Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled +// porta_input_event_enable_3 +#ifndef CONF_PORTA_EVCTRL_PORTEI_3 +#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTA Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_3 +#ifndef CONF_PORTA_EVCTRL_PID_3 +#define CONF_PORTA_EVCTRL_PID_3 0x0 +#endif + +// PORTA Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 3 +// porta_event_action_3 +#ifndef CONF_PORTA_EVCTRL_EVACT_3 +#define CONF_PORTA_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT B + +// PORTB Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled +// portb_input_event_enable_3 +#ifndef CONF_PORTB_EVCTRL_PORTEI_3 +#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTB Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_3 +#ifndef CONF_PORTB_EVCTRL_PID_3 +#define CONF_PORTB_EVCTRL_PID_3 0x0 +#endif + +// PORTB Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 3 +// portb_event_action_3 +#ifndef CONF_PORTB_EVCTRL_EVACT_3 +#define CONF_PORTB_EVCTRL_EVACT_3 0 +#endif + +// + +// + +#define CONF_PORTA_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) +#define CONF_PORTB_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) + +// <<< end of configuration section >>> + +#endif // HPL_PORT_CONFIG_H diff --git a/watch-library/shared/config/hpl_rtc_config.h b/watch-library/shared/config/hpl_rtc_config.h new file mode 100644 index 00000000..9085ca37 --- /dev/null +++ b/watch-library/shared/config/hpl_rtc_config.h @@ -0,0 +1,318 @@ +/* Auto-generated config file hpl_rtc_config.h */ +#ifndef HPL_RTC_CONFIG_H +#define HPL_RTC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic settings + +#ifndef CONF_RTC_ENABLE +#define CONF_RTC_ENABLE 1 +#endif + +// Force reset RTC on initialization +// Force RTC to reset on initialization. +// Note that the previous power down data in RTC is lost if it's enabled. +// rtc_arch_init_reset +#ifndef CONF_RTC_INIT_RESET +#define CONF_RTC_INIT_RESET 0 +#endif + +// Prescaler configuration +// <0x0=>OFF(Peripheral clock divided by 1) +// <0x1=>Peripheral clock divided by 1 +// <0x2=>Peripheral clock divided by 2 +// <0x3=>Peripheral clock divided by 4 +// <0x4=>Peripheral clock divided by 8 +// <0x5=>Peripheral clock divided by 16 +// <0x6=>Peripheral clock divided by 32 +// <0x7=>Peripheral clock divided by 64 +// <0x8=>Peripheral clock divided by 128 +// <0x9=>Peripheral clock divided by 256 +// <0xA=>Peripheral clock divided by 512 +// <0xB=>Peripheral clock divided by 1024 +// These bits define the RTC clock relative to the peripheral clock +// rtc_arch_prescaler +#ifndef CONF_RTC_PRESCALER + +#define CONF_RTC_PRESCALER 0xb + +#endif + +#ifndef CONF_RTC_COMP_VAL + +#define CONF_RTC_COMP_VAL 0 + +#endif + +// RTC Tamper Input 0 settings +// tamper_input_0_settings +#ifndef CONF_TAMPER_INPUT_0_SETTINGS +#define CONF_TAMPER_INPUT_0_SETTINGS 0 +#endif + +// Tamper Level Settings +// Indicates Tamper input 0 level +// tamper_level_0 +#ifndef CONF_RTC_TAMP_LVL_0 +#define CONF_RTC_TAMP_LVL_0 0 +#endif + +// RTC Tamper Input Action +// <0x0=>OFF(Disabled) +// <0x1=>Wake and Set Tamper Flag +// <0x2=>Capture Timestamp and Set Tamper Flag +// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. +// These bits define the RTC Tamper Input Action to be performed +// rtc_tamper_input_action_0 +#ifndef CONF_RTC_TAMPER_INACT_0 +#define CONF_RTC_TAMPER_INACT_0 0 +#endif + +// Debounce Enable for Tamper Input +// Indicates Debounce should be enabled for Tamper input 0 +// tamper_debounce_enable_0 +#ifndef CONF_RTC_TAMP_DEBNC_0 +#define CONF_RTC_TAMP_DEBNC_0 0 +#endif + +// + +// RTC Tamper Input 1 settings +// tamper_input_1_settings +#ifndef CONF_TAMPER_INPUT_1_SETTINGS +#define CONF_TAMPER_INPUT_1_SETTINGS 0 +#endif + +// Tamper Level Settings +// Indicates Tamper input 1 level +// tamper_level_1 +#ifndef CONF_RTC_TAMP_LVL_1 +#define CONF_RTC_TAMP_LVL_1 0 +#endif + +// RTC Tamper Input Action +// <0x0=>OFF(Disabled) +// <0x1=>Wake and Set Tamper Flag +// <0x2=>Capture Timestamp and Set Tamper Flag +// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. +// These bits define the RTC Tamper Input Action to be performed +// rtc_tamper_input_action_1 +#ifndef CONF_RTC_TAMPER_INACT_1 +#define CONF_RTC_TAMPER_INACT_1 0 +#endif + +// Debounce Enable for Tamper Input +// Indicates Debounce should be enabled for Tamper input 1 +// tamper_debounce_enable_1 +#ifndef CONF_RTC_TAMP_DEBNC_1 +#define CONF_RTC_TAMP_DEBNC_1 0 +#endif + +// + +// RTC Tamper Input 2 settings +// tamper_input_2_settings +#ifndef CONF_TAMPER_INPUT_2_SETTINGS +#define CONF_TAMPER_INPUT_2_SETTINGS 0 +#endif + +// Tamper Level Settings +// Indicates Tamper input 2 level +// tamper_level_2 +#ifndef CONF_RTC_TAMP_LVL_2 +#define CONF_RTC_TAMP_LVL_2 0 +#endif + +// RTC Tamper Input Action +// <0x0=>OFF(Disabled) +// <0x1=>Wake and Set Tamper Flag +// <0x2=>Capture Timestamp and Set Tamper Flag +// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. +// These bits define the RTC Tamper Input Action to be performed +// rtc_tamper_input_action_2 +#ifndef CONF_RTC_TAMPER_INACT_2 +#define CONF_RTC_TAMPER_INACT_2 0 +#endif + +// Debounce Enable for Tamper Input +// Indicates Debounce should be enabled for Tamper input 2 +// tamper_debounce_enable_2 +#ifndef CONF_RTC_TAMP_DEBNC_2 +#define CONF_RTC_TAMP_DEBNC_2 0 +#endif + +// + +// RTC Tamper Input 3 settings +// tamper_input_3_settings +#ifndef CONF_TAMPER_INPUT_3_SETTINGS +#define CONF_TAMPER_INPUT_3_SETTINGS 0 +#endif + +// Tamper Level Settings +// Indicates Tamper input 3 level +// tamper_level_3 +#ifndef CONF_RTC_TAMP_LVL_3 +#define CONF_RTC_TAMP_LVL_3 0 +#endif + +// RTC Tamper Input Action +// <0x0=>OFF(Disabled) +// <0x1=>Wake and Set Tamper Flag +// <0x2=>Capture Timestamp and Set Tamper Flag +// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. +// These bits define the RTC Tamper Input Action to be performed +// rtc_tamper_input_action_3 +#ifndef CONF_RTC_TAMPER_INACT_3 +#define CONF_RTC_TAMPER_INACT_3 0 +#endif + +// Debounce Enable for Tamper Input +// Indicates Debounce should be enabled for Tamper input 3 +// tamper_debounce_enable_3 +#ifndef CONF_RTC_TAMP_DEBNC_3 +#define CONF_RTC_TAMP_DEBNC_3 0 +#endif + +// + +// RTC Tamper Input 4 settings +// tamper_input_4_settings +#ifndef CONF_TAMPER_INPUT_4_SETTINGS +#define CONF_TAMPER_INPUT_4_SETTINGS 0 +#endif + +// Tamper Level Settings +// Indicates Tamper input 4 level +// tamper_level_4 +#ifndef CONF_RTC_TAMP_LVL_4 +#define CONF_RTC_TAMP_LVL_4 0 +#endif + +// RTC Tamper Input Action +// <0x0=>OFF(Disabled) +// <0x1=>Wake and Set Tamper Flag +// <0x2=>Capture Timestamp and Set Tamper Flag +// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. +// These bits define the RTC Tamper Input Action to be performed +// rtc_tamper_input_action_4 +#ifndef CONF_RTC_TAMPER_INACT_4 +#define CONF_RTC_TAMPER_INACT_4 0 +#endif + +// Debounce Enable for Tamper Input +// Indicates Debounce should be enabled for Tamper input 4 +// tamper_debounce_enable_4 +#ifndef CONF_RTC_TAMP_DEBNC_4 +#define CONF_RTC_TAMP_DEBNC_4 0 +#endif + +// + +// RTC Tamper Active Layer Frequency Prescalar +// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2 +// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4 +// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8 +// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16 +// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32 +// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64 +// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128 +// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256 +// These bits define the RTC Tamper Active Layer Frequecny Prescalar +// rtc_tamper_active_layer_frequency_prescalar +#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES +#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0 +#endif + +// RTC Tamper Debounce Frequency Prescalar +// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2 +// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4 +// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8 +// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16 +// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32 +// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64 +// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128 +// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256 +// These bits define the RTC Debounce Frequency Prescalar +// rtc_tamper_debounce_frequency_prescalar +#ifndef CONF_RTC_TAMP_DEBF_PRES +#define CONF_RTC_TAMP_DEBF_PRES 0 +#endif + +// Event control +// rtc_event_control +#ifndef CONF_RTC_EVENT_CONTROL_ENABLE +#define CONF_RTC_EVENT_CONTROL_ENABLE 0 +#endif + +// Periodic Interval 0 Event Output +// This bit indicates whether Periodic interval 0 event is enabled and will be generated +// rtc_pereo0 +#ifndef CONF_RTC_PEREO0 +#define CONF_RTC_PEREO0 0 +#endif +// Periodic Interval 1 Event Output +// This bit indicates whether Periodic interval 1 event is enabled and will be generated +// rtc_pereo1 +#ifndef CONF_RTC_PEREO1 +#define CONF_RTC_PEREO1 0 +#endif +// Periodic Interval 2 Event Output +// This bit indicates whether Periodic interval 2 event is enabled and will be generated +// rtc_pereo2 +#ifndef CONF_RTC_PEREO2 +#define CONF_RTC_PEREO2 0 +#endif +// Periodic Interval 3 Event Output +// This bit indicates whether Periodic interval 3 event is enabled and will be generated +// rtc_pereo3 +#ifndef CONF_RTC_PEREO3 +#define CONF_RTC_PEREO3 0 +#endif +// Periodic Interval 4 Event Output +// This bit indicates whether Periodic interval 4 event is enabled and will be generated +// rtc_pereo4 +#ifndef CONF_RTC_PEREO4 +#define CONF_RTC_PEREO4 0 +#endif +// Periodic Interval 5 Event Output +// This bit indicates whether Periodic interval 5 event is enabled and will be generated +// rtc_pereo5 +#ifndef CONF_RTC_PEREO5 +#define CONF_RTC_PEREO5 0 +#endif +// Periodic Interval 6 Event Output +// This bit indicates whether Periodic interval 6 event is enabled and will be generated +// rtc_pereo6 +#ifndef CONF_RTC_PEREO6 +#define CONF_RTC_PEREO6 0 +#endif +// Periodic Interval 7 Event Output +// This bit indicates whether Periodic interval 7 event is enabled and will be generated +// rtc_pereo7 +#ifndef CONF_RTC_PEREO7 +#define CONF_RTC_PEREO7 0 +#endif + +// Compare 0 Event Output +// This bit indicates whether Compare O event is enabled and will be generated +// rtc_cmpeo0 +#ifndef CONF_RTC_COMPE0 +#define CONF_RTC_COMPE0 0 +#endif + +// Overflow Event Output +// This bit indicates whether Overflow event is enabled and will be generated +// rtc_ovfeo +#ifndef CONF_RTC_OVFEO +#define CONF_RTC_OVFEO 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_RTC_CONFIG_H diff --git a/watch-library/shared/config/hpl_sercom_config.h b/watch-library/shared/config/hpl_sercom_config.h new file mode 100644 index 00000000..6df4b08e --- /dev/null +++ b/watch-library/shared/config/hpl_sercom_config.h @@ -0,0 +1,303 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 1 +#endif + +// Basic + +// I2C Bus clock speed (Hz) <1-400000> +// I2C Bus clock (SCL) speed measured in Hz +// i2c_master_baud_rate +#ifndef CONF_SERCOM_1_I2CM_BAUD +#define CONF_SERCOM_1_I2CM_BAUD 100000 +#endif + +// + +// Advanced +// i2c_master_advanced +#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0 +#endif + +// TRise (ns) <0-300> +// Determined by the bus impedance, check electric characteristics in the datasheet +// Standard Fast Mode: typical 215ns, max 300ns +// Fast Mode +: typical 60ns, max 100ns +// High Speed Mode: typical 20ns, max 40ns +// i2c_master_arch_trise + +#ifndef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215 +#endif + +// Master SCL Low Extended Time-Out (MEXTTOEN) +// This enables the master SCL low extend time-out +// i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN +#define CONF_SERCOM_1_I2CM_MEXTTOEN 0 +#endif + +// Slave SCL Low Extend Time-Out (SEXTTOEN) +// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN +#define CONF_SERCOM_1_I2CM_SEXTTOEN 0 +#endif + +// SCL Low Time-Out (LOWTOUT) +// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// i2c_master_arch_lowtout +#ifndef CONF_SERCOM_1_I2CM_LOWTOUT +#define CONF_SERCOM_1_I2CM_LOWTOUT 0 +#endif + +// Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// Defines if inactivity time-out should be enabled, and how long the time-out should be +// i2c_master_arch_inactout +#ifndef CONF_SERCOM_1_I2CM_INACTOUT +#define CONF_SERCOM_1_I2CM_INACTOUT 0x0 +#endif + +// SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// Defines the SDA hold time with respect to the negative edge of SCL +// i2c_master_arch_sdahold +#ifndef CONF_SERCOM_1_I2CM_SDAHOLD +#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2 +#endif + +// Run in stand-by +// Determine if the module shall run in standby sleep mode +// i2c_master_arch_runstdby +#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY +#define CONF_SERCOM_1_I2CM_RUNSTDBY 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_1_I2CM_SPEED +#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215U +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ + / 1000U)) \ + * 10U \ + + 5U) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10U)) +#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE +#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_1_I2CM_BAUD_RATE \ + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + +#include + +// Enable configuration of module +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 1 +#endif + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_3_SPI_MODE +#define CONF_SERCOM_3_SPI_MODE 0x03 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable receive buffer to receive data from slave (RXEN) +// spi_master_rx_enable +#ifndef CONF_SERCOM_3_SPI_RXEN +#define CONF_SERCOM_3_SPI_RXEN 0x1 +#endif + +// Character Size +// Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// spi_master_character_size +#ifndef CONF_SERCOM_3_SPI_CHSIZE +#define CONF_SERCOM_3_SPI_CHSIZE 0x0 +#endif +// Baud rate <1-12000000> +// The SPI data transfer rate +// spi_master_baud_rate +#ifndef CONF_SERCOM_3_SPI_BAUD +#define CONF_SERCOM_3_SPI_BAUD 50000 +#endif + +// + +// Advanced Configuration +// spi_master_advanced +#ifndef CONF_SERCOM_3_SPI_ADVANCED +#define CONF_SERCOM_3_SPI_ADVANCED 1 +#endif + +// Dummy byte <0x00-0x1ff> +// spi_master_dummybyte +// Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE +#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff +#endif + +// Data Order +// <0=>MSB first +// <1=>LSB first +// I least significant or most significant bit is shifted out first (DORD) +// spi_master_arch_dord +#ifndef CONF_SERCOM_3_SPI_DORD +#define CONF_SERCOM_3_SPI_DORD 0x0 +#endif + +// Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// spi_master_arch_cpol +#ifndef CONF_SERCOM_3_SPI_CPOL +#define CONF_SERCOM_3_SPI_CPOL 0x0 +#endif + +// Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// spi_master_arch_cpha +#ifndef CONF_SERCOM_3_SPI_CPHA +#define CONF_SERCOM_3_SPI_CPHA 0x0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// spi_master_arch_ibon +#ifndef CONF_SERCOM_3_SPI_IBON +#define CONF_SERCOM_3_SPI_IBON 0x0 +#endif + +// Run in stand-by +// Module stays active in stand-by sleep mode. (RUNSTDBY) +// spi_master_arch_runstdby +#ifndef CONF_SERCOM_3_SPI_RUNSTDBY +#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// spi_master_arch_dbgstop +#ifndef CONF_SERCOM_3_SPI_DBGSTOP +#define CONF_SERCOM_3_SPI_DBGSTOP 0 +#endif + +// + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_3_SPI_AMODE_EN +#define CONF_SERCOM_3_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_AMODE +#define CONF_SERCOM_3_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_ADDR +#define CONF_SERCOM_3_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_ADDRMASK +#define CONF_SERCOM_3_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_SSDE +#define CONF_SERCOM_3_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_3_SPI_MSSEN +#define CONF_SERCOM_3_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_3_SPI_PLOADEN +#define CONF_SERCOM_3_SPI_PLOADEN 0 +#endif + +// Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// spi_master_rxpo +#ifndef CONF_SERCOM_3_SPI_RXPO +#define CONF_SERCOM_3_SPI_RXPO 2 +#endif + +// Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// spi_master_txpo +#ifndef CONF_SERCOM_3_SPI_TXPO +#define CONF_SERCOM_3_SPI_TXPO 3 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_3_SPI_BAUD_RATE +#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1 +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/watch-library/shared/config/hpl_slcd_config.h b/watch-library/shared/config/hpl_slcd_config.h new file mode 100644 index 00000000..d78e3391 --- /dev/null +++ b/watch-library/shared/config/hpl_slcd_config.h @@ -0,0 +1,239 @@ +/* Auto-generated config file hpl_slcd_config.h */ +#ifndef HPL_SLCD_CONFIG_H +#define HPL_SLCD_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include +#include +#include "pins.h" + +// Standard configuration + +// Number of COM Lines +// Number of COM Lines +// <0=>1 +// <1=>2 +// <2=>3 +// <3=>4 +// <4=>6 +// <5=>8 +// slcd_arch_com_num +#ifndef CONF_SLCD_COM_NUM +#define CONF_SLCD_COM_NUM 2 +#endif + +// Number of Segment Lines <1-44> +// Number of Segment Lines +// slcd_arch_seg_num +#ifndef CONF_SLCD_SEG_NUM +#define CONF_SLCD_SEG_NUM 24 +#endif + +#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_SIXTH_Val && CONF_SLCD_SEG_NUM > 42 +#warning Segment number should less than or equals to 42 +#endif +#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_EIGHT_Val && CONF_SLCD_SEG_NUM > 40 +#warning Segment number should less than or equals to 40 +#endif + +// Bias +// Bias Settting +// <0=>STATIC +// <1=>HALF +// <2=>THIRD +// <3=>FOURTH +// slcd_arch_bias +#ifndef CONF_SLCD_BIAS +#define CONF_SLCD_BIAS 2 +#endif + +#if CONF_SLCD_COM_NUM == 0 && CONF_SLCD_BIAS != 0 +#warning Recommended Bias for 1 common terminal is STATIC +#elif CONF_SLCD_COM_NUM == 1 && CONF_SLCD_BIAS != 1 +#warning Recommended Bias for 2 Common Terminals is HALF +#elif CONF_SLCD_COM_NUM <= 4 && CONF_SLCD_BIAS != 2 +#warning Recommended Bias for 3/4/6 Common Terminals is THIRD +#elif CONF_SLCD_COM_NUM == 5 && CONF_SLCD_BIAS != 3 +#warning Recommended Bias for 8 Common Terminals is FOURTH +#endif + +// Bias Buffer Enable +// Enable Bias Buffer +// slcd_arch_bben +#ifndef CONF_SLCD_BBEN +#define CONF_SLCD_BBEN 1 +#endif + +// Bias Buffer Enable Duration <1-16> +// Configure the enable duration of the bias buffer, unit is cycle of SLCD OSC clock source +// slcd_arch_bbd +#ifndef CONF_SLCD_BBD +#define CONF_SLCD_BBD 2 +#endif + +// Clock Prescaler +// Setting for LCD frame frequency +// <0=>16 +// <1=>32 +// <2=>64 +// <3=>128 +// slcd_arch_presc +#ifndef CONF_SLCD_PRESC +#define CONF_SLCD_PRESC 1 +#endif + +// Clock Divider +// Setting for LCD frame frequency +// <0=>1 +// <1=>2 +// <2=>3 +// <3=>4 +// <4=>5 +// <5=>6 +// <6=>7 +// <7=>8 +// slcd_arch_ckdiv +#ifndef CONF_SLCD_CKDIV +#define CONF_SLCD_CKDIV 5 +#endif + +/* TODO add frame frequency check */ + +// Reference Refresh Frequency +// Setting for Reference Refresh Frequency +// <0=>2kHz +// <1=>1kHz +// <2=>500Hz +// <3=>250Hz +// <4=>125Hz +// <5=>62.5Hz +// slcd_arch_rrf +#ifndef CONF_SLCD_RRF +#define CONF_SLCD_RRF 0 +#endif + +// Power Refresh Frequency +// Setting for Charge pump Refresh Frequency +// <0=>2kHz +// <1=>1kHz +// <2=>500Hz +// <3=>250Hz +// slcd_arch_prf +#ifndef CONF_SLCD_PRF +#define CONF_SLCD_PRF 3 +#endif + +// External VLCD +// Setting for how VLCD is generated +// slcd_arch_xvlcd +#ifndef CONF_SLCD_XVLCD +#define CONF_SLCD_XVLCD 0 +#endif + +// Waveform Mode +// Setting for Waveform Mode +// <0=>Low Power Waveform(frame-inversion) +// <1=>Standard Waveform Mode(bit-inversion) +// slcd_arch_wmod +#ifndef CONF_SLCD_WMOD +#define CONF_SLCD_WMOD 0 +#endif + +// Contrast Adjustment +// The contrast of the LCD is determined by the value of VLCD voltage. +// The higher the VLCD voltage, the higher is the contrast. +// The software contrast adjustment is only possible in internal supply mode. +// <0=>2.5056V +// <1=>2.5731V +// <2=>2.6379V +// <3=>2.7054V +// <4=>2.7729V +// <5=>2.8404V +// <6=>2.9052V +// <7=>2.9727V +// <8=>3.0402V +// <9=>3.1077V +// <10=>3.1725V +// <11=>3.24V +// <12=>3.3075V +// <13=>3.375V +// <14=>3.4398V +// <15=>3.5073V +// slcd_arch_contrast_adjust +#ifndef CONF_SLCD_CONTRAST_ADJUST +#define CONF_SLCD_CONTRAST_ADJUST 14 +#endif + +// + +// Advanced configuration +// slcd_arch_advanced_settings +#ifndef CONF_SLCD_ADVANCED_SETTINGS +#define CONF_SLCD_ADVANCED_SETTINGS 1 +#endif + +// Run in standby +// Indicates whether the SLCD will continue running in standby sleep mode or not +// slcd_arch_runstdby +#ifndef CONF_SLCD_RUNSTDBY +#define CONF_SLCD_RUNSTDBY 1 +#endif + +// + +#if SLCD_FRAME_FREQUENCY < 30 || SLCD_FRAME_FREQUENCY > 100 +#warning The optimal frame frequency should be in range from 30Hz up to 100Hz to avoid flickering and ghosting effect. +#endif + +#define SLCD_FC_MAX_MS (((0x1F + 1) * 8) * (1000 / SLCD_FRAME_FREQUENCY)) +#define SLCD_FC_MIN_MS (1000 / SLCD_FRAME_FREQUENCY) +#define SLCD_FC_BYPASS_MAX_MS ((0x1F + 1) * (1000 / SLCD_FRAME_FREQUENCY)) + +// Character Mapping Setting +// slcd_arch_cm_setting +#ifndef CONF_SLCD_CM_ENABLE +#define CONF_SLCD_CM_ENABLE 0 +#endif + +/** + * character lookup table + */ +#ifndef CONF_SLCD_LPENL +#define CONF_SLCD_LPENL (\ + (uint32_t)1 << 0 | \ + (uint32_t)1 << 1 | \ + (uint32_t)1 << 2 | \ + (uint32_t)1 << 3 | \ + (uint32_t)1 << 4 | \ + (uint32_t)1 << 5 | \ + (uint32_t)1 << 6 | \ + (uint32_t)1 << 7 | \ + (uint32_t)1 << 11 | \ + (uint32_t)1 << 12 | \ + (uint32_t)1 << 13 | \ + (uint32_t)1 << 14 | \ + (uint32_t)1 << 21 | \ + (uint32_t)1 << 22 | \ + (uint32_t)1 << 23 | \ + (uint32_t)1 << 24 | \ + (uint32_t)1 << 25 | \ + (uint32_t)1 << 28 | \ + (uint32_t)1 << 29 | \ + (uint32_t)1 << 30 | \ + (uint32_t)1 << 31 | 0) +#endif // CONF_SLCD_LPENL + +#ifndef CONF_SLCD_LPENH +#define CONF_SLCD_LPENH (\ + (uint32_t)1 << (32 - 32) | \ + (uint32_t)1 << (33 - 32) | \ + (uint32_t)1 << (34 - 32) | \ + (uint32_t)1 << (35 - 32) | \ + (uint32_t)1 << (42 - 32) | \ + (uint32_t)1 << (43 - 32) | 0) +#endif // CONF_SLCD_LPENH + +// <<< end of configuration section >>> + +#endif // HPL_SLCD_CONFIG_H diff --git a/watch-library/shared/config/hpl_systick_config.h b/watch-library/shared/config/hpl_systick_config.h new file mode 100644 index 00000000..a7f2f362 --- /dev/null +++ b/watch-library/shared/config/hpl_systick_config.h @@ -0,0 +1,18 @@ +/* Auto-generated config file hpl_systick_config.h */ +#ifndef HPL_SYSTICK_CONFIG_H +#define HPL_SYSTICK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced settings +// SysTick exception request +// Indicates whether the generation of SysTick exception is enabled or not +// systick_arch_tickint +#ifndef CONF_SYSTICK_TICKINT +#define CONF_SYSTICK_TICKINT 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_SYSTICK_CONFIG_H diff --git a/watch-library/shared/config/hpl_trng_config.h b/watch-library/shared/config/hpl_trng_config.h new file mode 100755 index 00000000..ba901498 --- /dev/null +++ b/watch-library/shared/config/hpl_trng_config.h @@ -0,0 +1,27 @@ +/* Auto-generated config file hpl_trng_config.h */ +#ifndef HPL_TRNG_CONFIG_H +#define HPL_TRNG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced configurations + +// Run In Standby +// Indicates whether the TRNG works in standby mode +// trng_runstdby +#ifndef CONF_TRNG_RUNSTDBY +#define CONF_TRNG_RUNSTDBY 0 +#endif + +// Data Ready Event Output Enable +// Indicates whether the TRNG generates event on Data Ready +// trng_datardyeo +#ifndef CONF_TRNG_DATARDYEO +#define CONF_TRNG_DATARDYEO 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_TRNG_CONFIG_H diff --git a/watch-library/shared/config/nv_storage_config.h b/watch-library/shared/config/nv_storage_config.h new file mode 100755 index 00000000..4888d1bd --- /dev/null +++ b/watch-library/shared/config/nv_storage_config.h @@ -0,0 +1,51 @@ +/* Auto-generated config file nv_storage_config.h */ +#ifndef NV_STORAGE_CONFIG_H +#define NV_STORAGE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Storage start address <0x00000000-0xFFFFFFFF> +// This defines the start address of device flash for storage. +// The start address should be in device flash area. +// The start address and (start address + Item Number * Sector size) cannot beyond device flash area. +// conf_storage_memory_start +#ifndef CONF_STORAGE_MEMORY_START +#define CONF_STORAGE_MEMORY_START 0x10000 +#endif + +// Item number <0-65535> +// This defines the maximum number of elements stored in persistent storage +// conf_max_item_number +#ifndef CONF_MAX_ITEM_NUMBER +#define CONF_MAX_ITEM_NUMBER 10 +#endif + +// Sector size <0-65535> +// This defines the size of one storage sector in bytes +// conf_sector_size +#ifndef CONF_SECTOR_SIZE +#define CONF_SECTOR_SIZE 4096 +#endif + +/** + * Check If the Storage configuration out of the flash area. + */ +#ifdef FLASH_SIZE +#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > FLASH_SIZE +#error Invalidate storage configuration, make sure the configuration with \ +the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \ +are located within the device flash size. +#endif +#endif + +#ifdef IFLASH_SIZE +#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > IFLASH_SIZE +#error Invalidate storage configuration, make sure the configuration with \ +the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \ +are located within the device flash size. +#endif +#endif + +// <<< end of configuration section >>> + +#endif // NV_STORAGE_CONFIG_H diff --git a/watch-library/shared/config/peripheral_clk_config.h b/watch-library/shared/config/peripheral_clk_config.h new file mode 100644 index 00000000..523b036c --- /dev/null +++ b/watch-library/shared/config/peripheral_clk_config.h @@ -0,0 +1,266 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// ADC Clock Source +// adc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Select the clock source for ADC. +#ifndef CONF_GCLK_ADC_SRC +#define CONF_GCLK_ADC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_ADC_FREQUENCY + * \brief ADC's Clock frequency + */ +#ifndef CONF_GCLK_ADC_FREQUENCY +#define CONF_GCLK_ADC_FREQUENCY 4000000 +#endif + +// EIC Clock Source +// eic_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Select the clock source for EIC. +#ifndef CONF_GCLK_EIC_SRC +#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_EIC_FREQUENCY + * \brief EIC's Clock frequency + */ +#ifndef CONF_GCLK_EIC_FREQUENCY +#define CONF_GCLK_EIC_FREQUENCY 32768 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 4000000 +#endif + +// RTC Clock Source +// rtc_clk_selection +// RTC source +// Select the clock source for RTC. +#ifndef CONF_GCLK_RTC_SRC +#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE +#endif + +/** + * \def CONF_GCLK_RTC_FREQUENCY + * \brief RTC's Clock frequency + */ +#ifndef CONF_GCLK_RTC_FREQUENCY +#define CONF_GCLK_RTC_FREQUENCY 1024 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM1_CORE_SRC +#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM1_SLOW_SRC +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY + * \brief SERCOM1's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 4000000 +#endif + +/** + * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY + * \brief SERCOM1's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM3_CORE_SRC +#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM3_SLOW_SRC +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY + * \brief SERCOM3's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY +#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 4000000 +#endif + +/** + * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY + * \brief SERCOM3's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 +#endif + +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC3_SRC +#define CONF_GCLK_TC3_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_TC3_FREQUENCY + * \brief TC3's Clock frequency + */ +#ifndef CONF_GCLK_TC3_FREQUENCY +#define CONF_GCLK_TC3_FREQUENCY 32768 +#endif + +// TCC Clock Source +// tcc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Select the clock source for TCC. +#ifndef CONF_GCLK_TCC0_SRC +#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TCC0_FREQUENCY + * \brief TCC0's Clock frequency + */ +#ifndef CONF_GCLK_TCC0_FREQUENCY +#define CONF_GCLK_TCC0_FREQUENCY 16000000 +#endif + +#include + +// SLCD Clock Source +// slcd_clk_selection +// SLCD source +// Select the clock source for SLCD. +#ifndef CONF_GCLK_SLCD_SRC +#define CONF_GCLK_SLCD_SRC SLCD_CLOCK_SOURCE +#endif + +/** + * \def CONF_GCLK_SLCD_FREQUENCY + * \brief SLCD's Clock frequency + */ +#ifndef CONF_GCLK_SLCD_FREQUENCY +#define CONF_GCLK_SLCD_FREQUENCY 32768 +#endif + +#ifndef SLCD_FRAME_FREQUENCY +#define SLCD_FRAME_FREQUENCY \ + (CONF_GCLK_SLCD_FREQUENCY \ + / (((CONF_SLCD_PRESC + 1) * 16) * (CONF_SLCD_CKDIV + 1) \ + * ((CONF_SLCD_COM_NUM == 4) ? 6 : ((CONF_SLCD_COM_NUM == 5) ? 8 : (CONF_SLCD_COM_NUM + 1))))) +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/watch-library/shared/driver/lis2dh.c b/watch-library/shared/driver/lis2dh.c new file mode 100644 index 00000000..20702bf5 --- /dev/null +++ b/watch-library/shared/driver/lis2dh.c @@ -0,0 +1,143 @@ +/* + * MIT License + * + * Copyright (c) 2021 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "lis2dh.h" +#include "watch.h" + +bool lis2dh_begin(void) { + if (lis2dh_get_device_id() != LIS2DH_WHO_AM_I_VAL) { + return false; + } + // Enable all axes, start at lowest possible data rate + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1, LIS2DH_CTRL1_VAL_XEN | + LIS2DH_CTRL1_VAL_YEN | + LIS2DH_CTRL1_VAL_ZEN | + LIS2DH_CTRL1_VAL_ODR_1HZ); + // Set range to ±2G and enable block data update (output registers not updated until MSB and LSB have been read) + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4, LIS2DH_CTRL4_VAL_BDU | LIS2DH_RANGE_2_G); + + return true; +} + +uint8_t lis2dh_get_device_id(void) { + return watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_WHO_AM_I); +} + +bool lis2dh_have_new_data(void) { + uint8_t retval = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_STATUS); + return !!retval; // return true if any bit is set +} + +lis2dh_reading lis2dh_get_raw_reading(void) { + uint8_t buffer[6]; + uint8_t reg = LIS2DH_REG_OUT_X_L | 0x80; // set high bit for consecutive reads + lis2dh_reading retval; + + watch_i2c_send(LIS2DH_ADDRESS, ®, 1); + watch_i2c_receive(LIS2DH_ADDRESS, (uint8_t *)&buffer, 6); + + retval.x = buffer[0]; + retval.x |= ((uint16_t)buffer[1]) << 8; + retval.y = buffer[2]; + retval.y |= ((uint16_t)buffer[3]) << 8; + retval.z = buffer[4]; + retval.z |= ((uint16_t)buffer[5]) << 8; + + return retval; +} + + lis2dh_acceleration_measurement lis2dh_get_acceleration_measurement(lis2dh_reading *out_reading) { + lis2dh_reading reading = lis2dh_get_raw_reading(); + uint8_t range = lis2dh_get_range(); + if (out_reading != NULL) *out_reading = reading; + + // this bit is cribbed from Adafruit's LIS3DH driver; from their notes, the magic number below + // converts from 16-bit lsb to 10-bit and divides by 1k to convert from milli-gs. + // final value is raw_lsb => 10-bit lsb -> milli-gs -> gs + uint8_t lsb_value = 1; + if (range == LIS2DH_RANGE_2_G) lsb_value = 4; + if (range == LIS2DH_RANGE_4_G) lsb_value = 8; + if (range == LIS2DH_RANGE_8_G) lsb_value = 16; + if (range == LIS2DH_RANGE_16_G) lsb_value = 48; + + lis2dh_acceleration_measurement retval; + + retval.x = lsb_value * ((float)reading.x / 64000.0); + retval.y = lsb_value * ((float)reading.y / 64000.0); + retval.z = lsb_value * ((float)reading.z / 64000.0); + + return retval; +} + +void lis2dh_set_range(lis2dh_range_t range) { + uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4) & 0xCF; + uint8_t bits = range << 4; + + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4, val | bits); +} + +lis2dh_range_t lis2dh_get_range(void) { + uint8_t retval = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL4) & 0x30; + retval >>= 4; + return (lis2dh_range_t)retval; +} + + +void lis2dh_set_data_rate(lis2dh_data_rate_t dataRate) { + uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1) & 0x0F; + uint8_t bits = dataRate << 4; + + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1, val | bits); +} + +lis2dh_data_rate_t lis2dh_get_data_rate(void) { + return watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL1) >> 4; +} + +void lis2dh_configure_aoi_int1(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch) { + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL3, LIS2DH_CTRL3_VAL_I1_AOI1); + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_CFG, configuration); + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_THS, threshold); + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_DUR, duration); + uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5) & 0xF7; + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5, val | latch ? LIS2DH_CTRL5_VAL_LIR_INT1 : 0); +} + +lis2dh_interrupt_state lis2dh_get_int1_state(void) { + return (lis2dh_interrupt_state) watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_INT1_SRC); +} + +void lis2dh_configure_aoi_int2(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch) { + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL6, LIS2DH_CTRL6_VAL_I2_INT2); + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_CFG, configuration); + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_THS, threshold); + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_DUR, duration); + uint8_t val = watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5) & 0xFD; + watch_i2c_write8(LIS2DH_ADDRESS, LIS2DH_REG_CTRL5, val | latch ? LIS2DH_CTRL5_VAL_LIR_INT2 : 0); +} + +lis2dh_interrupt_state lis2dh_get_int2_state(void) { + return (lis2dh_interrupt_state) watch_i2c_read8(LIS2DH_ADDRESS, LIS2DH_REG_INT2_SRC); +} + diff --git a/watch-library/shared/driver/lis2dh.h b/watch-library/shared/driver/lis2dh.h new file mode 100644 index 00000000..68831519 --- /dev/null +++ b/watch-library/shared/driver/lis2dh.h @@ -0,0 +1,222 @@ +/* + * MIT License + * + * Copyright (c) 2021 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef LIS2DH_H +#define LIS2DH_H + +#include +#include + +typedef struct { + int16_t x; + int16_t y; + int16_t z; +} lis2dh_reading; + +typedef struct { + float x; + float y; + float z; +} lis2dh_acceleration_measurement; + +typedef enum { + LIS2DH_RANGE_16_G = 0b11, // +/- 16g + LIS2DH_RANGE_8_G = 0b10, // +/- 8g + LIS2DH_RANGE_4_G = 0b01, // +/- 4g + LIS2DH_RANGE_2_G = 0b00 // +/- 2g (default value) +} lis2dh_range_t; + +typedef enum { + LIS2DH_DATA_RATE_POWERDOWN = 0, + LIS2DH_DATA_RATE_1_HZ = 0b0001, + LIS2DH_DATA_RATE_10_HZ = 0b0010, + LIS2DH_DATA_RATE_25_HZ = 0b0011, + LIS2DH_DATA_RATE_50_HZ = 0b0100, + LIS2DH_DATA_RATE_100_HZ = 0b0101, + LIS2DH_DATA_RATE_200_HZ = 0b0110, + LIS2DH_DATA_RATE_400_HZ = 0b0111, + LIS2DH_DATA_RATE_LP1620HZ = 0b1000, + LIS2DH_DATA_RATE_LP5376HZ = 0b1001, + +} lis2dh_data_rate_t; + +typedef enum { + LIS2DH_INTERRUPT_CONFIGURATION_OR = 0b00000000, + LIS2DH_INTERRUPT_CONFIGURATION_AND = 0b10000000, + LIS2DH_INTERRUPT_CONFIGURATION_6D_MOVEMENT = 0b01000000, + LIS2DH_INTERRUPT_CONFIGURATION_6D_POSITION = 0b11000000, // in 6D mode, these have an alternate meaning: + LIS2DH_INTERRUPT_CONFIGURATION_Z_HIGH_ENABLE = 0b00100000, // Z up enable + LIS2DH_INTERRUPT_CONFIGURATION_Z_LOW_ENABLE = 0b00010000, // Z down enable + LIS2DH_INTERRUPT_CONFIGURATION_Y_HIGH_ENABLE = 0b00001000, // Y up enable + LIS2DH_INTERRUPT_CONFIGURATION_Y_LOW_ENABLE = 0b00000100, // Y down enable + LIS2DH_INTERRUPT_CONFIGURATION_X_HIGH_ENABLE = 0b00000010, // X up enable + LIS2DH_INTERRUPT_CONFIGURATION_X_LOW_ENABLE = 0b00000001, // X down enable +} lis2dh_interrupt_configuration; + +typedef enum { + LIS2DH_INTERRUPT_STATE_ACTIVE = 0b01000000, + LIS2DH_INTERRUPT_STATE_Z_HIGH = 0b00100000, // Z up + LIS2DH_INTERRUPT_STATE_Z_LOW = 0b00010000, // Z down + LIS2DH_INTERRUPT_STATE_Y_HIGH = 0b00001000, // Y up + LIS2DH_INTERRUPT_STATE_Y_LOW = 0b00000100, // Y down + LIS2DH_INTERRUPT_STATE_X_HIGH = 0b00000010, // X up + LIS2DH_INTERRUPT_STATE_X_LOW = 0b00000001, // X down +} lis2dh_interrupt_state; + +bool lis2dh_begin(void); + +uint8_t lis2dh_get_device_id(void); + +bool lis2dh_have_new_data(void); + +lis2dh_reading lis2dh_get_raw_reading(void); + +lis2dh_acceleration_measurement lis2dh_get_acceleration_measurement(lis2dh_reading *out_reading); + +void lis2dh_set_range(lis2dh_range_t range); + +lis2dh_range_t lis2dh_get_range(void); + +void lis2dh_set_data_rate(lis2dh_data_rate_t dataRate); + +lis2dh_data_rate_t lis2dh_get_data_rate(void); + +void lis2dh_configure_aoi_int1(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch); + +lis2dh_interrupt_state lis2dh_get_int1_state(void); + +void lis2dh_configure_aoi_int2(lis2dh_interrupt_configuration configuration, uint8_t threshold, uint8_t duration, bool latch); + +lis2dh_interrupt_state lis2dh_get_int2_state(void); + +// Assumes SA0 is high; if low, its 0x18 +#define LIS2DH_ADDRESS (0x19) + +#define LIS2DH_REG_STATUS_AUX 0x07 ///< Auxiliary status register +#define LIS2DH_REG_STATUS_AUX_TDA (1 << 2) ///< Temperature data available +#define LIS2DH_REG_STATUS_AUX_TOR (1 << 6) ///< Temperature data overrun + +#define LIS2DH_REG_OUT_TEMP_L 0x0C ///< Temperature data low bit +#define LIS2DH_REG_OUT_TEMP_H 0x0D ///< Temperature data high bit + +#define LIS2DH_REG_INT_COUNTER 0x0E + +#define LIS2DH_REG_WHO_AM_I 0x0F ///< Device identification, will read 0x33 +#define LIS2DH_WHO_AM_I_VAL 0x33 ///< Expected value of the WHO_AM_I register + +#define LIS2DH_REG_TEMP_CFG 0x1F ///< Temperature configuration; 0 to disable, 0xC0 to enable. +#define LIS2DH_TEMP_CFG_VAL_ENABLE 0xC0 ///< Value for LIS2DH_REG_TEMP_CFG that enables temperature sensing. +#define LIS2DH_TEMP_CFG_VAL_DISABLE 0x00 ///< Value for LIS2DH_REG_TEMP_CFG that disables temperature sensing. + +#define LIS2DH_REG_CTRL1 0x20 ///< CTRL_REG1 in the data sheet. +#define LIS2DH_CTRL1_VAL_XEN 0b00000001 ///< Enable X-axis +#define LIS2DH_CTRL1_VAL_YEN 0b00000010 ///< Enable Y-axis +#define LIS2DH_CTRL1_VAL_ZEN 0b00000100 ///< Enable Z-axis +#define LIS2DH_CTRL1_VAL_LPEN 0b00001000 ///< Enable low power mode +#define LIS2DH_CTRL1_VAL_ODR_POWERDOWN 0 ///< Power down +#define LIS2DH_CTRL1_VAL_ODR_1HZ (LIS2DH_DATA_RATE_1_HZ << 4) +#define LIS2DH_CTRL1_VAL_ODR_10HZ (LIS2DH_DATA_RATE_10_HZ << 4) +#define LIS2DH_CTRL1_VAL_ODR_25HZ (LIS2DH_DATA_RATE_25_HZ << 4) +#define LIS2DH_CTRL1_VAL_ODR_50HZ (LIS2DH_DATA_RATE_50_HZ << 4) +#define LIS2DH_CTRL1_VAL_ODR_100HZ (LIS2DH_DATA_RATE_100_HZ << 4) +#define LIS2DH_CTRL1_VAL_ODR_200HZ (LIS2DH_DATA_RATE_200_HZ << 4) +#define LIS2DH_CTRL1_VAL_ODR_400HZ (LIS2DH_DATA_RATE_400_HZ << 4) +#define LIS2DH_CTRL1_VAL_ODR_LP1620HZ (LIS2DH_DATA_RATE_LP1620HZ << 4) +#define LIS2DH_CTRL1_VAL_ODR_LP5376HZ (LIS2DH_DATA_RATE_LP5376HZ << 4) + +#define LIS2DH_REG_CTRL2 0x21 + +#define LIS2DH_REG_CTRL3 0x22 +#define LIS2DH_CTRL3_VAL_I1_CLICK 0b10000000 +#define LIS2DH_CTRL3_VAL_I1_AOI1 0b01000000 +#define LIS2DH_CTRL3_VAL_I1_AOI2 0b00100000 +#define LIS2DH_CTRL3_VAL_I1_DRDY1 0b00010000 +#define LIS2DH_CTRL3_VAL_I1_DRDY2 0b00001000 +#define LIS2DH_CTRL3_VAL_I1_WTM 0b00000100 +#define LIS2DH_CTRL3_VAL_I1_OVERRUN 0b00000010 + +#define LIS2DH_REG_CTRL4 0x23 +#define LIS2DH_CTRL4_VAL_BDU 0b10000000 +#define LIS2DH_CTRL4_VAL_BLE 0b01000000 +#define LIS2DH_CTRL4_VAL_RANGE_2G (LIS2DH_RANGE_2_G << 4) +#define LIS2DH_CTRL4_VAL_RANGE_4G (LIS2DH_RANGE_4_G << 4) +#define LIS2DH_CTRL4_VAL_RANGE_8G (LIS2DH_RANGE_8_G << 4) +#define LIS2DH_CTRL4_VAL_RANGE_16G (LIS2DH_RANGE_16_G << 4) +#define LIS2DH_CTRL4_VAL_HR 0b00001000 +#define LIS2DH_CTRL4_VAL_ST0 0b00000000 +#define LIS2DH_CTRL4_VAL_ST1 0b00000000 + +#define LIS2DH_REG_CTRL5 0x24 +#define LIS2DH_CTRL5_VAL_BOOT 0b10000000 +#define LIS2DH_CTRL5_VAL_FIFO_EN 0b01000000 +#define LIS2DH_CTRL5_VAL_LIR_INT1 0b00001000 +#define LIS2DH_CTRL5_VAL_D4D_INT1 0b00000100 +#define LIS2DH_CTRL5_VAL_LIR_INT2 0b00000010 +#define LIS2DH_CTRL5_VAL_D4D_INT2 0b00000001 + +#define LIS2DH_REG_CTRL6 0x25 +#define LIS2DH_CTRL6_VAL_I2_CLICK 0b10000000 +#define LIS2DH_CTRL6_VAL_I2_INT1 0b01000000 +#define LIS2DH_CTRL6_VAL_I2_INT2 0b00100000 +#define LIS2DH_CTRL6_VAL_BOOT_I2 0b00010000 +#define LIS2DH_CTRL6_VAL_P2_ACT 0b00001000 +#define LIS2DH_CTRL6_VAL_H_L_ACTIVE 0b00000000 + +#define LIS2DH_REG_REFERENCE 0x26 + +#define LIS2DH_REG_STATUS 0x27 +#define LIS2DH_STATUS_VAL_ZYXOR 0b10000000 +#define LIS2DH_STATUS_VAL_ZOR 0b01000000 +#define LIS2DH_STATUS_VAL_YOR 0b00100000 +#define LIS2DH_STATUS_VAL_XOR 0b00010000 +#define LIS2DH_STATUS_VAL_ZYXDA 0b00001000 +#define LIS2DH_STATUS_VAL_ZDA 0b00000100 +#define LIS2DH_STATUS_VAL_YDA 0b00000010 +#define LIS2DH_STATUS_VAL_XDA 0b00000001 + +#define LIS2DH_REG_OUT_X_L 0x28 +#define LIS2DH_REG_OUT_X_H 0x29 +#define LIS2DH_REG_OUT_Y_L 0x2A +#define LIS2DH_REG_OUT_Y_H 0x2B +#define LIS2DH_REG_OUT_Z_L 0x2C +#define LIS2DH_REG_OUT_Z_H 0x2D + +#define LIS2DH_REG_FIFO_CTRL 0x2E +#define LIS2DH_REG_FIFO_SRC 0x2F +#define LIS2DH_REG_INT1_CFG 0x30 +#define LIS2DH_REG_INT1_SRC 0x31 +#define LIS2DH_REG_INT1_THS 0x32 +#define LIS2DH_REG_INT1_DUR 0x33 +#define LIS2DH_REG_INT2_CFG 0x34 +#define LIS2DH_REG_INT2_SRC 0x35 +#define LIS2DH_REG_INT2_THS 0x36 +#define LIS2DH_REG_INT2_DUR 0x37 +#define LIS2DH_REG_CLICK_CFG 0x38 +#define LIS2DH_REG_CLICK_SRC 0x39 +#define LIS2DH_REG_CLICK_THS 0x3A +#define LIS2DH_REG_TIME_LIMIT 0x3B +#define LIS2DH_REG_TIME_LATENCY 0x3C +#define LIS2DH_REG_TIME_WINDOW 0x3D + +#endif // LIS2DH_H diff --git a/watch-library/shared/driver/lis2dw.c b/watch-library/shared/driver/lis2dw.c new file mode 100644 index 00000000..6e1ac56d --- /dev/null +++ b/watch-library/shared/driver/lis2dw.c @@ -0,0 +1,139 @@ +/* + * MIT License + * + * Copyright (c) 2021 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "lis2dw.h" +#include "watch.h" + +bool lis2dw_begin(void) { + if (lis2dw_get_device_id() != LIS2DW_WHO_AM_I_VAL) { + return false; + } + watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL2, LIS2DW_CTRL2_VAL_BOOT); + watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL2, LIS2DW_CTRL2_VAL_SOFT_RESET); + // Start at lowest possible data rate and lowest possible power mode + watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, LIS2DW_CTRL1_VAL_ODR_LOWEST | LIS2DW_CTRL1_VAL_MODE_LOW_POWER | LIS2DW_CTRL1_VAL_LPMODE_1); + // Enable block data update (output registers not updated until MSB and LSB have been read) and address autoincrement + watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL2, LIS2DW_CTRL2_VAL_BDU | LIS2DW_CTRL2_VAL_IF_ADD_INC); + // Set range to ±2G + watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6, LIS2DW_CTRL6_VAL_RANGE_2G); + + return true; +} + +uint8_t lis2dw_get_device_id(void) { + return watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_WHO_AM_I); +} + +bool lis2dw_have_new_data(void) { + uint8_t retval = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_STATUS); + return retval & LIS2DW_STATUS_VAL_DRDY; +} + +lis2dw_reading lis2dw_get_raw_reading(void) { + uint8_t buffer[6]; + uint8_t reg = LIS2DW_REG_OUT_X_L | 0x80; // set high bit for consecutive reads + lis2dw_reading retval; + + watch_i2c_send(LIS2DW_ADDRESS, ®, 1); + watch_i2c_receive(LIS2DW_ADDRESS, (uint8_t *)&buffer, 6); + + retval.x = buffer[0]; + retval.x |= ((uint16_t)buffer[1]) << 8; + retval.y = buffer[2]; + retval.y |= ((uint16_t)buffer[3]) << 8; + retval.z = buffer[4]; + retval.z |= ((uint16_t)buffer[5]) << 8; + + return retval; +} + + lis2dw_acceleration_measurement lis2dw_get_acceleration_measurement(lis2dw_reading *out_reading) { + lis2dw_reading reading = lis2dw_get_raw_reading(); + uint8_t range = lis2dw_get_range(); + if (out_reading != NULL) *out_reading = reading; + + // this bit is cribbed from Adafruit's LIS3DH driver; from their notes, the magic number below + // converts from 16-bit lsb to 10-bit and divides by 1k to convert from milli-gs. + // final value is raw_lsb => 10-bit lsb -> milli-gs -> gs + uint8_t lsb_value = 1; + if (range == LIS2DW_RANGE_2_G) lsb_value = 4; + if (range == LIS2DW_RANGE_4_G) lsb_value = 8; + if (range == LIS2DW_RANGE_8_G) lsb_value = 16; + if (range == LIS2DW_RANGE_16_G) lsb_value = 48; + + lis2dw_acceleration_measurement retval; + + retval.x = lsb_value * ((float)reading.x / 64000.0); + retval.y = lsb_value * ((float)reading.y / 64000.0); + retval.z = lsb_value * ((float)reading.z / 64000.0); + + return retval; +} + +void lis2dw_set_range(lis2dw_range_t range) { + uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6) & ~(LIS2DW_RANGE_16_G << 4); + uint8_t bits = range << 4; + + watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6, val | bits); +} + +lis2dw_range_t lis2dw_get_range(void) { + uint8_t retval = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL6) & (LIS2DW_RANGE_16_G << 4); + retval >>= 4; + return (lis2dw_range_t)retval; +} + + +void lis2dw_set_data_rate(lis2dw_data_rate_t dataRate) { + uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & ~(0b1111 << 4); + uint8_t bits = dataRate << 4; + + watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, val | bits); +} + +lis2dw_data_rate_t lis2dw_get_data_rate(void) { + return watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) >> 4; +} + +void lis2dw_set_low_power_mode(lis2dw_low_power_mode_t mode) { + uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & ~(0b11); + uint8_t bits = mode & 0b11; + + watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, val | bits); +} + +lis2dw_low_power_mode_t lis2dw_get_low_power_mode(void) { + return watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & 0b11; +} + +void lis2dw_set_low_noise_mode(bool on) { + uint8_t val = watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & ~(LIS2DW_CTRL6_VAL_LOW_NOISE); + uint8_t bits = on ? LIS2DW_CTRL6_VAL_LOW_NOISE : 0; + + watch_i2c_write8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1, val | bits); +} + +bool lis2dw_get_low_noise_mode(void) { + return (watch_i2c_read8(LIS2DW_ADDRESS, LIS2DW_REG_CTRL1) & LIS2DW_CTRL6_VAL_LOW_NOISE) != 0; +} diff --git a/watch-library/shared/driver/lis2dw.h b/watch-library/shared/driver/lis2dw.h new file mode 100644 index 00000000..22b4484f --- /dev/null +++ b/watch-library/shared/driver/lis2dw.h @@ -0,0 +1,265 @@ +/* + * MIT License + * + * Copyright (c) 2021 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef LIS2DW_H +#define LIS2DW_H + +#include +#include + +typedef struct { + int16_t x; + int16_t y; + int16_t z; +} lis2dw_reading; + +typedef struct { + float x; + float y; + float z; +} lis2dw_acceleration_measurement; + +typedef enum { + LIS2DW_DATA_RATE_POWERDOWN = 0, + LIS2DW_DATA_RATE_LOWEST = 0b0001, // 12.5 Hz in high performance mode, 1.6 Hz in low power + LIS2DW_DATA_RATE_12_5_HZ = 0b0010, + LIS2DW_DATA_RATE_25_HZ = 0b0011, + LIS2DW_DATA_RATE_50_HZ = 0b0100, + LIS2DW_DATA_RATE_100_HZ = 0b0101, + LIS2DW_DATA_RATE_200_HZ = 0b0110, + LIS2DW_DATA_RATE_HP_400_HZ = 0b0111, + LIS2DW_DATA_RATE_HP_800_HZ = 0b1000, + LIS2DW_DATA_RATE_HP_1600_HZ = 0b1001, + +} lis2dw_data_rate_t; + +typedef enum { + LIS2DW_MODE_LOW_POWER = 0b00, + LIS2DW_MODE_HIGH_PERFORMANCE = 0b01, + LIS2DW_MODE_ON_DEMAND = 0b10, +} lis2dw_mode_t; + +typedef enum { + LIS2DW_LP_MODE_1 = 0b00, // 12-bit + LIS2DW_LP_MODE_2 = 0b01, // 14-bit + LIS2DW_LP_MODE_3 = 0b10, // 14-bit + LIS2DW_LP_MODE_4 = 0b11, // 14-bit +} lis2dw_low_power_mode_t; + +typedef enum { + LIS2DW_BANDWIDTH_FILTER_DIV2 = 0b00, + LIS2DW_BANDWIDTH_FILTER_DIV4 = 0b01, + LIS2DW_BANDWIDTH_FILTER_DIV10 = 0b10, + LIS2DW_BANDWIDTH_FILTER_DIV20 = 0b11, +} lis2dw_bandwidth_filtering_mode_t; + +typedef enum { + LIS2DW_RANGE_16_G = 0b11, // +/- 16g + LIS2DW_RANGE_8_G = 0b10, // +/- 8g + LIS2DW_RANGE_4_G = 0b01, // +/- 4g + LIS2DW_RANGE_2_G = 0b00 // +/- 2g (default value) +} lis2dw_range_t; + +// Assumes SA0 is high; if low, its 0x18 +#define LIS2DW_ADDRESS (0x19) + +#define LIS2DW_REG_OUT_TEMP_L 0x0D ///< Temperature data low bit +#define LIS2DW_REG_OUT_TEMP_H 0x0E ///< Temperature data high bit + +#define LIS2DW_REG_WHO_AM_I 0x0F ///< Device identification, will read 0x44 +#define LIS2DW_WHO_AM_I_VAL 0x44 ///< Expected value of the WHO_AM_I register + +#define LIS2DW_REG_CTRL1 0x20 ///< CTRL_REG1 in the data sheet. +#define LIS2DW_CTRL1_VAL_ODR_POWERDOWN 0 +#define LIS2DW_CTRL1_VAL_ODR_LOWEST (LIS2DW_DATA_RATE_LOWEST << 4) +#define LIS2DW_CTRL1_VAL_ODR_12_5HZ (LIS2DW_DATA_RATE_12_5_HZ << 4) +#define LIS2DW_CTRL1_VAL_ODR_25HZ (LIS2DW_DATA_RATE_25_HZ << 4) +#define LIS2DW_CTRL1_VAL_ODR_50HZ (LIS2DW_DATA_RATE_50_HZ << 4) +#define LIS2DW_CTRL1_VAL_ODR_100HZ (LIS2DW_DATA_RATE_100_HZ << 4) +#define LIS2DW_CTRL1_VAL_ODR_200HZ (LIS2DW_DATA_RATE_200_HZ << 4) +#define LIS2DW_CTRL1_VAL_ODR_HP_400_HZ (LIS2DW_DATA_RATE_HP_400_HZ << 4) +#define LIS2DW_CTRL1_VAL_ODR_HP_800_HZ (LIS2DW_DATA_RATE_HP_800_HZ << 4) +#define LIS2DW_CTRL1_VAL_ODR_HP_1600_HZ (LIS2DW_DATA_RATE_HP_1600_HZ << 4) +#define LIS2DW_CTRL1_VAL_MODE_LOW_POWER (LIS2DW_MODE_LOW_POWER << 2) +#define LIS2DW_CTRL1_VAL_MODE_HIGH_PERFORMANCE (LIS2DW_MODE_HIGH_PERFORMANCE << 2) +#define LIS2DW_CTRL1_VAL_MODE_ON_DEMAND (LIS2DW_MODE_ON_DEMAND << 2) +#define LIS2DW_CTRL1_VAL_LPMODE_1 (LIS2DW_LP_MODE_1 << 0) +#define LIS2DW_CTRL1_VAL_LPMODE_2 (LIS2DW_LP_MODE_2 << 0) +#define LIS2DW_CTRL1_VAL_LPMODE_3 (LIS2DW_LP_MODE_3 << 0) +#define LIS2DW_CTRL1_VAL_LPMODE_4 (LIS2DW_LP_MODE_4 << 0) + +#define LIS2DW_REG_CTRL2 0x21 +#define LIS2DW_CTRL2_VAL_BOOT 0b10000000 +#define LIS2DW_CTRL2_VAL_SOFT_RESET 0b01000000 +#define LIS2DW_CTRL2_VAL_CS_PU_DISC 0b00010000 +#define LIS2DW_CTRL2_VAL_BDU 0b00001000 +#define LIS2DW_CTRL2_VAL_IF_ADD_INC 0b00000100 + +#define LIS2DW_REG_CTRL3 0x22 +#define LIS2DW_CTRL4_VAL_SELF_TEST_POS 0b10000000 +#define LIS2DW_CTRL4_VAL_SELF_TEST_NEG 0b01000000 +#define LIS2DW_CTRL3_VAL_PP_OD 0b00100000 +#define LIS2DW_CTRL3_VAL_LIR 0b00010000 +#define LIS2DW_CTRL3_VAL_H_L_ACTIVE 0b00001000 +#define LIS2DW_CTRL3_VAL_SLP_MODE_SEL 0b00000010 +#define LIS2DW_CTRL3_VAL_SLP_MODE_1 0b00000001 + +#define LIS2DW_REG_CTRL4 0x23 +#define LIS2DW_CTRL4_INT1_6D 0b10000000 +#define LIS2DW_CTRL4_INT1_SINGLE_TAP 0b01000000 +#define LIS2DW_CTRL4_INT1_WU 0b00100000 +#define LIS2DW_CTRL4_INT1_FF 0b00010000 +#define LIS2DW_CTRL4_INT1_TAP 0b00001000 +#define LIS2DW_CTRL4_INT1_DIFF5 0b00000100 +#define LIS2DW_CTRL4_INT1_FTH 0b00000010 +#define LIS2DW_CTRL4_INT1_DRDY 0b00000001 + +#define LIS2DW_REG_CTRL5 0x24 +#define LIS2DW_CTRL5_INT2_SLEEP_STATE 0b10000000 +#define LIS2DW_CTRL5_INT2_SLEEP_CHG 0b01000000 +#define LIS2DW_CTRL5_INT2_BOOT 0b00100000 +#define LIS2DW_CTRL5_INT2_DRDY_T 0b00010000 +#define LIS2DW_CTRL5_INT2_OVR 0b00001000 +#define LIS2DW_CTRL5_INT2_DIFF5 0b00000100 +#define LIS2DW_CTRL5_INT2_FTH 0b00000010 +#define LIS2DW_CTRL5_INT2_DRDY 0b00000001 + +#define LIS2DW_REG_CTRL6 0x25 +#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV2 (LIS2DW_BANDWIDTH_FILTER_DIV2 << 6) +#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV4 (LIS2DW_BANDWIDTH_FILTER_DIV4 << 6) +#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV10 (LIS2DW_BANDWIDTH_FILTER_DIV10 << 6) +#define LIS2DW_CTRL6_VAL_BANDWIDTH_DIV20 (LIS2DW_BANDWIDTH_FILTER_DIV20 << 6) +#define LIS2DW_CTRL6_VAL_RANGE_2G (LIS2DW_RANGE_2_G << 4) +#define LIS2DW_CTRL6_VAL_RANGE_4G (LIS2DW_RANGE_4_G << 4) +#define LIS2DW_CTRL6_VAL_RANGE_8G (LIS2DW_RANGE_8_G << 4) +#define LIS2DW_CTRL6_VAL_RANGE_16G (LIS2DW_RANGE_16_G << 4) +#define LIS2DW_CTRL6_VAL_FDS 0b00001000 +#define LIS2DW_CTRL6_VAL_LOW_NOISE 0b00000100 + +#define LIS2DW_REG_OUT_TEMP 0x26 + +#define LIS2DW_REG_STATUS 0x27 +#define LIS2DW_STATUS_VAL_FIFO_THS 0b10000000 +#define LIS2DW_STATUS_VAL_WU_IA 0b01000000 +#define LIS2DW_STATUS_VAL_SLEEP_STATE 0b00100000 +#define LIS2DW_STATUS_VAL_DOUBLE_TAP 0b00010000 +#define LIS2DW_STATUS_VAL_SINGLE_TAP 0b00001000 +#define LIS2DW_STATUS_VAL_6D_IA 0b00000100 +#define LIS2DW_STATUS_VAL_FF_IA 0b00000010 +#define LIS2DW_STATUS_VAL_DRDY 0b00000001 + +#define LIS2DW_REG_OUT_X_L 0x28 +#define LIS2DW_REG_OUT_X_H 0x29 +#define LIS2DW_REG_OUT_Y_L 0x2A +#define LIS2DW_REG_OUT_Y_H 0x2B +#define LIS2DW_REG_OUT_Z_L 0x2C +#define LIS2DW_REG_OUT_Z_H 0x2D + +#define LIS2DW_REG_FIFO_CTRL 0x2E +#define LIS2DW_REG_FIFO_SRC 0x2F + +#define LIS2DW_REG_TAP_THS_X 0x30 +#define LIS2DW_REG_TAP_THS_Y 0x31 +#define LIS2DW_REG_TAP_THS_Z 0x32 +#define LIS2DW_REG_INT1_DUR 0x33 +#define LIS2DW_REG_WAKE_UP_THS 0x34 +#define LIS2DW_REG_WAKE_UP_DUR 0x35 +#define LIS2DW_REG_FREE_FALL 0x36 +#define LIS2DW_REG_STATUS_DUP 0x37 + +#define LIS2DW_REG_WAKE_UP_SRC 0x38 +#define LIS2DW_WAKE_UP_SRC_VAL_FF_IA 0b00100000 +#define LIS2DW_WAKE_UP_SRC_VAL_SLEEP_STATE_IA 0b00010000 +#define LIS2DW_WAKE_UP_SRC_VAL_WU_IA 0b00001000 +#define LIS2DW_WAKE_UP_SRC_VAL_X_WU 0b00000100 +#define LIS2DW_WAKE_UP_SRC_VAL_Y_WU 0b00000010 +#define LIS2DW_WAKE_UP_SRC_VAL_Z_WU 0b00000001 + +#define LIS2DW_REG_TAP_SRC 0x39 +#define LIS2DW_TAP_SRC_VAL_TAP_IA 0b01000000 +#define LIS2DW_TAP_SRC_VAL_SINGLE_TAP 0b00100000 +#define LIS2DW_TAP_SRC_VAL_DOUBLE_TAP 0b00010000 +#define LIS2DW_TAP_SRC_VAL_TAP_SIGN 0b00001000 +#define LIS2DW_TAP_SRC_VAL_X_TAP 0b00000100 +#define LIS2DW_TAP_SRC_VAL_Y_TAP 0b00000010 +#define LIS2DW_TAP_SRC_VAL_Z_TAP 0b00000001 + +#define LIS2DW_REG_SIXD_SRC 0x3A +#define LIS2DW_WAKE_UP_SRC_VAL_6D_IA 0b01000000 +#define LIS2DW_WAKE_UP_SRC_VAL_ZH 0b00100000 +#define LIS2DW_WAKE_UP_SRC_VAL_ZL 0b00010000 +#define LIS2DW_WAKE_UP_SRC_VAL_YH 0b00001000 +#define LIS2DW_WAKE_UP_SRC_VAL_YL 0b00000100 +#define LIS2DW_WAKE_UP_SRC_VAL_XH 0b00000010 +#define LIS2DW_WAKE_UP_SRC_VAL_XL 0b00000001 + +#define LIS2DW_REG_ALL_INT_SRC 0x3B +#define LIS2DW_REG_ALL_INT_SRC_SLEEP_CHANGE_IA 0b00100000 +#define LIS2DW_REG_ALL_INT_SRC_6D_IA 0b00010000 +#define LIS2DW_REG_ALL_INT_SRC_DOUBLE_TAP 0b00001000 +#define LIS2DW_REG_ALL_INT_SRC_SINGLE_TAP 0b00000100 +#define LIS2DW_REG_ALL_INT_SRC_WU_IA 0b00000010 +#define LIS2DW_REG_ALL_INT_SRC_FF_IA 0b00000001 + +#define LIS2DW_REG_X_OFS_USR 0x3C +#define LIS2DW_REG_Y_OFS_USR 0x3D +#define LIS2DW_REG_Z_OFS_USR 0x3E + +#define LIS2DW_REG_CTRL7 0x3F +#define LIS2DW_CTRL7_VAL_DRDY_PULSED 0b10000000 +#define LIS2DW_CTRL7_VAL_INT2_ON_INT1 0b01000000 +#define LIS2DW_CTRL7_VAL_INTERRUPTS_ENABLE 0b00100000 +#define LIS2DW_CTRL7_VAL_USR_OFF_ON_OUT 0b00010000 +#define LIS2DW_CTRL7_VAL_USR_OFF_ON_WU 0b00001000 +#define LIS2DW_CTRL7_VAL_USR_OFF_W 0b00000100 +#define LIS2DW_CTRL7_VAL_HP_REF_MODE 0b00000010 +#define LIS2DW_CTRL7_VAL_LPASS_ON6D 0b00000001 + +bool lis2dw_begin(void); + +uint8_t lis2dw_get_device_id(void); + +bool lis2dw_have_new_data(void); + +lis2dw_reading lis2dw_get_raw_reading(void); + +lis2dw_acceleration_measurement lis2dw_get_acceleration_measurement(lis2dw_reading *out_reading); + +void lis2dw_set_range(lis2dw_range_t range); + +lis2dw_range_t lis2dw_get_range(void); + +void lis2dw_set_data_rate(lis2dw_data_rate_t dataRate); + +lis2dw_data_rate_t lis2dw_get_data_rate(void); + +void lis2dw_set_low_power_mode(lis2dw_low_power_mode_t mode); + +lis2dw_low_power_mode_t lis2dw_get_low_power_mode(void); + +void lis2dw_set_low_noise_mode(bool on); + +bool lis2dw_get_low_noise_mode(void); + +#endif // LIS2DW_H diff --git a/watch-library/shared/watch/watch.h b/watch-library/shared/watch/watch.h new file mode 100644 index 00000000..064f90ec --- /dev/null +++ b/watch-library/shared/watch/watch.h @@ -0,0 +1,83 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +/// @file watch.h + +#ifndef WATCH_H_ +#define WATCH_H_ +#include +#include +#include "driver_init.h" + +/** @mainpage Sensor Watch Documentation + * @brief This documentation covers most of the functions you will use to interact with the Sensor Watch + hardware. It is divided into the following sections: + - @ref app - This section covers the functions that you will implement in your app.c file when designing a + Sensor Watch app. + - @ref rtc - This section covers functions related to the SAM L22's real-time clock peripheral, including + date, time and alarm functions. + - @ref slcd - This section covers functions related to the Segment LCD display driver, which is responsible + for displaying strings of characters and indicators on the main watch display. + - @ref buttons - This section covers functions related to the three buttons: Light, Mode and Alarm. + - @ref led - This section covers functions related to the bi-color red/green LED mounted behind the LCD. + - @ref buzzer - This section covers functions related to the piezo buzzer. + - @ref adc - This section covers functions related to the SAM L22's analog-to-digital converter, as well as + configuring and reading values from the five analog-capable pins on the 9-pin connector. + - @ref gpio - This section covers functions related to general-purpose input and output signals. + - @ref i2c - This section covers functions related to the SAM L22's built-I2C driver, including configuring + the I2C bus, putting values directly on the bus and reading data from registers on I2C devices. + - @ref debug - This section covers functions related to the debug UART, available on pin D1 of the 9-pin connector. + - @ref deepsleep - This section covers functions related to preparing for and entering BACKUP mode, the + deepest sleep mode available on the SAM L22. + */ + +#include "watch_app.h" +#include "watch_rtc.h" +#include "watch_slcd.h" +#include "watch_extint.h" +#include "watch_led.h" +#include "watch_buzzer.h" +#include "watch_adc.h" +#include "watch_gpio.h" +#include "watch_i2c.h" +#include "watch_uart.h" +#include "watch_deepsleep.h" + +#include "watch_private.h" + +/** @brief Returns true when the battery voltage dips below 2.5V. + * @details A CR2016 battery will have a nominal voltage between 2.9 and 3 volts for most of its lifespan. Once the battery + * discharges to about 60%, the voltage will drift slightly lower; this may manifest as a dimmer LED. By the time + * the battery voltage has fallen to 2.5 volts, it will have probably less than 10% of its capacity remaining, and + * you can expect the voltage to drop relatively quickly as the battery dies. + */ +bool watch_is_battery_low(void); + +/** @brief Returns true if either the buzzer or the LED driver is enabled. + * @details Both the buzzer and the LED use the TCC peripheral to drive their behavior. This function returns true if that + * peripheral is enabled. You can use this function to determine whether you need to call the watch_disable_leds or + * or watch_enable_buzzer functions before using these peripherals. + */ +bool watch_is_buzzer_or_led_enabled(void); + +#endif /* WATCH_H_ */ \ No newline at end of file diff --git a/watch-library/shared/watch/watch_adc.h b/watch-library/shared/watch/watch_adc.h new file mode 100644 index 00000000..d4c8586d --- /dev/null +++ b/watch-library/shared/watch/watch_adc.h @@ -0,0 +1,174 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_ADC_H_INCLUDED +#define _WATCH_ADC_H_INCLUDED +////< @file watch_adc.h + +#include "watch.h" + +// matches adc.h +#ifndef ADC_REFCTRL_REFSEL_INTREF_Val +#define ADC_REFCTRL_REFSEL_INTREF_Val 0x0 +#endif + +#ifndef ADC_REFCTRL_REFSEL_INTVCC0_Val +#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1 +#endif + +#ifndef ADC_REFCTRL_REFSEL_INTVCC1_Val +#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2 +#endif + +#ifndef ADC_REFCTRL_REFSEL_INTVCC2_Val +#define ADC_REFCTRL_REFSEL_INTVCC2_Val 0x5 +#endif + +/** @addtogroup adc Analog Input + * @brief This section covers functions related to the SAM L22's analog-to-digital converter, + * as well as configuring and reading values from the five analog-capable pins on the + * 9-pin connector. + */ +/// @{ +/** @brief Enables the ADC peripheral. You must call this before attempting to read a value + * from an analog pin. + */ +void watch_enable_adc(void); + +/** @brief Configures the selected pin for analog input. + * @param pin One of pins A0-A4. + */ +void watch_enable_analog_input(const uint8_t pin); + +/** @brief Reads an analog value from one of the pins. + * @param pin One of pins A0-A4. + * @return a 16-bit unsigned integer from 0-65535 representing the sampled value, unless you + * have changed the number of samples. @see watch_set_num_analog_samples for details + * on how that function changes the values returned from this one. + **/ +uint16_t watch_get_analog_pin_level(const uint8_t pin); + +/** @brief Sets the number of samples to accumulate when measuring a pin level. Default is 16. + * @param samples A power of 2 <= 1024. Specifically: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 + or 1024. Any other value will be ignored. + * @details The SAM L22's ADC has a resolution of 12 bits. By default, the watch configures + * the ADC to take 16 samples of the analog input and accumulate them in the result + * register; this effectively gives us a 16-bit resolution, at the cost of taking 16 + * ADC cycles to complete a measurement. If you are measuring a slowly changing signal + * like a thermistor output or an ambient light sensor this is probably fine, even + * desirable. If you are measuring something a bit more fast-paced, like an analog + * accelerometer, you may wish to exchange precision for speed. In this case you may + * call this function to configure the ADC to accumulate fewer samples. HOWEVER! Note + * that this may change the range of values returned from watch_get_analog_pin_level: + * - For watch_set_num_analog_samples(1), the returned value will be 12 bits (0-4095). + * - For watch_set_num_analog_samples(2), the returned value will be 13 bits (0-8191). + * - For watch_set_num_analog_samples(4), the returned value will be 14 bits (0-16383). + * - For watch_set_num_analog_samples(8), the returned value will be 15 bits (0-32767). + * For sampling values over 16, the returned value will still be 16 bits (0-65535); the + * ADC will automatically divide the measured value by whatever factor is necessary to fit + * the result in 16 bits. + * @see watch_get_analog_pin_level + **/ +void watch_set_analog_num_samples(uint16_t samples); + +/** @brief Sets the length of time spent sampling, which allows measurement of higher impedance inputs. + * Default is 1. + * @param cycles The number of ADC cycles to sample, between 1 and 64. + * @see this article by Thea Flowers: https://blog.thea.codes/getting-the-most-out-of-the-samd21-adc/ + * which is where I learned all of this. + * @details To measure an analog value, the SAM L22 must charge a capacitor to the analog voltage + * presented at the input. This takes time. Importantly, the higher the input impedance, + * the more time this takes. As a basic example: if you are using a thermistor tied to + * VCC to measure temperature, the capacitor has to charge through the thermistor. The + * higher the resistor value, the higher the input impedance, and the more time we need + * to allow for the measurement. By default, the ADC is configured to run on a 500 kHz + * clock with a sample time of one cycle. This is appropriate for an input impedance up + * to about 28kΩ. Setting the sampling time to 4 cycles allows for an input impedance up + * to 123kΩ. Setting the sampling time to the maximum of 64 cycles theoretically allows + * for input impedance up to 2 MΩ. (I based these numbers on the calculator in the linked + * blog post; it also has a ton of great info on the SAM D21 ADC, which is similar to the + * SAM L22's). + **/ +void watch_set_analog_sampling_length(uint8_t cycles); + +typedef enum { + ADC_REFERENCE_INTREF = ADC_REFCTRL_REFSEL_INTREF_Val, + ADC_REFERENCE_VCC_DIV1POINT6 = ADC_REFCTRL_REFSEL_INTVCC0_Val, + ADC_REFERENCE_VCC_DIV2 = ADC_REFCTRL_REFSEL_INTVCC1_Val, + ADC_REFERENCE_VCC = ADC_REFCTRL_REFSEL_INTVCC2_Val, +} watch_adc_reference_voltage; + + +/** @brief Selects the reference voltage to use for analog readings. Default is ADC_REFERENCE_VCC. + * @param reference One of ADC_REFERENCE_VCC, ADC_REFERENCE_VCC_DIV1POINT6, ADC_REFERENCE_VCC_DIV2 + * or ADC_REFERENCE_INTREF. + * @details In order to turn an analog voltage into a 16-bit integer, the ADC needs to compare the + * measured voltage to a reference point. For example, if you were powering the watch with + * VCC == 3.0V and you had two 10K resistors connected in series from 3V to GND, you could + * expect to get 3 volts when you measure the top of the voltage divider, 0 volts at the + * bottom, and 1.5 volts in the middle. If you read these values uising a reference voltage + * of ADC_REFERENCE_VCC, the top value would be about 65535, the bottom about 0, and the + * middle about 32768. However! If we used ADC_REFERENCE_VCC_DIV2 as our reference, we would + * expect to get 65535 both at the top and the middle, because the largest value the ADC can + * measure in this configutation is 1.5V (VCC / 2). + * + * By changing the reference voltage from ADC_REFERENCE_VCC to ADC_REFERENCE_VCC_DIV1POINT6 + * or ADC_REFERENCE_VCC_DIV2, you can get more resolution when measuring small voltages (i.e. + * a phototransistor circuit in low light). + * + * There is also a special reference voltage called ADC_REFERENCE_INTREF. The SAM L22's + * Supply Controller provides a selectable voltage reference (by default, 1.024 V) that you + * can select as a reference voltage for ADC conversions. Unlike the three references we + * talked about in the last paragraph, this reference voltage does not depend on VCC, which + * makes it very useful for measuring the battery voltage (since you can't really compare + * VCC to itself). You can change the INTREF voltage to 2.048 or 4.096 V by poking at the + * supply controller's VREF register, but the watch library does not support this use case. + **/ +void watch_set_analog_reference_voltage(watch_adc_reference_voltage reference); + +/** @brief Returns the voltage of the VCC supply in millivolts (i.e. 3000 mV == 3.0 V). If running on + * a coin cell, this will be the battery voltage. + * @details Unlike other ADC functions, this function does not return a raw value from the ADC, but + * rather scales it to an actual number of millivolts. This is because the ADC doesn't let + * us measure VCC per se; it instead lets us measure VCC / 4, and we choose to measure it + * against the internal reference voltage of 1.024 V. In short, the ADC gives us a number + * that's complicated to deal with, so we just turn it into a useful number for you :) + * @note This function depends on INTREF being 1.024V. If you have changed it by poking at the supply + * controller's VREF.SEL bits, this function will return inaccurate values. + */ +uint16_t watch_get_vcc_voltage(void); + +/** @brief Disables the analog circuitry on the selected pin. + * @param pin One of pins A0-A4. + */ +void watch_disable_analog_input(const uint8_t pin); + +/** @brief Disables the ADC peripheral. + * @note You will need to call watch_enable_adc to re-enable the ADC peripheral. When you do, it will + * have the default settings of 16 samples and 1 measurement cycle; if you customized these + * parameters, you will need to set them up again. + **/ +void watch_disable_adc(void); + +/// @} +#endif diff --git a/watch-library/shared/watch/watch_app.h b/watch-library/shared/watch/watch_app.h new file mode 100644 index 00000000..4fa29df8 --- /dev/null +++ b/watch-library/shared/watch/watch_app.h @@ -0,0 +1,108 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_APP_H_INCLUDED +#define _WATCH_APP_H_INCLUDED +////< @file watch_app.h + +/** @addtogroup app Application Framework + * @brief This section covers the functions that you will implement in your app.c file when designing a Sensor Watch app. + * @details You should be able to write a watch app by simply implementing these functions and declaring callbacks for + * various GPIO and peripheral interrupts. The main.c file takes care of calling these functions for you. The + * general flow: + * + * 1. Your app_init() function is called. + * - This method should only be used to set your initial application state. + * 2. If your app is waking from BACKUP, app_wake_from_backup() is called. + * - If you saved state in the RTC's backup registers, you can restore it here. + * 3. Your app_setup() method is called. + * - You may wish to enable some functionality and peripherals here. + * - You should definitely set up some interrupts here. + * 4. The main run loop begins: your app_loop() function is called. + * - Run code and update your UI here. + * - Return true if your app is prepared to enter STANDBY mode. + * 5. This step differs depending on the value returned by app_loop: + * - If you returned false, execution resumes at (4). + * - If you returned true, app_prepare_for_standby() is called; execution moves on to (6). + * 6. The microcontroller enters STANDBY mode. + * - No user code will run, and the watch will enter a low power mode. + * - The watch will remain in this state until an interrupt wakes it. + * 7. Once woken from STANDBY, your app_wake_from_standby() function is called. + * - After this, execution resumes at (4). + */ +/// @{ +/** @brief A function you will implement to initialize your application state. The app_init function is called before + * anything else. Use it to set up any internal data structures or application state required by your app, + * but don't configure any peripherals just yet. + */ +void app_init(void); + +/** @brief A function you will implement to wake from BACKUP mode, which wipes the system's RAM, and with it, your + * application's state. You may have chosen to store some important application state in the RTC's backup + * registers prior to entering this mode. You may restore that state here. + */ +void app_wake_from_backup(void); + +/** @brief A function you will implement to set up your application. The app_setup function is like setup() in Arduino. + * It is called once when the program begins. You should set pin modes and enable any peripherals you want to + * set up (real-time clock, I2C, etc.) Depending on your application, you may or may not want to configure + * sensors on your sensor board here. For example, a low-power accelerometer that will run at all times should + * be configured here, whereas you may want to enable a more power-hungry sensor only when you need it. + * @note If your app enters the ultra-low power BACKUP sleep mode, this function will be called again when it wakes + * from that deep sleep state. In this state, the RTC will still be configured with the correct date and time. + */ +void app_setup(void); + +/** @brief A function you will implement to serve as the app's main run loop. This method will be called repeatedly, + or if you enter STANDBY mode, as soon as the device wakes from sleep. + * @return You should return true if your app is prepared to enter STANDBY mode. If you return false, your app's + * app_loop method will be called again immediately. Note that in STANDBY mode, the watch will consume only + * about 95 microamperes of power, whereas if you return false and keep the app awake, it will consume about + * 355 microamperes. This is the difference between months of battery life and days. As much as possible, + * you should limit the amount of time your app spends awake. + * @note Only the RTC, the segment LCD controller and the external interrupt controller run in STANDBY mode. If you + * are using, e.g. the PWM function to set a custom LED color, you should return false here until you are + * finished with that operation. Note however that the peripherals will continue running after waking up, + * so e.g. the I2C controller, if configured, will sleep in STANDBY. But you can use it again as soon as your + * app wakes up. + */ +bool app_loop(void); + +/** @brief A function you will implement to prepare to enter STANDBY mode. The app_prepare_for_standby function is + * called after your app_loop function returns true, and just before the watch enters STANDBY mode. In this + * mode most peripherals are shut down, and no code will run until the watch receives an interrupt (generally + * either the 1Hz tick or a press on one of the buttons). + * @note If you are PWM'ing the LED or playing a sound on the buzzer, the TC/TCC peripherals that drive those operations + * will not run in STANDBY. BUT! the output pins will retain the state they had when entering standby. This means + * you could end up entering standby with an LED on and draining power, or with a DC potential across the piezo + * buzzer that could damage it if left in this state. If your app_loop does not prevent sleep during these + * activities, you should make sure to disable these outputs in app_prepare_for_standby. + */ +void app_prepare_for_standby(void); + +/** @brief A method you will implement to configure the app after waking from STANDBY mode. + */ +void app_wake_from_standby(void); + +/// @} +#endif diff --git a/watch-library/shared/watch/watch_buzzer.h b/watch-library/shared/watch/watch_buzzer.h new file mode 100644 index 00000000..1b5d197c --- /dev/null +++ b/watch-library/shared/watch/watch_buzzer.h @@ -0,0 +1,164 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_BUZZER_H_INCLUDED +#define _WATCH_BUZZER_H_INCLUDED +////< @file watch_buzzer.h + +#include "watch.h" + +/** @addtogroup buzzer Buzzer + * @brief This section covers functions related to the piezo buzzer embedded in the F-91W's back plate. + */ +/// @{ +/** @brief Enables the TCC peripheral, which drives the buzzer. + */ +void watch_enable_buzzer(void); + +/** @brief Sets the period of the buzzer. + * @param period The period of a single cycle for the TCC peripheral. You can determine the period for + * a desired frequency with the following formula: period = 1000000 / freq + */ +void watch_set_buzzer_period(uint32_t period); + +/** @brief Disables the TCC peripheral that drives the buzzer. + * @note If you are using PWM to set custom LED colors, this method will also disable the LED PWM driver, + * since the buzzer and LED both make use of the same peripheral to drive their PWM behavior. + */ +void watch_disable_buzzer(void); + +/** @brief Turns the buzzer output on. It will emit a continuous sound at the given frequency. + * @note The TCC peripheral that drives the buzzer does not run in standby mode; if you wish for buzzer + * output to continue, you should prevent your app from going to sleep. + */ +void watch_set_buzzer_on(void); + +/** @brief Turns the buzzer output off. + */ +void watch_set_buzzer_off(void); + +/// @brief 87 notes for use with watch_buzzer_play_note +typedef enum BuzzerNote { + BUZZER_NOTE_A1, ///< 55.00 Hz + BUZZER_NOTE_A1SHARP_B1FLAT, ///< 58.27 Hz + BUZZER_NOTE_B1, ///< 61.74 Hz + BUZZER_NOTE_C2, ///< 65.41 Hz + BUZZER_NOTE_C2SHARP_D2FLAT, ///< 69.30 Hz + BUZZER_NOTE_D2, ///< 73.42 Hz + BUZZER_NOTE_D2SHARP_E2FLAT, ///< 77.78 Hz + BUZZER_NOTE_E2, ///< 82.41 Hz + BUZZER_NOTE_F2, ///< 87.31 Hz + BUZZER_NOTE_F2SHARP_G2FLAT, ///< 92.50 Hz + BUZZER_NOTE_G2, ///< 98.00 Hz + BUZZER_NOTE_G2SHARP_A2FLAT, ///< 103.83 Hz + BUZZER_NOTE_A2, ///< 110.00 Hz + BUZZER_NOTE_A2SHARP_B2FLAT, ///< 116.54 Hz + BUZZER_NOTE_B2, ///< 123.47 Hz + BUZZER_NOTE_C3, ///< 130.81 Hz + BUZZER_NOTE_C3SHARP_D3FLAT, ///< 138.59 Hz + BUZZER_NOTE_D3, ///< 146.83 Hz + BUZZER_NOTE_D3SHARP_E3FLAT, ///< 155.56 Hz + BUZZER_NOTE_E3, ///< 164.81 Hz + BUZZER_NOTE_F3, ///< 174.61 Hz + BUZZER_NOTE_F3SHARP_G3FLAT, ///< 185.00 Hz + BUZZER_NOTE_G3, ///< 196.00 Hz + BUZZER_NOTE_G3SHARP_A3FLAT, ///< 207.65 Hz + BUZZER_NOTE_A3, ///< 220.00 Hz + BUZZER_NOTE_A3SHARP_B3FLAT, ///< 233.08 Hz + BUZZER_NOTE_B3, ///< 246.94 Hz + BUZZER_NOTE_C4, ///< 261.63 Hz + BUZZER_NOTE_C4SHARP_D4FLAT, ///< 277.18 Hz + BUZZER_NOTE_D4, ///< 293.66 Hz + BUZZER_NOTE_D4SHARP_E4FLAT, ///< 311.13 Hz + BUZZER_NOTE_E4, ///< 329.63 Hz + BUZZER_NOTE_F4, ///< 349.23 Hz + BUZZER_NOTE_F4SHARP_G4FLAT, ///< 369.99 Hz + BUZZER_NOTE_G4, ///< 392.00 Hz + BUZZER_NOTE_G4SHARP_A4FLAT, ///< 415.30 Hz + BUZZER_NOTE_A4, ///< 440.00 Hz + BUZZER_NOTE_A4SHARP_B4FLAT, ///< 466.16 Hz + BUZZER_NOTE_B4, ///< 493.88 Hz + BUZZER_NOTE_C5, ///< 523.25 Hz + BUZZER_NOTE_C5SHARP_D5FLAT, ///< 554.37 Hz + BUZZER_NOTE_D5, ///< 587.33 Hz + BUZZER_NOTE_D5SHARP_E5FLAT, ///< 622.25 Hz + BUZZER_NOTE_E5, ///< 659.25 Hz + BUZZER_NOTE_F5, ///< 698.46 Hz + BUZZER_NOTE_F5SHARP_G5FLAT, ///< 739.99 Hz + BUZZER_NOTE_G5, ///< 783.99 Hz + BUZZER_NOTE_G5SHARP_A5FLAT, ///< 830.61 Hz + BUZZER_NOTE_A5, ///< 880.00 Hz + BUZZER_NOTE_A5SHARP_B5FLAT, ///< 932.33 Hz + BUZZER_NOTE_B5, ///< 987.77 Hz + BUZZER_NOTE_C6, ///< 1046.50 Hz + BUZZER_NOTE_C6SHARP_D6FLAT, ///< 1108.73 Hz + BUZZER_NOTE_D6, ///< 1174.66 Hz + BUZZER_NOTE_D6SHARP_E6FLAT, ///< 1244.51 Hz + BUZZER_NOTE_E6, ///< 1318.51 Hz + BUZZER_NOTE_F6, ///< 1396.91 Hz + BUZZER_NOTE_F6SHARP_G6FLAT, ///< 1479.98 Hz + BUZZER_NOTE_G6, ///< 1567.98 Hz + BUZZER_NOTE_G6SHARP_A6FLAT, ///< 1661.22 Hz + BUZZER_NOTE_A6, ///< 1760.00 Hz + BUZZER_NOTE_A6SHARP_B6FLAT, ///< 1864.66 Hz + BUZZER_NOTE_B6, ///< 1975.53 Hz + BUZZER_NOTE_C7, ///< 2093.00 Hz + BUZZER_NOTE_C7SHARP_D7FLAT, ///< 2217.46 Hz + BUZZER_NOTE_D7, ///< 2349.32 Hz + BUZZER_NOTE_D7SHARP_E7FLAT, ///< 2489.02 Hz + BUZZER_NOTE_E7, ///< 2637.02 Hz + BUZZER_NOTE_F7, ///< 2793.83 Hz + BUZZER_NOTE_F7SHARP_G7FLAT, ///< 2959.96 Hz + BUZZER_NOTE_G7, ///< 3135.96 Hz + BUZZER_NOTE_G7SHARP_A7FLAT, ///< 3322.44 Hz + BUZZER_NOTE_A7, ///< 3520.00 Hz + BUZZER_NOTE_A7SHARP_B7FLAT, ///< 3729.31 Hz + BUZZER_NOTE_B7, ///< 3951.07 Hz + BUZZER_NOTE_C8, ///< 4186.01 Hz + BUZZER_NOTE_C8SHARP_D8FLAT, ///< 4434.92 Hz + BUZZER_NOTE_D8, ///< 4698.63 Hz + BUZZER_NOTE_D8SHARP_E8FLAT, ///< 4978.03 Hz + BUZZER_NOTE_E8, ///< 5274.04 Hz + BUZZER_NOTE_F8, ///< 5587.65 Hz + BUZZER_NOTE_F8SHARP_G8FLAT, ///< 5919.91 Hz + BUZZER_NOTE_G8, ///< 6271.93 Hz + BUZZER_NOTE_G8SHARP_A8FLAT, ///< 6644.88 Hz + BUZZER_NOTE_A8, ///< 7040.00 Hz + BUZZER_NOTE_A8SHARP_B8FLAT, ///< 7458.62 Hz + BUZZER_NOTE_B8, ///< 7902.13 Hz + BUZZER_NOTE_REST ///< no sound +} BuzzerNote; + +/** @brief Plays the given note for a set duration. + * @param note The note you wish to play, or BUZZER_NOTE_REST to disable output for the given duration. + * @param duration_ms The duration of the note. + * @note Note that this will block your UI for the duration of the note's play time, and it will + * after this call, the buzzer period will be set to the period of this note. + */ +void watch_buzzer_play_note(BuzzerNote note, uint16_t duration_ms); + +/// @brief An array of periods for all the notes on a piano, corresponding to the names in BuzzerNote. +extern const uint16_t NotePeriods[108]; + +/// @} +#endif diff --git a/watch-library/shared/watch/watch_deepsleep.h b/watch-library/shared/watch/watch_deepsleep.h new file mode 100644 index 00000000..56d75478 --- /dev/null +++ b/watch-library/shared/watch/watch_deepsleep.h @@ -0,0 +1,159 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_DEEPSLEEP_H_INCLUDED +#define _WATCH_DEEPSLEEP_H_INCLUDED +////< @file watch_deepsleep.h + +#include "watch.h" + +// These are declared in watch_rtc.c. +extern ext_irq_cb_t btn_alarm_callback; +extern ext_irq_cb_t a2_callback; +extern ext_irq_cb_t a4_callback; + +/** @addtogroup deepsleep Sleep Control + * @brief This section covers functions related to the various sleep modes available to the watch, + * including Sleep, Deep Sleep, and BACKUP mode. + * @details These terms changed meaning a bit over the course of development; if you are coming + * to this documentation after having worked with an earlier version of the library, + * these definitions should clarify the terminology. Terms in all caps are modes of the + * SAM L22; terms in Title Case are specific implementations in this library. + * - ACTIVE mode is the mode the SAM L22 is in when both the main clock and the CPU are + * running. It is the most power-hungry mode. If you ever call delay_ms to wait a beat, + * the watch will remain in ACTIVE mode while taking that delay. In addition, whenever + * your `app_loop` function returns false, the device will remain in ACTIVE mode and + * call your `app_loop` function again. + * - STANDBY mode turns off the main clock and halts the CPU. Since the PWM driver is + * run from the main clock, it also stops the buzzer and any dimming of the LEDs. + * In this mode, the watch can wake from any interrupt source. Whenever your `app_loop` + * function returns true, the watch enters STANDBY mode until the next tick or other + * interrupt. This mode uses much less power than ACTIVE mode. + * - Sleep Mode is a special case of STANDBY mode. In this mode, the watch turns off + * almost all peripherals (including the external interrupt controller), and disables + * all pins except for the external wake pins. In this mode the watch can only wake + * from the RTC alarm interrupt or an external wake pin (A2, A4 or the alarm button), + * but the display remains on and your app's state is retained. You can enter this + * mode by calling `watch_enter_sleep_mode`. It consumes an order of magnitude less + * power than STANDBY mode. + * - Deep Sleep Mode is identical to sleep mode, but it also turns off the LCD to save + * a bit more power. You can enter this mode by calling `watch_enter_deep_sleep_mode`. + * - BACKUP mode is the lowest possible power mode on the SAM L22. It turns off all pins + * and peripherals except for the RTC. It also turns off the RAM, obliterating your + * application's state. The only way to wake from this mode is by setting an external + * wake interrupt on pin A2 or pin A4, and when you do wake it will be much like a + * wake from reset. You can enter this mode by calling `watch_enter_backup_mode`. + */ +/// @{ + +/** @brief Registers a callback on one of the RTC's external wake pins, which can wake the device + * from Sleep, Deep Sleep and BACKUP modes (but see warning re: BACKUP mode). + * @param pin Either pin BTN_ALARM, A2, or A4. These are the three external wake pins. If the pin + * is BTN_ALARM, this function also enables an internal pull down on that pin. + * @param callback The callback to be called if this pin triggers outside of BACKUP mode. If this is + * NULL, no callback will be called even in normal modes, but the interrupt will + * still be enabled so that it can wake the device. + * @param level The level you wish to scan for: true for rising, false for falling. Note that you + * cannot scan for both rising and falling edges like you can with the external interrupt + * pins; with the external wake interrupt, you can only get one or the other. + * @note When in ACTIVE, STANDBY and Sleep / Deep sleep modes, this will function much like a standard + * external interrupt situation: these pins will wake the device, and your callback will be + * called. However, if the device enters BACKUP mode and one of these pins wakes the device, your + * callback WILL NOT be called, as the device is basically waking from reset at that point. + * @warning As of the current SAM L22 silicon revision (rev B), the BTN_ALARM pin cannot wake the + * device from BACKUP mode. You can still use this function to register a BTN_ALARM interrupt + * in normal or deep sleep mode, but to wake from BACKUP, you will need to use pin A2 or A4. + */ +void watch_register_extwake_callback(uint8_t pin, ext_irq_cb_t callback, bool level); + +/** @brief Unregisters the RTC interrupt on one of the EXTWAKE pins. This will prevent a value change on + * one of these pins from waking the device. + * @param pin Either pin BTN_ALARM, A2, or A4. If the pin is BTN_ALARM, this function DOES NOT disable + * the internal pull down on that pin. + */ +void watch_disable_extwake_interrupt(uint8_t pin); + +/** @brief Stores data in one of the RTC's backup registers, which retain their data in BACKUP mode. + * @param data An unsigned 32 bit integer with the data you wish to store. + * @param reg A register from 0-7. + */ +void watch_store_backup_data(uint32_t data, uint8_t reg); + +/** @brief Gets 32 bits of data from the RTC's BACKUP register. + * @param reg A register from 0-7. + * @return An unsigned 32 bit integer with the from the backup register. + */ +uint32_t watch_get_backup_data(uint8_t reg); + +/** @brief enters Sleep Mode by disabling all pins and peripherals except the RTC and the LCD. + * @details This sleep mode is not the lowest power mode available, but it has the benefit of allowing you + * to display a message to the user while asleep. You can also set an alarm interrupt to wake at a + * configfurable interval (every minute, hour or day) to update the display. You can wake from this + * mode by pressing the ALARM button, if you registered an extwake callback on the ALARM button. + * Also note that when your app wakes from this sleep mode, your app_setup method will be called + * again, since this function will have disabled things you set up there. + * + * Note that to wake from either the ALARM button, the A2 interrupt or the A4 interrupt, you + * must first configure this by calling watch_register_extwake_callback. + * + * You can estimate the power consumption of this mode to be on the order of 30 microwatts + * (about 10 µA at 3 V). + */ +void watch_enter_sleep_mode(void); + +/** @brief enters Deep Sleep Mode by disabling all pins and peripherals except the RTC. + * @details Short of BACKUP mode, this is the lowest power mode you can enter while retaining your + * application state (and the ability to wake with the alarm button). Just note that the display + * will be completely off, so you should document to the user of your application that they will + * need to press the alarm button to wake the device, or use a sensor board with support for + * an external wake pin. + * + * All notes from watch_enter_sleep_mode apply here, except for power consumption. You can estimate + * the power consumption of this mode to be on the order of 12 microwatts (about 4µA at 3 V). + */ +void watch_enter_deep_sleep_mode(void); + +/** @brief Enters the SAM L22's lowest-power mode, BACKUP. + * @details This function does some housekeeping before entering BACKUP mode. It first disables all pins + * and peripherals except for the RTC, and disables the tick interrupt (since that would wake + * us up from BACKUP mode). Once again, if you wish to wake from the A2 or the A4 interrupt, + * you must first configure this by calling watch_register_extwake_callback. + * @note If you have a callback set for an external wake interrupt, it will be called if triggered while + * in ACTIVE, STANDBY, Sleep and Deep Sleep modes, but it *will not be called* when waking from + * BACKUP mode. Waking from backup is effectively like waking from reset, except that your + * @ref app_wake_from_backup function will be called. + * @warning On current revisions of the SAM L22 silicon, the ALARM_BTN pin (PA02 RTC/IN2) cannot wake + * the device from deep sleep mode. There is an errata note (Reference: 15010) that says that + * due to a silicon bug, RTC/IN2 is not functional in BACKUP. As a result, you should not call + * this function unless you have a device on the nine-pin connector with an external interrupt + * on pin A2 or A4 (i.e. an accelerometer with an interrupt pin). + */ +void watch_enter_backup_mode(void); + +__attribute__((deprecated("Use watch_enter_sleep_mode or watch_enter_deep_sleep_mode instead"))) +void watch_enter_shallow_sleep(bool display_on); + +__attribute__((deprecated("Use watch_enter_backup_mode instead"))) +void watch_enter_deep_sleep(void); +/// @} +#endif diff --git a/watch-library/shared/watch/watch_extint.h b/watch-library/shared/watch/watch_extint.h new file mode 100644 index 00000000..452461b3 --- /dev/null +++ b/watch-library/shared/watch/watch_extint.h @@ -0,0 +1,85 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_EXTINT_H_INCLUDED +#define _WATCH_EXTINT_H_INCLUDED +////< @file watch_extint.h + +#include "watch.h" +#include "hal_ext_irq.h" + +/** @addtogroup buttons Buttons & External Interrupts + * @brief This section covers functions related to the three buttons: Light, Mode and Alarm, as well as + * external interrupts from devices on the nine-pin connector. + * @details The buttons are the core input UI of the watch, and the way the user will interact with + * your application. They are active high, pulled down by the microcontroller, and triggered + * when one of the "pushers" brings a tab from the metal frame into contact with the edge + * of the board. Note that the buttons can only wake the watch from STANDBY mode, at least as + * of the current SAM L22 silicon revision. The external interrupt controller runs in STANDBY + * mode, but it does not run in BACKUP mode; to wake from BACKUP, buttons will not cut it. + */ +/// @{ + +///@brief An enum defining the types of interrupt trigger you wish to scan for. +typedef enum watch_interrupt_trigger { + INTERRUPT_TRIGGER_NONE = 0, + INTERRUPT_TRIGGER_RISING, + INTERRUPT_TRIGGER_FALLING, + INTERRUPT_TRIGGER_BOTH, +} watch_interrupt_trigger; + +/// @brief Enables the external interrupt controller. +void watch_enable_external_interrupts(void); + +/// @brief Disables the external interrupt controller. +void watch_disable_external_interrupts(void); + +/** @brief Configures an external interrupt callback on one of the external interrupt pins. + * @details You can set one interrupt callback per pin, and you can monitor for a rising condition, + * a falling condition, or both. If you just want to detect a button press, register your + * interrupt with INTERRUPT_TRIGGER_RISING; if you want to detect an active-low interrupt + * signal from a device on the nine-pin connector, use INTERRUPT_TRIGGER_FALLING. If you + * want to detect both rising and falling conditions (i.e. button down and button up), use + * INTERRUPT_TRIGGER_BOTH and use watch_get_pin_level to check the pin level in your callback + * to determine which condition caused the interrupt. + * @param pin One of BTN_LIGHT, BTN_MODE, BTN_ALARM, A0, A1, A3 or A4. If the pin parameter matches one of + * the three button pins, this function will also enable an internal pull-down resistor. If + * the pin parameter is A0-A4, you are responsible for setting any required pull configuration + * using watch_enable_pull_up or watch_enable_pull_down. + * @param callback The function you wish to have called when the button is pressed. + * @param trigger The condition on which you wish to trigger: rising, falling or both. + * @note Pins A2 and A4 can also generate interrupts via the watch_register_extwake_callback function, which + * will allow them to trigger even when the watch is in deep sleep mode. + * @warning As of now, A2 is not usable via the watch_register_interrupt_callback function. To enable an + * external interrupt on pin A2, use the watch_register_extwake_callback function. This issue will be + * addressed in a future revision of the watch library. + */ +void watch_register_interrupt_callback(const uint8_t pin, ext_irq_cb_t callback, watch_interrupt_trigger trigger); + +__attribute__((deprecated("Use watch_register_interrupt_callback or watch_register_extwake_callback instead"))) +void watch_register_button_callback(const uint8_t pin, ext_irq_cb_t callback); + +__attribute__((deprecated("Use watch_enable_external_interrupts instead"))) +void watch_enable_buttons(void); +/// @} +#endif diff --git a/watch-library/shared/watch/watch_gpio.h b/watch-library/shared/watch/watch_gpio.h new file mode 100644 index 00000000..fc43642c --- /dev/null +++ b/watch-library/shared/watch/watch_gpio.h @@ -0,0 +1,76 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_GPIO_H_INCLUDED +#define _WATCH_GPIO_H_INCLUDED +////< @file watch_gpio.h + +#include "watch.h" + +/** @addtogroup gpio Digital Input and Output + * @brief This section covers functions related to general-purpose input and output signals. + */ +/// @{ +/** @brief Configures the selected pin for digital input. + * @param pin The pin that you wish to act as an input. + */ +void watch_enable_digital_input(const uint8_t pin); + +/** @brief Disables any digital input, along with any pull-up or pull-down configuration. + * @param pin The pin that you wish to disable. + */ +void watch_disable_digital_input(const uint8_t pin); + +/** @brief Enables a pull-up resistor on the selected pin. + * @param pin The pin that you wish to configure. + */ +void watch_enable_pull_up(const uint8_t pin); + +/** @brief Enables a pull-down resistor on the selected pin. + * @param pin The pin that you wish to configure. + */ +void watch_enable_pull_down(const uint8_t pin); + +/** @brief Gets the level of the selected pin. + * @param pin The pin whose value you wish to read. + * @return true if the pin was logic high; otherwise, false. + */ +bool watch_get_pin_level(const uint8_t pin); + +/** @brief Configures the selected pin for digital output. + * @param pin The pin that you wish to act as an output. + */ +void watch_enable_digital_output(const uint8_t pin); + +/** @brief Disables digital output on the selected pin. + * @param pin The pin that you wish disable. + */ +void watch_disable_digital_output(const uint8_t pin); + +/** @brief Sets the level of the selected pin. + * @param pin The pin whose value you wish to set. + * @param level The level you wish to set: true for high, false for low. + */ +void watch_set_pin_level(const uint8_t pin, const bool level); +/// @} +#endif diff --git a/watch-library/shared/watch/watch_i2c.h b/watch-library/shared/watch/watch_i2c.h new file mode 100644 index 00000000..fbcc1a92 --- /dev/null +++ b/watch-library/shared/watch/watch_i2c.h @@ -0,0 +1,106 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_I2C_H_INCLUDED +#define _WATCH_I2C_H_INCLUDED +////< @file watch_i2c.h + +#include "watch.h" + +/** @addtogroup i2c I2C Controller Driver + * @brief This section covers functions related to the SAM L22's built-I2C driver, including + * configuring the I2C bus, putting values directly on the bus and reading data from + * registers on I2C devices. + */ +/// @{ +/** @brief Enables the I2C peripheral. Call this before attempting to interface with I2C devices. + */ +void watch_enable_i2c(void); + +/** @brief Disables the I2C peripheral. + */ +void watch_disable_i2c(void); + +/** @brief Sends a series of values to a device on the I2C bus. + * @param addr The address of the device you wish to talk to. + * @param buf A series of unsigned bytes; the data you wish to transmit. + * @param length The number of bytes in buf that you wish to send. + */ +void watch_i2c_send(int16_t addr, uint8_t *buf, uint16_t length); + +/** @brief Receives a series of values from a device on the I2C bus. + * @param addr The address of the device you wish to hear from. + * @param buf Storage for the incoming bytes; on return, it will contain the received data. + * @param length The number of bytes that you wish to receive. + */ +void watch_i2c_receive(int16_t addr, uint8_t *buf, uint16_t length); + +/** @brief Writes a byte to a register in an I2C device. + * @param addr The address of the device you wish to address. + * @param reg The register on the device that you wish to set. + * @param data The value that you wish to set the register to. + */ +void watch_i2c_write8(int16_t addr, uint8_t reg, uint8_t data); + +/** @brief Reads a byte from a register in an I2C device. + * @param addr The address of the device you wish to address. + * @param reg The register on the device that you wish to read. + * @return An unsigned byte representing the value of the register that was read. + */ +uint8_t watch_i2c_read8(int16_t addr, uint8_t reg); + +/** @brief Reads an unsigned little-endian word from a register in an I2C device. + * @param addr The address of the device you wish to address. + * @param reg The register on the device that you wish to read. + * @return An unsigned word representing the value of the register that was read. + * @note This reads two bytes into the word in bus order. If the device returns + the LSB first and then the MSB, you can use this value as returned. + If the device returns the data in big-endian order or uses some other + kind of fancy bit packing, you may need to shuffle some bits around. + */ +uint16_t watch_i2c_read16(int16_t addr, uint8_t reg); + +/** @brief Reads three bytes as an unsigned little-endian int from a register in an I2C device. + * @param addr The address of the device you wish to address. + * @param reg The register on the device that you wish to read. + * @return An unsigned word representing the value of the register that was read. + * @note This reads three bytes into the word in bus order. If the device returns + these bytes LSB first, you can use this value as returned. If there is a + sign bit, the device returns the data in big-endian order, or it uses some + other kind of fancy bit packing, you may need to shuffle some bits around. + */ +uint32_t watch_i2c_read24(int16_t addr, uint8_t reg); + + +/** @brief Reads an unsigned little-endian int from a register in an I2C device. + * @param addr The address of the device you wish to address. + * @param reg The register on the device that you wish to read. + * @return An unsigned word representing the value of the register that was read. + * @note This reads three bytes into the word in bus order. If the device returns + these bytes LSB first, you can use this value as returned. If the device + returns the data in big-endian order, or it uses some other kind of fancy + bit packing, you may need to shuffle some bits around. + */ +uint32_t watch_i2c_read32(int16_t addr, uint8_t reg); +/// @} +#endif diff --git a/watch-library/shared/watch/watch_led.h b/watch-library/shared/watch/watch_led.h new file mode 100644 index 00000000..9e9f5640 --- /dev/null +++ b/watch-library/shared/watch/watch_led.h @@ -0,0 +1,93 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_LED_H_INCLUDED +#define _WATCH_LED_H_INCLUDED +////< @file watch_led.h + +#include "watch.h" + +/** @addtogroup led LED Control + * @brief This section covers functions related to the bi-color red/green LED mounted behind the LCD. + * @details The SAM L22 is an exceedingly power efficient chip, whereas the LED's are relatively power- + * hungry. The green LED, at full power, consumes more power than the whole chip in active mode, + * and the red LED consumes about twelve times as much power! The LED's should thus be used only + * sparingly in order to preserve battery life. + * @note Some watches use a red/blue LED instead of a red/green LED. You will be able to determine this + * easily when you double tap the reset button: if the pulsing bootloader LED is red, you have a + * red/green edition; if it is blue, you have a red/blue edition. For red/blue watches, build your + * project with the command `make LED=BLUE`, and the watch library will automatically swap the pins + * so that watch_set_led_red sets the red LED, and watch_set_led_green sets the blue one. + */ +/// @{ +/** @brief Enables the bi-color LED. + * @note The TCC peripheral that drives the LEDs does not run in STANDBY mode — but the outputs do! This + * means that if you set either red, green or both LEDs to full power, they will shine even when + * your app is asleep. If, however, you set a custom color using watch_set_led_color, the color will + * not display correctly in STANDBY mode. You will need to keep your app running while the LED is on. + */ +void watch_enable_leds(void); + +/** @brief Disables the LEDs. + * @note This method will also disable the buzzer, since the buzzer and LED both make use of the same + * peripheral to drive their PWM behavior. + */ +void watch_disable_leds(void); + +/** @brief Sets the LED to a custom color by modulating each output's duty cycle. + * @param red The red value from 0-255. + * @param green The green value from 0-255. If your watch has a red/blue LED, this will be the blue value. + * @note If you are displaying a custom color, you will need to prevent your app from going to sleep + * while the LED is on; otherwise, the color will not display correctly. You can do this by + * returning false in your app_loop method. + */ +void watch_set_led_color(uint8_t red, uint8_t green); + +/** @brief Sets the red LED to full brightness, and turns the green LED off. + * @details Of the two LED's in the RG bi-color LED, the red LED is the less power-efficient one (~4.5 mA). + */ +void watch_set_led_red(void); + +/** @brief Sets the green LED to full brightness, and turns the red LED off. + * @details Of the two LED's in the RG bi-color LED, the green LED is the more power-efficient one (~0.44 mA). + * @note If your watch has a red/blue LED, this method will set the LED to blue. + */ +void watch_set_led_green(void); + +/** @brief Sets both red and green LEDs to full brightness. + * @details The total current draw between the two LED's in this mode will be ~5 mA, which is more than the + * watch draws in any other mode. Take care not to drain the battery. + * @note If your watch has a red/blue LED, this method will set the LED to pink. + */ +void watch_set_led_yellow(void); + +/** @brief Turns both the red and the green LEDs off. */ +void watch_set_led_off(void); + +__attribute__((deprecated("Use watch_enable_leds instead"))) +void watch_enable_led(bool unused); + +__attribute__((deprecated("Use watch_disable_leds instead"))) +void watch_disable_led(bool unused); +/// @} +#endif diff --git a/watch-library/shared/watch/watch_private.h b/watch-library/shared/watch/watch_private.h new file mode 100644 index 00000000..7bb91d1f --- /dev/null +++ b/watch-library/shared/watch/watch_private.h @@ -0,0 +1,50 @@ +/* + * MIT License + * + * Copyright (c) 2021 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_PRIVATE_H_INCLUDED +#define _WATCH_PRIVATE_H_INCLUDED + +#include "watch.h" + +/// Called by main.c while setting up the app. You should not call this from your app. +void _watch_init(void); + +/// Initializes the real-time clock peripheral. +void _watch_rtc_init(void); + +/// Called by buzzer and LED setup functions. You should not call this from your app. +void _watch_enable_tcc(void); + +/// Called by buzzer and LED teardown functions. You should not call this from your app. +void _watch_disable_tcc(void); + +/// Called by main.c if plugged in to USB. You should not call this from your app. +void _watch_enable_usb(void); + +// this function ends up getting called by printf to log stuff to the USB console. +int _write(int file, char *ptr, int len); + +// this method could be overridden to read stuff from the USB console? but no need rn. +int _read(void); + +#endif diff --git a/watch-library/shared/watch/watch_private_display.c b/watch-library/shared/watch/watch_private_display.c new file mode 100644 index 00000000..87e3f1ae --- /dev/null +++ b/watch-library/shared/watch/watch_private_display.c @@ -0,0 +1,137 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_slcd.h" +#include "watch_private_display.h" + +static const uint32_t IndicatorSegments[] = { + SLCD_SEGID(0, 17), // WATCH_INDICATOR_SIGNAL + SLCD_SEGID(0, 16), // WATCH_INDICATOR_BELL + SLCD_SEGID(2, 17), // WATCH_INDICATOR_PM + SLCD_SEGID(2, 16), // WATCH_INDICATOR_24H + SLCD_SEGID(1, 10), // WATCH_INDICATOR_LAP +}; + +void watch_display_character(uint8_t character, uint8_t position) { + // special cases for positions 4 and 6 + if (position == 4 || position == 6) { + if (character == '7') character = '&'; // "lowercase" 7 + else if (character == 'A') character = 'a'; // A needs to be lowercase + else if (character == 'o') character = 'O'; // O needs to be uppercase + else if (character == 'L') character = '!'; // L needs to be in top half + else if (character == 'M' || character == 'm' || character == 'N') character = 'n'; // M and uppercase N need to be lowercase n + else if (character == 'c') character = 'C'; // C needs to be uppercase + else if (character == 'J') character = 'j'; // same + else if (character == 'v' || character == 'V' || character == 'U' || character == 'W' || character == 'w') character = 'u'; // bottom segment duplicated, so show in top half + } else { + if (character == 'u') character = 'v'; // we can use the bottom segment; move to lower half + else if (character == 'j') character = 'J'; // same but just display a normal J + } + if (position > 1) { + if (character == 'T') character = 't'; // uppercase T only works in positions 0 and 1 + } + if (position == 1) { + if (character == 'o') character = 'O'; // O needs to be uppercase + if (character == 'i') character = 'l'; // I needs to be uppercase (use an l, it looks the same) + if (character == 'n') character = 'N'; // N needs to be uppercase + if (character == 'r') character = 'R'; // R needs to be uppercase + if (character == 'd') character = 'D'; // D needs to be uppercase + if (character == 'v' || character == 'V' || character == 'u') character = 'U'; // side segments shared, make uppercase + if (character == 'b') character = 'B'; // B needs to be uppercase + if (character == 'c') character = 'C'; // C needs to be uppercase + } else { + if (character == 'R') character = 'r'; // R needs to be lowercase almost everywhere + } + if (position == 0) { + watch_clear_pixel(0, 15); // clear funky ninth segment + } else { + if (character == 'I') character = 'l'; // uppercase I only works in position 0 + } + + uint64_t segmap = Segment_Map[position]; + uint64_t segdata = Character_Set[character - 0x20]; + + for (int i = 0; i < 8; i++) { + uint8_t com = (segmap & 0xFF) >> 6; + if (com > 2) { + // COM3 means no segment exists; skip it. + segmap = segmap >> 8; + segdata = segdata >> 1; + continue; + } + uint8_t seg = segmap & 0x3F; + watch_clear_pixel(com, seg); + if (segdata & 1) watch_set_pixel(com, seg); + segmap = segmap >> 8; + segdata = segdata >> 1; + } + + if (character == 'T' && position == 1) watch_set_pixel(1, 12); // add descender + else if (position == 0 && (character == 'B' || character == 'D')) watch_set_pixel(0, 15); // add funky ninth segment + else if (position == 1 && (character == 'B' || character == 'D' || character == '@')) watch_set_pixel(0, 12); // add funky ninth segment +} + +void watch_display_string(char *string, uint8_t position) { + size_t i = 0; + while(string[i] != 0) { + watch_display_character(string[i], position + i); + i++; + if (position + i >= Num_Chars) break; + } + // uncomment this line to see screen output on terminal, i.e. + // FR 29 + // 11 50 23 + // note that for partial displays (positon > 0) it will only show the characters that were updated. + // printf("________\n %c%c %c%c\n%c%c %c%c %c%c\n--------\n", (position > 0) ? ' ' : string[0], (position > 1) ? ' ' : string[1 - position], (position > 2) ? ' ' : string[2 - position], (position > 3) ? ' ' : string[3 - position], (position > 4) ? ' ' : string[4 - position], (position > 5) ? ' ' : string[5 - position], (position > 6) ? ' ' : string[6 - position], (position > 7) ? ' ' : string[7 - position], (position > 8) ? ' ' : string[8 - position], (position > 9) ? ' ' : string[9 - position]); +} + +void watch_set_colon(void) { + watch_set_pixel(1, 16); +} + +void watch_clear_colon(void) { + watch_clear_pixel(1, 16); +} + +void watch_set_indicator(WatchIndicatorSegment indicator) { + uint32_t value = IndicatorSegments[indicator]; + uint8_t com = SLCD_COMNUM(value); + uint8_t seg = SLCD_SEGNUM(value); + watch_set_pixel(com, seg); +} + +void watch_clear_indicator(WatchIndicatorSegment indicator) { + uint32_t value = IndicatorSegments[indicator]; + uint8_t com = SLCD_COMNUM(value); + uint8_t seg = SLCD_SEGNUM(value); + watch_clear_pixel(com, seg); +} + +void watch_clear_all_indicators(void) { + watch_clear_pixel(2, 17); + watch_clear_pixel(2, 16); + watch_clear_pixel(0, 17); + watch_clear_pixel(0, 16); + watch_clear_pixel(1, 10); +} diff --git a/watch-library/shared/watch/watch_private_display.h b/watch-library/shared/watch/watch_private_display.h new file mode 100644 index 00000000..08597848 --- /dev/null +++ b/watch-library/shared/watch/watch_private_display.h @@ -0,0 +1,146 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_PRIVATE_DISPLAY_H_INCLUDED +#define _WATCH_PRIVATE_DISPLAY_H_INCLUDED + +#include "hpl_slcd_config.h" +#include "driver_init.h" + +static const uint8_t Character_Set[] = +{ + 0b00000000, // + 0b01100000, // ! (L in the top half for positions 4 and 6) + 0b00100010, // " + 0b01100011, // # (degree symbol, hash mark doesn't fit) + 0b00000000, // $ (unused) + 0b00000000, // % (unused) + 0b01000100, // & ("lowercase 7" for positions 4 and 6) + 0b00100000, // ' + 0b00111001, // ( + 0b00001111, // ) + 0b00000000, // * (unused) + 0b11000000, // + (only works in position 0) + 0b00000100, // , + 0b01000000, // - + 0b01000000, // . (same as -, semantically most useful) + 0b00010010, // / + 0b00111111, // 0 + 0b00000110, // 1 + 0b01011011, // 2 + 0b01001111, // 3 + 0b01100110, // 4 + 0b01101101, // 5 + 0b01111101, // 6 + 0b00000111, // 7 + 0b01111111, // 8 + 0b01101111, // 9 + 0b00000000, // : (unused) + 0b00000000, // ; (unused) + 0b01011000, // < + 0b01001000, // = + 0b01001100, // > + 0b01010011, // ? + 0b11111111, // @ (all segments on) + 0b01110111, // A + 0b01111111, // B + 0b00111001, // C + 0b00111111, // D + 0b01111001, // E + 0b01110001, // F + 0b00111101, // G + 0b01110110, // H + 0b10001001, // I (only works in position 0) + 0b00001110, // J + 0b01110101, // K + 0b00111000, // L + 0b10110111, // M (only works in position 0) + 0b00110111, // N + 0b00111111, // O + 0b01110011, // P + 0b01100111, // Q + 0b11110111, // R (only works in position 1) + 0b01101101, // S + 0b10000001, // T (only works in position 0; set (1, 12) to make it work in position 1) + 0b00111110, // U + 0b00111110, // V + 0b10111110, // W (only works in position 0) + 0b01111110, // X + 0b01101110, // Y + 0b00011011, // Z + 0b00111001, // [ + 0b00100100, // backslash + 0b00001111, // ] + 0b00100011, // ^ + 0b00001000, // _ + 0b00000010, // ` + 0b01011111, // a + 0b01111100, // b + 0b01011000, // c + 0b01011110, // d + 0b01111011, // e + 0b01110001, // f + 0b01101111, // g + 0b01110100, // h + 0b00010000, // i + 0b01000010, // j (appears as superscript to work in more positions) + 0b01110101, // k + 0b00110000, // l + 0b10110111, // m (only works in position 0) + 0b01010100, // n + 0b01011100, // o + 0b01110011, // p + 0b01100111, // q + 0b01010000, // r + 0b01101101, // s + 0b01111000, // t + 0b01100010, // u (appears in (u)pper half to work in more positions) + 0b00011100, // v (looks like u but in the lower half) + 0b10111110, // w (only works in position 0) + 0b01111110, // x + 0b01101110, // y + 0b00011011, // z + 0b00111001, // { + 0b00110000, // | + 0b00001111, // } + 0b00000001, // ~ +}; + +static const uint64_t Segment_Map[] = { + 0x4e4f0e8e8f8d4d0d, // Position 0, mode + 0xc8c4c4c8b4b4b0b, // Position 1, mode (Segments B and C shared, as are segments E and F) + 0xc049c00a49890949, // Position 2, day of month (Segments A, D, G shared; missing segment F) + 0xc048088886874707, // Position 3, day of month + 0xc053921252139352, // Position 4, clock hours (Segments A and D shared) + 0xc054511415559594, // Position 5, clock hours + 0xc057965616179716, // Position 6, clock minutes (Segments A and D shared) + 0xc041804000018a81, // Position 7, clock minutes + 0xc043420203048382, // Position 8, clock seconds + 0xc045440506468584, // Position 9, clock seconds +}; + +static const uint8_t Num_Chars = 10; + +void watch_display_character(uint8_t character, uint8_t position); + +#endif diff --git a/watch-library/shared/watch/watch_rtc.h b/watch-library/shared/watch/watch_rtc.h new file mode 100644 index 00000000..6dac63f5 --- /dev/null +++ b/watch-library/shared/watch/watch_rtc.h @@ -0,0 +1,164 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_RTC_H_INCLUDED +#define _WATCH_RTC_H_INCLUDED +////< @file watch_rtc.h + +#include "watch.h" +#include "hpl_calendar.h" + +/** @addtogroup rtc Real-Time Clock + * @brief This section covers functions related to the SAM L22's real-time clock peripheral, including + * date, time and alarm functions. + * @details The real-time clock is the only peripheral that main.c enables for you. It is the cornerstone + * of low power operation on the watch, and it is required for several key functions that we + * assume will be available, namely the wake from BACKUP mode and the callback on the ALARM button. + * It is also required for the operation of the 1 Hz tick interrupt, which you will most likely use + * to wake from STANDBY mode. + */ +/// @{ + +#define WATCH_RTC_REFERENCE_YEAR (2020) + +typedef union { + struct { + uint32_t second : 6; // 0-59 + uint32_t minute : 6; // 0-59 + uint32_t hour : 5; // 0-23 + uint32_t day : 5; // 1-31 + uint32_t month : 4; // 1-12 + uint32_t year : 6; // 0-63 (representing 2020-2083) + } unit; + uint32_t reg; // the bit-packed value as expected by the RTC peripheral's CLOCK register. +} watch_date_time; + +typedef enum watch_rtc_alarm_match { + ALARM_MATCH_DISABLED = 0, + ALARM_MATCH_SS, + ALARM_MATCH_MMSS, + ALARM_MATCH_HHMMSS, +} watch_rtc_alarm_match; + +/** @brief Called by main.c to check if the RTC is enabled. + * You may call this function, but outside of app_init, it should always return true. + */ +bool _watch_rtc_is_enabled(void); + +/** @brief Sets the date and time. + * @param date_time The date and time you wish to set, with a year value from 0-63 representing 2020-2083. + * @note The SAM L22 stores the year as six bits representing a value from 0 to 63. It treats this as a year + * offset from a reference year, which must be a leap year. Since 2020 was a leap year, and it allows + * useful dates through 2083, it is assumed that watch apps will use 2020 as the reference year; thus + * 1 means 2021, 2 means 2022, etc. **You will be responsible for handling this offset in your code**, + * if the calendar year is needed for timestamp calculation logic or display purposes. + */ +void watch_rtc_set_date_time(watch_date_time date_time); + +/** @brief Returns the date and time. + * @return A watch_date_time with the current date and time, with a year value from 0-63 representing 2020-2083. + * @see watch_rtc_set_date_time for notes about how the year is stored. + */ +watch_date_time watch_rtc_get_date_time(void); + +/** @brief Registers an alarm callback that will be called when the RTC time matches the target time, as masked + * by the provided mask. + * @param callback The function you wish to have called when the alarm fires. If this value is NULL, the alarm + * interrupt will still be enabled, but no callback function will be called. + * @param alarm_time The time that you wish to match. The date is currently ignored. + * @param mask One of the values in watch_rtc_alarm_match indicating which values to check. + * @details The alarm interrupt is a versatile tool for scheduling events in the future, especially since it can + * wake the device from all sleep modes. The key to its versatility is the mask parameter. + * Suppose we set an alarm for midnight, 00:00:00. + * * if mask is ALARM_MATCH_SS, the alarm will fire every minute when the clock ticks to seconds == 0. + * * with ALARM_MATCH_MMSS, the alarm will once an hour, at the top of each hour. + * * with ALARM_MATCH_HHMMSS, the alarm will fire at midnight every day. + * In theory the SAM L22's alarm function can match on days, months and even years, but I have not had + * success with this yet; as such, I am omitting these options for now. + */ +void watch_rtc_register_alarm_callback(ext_irq_cb_t callback, watch_date_time alarm_time, watch_rtc_alarm_match mask); + +/** @brief Disables the alarm callback. + */ +void watch_rtc_disable_alarm_callback(void); + +/** @brief Registers a "tick" callback that will be called once per second. + * @param callback The function you wish to have called when the clock ticks. If you pass in NULL, the tick + * interrupt will still be enabled, but no callback function will be called. + * @note this is equivalent to calling watch_rtc_register_periodic_callback with a frequency of 1. It can be + * disabled with either watch_rtc_disable_tick_callback() or watch_rtc_disable_periodic_callback(1), + * and will also be disabled when watch_rtc_disable_all_periodic_callbacks is called. + */ +void watch_rtc_register_tick_callback(ext_irq_cb_t callback); + +/** @brief Disables the tick callback for the given period. + */ +void watch_rtc_disable_tick_callback(void); + +/** @brief Registers a callback that will be called at a configurable period. + * @param callback The function you wish to have called at the specified period. If you pass in NULL, the periodic + * interrupt will still be enabled, but no callback function will be called. + * @param frequency The frequency of the tick in Hz. **Must be a power of 2**, from 1 to 128 inclusive. + * @note A 1 Hz tick (@see watch_rtc_register_tick_callback) is suitable for most applications, in that it gives you a + * chance to update the display once a second — an ideal update rate for a watch! If however you are displaying + * a value (such as an accelerometer output) that updates more frequently than once per second, you may want to + * tick at 16 or 32 Hz to update the screen more quickly. Just remember that the more frequent the tick, the more + * power your app will consume. Ideally you should enable the fast tick only when the user requires it (i.e. in + * response to an input event), and move back to the slow tick after some time. + * + * Also note that the RTC peripheral does not have sub-second resolution, so even if you set a 2 or 4 Hz interval, + * the system will not have any way of telling you where you are within a given second; watch_rtc_get_date_time + * will return the exact same timestamp until the second ticks over. + */ +void watch_rtc_register_periodic_callback(ext_irq_cb_t callback, uint8_t frequency); + +/** @brief Disables the tick callback for the given period. + * @param frequency The frequency of the tick you wish to disable, in Hz. **Must be a power of 2**, from 1 to 128. + */ +void watch_rtc_disable_periodic_callback(uint8_t frequency); + +/** @brief Disables all periodic callbacks, including the once-per-second tick callback. + */ +void watch_rtc_disable_all_periodic_callbacks(void); + +/** @brief Sets the system date and time. + * @param date_time A struct representing the date and time you wish to set. + */ +__attribute__((deprecated("Use watch_rtc_set_date_time function instead"))) +void watch_set_date_time(struct calendar_date_time date_time); + +/** @brief Returns the system date and time in the provided struct. + * @param date_time A pointer to a calendar_date_time struct. It will have with the correct date and time on return. + */ +__attribute__((deprecated("Use the watch_rtc_get_date_time function instead"))) +void watch_get_date_time(struct calendar_date_time *date_time); + +/** @brief Registers a "tick" callback that will be called once per second. + * @param callback The function you wish to have called when the clock ticks. If you pass in NULL, the tick + * interrupt will still be enabled, but no callback function will be called. + */ +__attribute__((deprecated("Use the watch_rtc_register_tick_callback function instead"))) +void watch_register_tick_callback(ext_irq_cb_t callback); + +/// @} +#endif diff --git a/watch-library/shared/watch/watch_slcd.h b/watch-library/shared/watch/watch_slcd.h new file mode 100644 index 00000000..3f550bb0 --- /dev/null +++ b/watch-library/shared/watch/watch_slcd.h @@ -0,0 +1,151 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_SLCD_H_INCLUDED +#define _WATCH_SLCD_H_INCLUDED +////< @file watch_slcd.h + +#include "watch.h" + +/** @addtogroup slcd Segment LCD Display + * @brief This section covers functions related to the Segment LCD display driver, which is responsible + * for displaying strings of characters and indicators on the main watch display. + * @details The segment LCD controller consumes about 3 microamperes of power with no segments on, and + * about 4 microamperes with all segments on. There is also a slight power impact associated + * with updating the screen (about 1 microampere to update at 1 Hz). For the absolute lowest + * power operation, update the display only when its contents have changed, and disable the + * SLCD peripheral when the screen is not in use. + * For a map of all common and segment pins, see segmap.html. You can + * hover over any segment in that diagram to view the common and segment pins associated with + * each segment of the display. + */ +/// @{ + +/// An enum listing the icons and indicators available on the watch. +typedef enum WatchIndicatorSegment { + WATCH_INDICATOR_SIGNAL = 0, ///< The hourly signal indicator; also useful for indicating that sensors are on. + WATCH_INDICATOR_BELL, ///< The small bell indicating that an alarm is set. + WATCH_INDICATOR_PM, ///< The PM indicator, indicating that a time is in the afternoon. + WATCH_INDICATOR_24H, ///< The 24H indicator, indicating that the watch is in a 24-hour mode. + WATCH_INDICATOR_LAP ///< The LAP indicator; the F-91W uses this in its stopwatch UI. +} WatchIndicatorSegment; + +/** @brief Enables the Segment LCD display. + * Call this before attempting to set pixels or display strings. + */ +void watch_enable_display(void); + +/** @brief Sets a pixel. Use this to manually set a pixel with a given common and segment number. + * See segmap.html. + * @param com the common pin, numbered from 0-2. + * @param seg the segment pin, numbered from 0-23. + */ +void watch_set_pixel(uint8_t com, uint8_t seg); + +/** @brief Clears a pixel. Use this to manually clear a pixel with a given common and segment number. + * See segmap.html. + * @param com the common pin, numbered from 0-2. + * @param seg the segment pin, numbered from 0-23. + */ +void watch_clear_pixel(uint8_t com, uint8_t seg); + +/** @brief Clears all segments of the display, including incicators and the colon. + */ +void watch_clear_display(void); + +/** @brief Displays a string at the given position, starting from the top left. There are ten digits. + A space in any position will clear that digit. + * @param string A null-terminated string. + * @param position The position where you wish to start displaying the string. The day of week digits + * are positions 0 and 1; the day of month digits are positions 2 and 3, and the main + * clock line occupies positions 4-9. + * @note This method does not clear the display; if for example you display a two-character string at + position 0, positions 2-9 will retain whatever state they were previously displaying. + */ +void watch_display_string(char *string, uint8_t position); + +/** @brief Turns the colon segment on. + */ +void watch_set_colon(void); + +/** @brief Turns the colon segment off. + */ +void watch_clear_colon(void); + +/** @brief Sets an indicator on the LCD. Use this to turn on one of the indicator segments. + * @param indicator One of the indicator segments from the enum. @see WatchIndicatorSegment + */ +void watch_set_indicator(WatchIndicatorSegment indicator); + +/** @brief Clears an indicator on the LCD. Use this to turn off one of the indicator segments. + * @param indicator One of the indicator segments from the enum. @see WatchIndicatorSegment + */ +void watch_clear_indicator(WatchIndicatorSegment indicator); + +/** @brief Clears all indicator segments. + * @see WatchIndicatorSegment + */ +void watch_clear_all_indicators(void); + +/** @brief Blinks a single character in position 7. Does not affect other positions. + * @details Six of the seven segments in position 7 (and only position 7) are capable of autonomous + * blinking. This blinking does not require any CPU resources, and will continue even in + * STANDBY and Sleep mode (but not Deep Sleep mode, since that mode turns off the LCD). + * @param character The character you wish to blink. + * @param duration The duration of the on/off cycle in milliseconds, from 50 to ~4250 ms. + * @note Segment B of position 7 cannot blink autonomously, so not all characters will work well. + * Supported characters for blinking: + * * Punctuation: underscore, apostrophe, comma, hyphen, equals sign, tilde (top segment only) + * * Numbers: 5, 6, ampersand (lowercase 7) + * * Letters: b, C, c, E, F, h, i, L, l, n, o, S, t + */ +void watch_start_character_blink(char character, uint32_t duration); + +/** @brief Stops and clears all blinking segments. + * @details This will stop all blinking in position 7, and clear all segments in that digit. + */ +void watch_stop_blink(void); + +/** @brief Begins a two-segment "tick-tock" animation in position 8. + * @details Six of the seven segments in position 8 (and only position 8) are capable of autonomous + * animation. This animation is very basic, and consists of moving a bit pattern forward + * or backward in a shift register whose positions map to fixed segments on the LCD. Given + * this constraint, an animation across all six segments does not make sense; so the watch + * library offers only a simple "tick/tock" in segments D and E. This animation does not + * require any CPU resources, and will continue even in STANDBY and Sleep mode (but not Deep + * Sleep mode, since that mode turns off the LCD). + * @param duration The duration of each frame in ms. 500 milliseconds produces a classic tick/tock. + */ +void watch_start_tick_animation(uint32_t duration); + +/** @brief Checks if the tick animation is currently running. + * @return true if the animation is running; false otherwise. + */ +bool watch_tick_animation_is_running(void); + +/** @brief Stops the tick/tock animation and clears all animating segments. + * @details This will stop the animation and clear all segments in position 8. + */ +void watch_stop_tick_animation(void); +/// @} +#endif diff --git a/watch-library/shared/watch/watch_uart.h b/watch-library/shared/watch/watch_uart.h new file mode 100644 index 00000000..3e98bd35 --- /dev/null +++ b/watch-library/shared/watch/watch_uart.h @@ -0,0 +1,58 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef _WATCH_UART_H_INCLUDED +#define _WATCH_UART_H_INCLUDED +////< @file watch_uart.h + +#include "watch.h" + +/** @addtogroup debug Debug UART + * @brief This section covers functions related to the debug UART, available on + * pin D1 of the 9-pin connector. + * @warning These functions were used early on in development, before the TinyUSB + * CDC was implemented. You can now print debug messages to the USB console + * using printf, rendering this bit irrelevant. These methods will likely + * be refactored out in the future, in favor of a more full-featured UART + * on the nine-pin connector. + **/ +/// @{ +/** @brief Initializes the debug UART. + * @param baud The baud rate + */ +__attribute__((deprecated("Use printf to log debug messages over USB."))) +void watch_enable_debug_uart(uint32_t baud); + +/** @brief Outputs a single character on the debug UART. + * @param c The character you wish to output. + */ +__attribute__((deprecated("Use printf to log debug messages over USB."))) +void watch_debug_putc(char c); + +/** @brief Outputs a string on the debug UART. + * @param s A null-terminated string. + */ +__attribute__((deprecated("Use printf to log debug messages over USB."))) +void watch_debug_puts(char *s); +/// @} +#endif diff --git a/watch-library/shared/watch/watch_utility.c b/watch-library/shared/watch/watch_utility.c new file mode 100644 index 00000000..835076d9 --- /dev/null +++ b/watch-library/shared/watch/watch_utility.c @@ -0,0 +1,172 @@ +/* + * MIT License + * + * Copyright (c) 2021 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include "watch_utility.h" + +const char * watch_utility_get_weekday(watch_date_time date_time) { + static const char weekdays[7][3] = {"SA", "SU", "MO", "TU", "WE", "TH", "FR"}; + date_time.unit.year += 20; + if (date_time.unit.month <= 2) { + date_time.unit.month += 12; + date_time.unit.year--; + } + return weekdays[(date_time.unit.day + 13 * (date_time.unit.month + 1) / 5 + date_time.unit.year + date_time.unit.year / 4 + 525) % 7]; +} + +uint32_t watch_utility_convert_to_unix_time(uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second, uint32_t utc_offset) { + uint16_t DAYS_SO_FAR[] = { + 0, // Jan + 31, // Feb + 59, // March + 90, // April + 120, // May + 151, // June + 181, // July + 212, // August + 243, // September + 273, // October + 304, // November + 334 // December + }; + + uint32_t year_adj = year + 4800; + uint32_t febs = year_adj - (month <= 2 ? 1 : 0); /* Februaries since base. */ + uint32_t leap_days = 1 + (febs / 4) - (febs / 100) + (febs / 400); + uint32_t days = 365 * year_adj + leap_days + DAYS_SO_FAR[month - 1] + day - 1; + days -= 2472692; /* Adjust to Unix epoch. */ + + uint32_t timestamp = days * 86400; + timestamp += hour * 3600; + timestamp += minute * 60; + timestamp += second; + timestamp -= utc_offset; + + return timestamp; +} + +uint32_t watch_utility_date_time_to_unix_time(watch_date_time date_time, uint32_t utc_offset) { + return watch_utility_convert_to_unix_time(date_time.unit.year + WATCH_RTC_REFERENCE_YEAR, date_time.unit.month, date_time.unit.day, date_time.unit.hour, date_time.unit.minute, date_time.unit.second, utc_offset); +} + +#define LEAPOCH (946684800LL + 86400*(31+29)) + +#define DAYS_PER_400Y (365*400 + 97) +#define DAYS_PER_100Y (365*100 + 24) +#define DAYS_PER_4Y (365*4 + 1) + +watch_date_time watch_utility_date_time_from_unix_time(uint32_t timestamp, uint32_t utc_offset) { + watch_date_time retval; + retval.reg = 0; + int32_t days, secs; + int32_t remdays, remsecs, remyears; + int32_t qc_cycles, c_cycles, q_cycles; + int32_t years, months; + int32_t wday, yday, leap; + static const int8_t days_in_month[] = {31,30,31,30,31,31,30,31,30,31,31,29}; + timestamp += utc_offset; + + secs = timestamp - LEAPOCH; + days = secs / 86400; + remsecs = secs % 86400; + if (remsecs < 0) { + remsecs += 86400; + days--; + } + + wday = (3+days)%7; + if (wday < 0) wday += 7; + + qc_cycles = (int)(days / DAYS_PER_400Y); + remdays = days % DAYS_PER_400Y; + if (remdays < 0) { + remdays += DAYS_PER_400Y; + qc_cycles--; + } + + c_cycles = remdays / DAYS_PER_100Y; + if (c_cycles == 4) c_cycles--; + remdays -= c_cycles * DAYS_PER_100Y; + + q_cycles = remdays / DAYS_PER_4Y; + if (q_cycles == 25) q_cycles--; + remdays -= q_cycles * DAYS_PER_4Y; + + remyears = remdays / 365; + if (remyears == 4) remyears--; + remdays -= remyears * 365; + + leap = !remyears && (q_cycles || !c_cycles); + yday = remdays + 31 + 28 + leap; + if (yday >= 365+leap) yday -= 365+leap; + + years = remyears + 4*q_cycles + 100*c_cycles + 400*qc_cycles; + + for (months=0; days_in_month[months] <= remdays; months++) + remdays -= days_in_month[months]; + + years += 2000; + + months += 2; + if (months >= 12) { + months -=12; + years++; + } + + if (years < 2020 || years > 2083) return retval; + retval.unit.year = years - WATCH_RTC_REFERENCE_YEAR; + retval.unit.month = months + 1; + retval.unit.day = remdays + 1; + + retval.unit.hour = remsecs / 3600; + retval.unit.minute = remsecs / 60 % 60; + retval.unit.second = remsecs % 60; + + return retval; +} + +watch_date_time watch_utility_date_time_convert_zone(watch_date_time date_time, uint32_t origin_utc_offset, uint32_t destination_utc_offset) { + uint32_t timestamp = watch_utility_date_time_to_unix_time(date_time, origin_utc_offset); + return watch_utility_date_time_from_unix_time(timestamp, destination_utc_offset); +} + +float watch_utility_thermistor_temperature(uint16_t value, bool highside, float b_coefficient, float nominal_temperature, float nominal_resistance, float series_resistance) { + float reading = (float)value; + + if (highside) { + reading = (1023.0 * series_resistance) / (reading / 64.0); + reading -= series_resistance; + } else { + reading = series_resistance / (65535.0 / value - 1.0); + } + + reading = reading / nominal_resistance; + reading = log(reading); + reading /= b_coefficient; + reading += 1.0 / (nominal_temperature + 273.15); + reading = 1.0 / reading; + reading -= 273.15; + + return reading; +} diff --git a/watch-library/shared/watch/watch_utility.h b/watch-library/shared/watch/watch_utility.h new file mode 100644 index 00000000..66af6ed5 --- /dev/null +++ b/watch-library/shared/watch/watch_utility.h @@ -0,0 +1,100 @@ +/* + * MIT License + * + * Copyright (c) 2021 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef _WATCH_UTILITY_H_INCLUDED +#define _WATCH_UTILITY_H_INCLUDED +////< @file watch_utility.h + +#include "watch.h" + +/** @addtogroup utility Utility Functions + * @brief This section covers various useful functions that don't fit anywhere else. + **/ +/// @{ +/** @brief Returns a two-letter weekday for the given timestamp, suitable for display + * in positions 0-1 of the watch face + * @param date_time The watch_date_time whose weekday you want. + */ +const char * watch_utility_get_weekday(watch_date_time date_time); + +/** @brief Returns the UNIX time (seconds since 1970) for a given date/time in UTC. + * @param date_time The watch_date_time that you wish to convert. + * @param year The year of the date you wish to convert. + * @param month The month of the date you wish to convert. + * @param day The day of the date you wish to convert. + * @param hour The hour of the date you wish to convert. + * @param minute The minute of the date you wish to convert. + * @param second The second of the date you wish to convert. + * @param utc_offset The number of seconds that date_time is offset from UTC, or 0 if the time is UTC. + * @return A UNIX timestamp for the given date/time and UTC offset. + * @note Implemented by Wesley Ellis (tahnok) and based on BSD-licensed code by Josh Haberman: + * https://blog.reverberate.org/2020/05/12/optimizing-date-algorithms.html + */ +uint32_t watch_utility_convert_to_unix_time(uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second, uint32_t utc_offset); + +/** @brief Returns the UNIX time (seconds since 1970) for a given watch_date_time struct. + * @param date_time The watch_date_time that you wish to convert. + * @param utc_offset The number of seconds that date_time is offset from UTC, or 0 if the time is UTC. + * @return A UNIX timestamp for the given watch_date_time and UTC offset. + */ +uint32_t watch_utility_date_time_to_unix_time(watch_date_time date_time, uint32_t utc_offset); + +/** @brief Returns the UNIX time (seconds since 1970) for a given watch_date_time struct. + * @param timestamp The UNIX timestamp that you wish to convert. + * @param utc_offset The number of seconds that you wish date_time to be offset from UTC. + * @return A watch_date_time for the given UNIX timestamp and UTC offset, or if outside the range that + * watch_date_time can represent, a watch_date_time with all fields set to 0. + * @note Adapted from MIT-licensed code from musl, Copyright © 2005-2014 Rich Felker, et al.: + * https://github.com/esmil/musl/blob/1cc81f5cb0df2b66a795ff0c26d7bbc4d16e13c6/src/time/__secs_to_tm.c + */ +watch_date_time watch_utility_date_time_from_unix_time(uint32_t timestamp, uint32_t utc_offset); + +/** @brief Converts a time from a given time zone to another time zone. + * @param date_time The watch_date_time that you wish to convert + * @param origin_utc_offset The number of seconds from UTC in the origin time zone + * @param destination_utc_offset The number of seconds from UTC in the destination time zone + * @return A watch_date_time for the given UNIX timestamp and UTC offset, or if outside the range that + * watch_date_time can represent, a watch_date_time with all fields set to 0. + * @note Adapted from MIT-licensed code from musl, Copyright © 2005-2014 Rich Felker, et al.: + * https://github.com/esmil/musl/blob/1cc81f5cb0df2b66a795ff0c26d7bbc4d16e13c6/src/time/__secs_to_tm.c + */ +watch_date_time watch_utility_date_time_convert_zone(watch_date_time date_time, uint32_t origin_utc_offset, uint32_t destination_utc_offset); + +/** @brief Returns a temperature in degrees Celsius for a given thermistor voltage divider circuit. + * @param value The raw analog reading from the thermistor pin (0-65535) + * @param highside True if the thermistor is connected to VCC and the series resistor is connected + * to GND; false if the thermistor is connected to GND and the series resistor is + * connected to VCC. + * @param b_coefficient From your thermistor's data sheet, the B25/85 coefficient. A typical value + * will be between 2000 and 5000. + * @param nominal_temperature From your thermistor's data sheet, the temperature (in Celsius) at + * which the thermistor's resistance is at its nominal value. + * @param nominal_resistance The thermistor's resistance at the nominal temperature. + * @param series_resistance The value of the other resistor in the voltage divider. + * @note Ported from Adafruit's MIT-licensed CircuitPython thermistor code, (c) 2017 Scott Shawcroft: + * https://github.com/adafruit/Adafruit_CircuitPython_Thermistor/blob/main/adafruit_thermistor.py + */ +float watch_utility_thermistor_temperature(uint16_t value, bool highside, float b_coefficient, float nominal_temperature, float nominal_resistance, float series_resistance); + +#endif diff --git a/watch-library/simulator/hpl/port/hpl_gpio_base.h b/watch-library/simulator/hpl/port/hpl_gpio_base.h new file mode 100644 index 00000000..c8fd6e0e --- /dev/null +++ b/watch-library/simulator/hpl/port/hpl_gpio_base.h @@ -0,0 +1,87 @@ + +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp = 0; + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ +} + +static inline void _port_event_init() +{ +} diff --git a/watch-library/simulator/main.c b/watch-library/simulator/main.c new file mode 100644 index 00000000..5596bf82 --- /dev/null +++ b/watch-library/simulator/main.c @@ -0,0 +1,70 @@ +/* + * MIT License + * + * Copyright (c) 2022 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include "watch.h" + +#include +#include + +static bool sleeping = true; + +static EM_BOOL main_loop(double time, void *userData) { + if (sleeping) { + sleeping = false; + app_wake_from_standby(); + } + + bool can_sleep = app_loop(); + + if (can_sleep) { + app_prepare_for_standby(); + sleeping = true; + return EM_FALSE; + } + + return EM_TRUE; +} + +// make compiler happy +void resume_main_loop(void); + +EMSCRIPTEN_KEEPALIVE +void resume_main_loop(void) { + if (sleeping) { + emscripten_request_animation_frame_loop(main_loop, NULL); + } +} + +int main(void) { + printf("Hello, world!\n"); + + app_init(); + _watch_init(); + app_setup(); + + resume_main_loop(); + + return 0; +} diff --git a/watch-library/simulator/shell.html b/watch-library/simulator/shell.html new file mode 100644 index 00000000..1a4de984 --- /dev/null +++ b/watch-library/simulator/shell.html @@ -0,0 +1,368 @@ + + + + + Sensor Watch Emulator + + + + + + +
+

Sensor Watch Emulator

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Original F-91W SVG is © 2020 Alexis Philip, and is used here under the terms of the MIT license.

+
+ + + + +{{{ SCRIPT }}} + + + diff --git a/watch-library/simulator/watch/watch.c b/watch-library/simulator/watch/watch.c new file mode 100644 index 00000000..2b14d0ab --- /dev/null +++ b/watch-library/simulator/watch/watch.c @@ -0,0 +1,9 @@ +#include "watch.h" + +bool watch_is_battery_low(void) { + return false; +} + +bool watch_is_buzzer_or_led_enabled(void) { + return false; +} diff --git a/watch-library/simulator/watch/watch_adc.c b/watch-library/simulator/watch/watch_adc.c new file mode 100644 index 00000000..364e2119 --- /dev/null +++ b/watch-library/simulator/watch/watch_adc.c @@ -0,0 +1,48 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_adc.h" + +void watch_enable_adc(void) {} + +void watch_enable_analog_input(const uint8_t pin) {} + +uint16_t watch_get_analog_pin_level(const uint8_t pin) { + return 0; +} + +void watch_set_analog_num_samples(uint16_t samples) {} + +void watch_set_analog_sampling_length(uint8_t cycles) {} + +void watch_set_analog_reference_voltage(watch_adc_reference_voltage reference) {} + +uint16_t watch_get_vcc_voltage(void) { + // TODO: (a2) hook to UI + return 3000; +} + +inline void watch_disable_analog_input(const uint8_t pin) {} + +inline void watch_disable_adc(void) {} diff --git a/watch-library/simulator/watch/watch_buzzer.c b/watch-library/simulator/watch/watch_buzzer.c new file mode 100644 index 00000000..f19e1928 --- /dev/null +++ b/watch-library/simulator/watch/watch_buzzer.c @@ -0,0 +1,60 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_buzzer.h" + +inline void watch_enable_buzzer(void) { + // TODO: (a2) hook to UI +} +inline void watch_set_buzzer_period(uint32_t period) { + // TODO: (a2) hook to UI +} + +void watch_disable_buzzer(void) { + _watch_disable_tcc(); +} + +inline void watch_set_buzzer_on(void) { + // TODO: (a2) hook to UI +} + +inline void watch_set_buzzer_off(void) { + // TODO: (a2) hook to UI +} + +// note: the buzzer uses a 1 MHz clock. these values were determined by dividing 1,000,000 by the target frequency. +// i.e. for a 440 Hz tone (A4 on the piano), 1MHz/440Hz = 2273 +const uint16_t NotePeriods[108] = {0}; + +void watch_buzzer_play_note(BuzzerNote note, uint16_t duration_ms) { + if (note == BUZZER_NOTE_REST) { + watch_set_buzzer_off(); + } // else { + // hri_tcc_write_PERBUF_reg(TCC0, NotePeriods[note]); + // hri_tcc_write_CCBUF_reg(TCC0, WATCH_BUZZER_TCC_CHANNEL, NotePeriods[note] / 2); + // watch_set_buzzer_on(); + // } + // delay_ms(duration_ms); + // watch_set_buzzer_off(); +} diff --git a/watch-library/simulator/watch/watch_deepsleep.c b/watch-library/simulator/watch/watch_deepsleep.c new file mode 100644 index 00000000..9f409570 --- /dev/null +++ b/watch-library/simulator/watch/watch_deepsleep.c @@ -0,0 +1,99 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_extint.h" + +// this warning only appears when you `make BOARD=OSO-SWAT-A1-02`. it's annoying, +// but i'd rather have it warn us at build-time than fail silently at run-time. +// besides, no one but me really has any of these boards anyway. +#if BTN_ALARM != GPIO(GPIO_PORTA, 2) +#warning This board revision does not support external wake on BTN_ALARM, so watch_register_extwake_callback will not work with it. Use watch_register_interrupt_callback instead. +#endif + +static uint32_t watch_backup_data[8]; + +void watch_register_extwake_callback(uint8_t pin, ext_irq_cb_t callback, bool level) { + if (pin == BTN_ALARM) { + watch_register_interrupt_callback(pin, callback, level ? INTERRUPT_TRIGGER_RISING : INTERRUPT_TRIGGER_FALLING); + } +} + +void watch_disable_extwake_interrupt(uint8_t pin) { + if (pin == BTN_ALARM) { + watch_register_interrupt_callback(pin, NULL, INTERRUPT_TRIGGER_NONE); + } +} + +void watch_store_backup_data(uint32_t data, uint8_t reg) { + if (reg < 8) { + watch_backup_data[reg] = data; + } +} + +uint32_t watch_get_backup_data(uint8_t reg) { + if (reg < 8) { + return watch_backup_data[reg]; + } + + return 0; +} + +void watch_enter_sleep_mode(void) { + // TODO: (a2) hook to UI + + // enter standby (4); we basically hang out here until an interrupt wakes us. + // sleep(4); + + // call app_setup so the app can re-enable everything we disabled. + app_setup(); + + // and call app_wake_from_standby (since main won't have a chance to do it) + app_wake_from_standby(); +} + +void watch_enter_deep_sleep_mode(void) { + // identical to sleep mode except we disable the LCD first. + // TODO: (a2) hook to UI + + watch_enter_sleep_mode(); +} + +void watch_enter_backup_mode(void) { + // TODO: (a2) hook to UI + + // go into backup sleep mode (5). when we exit, the reset controller will take over. + // sleep(5); +} + +// deprecated +void watch_enter_shallow_sleep(bool display_on) { + if (display_on) watch_enter_sleep_mode(); + else watch_enter_deep_sleep_mode(); +} + +// deprecated +void watch_enter_deep_sleep(void) { + watch_register_extwake_callback(BTN_ALARM, NULL, true); + watch_enter_backup_mode(); +} diff --git a/watch-library/simulator/watch/watch_extint.c b/watch-library/simulator/watch/watch_extint.c new file mode 100644 index 00000000..d37059bf --- /dev/null +++ b/watch-library/simulator/watch/watch_extint.c @@ -0,0 +1,191 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_extint.h" + +#include +#include + +static bool output_focused = false; +static bool external_interrupt_enabled = false; +static bool button_callbacks_installed = false; +static ext_irq_cb_t external_interrupt_mode_callback = NULL; +static watch_interrupt_trigger external_interrupt_mode_trigger = INTERRUPT_TRIGGER_NONE; +static ext_irq_cb_t external_interrupt_light_callback = NULL; +static watch_interrupt_trigger external_interrupt_light_trigger = INTERRUPT_TRIGGER_NONE; +static ext_irq_cb_t external_interrupt_alarm_callback = NULL; +static watch_interrupt_trigger external_interrupt_alarm_trigger = INTERRUPT_TRIGGER_NONE; + +#define BTN_ID_ALARM 3 +#define BTN_ID_LIGHT 1 +#define BTN_ID_MODE 2 +static const uint8_t BTN_IDS[] = { BTN_ID_ALARM, BTN_ID_LIGHT, BTN_ID_MODE }; +static void watch_invoke_interrupt_callback(const uint8_t button_id, watch_interrupt_trigger trigger); + +static EM_BOOL watch_invoke_key_callback(int eventType, const EmscriptenKeyboardEvent *keyEvent, void *userData) { + if (output_focused || keyEvent->repeat) return EM_FALSE; + + const char *key = keyEvent->key; + if (key[1] != 0) return EM_FALSE; + + uint8_t button_id; + switch (key[0]) { + case 'A': + case 'a': + button_id = BTN_ID_ALARM; + break; + case 'L': + case 'l': + button_id = BTN_ID_LIGHT; + break; + case 'M': + case 'm': + button_id = BTN_ID_MODE; + break; + default: + return EM_FALSE; + } + + watch_interrupt_trigger trigger = eventType == EMSCRIPTEN_EVENT_KEYDOWN ? INTERRUPT_TRIGGER_RISING : INTERRUPT_TRIGGER_FALLING; + watch_invoke_interrupt_callback(button_id, trigger); + return EM_TRUE; +} + +static EM_BOOL watch_invoke_mouse_callback(int eventType, const EmscriptenMouseEvent *mouseEvent, void *userData) { + if (eventType == EMSCRIPTEN_EVENT_MOUSEOUT && mouseEvent->buttons == 0) return EM_FALSE; + uint8_t button_id = *(const char *)userData; + watch_interrupt_trigger trigger = eventType == EMSCRIPTEN_EVENT_MOUSEDOWN ? INTERRUPT_TRIGGER_RISING : INTERRUPT_TRIGGER_FALLING; + watch_invoke_interrupt_callback(button_id, trigger); + return EM_TRUE; +} + +static EM_BOOL watch_invoke_touch_callback(int eventType, const EmscriptenTouchEvent *touchEvent, void *userData) { + uint8_t button_id = *(const char *)userData; + watch_interrupt_trigger trigger = eventType == EMSCRIPTEN_EVENT_TOUCHSTART ? INTERRUPT_TRIGGER_RISING : INTERRUPT_TRIGGER_FALLING; + watch_invoke_interrupt_callback(button_id, trigger); + return EM_TRUE; +} + +static EM_BOOL watch_invoke_focus_callback(int eventType, const EmscriptenFocusEvent *focusEvent, void *userData) { + output_focused = eventType == EMSCRIPTEN_EVENT_FOCUS; + return EM_TRUE; +} + +static void watch_install_button_callbacks(void) { + emscripten_set_keydown_callback(EMSCRIPTEN_EVENT_TARGET_DOCUMENT, NULL, EM_FALSE, watch_invoke_key_callback); + emscripten_set_keyup_callback(EMSCRIPTEN_EVENT_TARGET_DOCUMENT, NULL, EM_FALSE, watch_invoke_key_callback); + + const char *target_output = "#output"; + emscripten_set_focus_callback(target_output, NULL, EM_FALSE, watch_invoke_focus_callback); + emscripten_set_blur_callback(target_output, NULL, EM_FALSE, watch_invoke_focus_callback); + + for (int i = 0, count = sizeof(BTN_IDS) / sizeof(BTN_IDS[0]); i < count; i++) { + char target[] = "#btn_"; + target[4] = BTN_IDS[i] + '0'; + + emscripten_set_mousedown_callback(target, (void *)&BTN_IDS[i], EM_FALSE, watch_invoke_mouse_callback); + emscripten_set_mouseup_callback(target, (void *)&BTN_IDS[i], EM_FALSE, watch_invoke_mouse_callback); + emscripten_set_mouseout_callback(target, (void *)&BTN_IDS[i], EM_FALSE, watch_invoke_mouse_callback); + + emscripten_set_touchstart_callback(target, (void *)&BTN_IDS[i], EM_FALSE, watch_invoke_touch_callback); + emscripten_set_touchend_callback(target, (void *)&BTN_IDS[i], EM_FALSE, watch_invoke_touch_callback); + } +} + +void watch_enable_external_interrupts(void) { + external_interrupt_enabled = true; + + if (!button_callbacks_installed) { + watch_install_button_callbacks(); + button_callbacks_installed = true; + } +} + +void watch_disable_external_interrupts(void) { + external_interrupt_enabled = false; +} + +static void watch_invoke_interrupt_callback(const uint8_t button_id, watch_interrupt_trigger event) { + if (!external_interrupt_enabled) return; + + ext_irq_cb_t callback; + watch_interrupt_trigger trigger; + uint8_t pin; + switch (button_id) { + case BTN_ID_MODE: + pin = BTN_MODE; + callback = external_interrupt_mode_callback; + trigger = external_interrupt_mode_trigger; + break; + case BTN_ID_LIGHT: + pin = BTN_LIGHT; + callback = external_interrupt_light_callback; + trigger = external_interrupt_light_trigger; + break; + case BTN_ID_ALARM: + pin = BTN_ALARM; + callback = external_interrupt_alarm_callback; + trigger = external_interrupt_alarm_trigger; + break; + default: + return; + } + + const bool level = (event & INTERRUPT_TRIGGER_RISING) != 0; + EM_ASM({ + const classList = document.querySelector('#btn' + $0).classList; + const highlight = 'highlight'; + $1 ? classList.add(highlight) : classList.remove(highlight); + }, button_id, level); + + watch_set_pin_level(pin, level); + + if (callback && (event & trigger) != 0) { + callback(); + + void resume_main_loop(void); + resume_main_loop(); + } +} + +void watch_register_interrupt_callback(const uint8_t pin, ext_irq_cb_t callback, watch_interrupt_trigger trigger) { + if (pin == BTN_MODE) { + external_interrupt_mode_callback = callback; + external_interrupt_mode_trigger = trigger; + } else if (pin == BTN_LIGHT) { + external_interrupt_light_callback = callback; + external_interrupt_light_trigger = trigger; + } else if (pin == BTN_ALARM) { + external_interrupt_alarm_callback = callback; + external_interrupt_alarm_trigger = trigger; + } +} + +void watch_register_button_callback(const uint8_t pin, ext_irq_cb_t callback) { + watch_register_interrupt_callback(pin, callback, INTERRUPT_TRIGGER_RISING); +} + +void watch_enable_buttons(void) { + watch_enable_external_interrupts(); +} diff --git a/watch-library/simulator/watch/watch_gpio.c b/watch-library/simulator/watch/watch_gpio.c new file mode 100644 index 00000000..4bea2c11 --- /dev/null +++ b/watch-library/simulator/watch/watch_gpio.c @@ -0,0 +1,47 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_gpio.h" + +static bool pin_levels[UINT8_MAX]; + +void watch_enable_digital_input(const uint8_t pin) {} + +void watch_disable_digital_input(const uint8_t pin) {} + +void watch_enable_pull_up(const uint8_t pin) {} + +void watch_enable_pull_down(const uint8_t pin) {} + +bool watch_get_pin_level(const uint8_t pin) { + return pin_levels[pin]; +} + +void watch_enable_digital_output(const uint8_t pin) {} + +void watch_disable_digital_output(const uint8_t pin) {} + +void watch_set_pin_level(const uint8_t pin, const bool level) { + pin_levels[pin] = level; +} diff --git a/watch-library/simulator/watch/watch_i2c.c b/watch-library/simulator/watch/watch_i2c.c new file mode 100644 index 00000000..09339888 --- /dev/null +++ b/watch-library/simulator/watch/watch_i2c.c @@ -0,0 +1,51 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_i2c.h" + +void watch_enable_i2c(void) {} + +void watch_disable_i2c(void) {} + +void watch_i2c_send(int16_t addr, uint8_t *buf, uint16_t length) {} + +void watch_i2c_receive(int16_t addr, uint8_t *buf, uint16_t length) {} + +void watch_i2c_write8(int16_t addr, uint8_t reg, uint8_t data) {} + +uint8_t watch_i2c_read8(int16_t addr, uint8_t reg) { + return 0; +} + +uint16_t watch_i2c_read16(int16_t addr, uint8_t reg) { + return 0; +} + +uint32_t watch_i2c_read24(int16_t addr, uint8_t reg) { + return 0; +} + +uint32_t watch_i2c_read32(int16_t addr, uint8_t reg) { + return 0; +} diff --git a/watch-library/simulator/watch/watch_led.c b/watch-library/simulator/watch/watch_led.c new file mode 100644 index 00000000..173f1b08 --- /dev/null +++ b/watch-library/simulator/watch/watch_led.c @@ -0,0 +1,63 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_led.h" + +#include + +void watch_enable_leds(void) {} + +void watch_disable_leds(void) {} + +void watch_enable_led(bool unused) { + (void)unused; + watch_enable_leds(); +} + +void watch_disable_led(bool unused) { + (void)unused; + watch_disable_leds(); +} + +void watch_set_led_color(uint8_t red, uint8_t green) { + EM_ASM({ + document.getElementById('light').style.opacity = $1 / 255; + }, red, green); +} + +void watch_set_led_red(void) { + watch_set_led_color(255, 0); +} + +void watch_set_led_green(void) { + watch_set_led_color(0, 255); +} + +void watch_set_led_yellow(void) { + watch_set_led_color(255, 255); +} + +void watch_set_led_off(void) { + watch_set_led_color(0, 0); +} diff --git a/watch-library/simulator/watch/watch_private.c b/watch-library/simulator/watch/watch_private.c new file mode 100644 index 00000000..b852893b --- /dev/null +++ b/watch-library/simulator/watch/watch_private.c @@ -0,0 +1,78 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_private.h" +#include "watch_utility.h" +#include + +void _watch_init(void) { + // External wake depends on RTC; calendar is a required module. + _watch_rtc_init(); +} + +// this function is called by arc4random to get entropy for random number generation. +// let's use the SAM L22's true random number generator to seed the PRNG! +int getentropy(void *buf, size_t buflen); +int getentropy(void *buf, size_t buflen) { + // TODO: (a2) hook to RNG + return 0; +} + +int _gettimeofday(struct timeval *tv, void *tzvp); +int _gettimeofday(struct timeval *tv, void *tzvp) { + (void)tzvp; + watch_date_time date_time = watch_rtc_get_date_time(); + + // FIXME: this assumes the system time is UTC! Will break for any other time zone. + tv->tv_sec = watch_utility_date_time_to_unix_time(date_time, 0); + tv->tv_usec = 0; + + return 0; +} + +void _watch_enable_tcc(void) {} + +void _watch_disable_tcc(void) {} + +void _watch_enable_usb(void) {} + +// this function ends up getting called by printf to log stuff to the USB console. +int _write(int file, char *ptr, int len) { + // TODO: (a2) hook to UI + return 0; +} + +// this method could be overridden to read stuff from the USB console? but no need rn. +int _read(void) { + return 0; +} + +// Alternate function that outputs to the debug UART. useful for debugging USB issues. +// int _write(int file, char *ptr, int len) { +// (void)file; +// int pos = 0; +// while(pos < len) watch_debug_putc(ptr[pos++]); + +// return 0; +// } diff --git a/watch-library/simulator/watch/watch_rtc.c b/watch-library/simulator/watch/watch_rtc.c new file mode 100644 index 00000000..573c0ff2 --- /dev/null +++ b/watch-library/simulator/watch/watch_rtc.c @@ -0,0 +1,223 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_rtc.h" + +#include +#include + +static double time_offset = 0; +static long tick_callbacks[8]; + +static long alarm_interval_id; +static long alarm_timeout_id; +static double alarm_interval; +ext_irq_cb_t alarm_callback; +ext_irq_cb_t btn_alarm_callback; +ext_irq_cb_t a2_callback; +ext_irq_cb_t a4_callback; + +bool _watch_rtc_is_enabled(void) { + return true; +} + +void _watch_rtc_init(void) { +} + +void watch_rtc_set_date_time(watch_date_time date_time) { + time_offset = EM_ASM_DOUBLE({ + const year = 2020 + (($0 >> 26) & 0x3f); + const month = ($0 >> 22) & 0xf; + const day = ($0 >> 17) & 0x1f; + const hour = ($0 >> 12) & 0x1f; + const minute = ($0 >> 6) & 0x3f; + const second = $0 & 0x3f; + const date = new Date(year, month - 1, day, hour, minute, second); + return date - Date.now(); + }, date_time.reg); +} + +watch_date_time watch_rtc_get_date_time(void) { + watch_date_time retval; + retval.reg = EM_ASM_INT({ + const date = new Date(Date.now() + $0); + return date.getSeconds() | + (date.getMinutes() << 6) | + (date.getHours() << 12) | + (date.getDate() << 17) | + ((date.getMonth() + 1) << 22) | + ((date.getFullYear() - 2020) << 26); + }, time_offset); + return retval; +} + +void watch_rtc_register_tick_callback(ext_irq_cb_t callback) { + watch_rtc_register_periodic_callback(callback, 1); +} + +void watch_rtc_disable_tick_callback(void) { + watch_rtc_disable_periodic_callback(1); +} + +static void watch_invoke_periodic_callback(void *userData) { + ext_irq_cb_t callback = userData; + callback(); + + void resume_main_loop(void); + resume_main_loop(); +} + +void watch_rtc_register_periodic_callback(ext_irq_cb_t callback, uint8_t frequency) { + // we told them, it has to be a power of 2. + if (__builtin_popcount(frequency) != 1) return; + + // this left-justifies the period in a 32-bit integer. + uint32_t tmp = frequency << 24; + // now we can count the leading zeroes to get the value we need. + // 0x01 (1 Hz) will have 7 leading zeros for PER7. 0xF0 (128 Hz) will have no leading zeroes for PER0. + uint8_t per_n = __builtin_clz(tmp); + + // this also maps nicely to an index for our list of tick callbacks. + double interval = 1000 / frequency; // in msec + tick_callbacks[per_n] = emscripten_set_interval(watch_invoke_periodic_callback, interval, (void *)callback); +} + +void watch_rtc_disable_periodic_callback(uint8_t frequency) { + if (__builtin_popcount(frequency) != 1) return; + uint8_t per_n = __builtin_clz(frequency << 24); + emscripten_clear_interval(tick_callbacks[per_n]); + tick_callbacks[per_n] = 0; +} + +void watch_rtc_disable_all_periodic_callbacks(void) { + for (int i = 0; i < 8; i++) { + if (tick_callbacks[i] != 0) { + emscripten_clear_interval(tick_callbacks[i]); + tick_callbacks[i] = 0; + } + } +} + +static void watch_invoke_alarm_interval_callback(void *userData) { + (void)userData; + if (alarm_callback) alarm_callback(); +} + +static void watch_invoke_alarm_callback(void *userData) { + (void)userData; + if (alarm_callback) alarm_callback(); + alarm_interval_id = emscripten_set_interval(watch_invoke_alarm_interval_callback, alarm_interval, NULL); +} + +void watch_rtc_register_alarm_callback(ext_irq_cb_t callback, watch_date_time alarm_time, watch_rtc_alarm_match mask) { + watch_rtc_disable_alarm_callback(); + + switch (mask) { + case ALARM_MATCH_DISABLED: + return; + case ALARM_MATCH_SS: + alarm_interval = 60 * 1000; + break; + case ALARM_MATCH_MMSS: + alarm_interval = 60 * 60 * 1000; + break; + case ALARM_MATCH_HHMMSS: + alarm_interval = 60 * 60 * 60 * 1000; + break; + } + + double timeout = EM_ASM_DOUBLE({ + const now = Date.now(); + const date = new Date(now + $0); + + const hour = ($1 >> 12) & 0x1f; + const minute = ($1 >> 6) & 0x3f; + const second = $1 & 0x3f; + + if ($2 == 1) { // SS + if (second < date.getSeconds()) date.setMinutes(date.getMinutes() + 1); + date.setSeconds(second); + } else if ($2 == 2) { // MMSS + if (second < date.getSeconds()) date.setMinutes(date.getMinutes() + 1); + if (minute < date.getMinutes()) date.setHours(date.getHours() + 1); + date.setMinutes(minute, second); + } else if ($2 == 3) { // HHMMSS + if (second < date.getSeconds()) date.setMinutes(date.getMinutes() + 1); + if (minute < date.getMinutes()) date.setHours(date.getHours() + 1); + if (hour < date.getHours()) date.setDate(date.getDate() + 1); + date.setHours(hour, minute, second); + } else { + throw 'Invalid alarm match mask'; + } + + return date - now; + }, time_offset, alarm_time.reg, mask); + + alarm_callback = callback; + alarm_timeout_id = emscripten_set_timeout(watch_invoke_alarm_callback, timeout, NULL); +} + +void watch_rtc_disable_alarm_callback(void) { + alarm_callback = NULL; + alarm_interval = 0; + + if (alarm_timeout_id) { + emscripten_clear_timeout(alarm_timeout_id); + alarm_timeout_id = 0; + } + + if (alarm_interval_id) { + emscripten_clear_interval(alarm_interval_id); + alarm_interval_id = 0; + } +} + +/////////////////////// +// Deprecated functions + +void watch_set_date_time(struct calendar_date_time date_time) { + watch_date_time val; + val.unit.second = date_time.time.sec; + val.unit.minute = date_time.time.min; + val.unit.hour = date_time.time.hour; + val.unit.day = date_time.date.day; + val.unit.month = date_time.date.month; + val.unit.year = date_time.date.year - WATCH_RTC_REFERENCE_YEAR; + watch_rtc_set_date_time(val); +} + +void watch_get_date_time(struct calendar_date_time *date_time) { + if (date_time == NULL) return; + watch_date_time val = watch_rtc_get_date_time(); + date_time->time.sec = val.unit.second; + date_time->time.min = val.unit.minute; + date_time->time.hour = val.unit.hour; + date_time->date.day = val.unit.day; + date_time->date.month = val.unit.month; + date_time->date.year = val.unit.year + WATCH_RTC_REFERENCE_YEAR; +} + +void watch_register_tick_callback(ext_irq_cb_t callback) { + watch_rtc_register_tick_callback(callback); +} diff --git a/watch-library/simulator/watch/watch_slcd.c b/watch-library/simulator/watch/watch_slcd.c new file mode 100644 index 00000000..2af96847 --- /dev/null +++ b/watch-library/simulator/watch/watch_slcd.c @@ -0,0 +1,115 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "watch_slcd.h" +#include "watch_private_display.h" +#include "hpl_slcd_config.h" + +#include +#include + +////////////////////////////////////////////////////////////////////////////////////////// +// Segmented Display + +static char blink_character; +static bool blink_state; +static long blink_interval_id; +static bool tick_state; +static long tick_interval_id; + +void watch_enable_display(void) { + watch_clear_display(); +} + +void watch_set_pixel(uint8_t com, uint8_t seg) { + EM_ASM({ + document.querySelectorAll("[data-com='" + $0 + "'][data-seg='" + $1 + "']") + .forEach((e) => e.style.opacity = 1); + }, com, seg); +} + +void watch_clear_pixel(uint8_t com, uint8_t seg) { + EM_ASM({ + document.querySelectorAll("[data-com='" + $0 + "'][data-seg='" + $1 + "']") + .forEach((e) => e.style.opacity = 0); + }, com, seg); +} + +void watch_clear_display(void) { + EM_ASM({ + document.querySelectorAll("[data-com][data-seg]") + .forEach((e) => e.style.opacity = 0); + }); +} + +static void watch_invoke_blink_callback(void *userData) { + blink_state = !blink_state; + watch_display_character(blink_state ? blink_character : ' ', 7); + watch_clear_pixel(2, 10); // clear segment B of position 7 since it can't blink +} + +void watch_start_character_blink(char character, uint32_t duration) { + watch_display_character(character, 7); + watch_clear_pixel(2, 10); // clear segment B of position 7 since it can't blink + + blink_state = true; + blink_character = character; + blink_interval_id = emscripten_set_interval(watch_invoke_blink_callback, (double)duration, NULL); +} + +void watch_stop_blink(void) { + emscripten_clear_timeout(blink_interval_id); + blink_interval_id = 0; + blink_state = false; +} + +static void watch_invoke_tick_callback(void *userData) { + tick_state = !tick_state; + if (tick_state) { + watch_clear_pixel(0, 2); + watch_set_pixel(0, 3); + } else { + watch_clear_pixel(0, 3); + watch_set_pixel(0, 2); + } +} + +void watch_start_tick_animation(uint32_t duration) { + watch_display_character(' ', 8); + + tick_state = true; + tick_interval_id = emscripten_set_interval(watch_invoke_tick_callback, (double)duration, NULL); +} + +bool watch_tick_animation_is_running(void) { + return tick_interval_id != 0; +} + +void watch_stop_tick_animation(void) { + emscripten_clear_timeout(tick_interval_id); + tick_interval_id = 0; + tick_state = false; + + watch_display_character(' ', 8); +} diff --git a/watch-library/simulator/watch/watch_uart.c b/watch-library/simulator/watch/watch_uart.c new file mode 100644 index 00000000..e37fabff --- /dev/null +++ b/watch-library/simulator/watch/watch_uart.c @@ -0,0 +1,65 @@ +/* + * MIT License + * + * Copyright (c) 2020 Joey Castillo + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /* + * UART methods are Copyright (c) 2014-2017, Alex Taradov + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "watch_uart.h" +#include "peripheral_clk_config.h" + +void watch_enable_debug_uart(uint32_t baud) {} + +void watch_debug_putc(char c) {} + +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wdeprecated-declarations" +void watch_debug_puts(char *s) { + while (*s) watch_debug_putc(*s++); +} +#pragma GCC diagnostic pop diff --git a/watch-library/startup_saml22.c b/watch-library/startup_saml22.c deleted file mode 100755 index f4982564..00000000 --- a/watch-library/startup_saml22.c +++ /dev/null @@ -1,225 +0,0 @@ -/** - * \file - * - * \brief gcc starttup file for SAML22 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "saml22.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M0+ core handlers */ -void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSC32KCTRL, OSCCTRL, PAC, PM, SUPC, TAL */ -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_USB -void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_SERCOM3 -void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_SERCOM4 -void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_SERCOM5 -void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_PTC -void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -void SLCD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_AES -void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TRNG -void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void*) (&_estack), - - .pfnReset_Handler = (void*) Reset_Handler, - .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, - .pfnHardFault_Handler = (void*) HardFault_Handler, - .pvReservedM12 = (void*) (0UL), /* Reserved */ - .pvReservedM11 = (void*) (0UL), /* Reserved */ - .pvReservedM10 = (void*) (0UL), /* Reserved */ - .pvReservedM9 = (void*) (0UL), /* Reserved */ - .pvReservedM8 = (void*) (0UL), /* Reserved */ - .pvReservedM7 = (void*) (0UL), /* Reserved */ - .pvReservedM6 = (void*) (0UL), /* Reserved */ - .pfnSVCall_Handler = (void*) SVCall_Handler, - .pvReservedM4 = (void*) (0UL), /* Reserved */ - .pvReservedM3 = (void*) (0UL), /* Reserved */ - .pfnPendSV_Handler = (void*) PendSV_Handler, - .pfnSysTick_Handler = (void*) SysTick_Handler, - - /* Configurable interrupts */ - .pfnSYSTEM_Handler = (void*) SYSTEM_Handler, /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - .pfnWDT_Handler = (void*) WDT_Handler, /* 1 Watchdog Timer */ - .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-Time Counter */ - .pfnEIC_Handler = (void*) EIC_Handler, /* 3 External Interrupt Controller */ - .pfnFREQM_Handler = (void*) FREQM_Handler, /* 4 Frequency Meter */ -#ifdef ID_USB - .pfnUSB_Handler = (void*) USB_Handler, /* 5 Universal Serial Bus */ -#else - .pvReserved5 = (void*) (0UL), /* 5 Reserved */ -#endif - .pfnNVMCTRL_Handler = (void*) NVMCTRL_Handler, /* 6 Non-Volatile Memory Controller */ - .pfnDMAC_Handler = (void*) DMAC_Handler, /* 7 Direct Memory Access Controller */ - .pfnEVSYS_Handler = (void*) EVSYS_Handler, /* 8 Event System Interface */ - .pfnSERCOM0_Handler = (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - .pfnSERCOM1_Handler = (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - .pfnSERCOM2_Handler = (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ -#ifdef ID_SERCOM3 - .pfnSERCOM3_Handler = (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ -#else - .pvReserved12 = (void*) (0UL), /* 12 Reserved */ -#endif -#ifdef ID_SERCOM4 - .pfnSERCOM4_Handler = (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ -#else - .pvReserved13 = (void*) (0UL), /* 13 Reserved */ -#endif -#ifdef ID_SERCOM5 - .pfnSERCOM5_Handler = (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ -#else - .pvReserved14 = (void*) (0UL), /* 14 Reserved */ -#endif - .pfnTCC0_Handler = (void*) TCC0_Handler, /* 15 Timer Counter Control */ - .pfnTC0_Handler = (void*) TC0_Handler, /* 16 Basic Timer Counter 0 */ - .pfnTC1_Handler = (void*) TC1_Handler, /* 17 Basic Timer Counter 1 */ - .pfnTC2_Handler = (void*) TC2_Handler, /* 18 Basic Timer Counter 2 */ - .pfnTC3_Handler = (void*) TC3_Handler, /* 19 Basic Timer Counter 3 */ - .pfnADC_Handler = (void*) ADC_Handler, /* 20 Analog Digital Converter */ - .pfnAC_Handler = (void*) AC_Handler, /* 21 Analog Comparators */ -#ifdef ID_PTC - .pfnPTC_Handler = (void*) PTC_Handler, /* 22 Peripheral Touch Controller */ -#else - .pvReserved22 = (void*) (0UL), /* 22 Reserved */ -#endif - .pfnSLCD_Handler = (void*) SLCD_Handler, /* 23 Segment Liquid Crystal Display Controller */ -#ifdef ID_AES - .pfnAES_Handler = (void*) AES_Handler, /* 24 Advanced Encryption Standard */ -#else - .pvReserved24 = (void*) (0UL), /* 24 Reserved */ -#endif -#ifdef ID_TRNG - .pfnTRNG_Handler = (void*) TRNG_Handler /* 25 True Random Generator */ -#else - .pvReserved25 = (void*) (0UL) /* 25 Reserved */ -#endif -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/watch-library/watch/tusb_config.h b/watch-library/watch/tusb_config.h deleted file mode 100644 index a22b2b99..00000000 --- a/watch-library/watch/tusb_config.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - */ - -#ifndef _TUSB_CONFIG_H_ -#define _TUSB_CONFIG_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -//-------------------------------------------------------------------- -// COMMON CONFIGURATION -//-------------------------------------------------------------------- - -// defined by board.mk -#define CFG_TUSB_MCU OPT_MCU_SAML22 - -#define BOARD_DEVICE_RHPORT_NUM 0 -#define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_FULL_SPEED -#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | OPT_MODE_FULL_SPEED) - -#define CFG_TUSB_OS OPT_OS_NONE - -// disable TinyUSB debug. our printf method prints stuff to the USB console, so you just get infinite noise. -// if you need to debug tinyUSB issues, use the alternate _write function in watch_private.c to echo to the UART. -#define CFG_TUSB_DEBUG 0 - -/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. - * Tinyusb use follows macros to declare transferring memory so that they can be put - * into those specific section. - * e.g - * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) - * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) - */ -#ifndef CFG_TUSB_MEM_SECTION -#define CFG_TUSB_MEM_SECTION -#endif - -#ifndef CFG_TUSB_MEM_ALIGN -#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4))) -#endif - -//-------------------------------------------------------------------- -// DEVICE CONFIGURATION -//-------------------------------------------------------------------- - -#ifndef CFG_TUD_ENDPOINT0_SIZE -#define CFG_TUD_ENDPOINT0_SIZE 64 -#endif - -//------------- CLASS -------------// -#define CFG_TUD_CDC 1 -#define CFG_TUD_MSC 0 -#define CFG_TUD_HID 0 -#define CFG_TUD_MIDI 0 -#define CFG_TUD_VENDOR 0 - -// CDC FIFO size of TX and RX -#define CFG_TUD_CDC_RX_BUFSIZE (64) -#define CFG_TUD_CDC_TX_BUFSIZE (64) - -// CDC Endpoint transfer buffer size, more is faster -#define CFG_TUD_CDC_EP_BUFSIZE (64) - -#ifdef __cplusplus - } -#endif - -#endif /* _TUSB_CONFIG_H_ */ diff --git a/watch-library/watch/watch.c b/watch-library/watch/watch.c deleted file mode 100644 index 791fd974..00000000 --- a/watch-library/watch/watch.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2021 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "watch.h" - -bool battery_is_low = false; - -// receives interrupts from MCLK, OSC32KCTRL, OSCCTRL, PAC, PM, SUPC and TAL, whatever that is. -void SYSTEM_Handler(void) { - if (SUPC->INTFLAG.bit.BOD33DET) { - battery_is_low = true; - SUPC->INTENCLR.bit.BOD33DET = 1; - SUPC->INTFLAG.reg &= ~SUPC_INTFLAG_BOD33DET; - } -} - -bool watch_is_battery_low(void) { - return battery_is_low; -} - -bool watch_is_buzzer_or_led_enabled(void){ - return hri_mclk_get_APBCMASK_TCC0_bit(MCLK); -} diff --git a/watch-library/watch/watch.h b/watch-library/watch/watch.h deleted file mode 100644 index 064f90ec..00000000 --- a/watch-library/watch/watch.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -/// @file watch.h - -#ifndef WATCH_H_ -#define WATCH_H_ -#include -#include -#include "driver_init.h" - -/** @mainpage Sensor Watch Documentation - * @brief This documentation covers most of the functions you will use to interact with the Sensor Watch - hardware. It is divided into the following sections: - - @ref app - This section covers the functions that you will implement in your app.c file when designing a - Sensor Watch app. - - @ref rtc - This section covers functions related to the SAM L22's real-time clock peripheral, including - date, time and alarm functions. - - @ref slcd - This section covers functions related to the Segment LCD display driver, which is responsible - for displaying strings of characters and indicators on the main watch display. - - @ref buttons - This section covers functions related to the three buttons: Light, Mode and Alarm. - - @ref led - This section covers functions related to the bi-color red/green LED mounted behind the LCD. - - @ref buzzer - This section covers functions related to the piezo buzzer. - - @ref adc - This section covers functions related to the SAM L22's analog-to-digital converter, as well as - configuring and reading values from the five analog-capable pins on the 9-pin connector. - - @ref gpio - This section covers functions related to general-purpose input and output signals. - - @ref i2c - This section covers functions related to the SAM L22's built-I2C driver, including configuring - the I2C bus, putting values directly on the bus and reading data from registers on I2C devices. - - @ref debug - This section covers functions related to the debug UART, available on pin D1 of the 9-pin connector. - - @ref deepsleep - This section covers functions related to preparing for and entering BACKUP mode, the - deepest sleep mode available on the SAM L22. - */ - -#include "watch_app.h" -#include "watch_rtc.h" -#include "watch_slcd.h" -#include "watch_extint.h" -#include "watch_led.h" -#include "watch_buzzer.h" -#include "watch_adc.h" -#include "watch_gpio.h" -#include "watch_i2c.h" -#include "watch_uart.h" -#include "watch_deepsleep.h" - -#include "watch_private.h" - -/** @brief Returns true when the battery voltage dips below 2.5V. - * @details A CR2016 battery will have a nominal voltage between 2.9 and 3 volts for most of its lifespan. Once the battery - * discharges to about 60%, the voltage will drift slightly lower; this may manifest as a dimmer LED. By the time - * the battery voltage has fallen to 2.5 volts, it will have probably less than 10% of its capacity remaining, and - * you can expect the voltage to drop relatively quickly as the battery dies. - */ -bool watch_is_battery_low(void); - -/** @brief Returns true if either the buzzer or the LED driver is enabled. - * @details Both the buzzer and the LED use the TCC peripheral to drive their behavior. This function returns true if that - * peripheral is enabled. You can use this function to determine whether you need to call the watch_disable_leds or - * or watch_enable_buzzer functions before using these peripherals. - */ -bool watch_is_buzzer_or_led_enabled(void); - -#endif /* WATCH_H_ */ \ No newline at end of file diff --git a/watch-library/watch/watch_adc.c b/watch-library/watch/watch_adc.c deleted file mode 100644 index 5ba7abdf..00000000 --- a/watch-library/watch/watch_adc.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "watch_adc.h" - -static void _watch_sync_adc(void) { - while (ADC->SYNCBUSY.reg); -} - -static uint16_t _watch_get_analog_value(uint16_t channel) { - if (ADC->INPUTCTRL.bit.MUXPOS != channel) { - ADC->INPUTCTRL.bit.MUXPOS = channel; - _watch_sync_adc(); - } - - ADC->SWTRIG.bit.START = 1; - while (!ADC->INTFLAG.bit.RESRDY); - - return ADC->RESULT.reg; -} - -void watch_enable_adc(void) { - MCLK->APBCMASK.reg |= MCLK_APBCMASK_ADC; - GCLK->PCHCTRL[ADC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN; - - uint16_t calib_reg = 0; - calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC_FUSES_BIASREFBUF_ADDR >> ADC_FUSES_BIASREFBUF_Pos)) | - ADC_CALIB_BIASCOMP((*(uint32_t *)ADC_FUSES_BIASCOMP_ADDR >> ADC_FUSES_BIASCOMP_Pos)); - - if (!ADC->SYNCBUSY.bit.SWRST) { - if (ADC->CTRLA.bit.ENABLE) { - ADC->CTRLA.bit.ENABLE = 0; - _watch_sync_adc(); - } - ADC->CTRLA.bit.SWRST = 1; - } - _watch_sync_adc(); - - if (USB->DEVICE.CTRLA.bit.ENABLE) { - // if USB is enabled, we are running an 8 MHz clock. - // divide by 16 for a 500kHz ADC clock. - ADC->CTRLB.bit.PRESCALER = ADC_CTRLB_PRESCALER_DIV16_Val; - } else { - // otherwise it's 4 Mhz. divide by 8 for a 500kHz ADC clock. - ADC->CTRLB.bit.PRESCALER = ADC_CTRLB_PRESCALER_DIV8_Val; - } - ADC->CALIB.reg = calib_reg; - ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC2_Val; - ADC->INPUTCTRL.bit.MUXNEG = ADC_INPUTCTRL_MUXNEG_GND_Val; - ADC->CTRLC.bit.RESSEL = ADC_CTRLC_RESSEL_16BIT_Val; - ADC->AVGCTRL.bit.SAMPLENUM = ADC_AVGCTRL_SAMPLENUM_16_Val; - ADC->SAMPCTRL.bit.SAMPLEN = 0; - ADC->INTENSET.reg = ADC_INTENSET_RESRDY; - ADC->CTRLA.bit.ENABLE = 1; - _watch_sync_adc(); - // throw away one measurement after reference change (the channel doesn't matter). - _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC); -} - -void watch_enable_analog_input(const uint8_t pin) { - gpio_set_pin_direction(pin, GPIO_DIRECTION_OFF); - switch (pin) { - case A0: - gpio_set_pin_function(pin, PINMUX_PB04B_ADC_AIN12); - break; - case A1: - gpio_set_pin_function(pin, PINMUX_PB01B_ADC_AIN9); - break; - case A2: - gpio_set_pin_function(pin, PINMUX_PB02B_ADC_AIN10); - break; - case A3: - gpio_set_pin_function(pin, PINMUX_PB03B_ADC_AIN11); - break; - case A4: - gpio_set_pin_function(pin, PINMUX_PB00B_ADC_AIN8); - break; - default: - return; - } -} - -uint16_t watch_get_analog_pin_level(const uint8_t pin) { - switch (pin) { - case A0: - return _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_AIN12_Val); - case A1: - return _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_AIN9_Val); - case A2: - return _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_AIN10_Val); - case A3: - return _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_AIN11_Val); - case A4: - return _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_AIN8_Val); - default: - return 0; - } -} - -void watch_set_analog_num_samples(uint16_t samples) { - // ignore any input that's not a power of 2 (i.e. only one bit set) - if (__builtin_popcount(samples) != 1) return; - // if only one bit is set, counting the trailing zeroes is equivalent to log2(samples) - uint8_t sample_val = __builtin_ctz(samples); - // make sure the desired value is within range and set it, if so. - if (sample_val <= ADC_AVGCTRL_SAMPLENUM_1024_Val) { - ADC->AVGCTRL.bit.SAMPLENUM = sample_val; - _watch_sync_adc(); - } -} - -void watch_set_analog_sampling_length(uint8_t cycles) { - // for clarity the API asks the user how many cycles they want the measurement to take. - // but the ADC always needs at least one cycle; it just wants to know how many *extra* cycles we want. - // so we subtract one from the user-provided value, and clamp to the maximum. - ADC->SAMPCTRL.bit.SAMPLEN = (cycles - 1) & 0x3F; - _watch_sync_adc(); -} - -void watch_set_analog_reference_voltage(watch_adc_reference_voltage reference) { - ADC->CTRLA.bit.ENABLE = 0; - - if (reference == ADC_REFERENCE_INTREF) SUPC->VREF.bit.VREFOE = 1; - else SUPC->VREF.bit.VREFOE = 0; - - ADC->REFCTRL.bit.REFSEL = reference; - ADC->CTRLA.bit.ENABLE = 1; - _watch_sync_adc(); - // throw away one measurement after reference change (the channel doesn't matter). - _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC); -} - -uint16_t watch_get_vcc_voltage(void) { - // stash the previous reference so we can restore it when we're done. - uint8_t oldref = ADC->REFCTRL.bit.REFSEL; - - // if we weren't already using the internal reference voltage, select it now. - if (oldref != ADC_REFERENCE_INTREF) watch_set_analog_reference_voltage(ADC_REFERENCE_INTREF); - - // get the data - uint32_t raw_val = _watch_get_analog_value(ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val); - - // restore the old reference, if needed. - if (oldref != ADC_REFERENCE_INTREF) watch_set_analog_reference_voltage(oldref); - - return (uint16_t)((raw_val * 1000) / (1024 * 1 << ADC->AVGCTRL.bit.SAMPLENUM)); -} - -inline void watch_disable_analog_input(const uint8_t pin) { - gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF); -} - -inline void watch_disable_adc(void) { - ADC->CTRLA.bit.ENABLE = 0; - _watch_sync_adc(); - - MCLK->APBCMASK.reg &= ~MCLK_APBCMASK_ADC; -} diff --git a/watch-library/watch/watch_adc.h b/watch-library/watch/watch_adc.h deleted file mode 100644 index aa7c801a..00000000 --- a/watch-library/watch/watch_adc.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef _WATCH_ADC_H_INCLUDED -#define _WATCH_ADC_H_INCLUDED -////< @file watch_adc.h - -#include "watch.h" - -/** @addtogroup adc Analog Input - * @brief This section covers functions related to the SAM L22's analog-to-digital converter, - * as well as configuring and reading values from the five analog-capable pins on the - * 9-pin connector. - */ -/// @{ -/** @brief Enables the ADC peripheral. You must call this before attempting to read a value - * from an analog pin. - */ -void watch_enable_adc(void); - -/** @brief Configures the selected pin for analog input. - * @param pin One of pins A0-A4. - */ -void watch_enable_analog_input(const uint8_t pin); - -/** @brief Reads an analog value from one of the pins. - * @param pin One of pins A0-A4. - * @return a 16-bit unsigned integer from 0-65535 representing the sampled value, unless you - * have changed the number of samples. @see watch_set_num_analog_samples for details - * on how that function changes the values returned from this one. - **/ -uint16_t watch_get_analog_pin_level(const uint8_t pin); - -/** @brief Sets the number of samples to accumulate when measuring a pin level. Default is 16. - * @param samples A power of 2 <= 1024. Specifically: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 - or 1024. Any other value will be ignored. - * @details The SAM L22's ADC has a resolution of 12 bits. By default, the watch configures - * the ADC to take 16 samples of the analog input and accumulate them in the result - * register; this effectively gives us a 16-bit resolution, at the cost of taking 16 - * ADC cycles to complete a measurement. If you are measuring a slowly changing signal - * like a thermistor output or an ambient light sensor this is probably fine, even - * desirable. If you are measuring something a bit more fast-paced, like an analog - * accelerometer, you may wish to exchange precision for speed. In this case you may - * call this function to configure the ADC to accumulate fewer samples. HOWEVER! Note - * that this may change the range of values returned from watch_get_analog_pin_level: - * - For watch_set_num_analog_samples(1), the returned value will be 12 bits (0-4095). - * - For watch_set_num_analog_samples(2), the returned value will be 13 bits (0-8191). - * - For watch_set_num_analog_samples(4), the returned value will be 14 bits (0-16383). - * - For watch_set_num_analog_samples(8), the returned value will be 15 bits (0-32767). - * For sampling values over 16, the returned value will still be 16 bits (0-65535); the - * ADC will automatically divide the measured value by whatever factor is necessary to fit - * the result in 16 bits. - * @see watch_get_analog_pin_level - **/ -void watch_set_analog_num_samples(uint16_t samples); - -/** @brief Sets the length of time spent sampling, which allows measurement of higher impedance inputs. - * Default is 1. - * @param cycles The number of ADC cycles to sample, between 1 and 64. - * @see this article by Thea Flowers: https://blog.thea.codes/getting-the-most-out-of-the-samd21-adc/ - * which is where I learned all of this. - * @details To measure an analog value, the SAM L22 must charge a capacitor to the analog voltage - * presented at the input. This takes time. Importantly, the higher the input impedance, - * the more time this takes. As a basic example: if you are using a thermistor tied to - * VCC to measure temperature, the capacitor has to charge through the thermistor. The - * higher the resistor value, the higher the input impedance, and the more time we need - * to allow for the measurement. By default, the ADC is configured to run on a 500 kHz - * clock with a sample time of one cycle. This is appropriate for an input impedance up - * to about 28kΩ. Setting the sampling time to 4 cycles allows for an input impedance up - * to 123kΩ. Setting the sampling time to the maximum of 64 cycles theoretically allows - * for input impedance up to 2 MΩ. (I based these numbers on the calculator in the linked - * blog post; it also has a ton of great info on the SAM D21 ADC, which is similar to the - * SAM L22's). - **/ -void watch_set_analog_sampling_length(uint8_t cycles); - -typedef enum { - ADC_REFERENCE_INTREF = ADC_REFCTRL_REFSEL_INTREF_Val, - ADC_REFERENCE_VCC_DIV1POINT6 = ADC_REFCTRL_REFSEL_INTVCC0_Val, - ADC_REFERENCE_VCC_DIV2 = ADC_REFCTRL_REFSEL_INTVCC1_Val, - ADC_REFERENCE_VCC = ADC_REFCTRL_REFSEL_INTVCC2_Val, -} watch_adc_reference_voltage; - - -/** @brief Selects the reference voltage to use for analog readings. Default is ADC_REFERENCE_VCC. - * @param reference One of ADC_REFERENCE_VCC, ADC_REFERENCE_VCC_DIV1POINT6, ADC_REFERENCE_VCC_DIV2 - * or ADC_REFERENCE_INTREF. - * @details In order to turn an analog voltage into a 16-bit integer, the ADC needs to compare the - * measured voltage to a reference point. For example, if you were powering the watch with - * VCC == 3.0V and you had two 10K resistors connected in series from 3V to GND, you could - * expect to get 3 volts when you measure the top of the voltage divider, 0 volts at the - * bottom, and 1.5 volts in the middle. If you read these values uising a reference voltage - * of ADC_REFERENCE_VCC, the top value would be about 65535, the bottom about 0, and the - * middle about 32768. However! If we used ADC_REFERENCE_VCC_DIV2 as our reference, we would - * expect to get 65535 both at the top and the middle, because the largest value the ADC can - * measure in this configutation is 1.5V (VCC / 2). - * - * By changing the reference voltage from ADC_REFERENCE_VCC to ADC_REFERENCE_VCC_DIV1POINT6 - * or ADC_REFERENCE_VCC_DIV2, you can get more resolution when measuring small voltages (i.e. - * a phototransistor circuit in low light). - * - * There is also a special reference voltage called ADC_REFERENCE_INTREF. The SAM L22's - * Supply Controller provides a selectable voltage reference (by default, 1.024 V) that you - * can select as a reference voltage for ADC conversions. Unlike the three references we - * talked about in the last paragraph, this reference voltage does not depend on VCC, which - * makes it very useful for measuring the battery voltage (since you can't really compare - * VCC to itself). You can change the INTREF voltage to 2.048 or 4.096 V by poking at the - * supply controller's VREF register, but the watch library does not support this use case. - **/ -void watch_set_analog_reference_voltage(watch_adc_reference_voltage reference); - -/** @brief Returns the voltage of the VCC supply in millivolts (i.e. 3000 mV == 3.0 V). If running on - * a coin cell, this will be the battery voltage. - * @details Unlike other ADC functions, this function does not return a raw value from the ADC, but - * rather scales it to an actual number of millivolts. This is because the ADC doesn't let - * us measure VCC per se; it instead lets us measure VCC / 4, and we choose to measure it - * against the internal reference voltage of 1.024 V. In short, the ADC gives us a number - * that's complicated to deal with, so we just turn it into a useful number for you :) - * @note This function depends on INTREF being 1.024V. If you have changed it by poking at the supply - * controller's VREF.SEL bits, this function will return inaccurate values. - */ -uint16_t watch_get_vcc_voltage(void); - -/** @brief Disables the analog circuitry on the selected pin. - * @param pin One of pins A0-A4. - */ -void watch_disable_analog_input(const uint8_t pin); - -/** @brief Disables the ADC peripheral. - * @note You will need to call watch_enable_adc to re-enable the ADC peripheral. When you do, it will - * have the default settings of 16 samples and 1 measurement cycle; if you customized these - * parameters, you will need to set them up again. - **/ -void watch_disable_adc(void); - -/// @} -#endif diff --git a/watch-library/watch/watch_app.h b/watch-library/watch/watch_app.h deleted file mode 100644 index 4fa29df8..00000000 --- a/watch-library/watch/watch_app.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef _WATCH_APP_H_INCLUDED -#define _WATCH_APP_H_INCLUDED -////< @file watch_app.h - -/** @addtogroup app Application Framework - * @brief This section covers the functions that you will implement in your app.c file when designing a Sensor Watch app. - * @details You should be able to write a watch app by simply implementing these functions and declaring callbacks for - * various GPIO and peripheral interrupts. The main.c file takes care of calling these functions for you. The - * general flow: - * - * 1. Your app_init() function is called. - * - This method should only be used to set your initial application state. - * 2. If your app is waking from BACKUP, app_wake_from_backup() is called. - * - If you saved state in the RTC's backup registers, you can restore it here. - * 3. Your app_setup() method is called. - * - You may wish to enable some functionality and peripherals here. - * - You should definitely set up some interrupts here. - * 4. The main run loop begins: your app_loop() function is called. - * - Run code and update your UI here. - * - Return true if your app is prepared to enter STANDBY mode. - * 5. This step differs depending on the value returned by app_loop: - * - If you returned false, execution resumes at (4). - * - If you returned true, app_prepare_for_standby() is called; execution moves on to (6). - * 6. The microcontroller enters STANDBY mode. - * - No user code will run, and the watch will enter a low power mode. - * - The watch will remain in this state until an interrupt wakes it. - * 7. Once woken from STANDBY, your app_wake_from_standby() function is called. - * - After this, execution resumes at (4). - */ -/// @{ -/** @brief A function you will implement to initialize your application state. The app_init function is called before - * anything else. Use it to set up any internal data structures or application state required by your app, - * but don't configure any peripherals just yet. - */ -void app_init(void); - -/** @brief A function you will implement to wake from BACKUP mode, which wipes the system's RAM, and with it, your - * application's state. You may have chosen to store some important application state in the RTC's backup - * registers prior to entering this mode. You may restore that state here. - */ -void app_wake_from_backup(void); - -/** @brief A function you will implement to set up your application. The app_setup function is like setup() in Arduino. - * It is called once when the program begins. You should set pin modes and enable any peripherals you want to - * set up (real-time clock, I2C, etc.) Depending on your application, you may or may not want to configure - * sensors on your sensor board here. For example, a low-power accelerometer that will run at all times should - * be configured here, whereas you may want to enable a more power-hungry sensor only when you need it. - * @note If your app enters the ultra-low power BACKUP sleep mode, this function will be called again when it wakes - * from that deep sleep state. In this state, the RTC will still be configured with the correct date and time. - */ -void app_setup(void); - -/** @brief A function you will implement to serve as the app's main run loop. This method will be called repeatedly, - or if you enter STANDBY mode, as soon as the device wakes from sleep. - * @return You should return true if your app is prepared to enter STANDBY mode. If you return false, your app's - * app_loop method will be called again immediately. Note that in STANDBY mode, the watch will consume only - * about 95 microamperes of power, whereas if you return false and keep the app awake, it will consume about - * 355 microamperes. This is the difference between months of battery life and days. As much as possible, - * you should limit the amount of time your app spends awake. - * @note Only the RTC, the segment LCD controller and the external interrupt controller run in STANDBY mode. If you - * are using, e.g. the PWM function to set a custom LED color, you should return false here until you are - * finished with that operation. Note however that the peripherals will continue running after waking up, - * so e.g. the I2C controller, if configured, will sleep in STANDBY. But you can use it again as soon as your - * app wakes up. - */ -bool app_loop(void); - -/** @brief A function you will implement to prepare to enter STANDBY mode. The app_prepare_for_standby function is - * called after your app_loop function returns true, and just before the watch enters STANDBY mode. In this - * mode most peripherals are shut down, and no code will run until the watch receives an interrupt (generally - * either the 1Hz tick or a press on one of the buttons). - * @note If you are PWM'ing the LED or playing a sound on the buzzer, the TC/TCC peripherals that drive those operations - * will not run in STANDBY. BUT! the output pins will retain the state they had when entering standby. This means - * you could end up entering standby with an LED on and draining power, or with a DC potential across the piezo - * buzzer that could damage it if left in this state. If your app_loop does not prevent sleep during these - * activities, you should make sure to disable these outputs in app_prepare_for_standby. - */ -void app_prepare_for_standby(void); - -/** @brief A method you will implement to configure the app after waking from STANDBY mode. - */ -void app_wake_from_standby(void); - -/// @} -#endif diff --git a/watch-library/watch/watch_buzzer.c b/watch-library/watch/watch_buzzer.c deleted file mode 100644 index a275b00d..00000000 --- a/watch-library/watch/watch_buzzer.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "watch_buzzer.h" - - inline void watch_enable_buzzer(void) { - if (!hri_tcc_get_CTRLA_reg(TCC0, TCC_CTRLA_ENABLE)) { - _watch_enable_tcc(); - } -} -inline void watch_set_buzzer_period(uint32_t period) { - hri_tcc_write_PERBUF_reg(TCC0, period); -} - -void watch_disable_buzzer(void) { - _watch_disable_tcc(); -} - -inline void watch_set_buzzer_on(void) { - gpio_set_pin_direction(BUZZER, GPIO_DIRECTION_OUT); - gpio_set_pin_function(BUZZER, WATCH_BUZZER_TCC_PINMUX); -} - -inline void watch_set_buzzer_off(void) { - gpio_set_pin_direction(BUZZER, GPIO_DIRECTION_OFF); - gpio_set_pin_function(BUZZER, GPIO_PIN_FUNCTION_OFF); -} - -// note: the buzzer uses a 1 MHz clock. these values were determined by dividing 1,000,000 by the target frequency. -// i.e. for a 440 Hz tone (A4 on the piano), 1MHz/440Hz = 2273 -const uint16_t NotePeriods[108] = {18182,17161,16197,15288,14430,13620,12857,12134,11453,10811,10204,9631,9091,8581,8099,7645,7216,6811,6428,6068,5727,5405,5102,4816,4545,4290,4050,3822,3608,3405,3214,3034,2863,2703,2551,2408,2273,2145,2025,1911,1804,1703,1607,1517,1432,1351,1276,1204,1136,1073,1012,956,902,851,804,758,716,676,638,602,568,536,506,478,451,426,402,379,358,338,319,301,284,268,253,239,225,213,201,190,179,169,159,150,142,134,127}; - -void watch_buzzer_play_note(BuzzerNote note, uint16_t duration_ms) { - if (note == BUZZER_NOTE_REST) { - watch_set_buzzer_off(); - } else { - hri_tcc_write_PERBUF_reg(TCC0, NotePeriods[note]); - hri_tcc_write_CCBUF_reg(TCC0, WATCH_BUZZER_TCC_CHANNEL, NotePeriods[note] / 2); - watch_set_buzzer_on(); - } - delay_ms(duration_ms); - watch_set_buzzer_off(); -} diff --git a/watch-library/watch/watch_buzzer.h b/watch-library/watch/watch_buzzer.h deleted file mode 100644 index 1b5d197c..00000000 --- a/watch-library/watch/watch_buzzer.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef _WATCH_BUZZER_H_INCLUDED -#define _WATCH_BUZZER_H_INCLUDED -////< @file watch_buzzer.h - -#include "watch.h" - -/** @addtogroup buzzer Buzzer - * @brief This section covers functions related to the piezo buzzer embedded in the F-91W's back plate. - */ -/// @{ -/** @brief Enables the TCC peripheral, which drives the buzzer. - */ -void watch_enable_buzzer(void); - -/** @brief Sets the period of the buzzer. - * @param period The period of a single cycle for the TCC peripheral. You can determine the period for - * a desired frequency with the following formula: period = 1000000 / freq - */ -void watch_set_buzzer_period(uint32_t period); - -/** @brief Disables the TCC peripheral that drives the buzzer. - * @note If you are using PWM to set custom LED colors, this method will also disable the LED PWM driver, - * since the buzzer and LED both make use of the same peripheral to drive their PWM behavior. - */ -void watch_disable_buzzer(void); - -/** @brief Turns the buzzer output on. It will emit a continuous sound at the given frequency. - * @note The TCC peripheral that drives the buzzer does not run in standby mode; if you wish for buzzer - * output to continue, you should prevent your app from going to sleep. - */ -void watch_set_buzzer_on(void); - -/** @brief Turns the buzzer output off. - */ -void watch_set_buzzer_off(void); - -/// @brief 87 notes for use with watch_buzzer_play_note -typedef enum BuzzerNote { - BUZZER_NOTE_A1, ///< 55.00 Hz - BUZZER_NOTE_A1SHARP_B1FLAT, ///< 58.27 Hz - BUZZER_NOTE_B1, ///< 61.74 Hz - BUZZER_NOTE_C2, ///< 65.41 Hz - BUZZER_NOTE_C2SHARP_D2FLAT, ///< 69.30 Hz - BUZZER_NOTE_D2, ///< 73.42 Hz - BUZZER_NOTE_D2SHARP_E2FLAT, ///< 77.78 Hz - BUZZER_NOTE_E2, ///< 82.41 Hz - BUZZER_NOTE_F2, ///< 87.31 Hz - BUZZER_NOTE_F2SHARP_G2FLAT, ///< 92.50 Hz - BUZZER_NOTE_G2, ///< 98.00 Hz - BUZZER_NOTE_G2SHARP_A2FLAT, ///< 103.83 Hz - BUZZER_NOTE_A2, ///< 110.00 Hz - BUZZER_NOTE_A2SHARP_B2FLAT, ///< 116.54 Hz - BUZZER_NOTE_B2, ///< 123.47 Hz - BUZZER_NOTE_C3, ///< 130.81 Hz - BUZZER_NOTE_C3SHARP_D3FLAT, ///< 138.59 Hz - BUZZER_NOTE_D3, ///< 146.83 Hz - BUZZER_NOTE_D3SHARP_E3FLAT, ///< 155.56 Hz - BUZZER_NOTE_E3, ///< 164.81 Hz - BUZZER_NOTE_F3, ///< 174.61 Hz - BUZZER_NOTE_F3SHARP_G3FLAT, ///< 185.00 Hz - BUZZER_NOTE_G3, ///< 196.00 Hz - BUZZER_NOTE_G3SHARP_A3FLAT, ///< 207.65 Hz - BUZZER_NOTE_A3, ///< 220.00 Hz - BUZZER_NOTE_A3SHARP_B3FLAT, ///< 233.08 Hz - BUZZER_NOTE_B3, ///< 246.94 Hz - BUZZER_NOTE_C4, ///< 261.63 Hz - BUZZER_NOTE_C4SHARP_D4FLAT, ///< 277.18 Hz - BUZZER_NOTE_D4, ///< 293.66 Hz - BUZZER_NOTE_D4SHARP_E4FLAT, ///< 311.13 Hz - BUZZER_NOTE_E4, ///< 329.63 Hz - BUZZER_NOTE_F4, ///< 349.23 Hz - BUZZER_NOTE_F4SHARP_G4FLAT, ///< 369.99 Hz - BUZZER_NOTE_G4, ///< 392.00 Hz - BUZZER_NOTE_G4SHARP_A4FLAT, ///< 415.30 Hz - BUZZER_NOTE_A4, ///< 440.00 Hz - BUZZER_NOTE_A4SHARP_B4FLAT, ///< 466.16 Hz - BUZZER_NOTE_B4, ///< 493.88 Hz - BUZZER_NOTE_C5, ///< 523.25 Hz - BUZZER_NOTE_C5SHARP_D5FLAT, ///< 554.37 Hz - BUZZER_NOTE_D5, ///< 587.33 Hz - BUZZER_NOTE_D5SHARP_E5FLAT, ///< 622.25 Hz - BUZZER_NOTE_E5, ///< 659.25 Hz - BUZZER_NOTE_F5, ///< 698.46 Hz - BUZZER_NOTE_F5SHARP_G5FLAT, ///< 739.99 Hz - BUZZER_NOTE_G5, ///< 783.99 Hz - BUZZER_NOTE_G5SHARP_A5FLAT, ///< 830.61 Hz - BUZZER_NOTE_A5, ///< 880.00 Hz - BUZZER_NOTE_A5SHARP_B5FLAT, ///< 932.33 Hz - BUZZER_NOTE_B5, ///< 987.77 Hz - BUZZER_NOTE_C6, ///< 1046.50 Hz - BUZZER_NOTE_C6SHARP_D6FLAT, ///< 1108.73 Hz - BUZZER_NOTE_D6, ///< 1174.66 Hz - BUZZER_NOTE_D6SHARP_E6FLAT, ///< 1244.51 Hz - BUZZER_NOTE_E6, ///< 1318.51 Hz - BUZZER_NOTE_F6, ///< 1396.91 Hz - BUZZER_NOTE_F6SHARP_G6FLAT, ///< 1479.98 Hz - BUZZER_NOTE_G6, ///< 1567.98 Hz - BUZZER_NOTE_G6SHARP_A6FLAT, ///< 1661.22 Hz - BUZZER_NOTE_A6, ///< 1760.00 Hz - BUZZER_NOTE_A6SHARP_B6FLAT, ///< 1864.66 Hz - BUZZER_NOTE_B6, ///< 1975.53 Hz - BUZZER_NOTE_C7, ///< 2093.00 Hz - BUZZER_NOTE_C7SHARP_D7FLAT, ///< 2217.46 Hz - BUZZER_NOTE_D7, ///< 2349.32 Hz - BUZZER_NOTE_D7SHARP_E7FLAT, ///< 2489.02 Hz - BUZZER_NOTE_E7, ///< 2637.02 Hz - BUZZER_NOTE_F7, ///< 2793.83 Hz - BUZZER_NOTE_F7SHARP_G7FLAT, ///< 2959.96 Hz - BUZZER_NOTE_G7, ///< 3135.96 Hz - BUZZER_NOTE_G7SHARP_A7FLAT, ///< 3322.44 Hz - BUZZER_NOTE_A7, ///< 3520.00 Hz - BUZZER_NOTE_A7SHARP_B7FLAT, ///< 3729.31 Hz - BUZZER_NOTE_B7, ///< 3951.07 Hz - BUZZER_NOTE_C8, ///< 4186.01 Hz - BUZZER_NOTE_C8SHARP_D8FLAT, ///< 4434.92 Hz - BUZZER_NOTE_D8, ///< 4698.63 Hz - BUZZER_NOTE_D8SHARP_E8FLAT, ///< 4978.03 Hz - BUZZER_NOTE_E8, ///< 5274.04 Hz - BUZZER_NOTE_F8, ///< 5587.65 Hz - BUZZER_NOTE_F8SHARP_G8FLAT, ///< 5919.91 Hz - BUZZER_NOTE_G8, ///< 6271.93 Hz - BUZZER_NOTE_G8SHARP_A8FLAT, ///< 6644.88 Hz - BUZZER_NOTE_A8, ///< 7040.00 Hz - BUZZER_NOTE_A8SHARP_B8FLAT, ///< 7458.62 Hz - BUZZER_NOTE_B8, ///< 7902.13 Hz - BUZZER_NOTE_REST ///< no sound -} BuzzerNote; - -/** @brief Plays the given note for a set duration. - * @param note The note you wish to play, or BUZZER_NOTE_REST to disable output for the given duration. - * @param duration_ms The duration of the note. - * @note Note that this will block your UI for the duration of the note's play time, and it will - * after this call, the buzzer period will be set to the period of this note. - */ -void watch_buzzer_play_note(BuzzerNote note, uint16_t duration_ms); - -/// @brief An array of periods for all the notes on a piano, corresponding to the names in BuzzerNote. -extern const uint16_t NotePeriods[108]; - -/// @} -#endif diff --git a/watch-library/watch/watch_deepsleep.c b/watch-library/watch/watch_deepsleep.c deleted file mode 100644 index 1813ff24..00000000 --- a/watch-library/watch/watch_deepsleep.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "watch_extint.h" - -// this warning only appears when you `make BOARD=OSO-SWAT-A1-02`. it's annoying, -// but i'd rather have it warn us at build-time than fail silently at run-time. -// besides, no one but me really has any of these boards anyway. -#if BTN_ALARM != GPIO(GPIO_PORTA, 2) -#warning This board revision does not support external wake on BTN_ALARM, so watch_register_extwake_callback will not work with it. Use watch_register_interrupt_callback instead. -#endif - -void watch_register_extwake_callback(uint8_t pin, ext_irq_cb_t callback, bool level) { - uint32_t pinmux; - hri_rtc_tampctrl_reg_t config = RTC->MODE2.TAMPCTRL.reg; - - switch (pin) { - case A4: - a4_callback = callback; - pinmux = PINMUX_PB00G_RTC_IN0; - config &= ~(3 << RTC_TAMPCTRL_IN0ACT_Pos); - config &= ~(1 << RTC_TAMPCTRL_TAMLVL0_Pos); - config |= 1 << RTC_TAMPCTRL_IN0ACT_Pos; - config |= 1 << RTC_TAMPCTRL_DEBNC0_Pos; - if (level) config |= 1 << RTC_TAMPCTRL_TAMLVL0_Pos; - break; - case A2: - a2_callback = callback; - pinmux = PINMUX_PB02G_RTC_IN1; - config &= ~(3 << RTC_TAMPCTRL_IN1ACT_Pos); - config &= ~(1 << RTC_TAMPCTRL_TAMLVL1_Pos); - config |= 1 << RTC_TAMPCTRL_IN1ACT_Pos; - config |= 1 << RTC_TAMPCTRL_DEBNC1_Pos; - if (level) config |= 1 << RTC_TAMPCTRL_TAMLVL1_Pos; - break; - case BTN_ALARM: - gpio_set_pin_pull_mode(pin, GPIO_PULL_DOWN); - btn_alarm_callback = callback; - pinmux = PINMUX_PA02G_RTC_IN2; - config &= ~(3 << RTC_TAMPCTRL_IN2ACT_Pos); - config &= ~(1 << RTC_TAMPCTRL_TAMLVL2_Pos); - config |= 1 << RTC_TAMPCTRL_IN2ACT_Pos; - config |= 1 << RTC_TAMPCTRL_DEBNC2_Pos; - if (level) config |= 1 << RTC_TAMPCTRL_TAMLVL2_Pos; - break; - default: - return; - } - gpio_set_pin_direction(pin, GPIO_DIRECTION_IN); - gpio_set_pin_function(pin, pinmux); - - // disable the RTC - RTC->MODE2.CTRLA.bit.ENABLE = 0; - while (RTC->MODE2.SYNCBUSY.bit.ENABLE); - - // update the configuration - RTC->MODE2.TAMPCTRL.reg = config; - // re-enable the RTC - RTC->MODE2.CTRLA.bit.ENABLE = 1; - - NVIC_ClearPendingIRQ(RTC_IRQn); - NVIC_EnableIRQ(RTC_IRQn); - RTC->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; -} - -void watch_disable_extwake_interrupt(uint8_t pin) { - hri_rtc_tampctrl_reg_t config = hri_rtc_get_TAMPCTRL_reg(RTC, 0xFFFFFFFF); - - switch (pin) { - case A4: - a4_callback = NULL; - config &= ~(3 << RTC_TAMPCTRL_IN0ACT_Pos); - break; - case A2: - a2_callback = NULL; - config &= ~(3 << RTC_TAMPCTRL_IN1ACT_Pos); - break; - case BTN_ALARM: - btn_alarm_callback = NULL; - config &= ~(3 << RTC_TAMPCTRL_IN2ACT_Pos); - break; - default: - return; - } - - if (hri_rtcmode0_get_CTRLA_ENABLE_bit(RTC)) { - hri_rtcmode0_clear_CTRLA_ENABLE_bit(RTC); - hri_rtcmode0_wait_for_sync(RTC, RTC_MODE0_SYNCBUSY_ENABLE); - } - hri_rtc_write_TAMPCTRL_reg(RTC, config); - hri_rtcmode0_set_CTRLA_ENABLE_bit(RTC); -} - -void watch_store_backup_data(uint32_t data, uint8_t reg) { - if (reg < 8) { - RTC->MODE0.BKUP[reg].reg = data; - } -} - -uint32_t watch_get_backup_data(uint8_t reg) { - if (reg < 8) { - return RTC->MODE0.BKUP[reg].reg; - } - - return 0; -} - -static void _watch_disable_all_pins_except_rtc(void) { - uint32_t config = RTC->MODE0.TAMPCTRL.reg; - uint32_t portb_pins_to_disable = 0xFFFFFFFF; - - // if there's an action set on RTC/IN[0], leave PB00 configured - if (config & RTC_TAMPCTRL_IN0ACT_Msk) portb_pins_to_disable &= 0xFFFFFFFE; - // same with RTC/IN[1] and PB02 - if (config & RTC_TAMPCTRL_IN1ACT_Msk) portb_pins_to_disable &= 0xFFFFFFFB; - - // port A: always keep PA02 configured as-is; that's our ALARM button. - gpio_set_port_direction(0, 0xFFFFFFFB, GPIO_DIRECTION_OFF); - // port B: disable all pins we didn't save above. - gpio_set_port_direction(1, portb_pins_to_disable, GPIO_DIRECTION_OFF); -} - -static void _watch_disable_all_peripherals_except_slcd(void) { - _watch_disable_tcc(); - watch_disable_adc(); - watch_disable_external_interrupts(); - watch_disable_i2c(); - // TODO: replace this with a proper function when we remove the debug UART - SERCOM3->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; - MCLK->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM3; -} - -void watch_enter_sleep_mode(void) { - // disable all other peripherals - _watch_disable_all_peripherals_except_slcd(); - - // disable tick interrupt - watch_rtc_disable_all_periodic_callbacks(); - - // disable brownout detector interrupt, which could inadvertently wake us up. - SUPC->INTENCLR.bit.BOD33DET = 1; - - // disable all pins - _watch_disable_all_pins_except_rtc(); - - // enter standby (4); we basically hang out here until an interrupt wakes us. - sleep(4); - - // and we awake! re-enable the brownout detector - SUPC->INTENSET.bit.BOD33DET = 1; - - // call app_setup so the app can re-enable everything we disabled. - app_setup(); - - // and call app_wake_from_standby (since main won't have a chance to do it) - app_wake_from_standby(); -} - -void watch_enter_deep_sleep_mode(void) { - // identical to sleep mode except we disable the LCD first. - slcd_sync_deinit(&SEGMENT_LCD_0); - hri_mclk_clear_APBCMASK_SLCD_bit(SLCD); - - watch_enter_sleep_mode(); -} - -void watch_enter_backup_mode(void) { - watch_rtc_disable_all_periodic_callbacks(); - _watch_disable_all_peripherals_except_slcd(); - slcd_sync_deinit(&SEGMENT_LCD_0); - hri_mclk_clear_APBCMASK_SLCD_bit(SLCD); - _watch_disable_all_pins_except_rtc(); - - // go into backup sleep mode (5). when we exit, the reset controller will take over. - sleep(5); -} - -// deprecated -void watch_enter_shallow_sleep(bool display_on) { - if (display_on) watch_enter_sleep_mode(); - else watch_enter_deep_sleep_mode(); -} - -// deprecated -void watch_enter_deep_sleep(void) { - watch_register_extwake_callback(BTN_ALARM, NULL, true); - watch_enter_backup_mode(); -} diff --git a/watch-library/watch/watch_deepsleep.h b/watch-library/watch/watch_deepsleep.h deleted file mode 100644 index 56d75478..00000000 --- a/watch-library/watch/watch_deepsleep.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef _WATCH_DEEPSLEEP_H_INCLUDED -#define _WATCH_DEEPSLEEP_H_INCLUDED -////< @file watch_deepsleep.h - -#include "watch.h" - -// These are declared in watch_rtc.c. -extern ext_irq_cb_t btn_alarm_callback; -extern ext_irq_cb_t a2_callback; -extern ext_irq_cb_t a4_callback; - -/** @addtogroup deepsleep Sleep Control - * @brief This section covers functions related to the various sleep modes available to the watch, - * including Sleep, Deep Sleep, and BACKUP mode. - * @details These terms changed meaning a bit over the course of development; if you are coming - * to this documentation after having worked with an earlier version of the library, - * these definitions should clarify the terminology. Terms in all caps are modes of the - * SAM L22; terms in Title Case are specific implementations in this library. - * - ACTIVE mode is the mode the SAM L22 is in when both the main clock and the CPU are - * running. It is the most power-hungry mode. If you ever call delay_ms to wait a beat, - * the watch will remain in ACTIVE mode while taking that delay. In addition, whenever - * your `app_loop` function returns false, the device will remain in ACTIVE mode and - * call your `app_loop` function again. - * - STANDBY mode turns off the main clock and halts the CPU. Since the PWM driver is - * run from the main clock, it also stops the buzzer and any dimming of the LEDs. - * In this mode, the watch can wake from any interrupt source. Whenever your `app_loop` - * function returns true, the watch enters STANDBY mode until the next tick or other - * interrupt. This mode uses much less power than ACTIVE mode. - * - Sleep Mode is a special case of STANDBY mode. In this mode, the watch turns off - * almost all peripherals (including the external interrupt controller), and disables - * all pins except for the external wake pins. In this mode the watch can only wake - * from the RTC alarm interrupt or an external wake pin (A2, A4 or the alarm button), - * but the display remains on and your app's state is retained. You can enter this - * mode by calling `watch_enter_sleep_mode`. It consumes an order of magnitude less - * power than STANDBY mode. - * - Deep Sleep Mode is identical to sleep mode, but it also turns off the LCD to save - * a bit more power. You can enter this mode by calling `watch_enter_deep_sleep_mode`. - * - BACKUP mode is the lowest possible power mode on the SAM L22. It turns off all pins - * and peripherals except for the RTC. It also turns off the RAM, obliterating your - * application's state. The only way to wake from this mode is by setting an external - * wake interrupt on pin A2 or pin A4, and when you do wake it will be much like a - * wake from reset. You can enter this mode by calling `watch_enter_backup_mode`. - */ -/// @{ - -/** @brief Registers a callback on one of the RTC's external wake pins, which can wake the device - * from Sleep, Deep Sleep and BACKUP modes (but see warning re: BACKUP mode). - * @param pin Either pin BTN_ALARM, A2, or A4. These are the three external wake pins. If the pin - * is BTN_ALARM, this function also enables an internal pull down on that pin. - * @param callback The callback to be called if this pin triggers outside of BACKUP mode. If this is - * NULL, no callback will be called even in normal modes, but the interrupt will - * still be enabled so that it can wake the device. - * @param level The level you wish to scan for: true for rising, false for falling. Note that you - * cannot scan for both rising and falling edges like you can with the external interrupt - * pins; with the external wake interrupt, you can only get one or the other. - * @note When in ACTIVE, STANDBY and Sleep / Deep sleep modes, this will function much like a standard - * external interrupt situation: these pins will wake the device, and your callback will be - * called. However, if the device enters BACKUP mode and one of these pins wakes the device, your - * callback WILL NOT be called, as the device is basically waking from reset at that point. - * @warning As of the current SAM L22 silicon revision (rev B), the BTN_ALARM pin cannot wake the - * device from BACKUP mode. You can still use this function to register a BTN_ALARM interrupt - * in normal or deep sleep mode, but to wake from BACKUP, you will need to use pin A2 or A4. - */ -void watch_register_extwake_callback(uint8_t pin, ext_irq_cb_t callback, bool level); - -/** @brief Unregisters the RTC interrupt on one of the EXTWAKE pins. This will prevent a value change on - * one of these pins from waking the device. - * @param pin Either pin BTN_ALARM, A2, or A4. If the pin is BTN_ALARM, this function DOES NOT disable - * the internal pull down on that pin. - */ -void watch_disable_extwake_interrupt(uint8_t pin); - -/** @brief Stores data in one of the RTC's backup registers, which retain their data in BACKUP mode. - * @param data An unsigned 32 bit integer with the data you wish to store. - * @param reg A register from 0-7. - */ -void watch_store_backup_data(uint32_t data, uint8_t reg); - -/** @brief Gets 32 bits of data from the RTC's BACKUP register. - * @param reg A register from 0-7. - * @return An unsigned 32 bit integer with the from the backup register. - */ -uint32_t watch_get_backup_data(uint8_t reg); - -/** @brief enters Sleep Mode by disabling all pins and peripherals except the RTC and the LCD. - * @details This sleep mode is not the lowest power mode available, but it has the benefit of allowing you - * to display a message to the user while asleep. You can also set an alarm interrupt to wake at a - * configfurable interval (every minute, hour or day) to update the display. You can wake from this - * mode by pressing the ALARM button, if you registered an extwake callback on the ALARM button. - * Also note that when your app wakes from this sleep mode, your app_setup method will be called - * again, since this function will have disabled things you set up there. - * - * Note that to wake from either the ALARM button, the A2 interrupt or the A4 interrupt, you - * must first configure this by calling watch_register_extwake_callback. - * - * You can estimate the power consumption of this mode to be on the order of 30 microwatts - * (about 10 µA at 3 V). - */ -void watch_enter_sleep_mode(void); - -/** @brief enters Deep Sleep Mode by disabling all pins and peripherals except the RTC. - * @details Short of BACKUP mode, this is the lowest power mode you can enter while retaining your - * application state (and the ability to wake with the alarm button). Just note that the display - * will be completely off, so you should document to the user of your application that they will - * need to press the alarm button to wake the device, or use a sensor board with support for - * an external wake pin. - * - * All notes from watch_enter_sleep_mode apply here, except for power consumption. You can estimate - * the power consumption of this mode to be on the order of 12 microwatts (about 4µA at 3 V). - */ -void watch_enter_deep_sleep_mode(void); - -/** @brief Enters the SAM L22's lowest-power mode, BACKUP. - * @details This function does some housekeeping before entering BACKUP mode. It first disables all pins - * and peripherals except for the RTC, and disables the tick interrupt (since that would wake - * us up from BACKUP mode). Once again, if you wish to wake from the A2 or the A4 interrupt, - * you must first configure this by calling watch_register_extwake_callback. - * @note If you have a callback set for an external wake interrupt, it will be called if triggered while - * in ACTIVE, STANDBY, Sleep and Deep Sleep modes, but it *will not be called* when waking from - * BACKUP mode. Waking from backup is effectively like waking from reset, except that your - * @ref app_wake_from_backup function will be called. - * @warning On current revisions of the SAM L22 silicon, the ALARM_BTN pin (PA02 RTC/IN2) cannot wake - * the device from deep sleep mode. There is an errata note (Reference: 15010) that says that - * due to a silicon bug, RTC/IN2 is not functional in BACKUP. As a result, you should not call - * this function unless you have a device on the nine-pin connector with an external interrupt - * on pin A2 or A4 (i.e. an accelerometer with an interrupt pin). - */ -void watch_enter_backup_mode(void); - -__attribute__((deprecated("Use watch_enter_sleep_mode or watch_enter_deep_sleep_mode instead"))) -void watch_enter_shallow_sleep(bool display_on); - -__attribute__((deprecated("Use watch_enter_backup_mode instead"))) -void watch_enter_deep_sleep(void); -/// @} -#endif diff --git a/watch-library/watch/watch_extint.c b/watch-library/watch/watch_extint.c deleted file mode 100644 index 5924b646..00000000 --- a/watch-library/watch/watch_extint.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "watch_extint.h" - -void watch_enable_external_interrupts(void) { - // Configure EIC to use GCLK3 (the 32.768 kHz crystal) - hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos)); - // Enable AHB clock for the EIC - hri_mclk_set_APBAMASK_EIC_bit(MCLK); - // call HAL's external interrupt init function - ext_irq_init(); -} - -void watch_disable_external_interrupts(void) { - ext_irq_deinit(); - hri_mclk_clear_APBAMASK_EIC_bit(MCLK); -} - -void watch_register_interrupt_callback(const uint8_t pin, ext_irq_cb_t callback, watch_interrupt_trigger trigger) { - uint8_t config_index; - uint8_t sense_pos; - switch (pin) { - case A0: - // for EIC channels 8-15, we need to set the SENSE value in CONFIG[1] - config_index = (WATCH_A0_EIC_CHANNEL > 7) ? 1 : 0; - // either way the index in CONFIG[n] must be 0-7 - sense_pos = 4 * (WATCH_A0_EIC_CHANNEL % 8); - break; - case A1: - config_index = (WATCH_A1_EIC_CHANNEL > 7) ? 1 : 0; - sense_pos = 4 * (WATCH_A1_EIC_CHANNEL % 8); - break; - case A2: - config_index = (WATCH_A2_EIC_CHANNEL > 7) ? 1 : 0; - sense_pos = 4 * (WATCH_A2_EIC_CHANNEL % 8); - break; - case A3: - config_index = (WATCH_A3_EIC_CHANNEL > 7) ? 1 : 0; - sense_pos = 4 * (WATCH_A3_EIC_CHANNEL % 8); - break; - case A4: - config_index = (WATCH_A4_EIC_CHANNEL > 7) ? 1 : 0; - sense_pos = 4 * (WATCH_A4_EIC_CHANNEL % 8); - break; - case BTN_ALARM: - config_index = (WATCH_BTN_ALARM_EIC_CHANNEL > 7) ? 1 : 0; - sense_pos = 4 * (WATCH_BTN_ALARM_EIC_CHANNEL % 8); - break; - case BTN_LIGHT: - config_index = (WATCH_BTN_LIGHT_EIC_CHANNEL > 7) ? 1 : 0; - sense_pos = 4 * (WATCH_BTN_LIGHT_EIC_CHANNEL % 8); - break; - case BTN_MODE: - config_index = (WATCH_BTN_MODE_EIC_CHANNEL > 7) ? 1 : 0; - sense_pos = 4 * (WATCH_BTN_MODE_EIC_CHANNEL % 8); - break; - default: - return; - } - - gpio_set_pin_direction(pin, GPIO_DIRECTION_IN); - - // EIC configuration register is enable-protected, so we have to disable it first... - if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) { - hri_eic_clear_CTRLA_ENABLE_bit(EIC); - // ...and wait for it to synchronize. - hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE); - } - // now update the configuration... - hri_eic_config_reg_t config = EIC->CONFIG[config_index].reg; - config &= ~(7 << sense_pos); - config |= trigger << (sense_pos); - hri_eic_write_CONFIG_reg(EIC, config_index, config); - // ...set the pin mode... - gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_A); - if (pin == BTN_ALARM || pin == BTN_LIGHT || pin == BTN_MODE) gpio_set_pin_pull_mode(pin, GPIO_PULL_DOWN); - // ...and re-enable the EIC - hri_eic_set_CTRLA_ENABLE_bit(EIC); - - ext_irq_register(pin, callback); -} - -inline void watch_register_button_callback(const uint8_t pin, ext_irq_cb_t callback) { - watch_register_interrupt_callback(pin, callback, INTERRUPT_TRIGGER_RISING); -} - -inline void watch_enable_buttons(void) { - watch_enable_external_interrupts(); -} diff --git a/watch-library/watch/watch_extint.h b/watch-library/watch/watch_extint.h deleted file mode 100644 index 452461b3..00000000 --- a/watch-library/watch/watch_extint.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef _WATCH_EXTINT_H_INCLUDED -#define _WATCH_EXTINT_H_INCLUDED -////< @file watch_extint.h - -#include "watch.h" -#include "hal_ext_irq.h" - -/** @addtogroup buttons Buttons & External Interrupts - * @brief This section covers functions related to the three buttons: Light, Mode and Alarm, as well as - * external interrupts from devices on the nine-pin connector. - * @details The buttons are the core input UI of the watch, and the way the user will interact with - * your application. They are active high, pulled down by the microcontroller, and triggered - * when one of the "pushers" brings a tab from the metal frame into contact with the edge - * of the board. Note that the buttons can only wake the watch from STANDBY mode, at least as - * of the current SAM L22 silicon revision. The external interrupt controller runs in STANDBY - * mode, but it does not run in BACKUP mode; to wake from BACKUP, buttons will not cut it. - */ -/// @{ - -///@brief An enum defining the types of interrupt trigger you wish to scan for. -typedef enum watch_interrupt_trigger { - INTERRUPT_TRIGGER_NONE = 0, - INTERRUPT_TRIGGER_RISING, - INTERRUPT_TRIGGER_FALLING, - INTERRUPT_TRIGGER_BOTH, -} watch_interrupt_trigger; - -/// @brief Enables the external interrupt controller. -void watch_enable_external_interrupts(void); - -/// @brief Disables the external interrupt controller. -void watch_disable_external_interrupts(void); - -/** @brief Configures an external interrupt callback on one of the external interrupt pins. - * @details You can set one interrupt callback per pin, and you can monitor for a rising condition, - * a falling condition, or both. If you just want to detect a button press, register your - * interrupt with INTERRUPT_TRIGGER_RISING; if you want to detect an active-low interrupt - * signal from a device on the nine-pin connector, use INTERRUPT_TRIGGER_FALLING. If you - * want to detect both rising and falling conditions (i.e. button down and button up), use - * INTERRUPT_TRIGGER_BOTH and use watch_get_pin_level to check the pin level in your callback - * to determine which condition caused the interrupt. - * @param pin One of BTN_LIGHT, BTN_MODE, BTN_ALARM, A0, A1, A3 or A4. If the pin parameter matches one of - * the three button pins, this function will also enable an internal pull-down resistor. If - * the pin parameter is A0-A4, you are responsible for setting any required pull configuration - * using watch_enable_pull_up or watch_enable_pull_down. - * @param callback The function you wish to have called when the button is pressed. - * @param trigger The condition on which you wish to trigger: rising, falling or both. - * @note Pins A2 and A4 can also generate interrupts via the watch_register_extwake_callback function, which - * will allow them to trigger even when the watch is in deep sleep mode. - * @warning As of now, A2 is not usable via the watch_register_interrupt_callback function. To enable an - * external interrupt on pin A2, use the watch_register_extwake_callback function. This issue will be - * addressed in a future revision of the watch library. - */ -void watch_register_interrupt_callback(const uint8_t pin, ext_irq_cb_t callback, watch_interrupt_trigger trigger); - -__attribute__((deprecated("Use watch_register_interrupt_callback or watch_register_extwake_callback instead"))) -void watch_register_button_callback(const uint8_t pin, ext_irq_cb_t callback); - -__attribute__((deprecated("Use watch_enable_external_interrupts instead"))) -void watch_enable_buttons(void); -/// @} -#endif diff --git a/watch-library/watch/watch_gpio.c b/watch-library/watch/watch_gpio.c deleted file mode 100644 index b37d009f..00000000 --- a/watch-library/watch/watch_gpio.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "watch_gpio.h" - - void watch_enable_digital_input(const uint8_t pin) { - gpio_set_pin_direction(pin, GPIO_DIRECTION_IN); - gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF); -} - -void watch_disable_digital_input(const uint8_t pin) { - gpio_set_pin_direction(pin, GPIO_DIRECTION_OFF); - gpio_set_pin_pull_mode(pin, GPIO_PULL_OFF); - gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF); -} - -void watch_enable_pull_up(const uint8_t pin) { - gpio_set_pin_pull_mode(pin, GPIO_PULL_UP); -} - -void watch_enable_pull_down(const uint8_t pin) { - gpio_set_pin_pull_mode(pin, GPIO_PULL_DOWN); -} - -bool watch_get_pin_level(const uint8_t pin) { - return gpio_get_pin_level(pin); -} - -void watch_enable_digital_output(const uint8_t pin) { - gpio_set_pin_direction(pin, GPIO_DIRECTION_OUT); - gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF); -} - -void watch_disable_digital_output(const uint8_t pin) { - gpio_set_pin_direction(pin, GPIO_DIRECTION_OFF); -} - -void watch_set_pin_level(const uint8_t pin, const bool level) { - gpio_set_pin_level(pin, level); -} diff --git a/watch-library/watch/watch_gpio.h b/watch-library/watch/watch_gpio.h deleted file mode 100644 index fc43642c..00000000 --- a/watch-library/watch/watch_gpio.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef _WATCH_GPIO_H_INCLUDED -#define _WATCH_GPIO_H_INCLUDED -////< @file watch_gpio.h - -#include "watch.h" - -/** @addtogroup gpio Digital Input and Output - * @brief This section covers functions related to general-purpose input and output signals. - */ -/// @{ -/** @brief Configures the selected pin for digital input. - * @param pin The pin that you wish to act as an input. - */ -void watch_enable_digital_input(const uint8_t pin); - -/** @brief Disables any digital input, along with any pull-up or pull-down configuration. - * @param pin The pin that you wish to disable. - */ -void watch_disable_digital_input(const uint8_t pin); - -/** @brief Enables a pull-up resistor on the selected pin. - * @param pin The pin that you wish to configure. - */ -void watch_enable_pull_up(const uint8_t pin); - -/** @brief Enables a pull-down resistor on the selected pin. - * @param pin The pin that you wish to configure. - */ -void watch_enable_pull_down(const uint8_t pin); - -/** @brief Gets the level of the selected pin. - * @param pin The pin whose value you wish to read. - * @return true if the pin was logic high; otherwise, false. - */ -bool watch_get_pin_level(const uint8_t pin); - -/** @brief Configures the selected pin for digital output. - * @param pin The pin that you wish to act as an output. - */ -void watch_enable_digital_output(const uint8_t pin); - -/** @brief Disables digital output on the selected pin. - * @param pin The pin that you wish disable. - */ -void watch_disable_digital_output(const uint8_t pin); - -/** @brief Sets the level of the selected pin. - * @param pin The pin whose value you wish to set. - * @param level The level you wish to set: true for high, false for low. - */ -void watch_set_pin_level(const uint8_t pin, const bool level); -/// @} -#endif diff --git a/watch-library/watch/watch_i2c.c b/watch-library/watch/watch_i2c.c deleted file mode 100644 index ff20afc6..00000000 --- a/watch-library/watch/watch_i2c.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "watch_i2c.h" - -struct io_descriptor *I2C_0_io; - -void watch_enable_i2c(void) { - I2C_0_init(); - i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); - i2c_m_sync_enable(&I2C_0); -} - -void watch_disable_i2c(void) { - i2c_m_sync_disable(&I2C_0); - hri_mclk_clear_APBCMASK_SERCOM1_bit(MCLK); -} - -void watch_i2c_send(int16_t addr, uint8_t *buf, uint16_t length) { - i2c_m_sync_set_periphaddr(&I2C_0, addr, I2C_M_SEVEN); - io_write(I2C_0_io, buf, length); -} - -void watch_i2c_receive(int16_t addr, uint8_t *buf, uint16_t length) { - i2c_m_sync_set_periphaddr(&I2C_0, addr, I2C_M_SEVEN); - io_read(I2C_0_io, buf, length); -} - -void watch_i2c_write8(int16_t addr, uint8_t reg, uint8_t data) { - uint8_t buf[2]; - buf[0] = reg; - buf[1] = data; - - watch_i2c_send(addr, (uint8_t *)&buf, 2); -} - -uint8_t watch_i2c_read8(int16_t addr, uint8_t reg) { - uint8_t data; - - watch_i2c_send(addr, (uint8_t *)®, 1); - watch_i2c_receive(addr, (uint8_t *)&data, 1); - - return data; -} - -uint16_t watch_i2c_read16(int16_t addr, uint8_t reg) { - uint16_t data; - - watch_i2c_send(addr, (uint8_t *)®, 1); - watch_i2c_receive(addr, (uint8_t *)&data, 2); - - return data; -} - -uint32_t watch_i2c_read24(int16_t addr, uint8_t reg) { - uint32_t data; - data = 0; - - watch_i2c_send(addr, (uint8_t *)®, 1); - watch_i2c_receive(addr, (uint8_t *)&data, 3); - - return data << 8; -} - -uint32_t watch_i2c_read32(int16_t addr, uint8_t reg) { - uint32_t data; - - watch_i2c_send(addr, (uint8_t *)®, 1); - watch_i2c_receive(addr, (uint8_t *)&data, 4); - - return data; -} diff --git a/watch-library/watch/watch_i2c.h b/watch-library/watch/watch_i2c.h deleted file mode 100644 index fbcc1a92..00000000 --- a/watch-library/watch/watch_i2c.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef _WATCH_I2C_H_INCLUDED -#define _WATCH_I2C_H_INCLUDED -////< @file watch_i2c.h - -#include "watch.h" - -/** @addtogroup i2c I2C Controller Driver - * @brief This section covers functions related to the SAM L22's built-I2C driver, including - * configuring the I2C bus, putting values directly on the bus and reading data from - * registers on I2C devices. - */ -/// @{ -/** @brief Enables the I2C peripheral. Call this before attempting to interface with I2C devices. - */ -void watch_enable_i2c(void); - -/** @brief Disables the I2C peripheral. - */ -void watch_disable_i2c(void); - -/** @brief Sends a series of values to a device on the I2C bus. - * @param addr The address of the device you wish to talk to. - * @param buf A series of unsigned bytes; the data you wish to transmit. - * @param length The number of bytes in buf that you wish to send. - */ -void watch_i2c_send(int16_t addr, uint8_t *buf, uint16_t length); - -/** @brief Receives a series of values from a device on the I2C bus. - * @param addr The address of the device you wish to hear from. - * @param buf Storage for the incoming bytes; on return, it will contain the received data. - * @param length The number of bytes that you wish to receive. - */ -void watch_i2c_receive(int16_t addr, uint8_t *buf, uint16_t length); - -/** @brief Writes a byte to a register in an I2C device. - * @param addr The address of the device you wish to address. - * @param reg The register on the device that you wish to set. - * @param data The value that you wish to set the register to. - */ -void watch_i2c_write8(int16_t addr, uint8_t reg, uint8_t data); - -/** @brief Reads a byte from a register in an I2C device. - * @param addr The address of the device you wish to address. - * @param reg The register on the device that you wish to read. - * @return An unsigned byte representing the value of the register that was read. - */ -uint8_t watch_i2c_read8(int16_t addr, uint8_t reg); - -/** @brief Reads an unsigned little-endian word from a register in an I2C device. - * @param addr The address of the device you wish to address. - * @param reg The register on the device that you wish to read. - * @return An unsigned word representing the value of the register that was read. - * @note This reads two bytes into the word in bus order. If the device returns - the LSB first and then the MSB, you can use this value as returned. - If the device returns the data in big-endian order or uses some other - kind of fancy bit packing, you may need to shuffle some bits around. - */ -uint16_t watch_i2c_read16(int16_t addr, uint8_t reg); - -/** @brief Reads three bytes as an unsigned little-endian int from a register in an I2C device. - * @param addr The address of the device you wish to address. - * @param reg The register on the device that you wish to read. - * @return An unsigned word representing the value of the register that was read. - * @note This reads three bytes into the word in bus order. If the device returns - these bytes LSB first, you can use this value as returned. If there is a - sign bit, the device returns the data in big-endian order, or it uses some - other kind of fancy bit packing, you may need to shuffle some bits around. - */ -uint32_t watch_i2c_read24(int16_t addr, uint8_t reg); - - -/** @brief Reads an unsigned little-endian int from a register in an I2C device. - * @param addr The address of the device you wish to address. - * @param reg The register on the device that you wish to read. - * @return An unsigned word representing the value of the register that was read. - * @note This reads three bytes into the word in bus order. If the device returns - these bytes LSB first, you can use this value as returned. If the device - returns the data in big-endian order, or it uses some other kind of fancy - bit packing, you may need to shuffle some bits around. - */ -uint32_t watch_i2c_read32(int16_t addr, uint8_t reg); -/// @} -#endif diff --git a/watch-library/watch/watch_led.c b/watch-library/watch/watch_led.c deleted file mode 100644 index 52174b54..00000000 --- a/watch-library/watch/watch_led.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "watch_led.h" - -void watch_enable_leds(void) { - if (!hri_tcc_get_CTRLA_reg(TCC0, TCC_CTRLA_ENABLE)) { - _watch_enable_tcc(); - } -} - -void watch_disable_leds(void) { - _watch_disable_tcc(); -} - -void watch_enable_led(bool unused) { - (void)unused; - watch_enable_leds(); -} - -void watch_disable_led(bool unused) { - (void)unused; - watch_disable_leds(); -} - -void watch_set_led_color(uint8_t red, uint8_t green) { - if (hri_tcc_get_CTRLA_reg(TCC0, TCC_CTRLA_ENABLE)) { - uint32_t period = hri_tcc_get_PER_reg(TCC0, TCC_PER_MASK); - hri_tcc_write_CCBUF_reg(TCC0, WATCH_RED_TCC_CHANNEL, ((period * red * 1000ull) / 255000ull)); - hri_tcc_write_CCBUF_reg(TCC0, WATCH_GREEN_TCC_CHANNEL, ((period * green * 1000ull) / 255000ull)); - } -} - -void watch_set_led_red(void) { - watch_set_led_color(255, 0); -} - -void watch_set_led_green(void) { - watch_set_led_color(0, 255); -} - -void watch_set_led_yellow(void) { - watch_set_led_color(255, 255); -} - -void watch_set_led_off(void) { - watch_set_led_color(0, 0); -} diff --git a/watch-library/watch/watch_led.h b/watch-library/watch/watch_led.h deleted file mode 100644 index 9e9f5640..00000000 --- a/watch-library/watch/watch_led.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef _WATCH_LED_H_INCLUDED -#define _WATCH_LED_H_INCLUDED -////< @file watch_led.h - -#include "watch.h" - -/** @addtogroup led LED Control - * @brief This section covers functions related to the bi-color red/green LED mounted behind the LCD. - * @details The SAM L22 is an exceedingly power efficient chip, whereas the LED's are relatively power- - * hungry. The green LED, at full power, consumes more power than the whole chip in active mode, - * and the red LED consumes about twelve times as much power! The LED's should thus be used only - * sparingly in order to preserve battery life. - * @note Some watches use a red/blue LED instead of a red/green LED. You will be able to determine this - * easily when you double tap the reset button: if the pulsing bootloader LED is red, you have a - * red/green edition; if it is blue, you have a red/blue edition. For red/blue watches, build your - * project with the command `make LED=BLUE`, and the watch library will automatically swap the pins - * so that watch_set_led_red sets the red LED, and watch_set_led_green sets the blue one. - */ -/// @{ -/** @brief Enables the bi-color LED. - * @note The TCC peripheral that drives the LEDs does not run in STANDBY mode — but the outputs do! This - * means that if you set either red, green or both LEDs to full power, they will shine even when - * your app is asleep. If, however, you set a custom color using watch_set_led_color, the color will - * not display correctly in STANDBY mode. You will need to keep your app running while the LED is on. - */ -void watch_enable_leds(void); - -/** @brief Disables the LEDs. - * @note This method will also disable the buzzer, since the buzzer and LED both make use of the same - * peripheral to drive their PWM behavior. - */ -void watch_disable_leds(void); - -/** @brief Sets the LED to a custom color by modulating each output's duty cycle. - * @param red The red value from 0-255. - * @param green The green value from 0-255. If your watch has a red/blue LED, this will be the blue value. - * @note If you are displaying a custom color, you will need to prevent your app from going to sleep - * while the LED is on; otherwise, the color will not display correctly. You can do this by - * returning false in your app_loop method. - */ -void watch_set_led_color(uint8_t red, uint8_t green); - -/** @brief Sets the red LED to full brightness, and turns the green LED off. - * @details Of the two LED's in the RG bi-color LED, the red LED is the less power-efficient one (~4.5 mA). - */ -void watch_set_led_red(void); - -/** @brief Sets the green LED to full brightness, and turns the red LED off. - * @details Of the two LED's in the RG bi-color LED, the green LED is the more power-efficient one (~0.44 mA). - * @note If your watch has a red/blue LED, this method will set the LED to blue. - */ -void watch_set_led_green(void); - -/** @brief Sets both red and green LEDs to full brightness. - * @details The total current draw between the two LED's in this mode will be ~5 mA, which is more than the - * watch draws in any other mode. Take care not to drain the battery. - * @note If your watch has a red/blue LED, this method will set the LED to pink. - */ -void watch_set_led_yellow(void); - -/** @brief Turns both the red and the green LEDs off. */ -void watch_set_led_off(void); - -__attribute__((deprecated("Use watch_enable_leds instead"))) -void watch_enable_led(bool unused); - -__attribute__((deprecated("Use watch_disable_leds instead"))) -void watch_disable_led(bool unused); -/// @} -#endif diff --git a/watch-library/watch/watch_private.c b/watch-library/watch/watch_private.c deleted file mode 100644 index ae2589e7..00000000 --- a/watch-library/watch/watch_private.c +++ /dev/null @@ -1,423 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "watch_private.h" -#include "watch_utility.h" -#include "tusb.h" - -void _watch_init(void) { - // disable the LED pin (it may have been enabled by the bootloader) - watch_disable_digital_output(RED); - - // RAM should be back-biased in STANDBY - PM->STDBYCFG.bit.BBIASHS = 1; - - // Use switching regulator for lower power consumption. - SUPC->VREG.bit.SEL = 1; - while(!SUPC->STATUS.bit.VREGRDY); - - // set up the brownout detector (low battery warning) - NVIC_DisableIRQ(SYSTEM_IRQn); - NVIC_ClearPendingIRQ(SYSTEM_IRQn); - NVIC_EnableIRQ(SYSTEM_IRQn); - SUPC->BOD33.bit.ENABLE = 0; // BOD33 must be disabled to change its configuration - SUPC->BOD33.bit.VMON = 0; // Monitor VDD in active and standby mode - SUPC->BOD33.bit.ACTCFG = 1; // Enable sampling mode when active - SUPC->BOD33.bit.RUNSTDBY = 1; // Enable sampling mode in standby - SUPC->BOD33.bit.STDBYCFG = 1; // Run in standby - SUPC->BOD33.bit.RUNBKUP = 0; // Don't run in backup mode - SUPC->BOD33.bit.PSEL = 0xB; // Check battery level every 4 seconds - SUPC->BOD33.bit.LEVEL = 31; // Detect brownout at 2.5V (1.445V + level * 34mV) - SUPC->BOD33.bit.ACTION = 0x2; // Generate an interrupt when BOD33 is triggered - SUPC->BOD33.bit.HYST = 0; // Disable hysteresis - while(!SUPC->STATUS.bit.B33SRDY); - - // Enable interrupt on BOD33 detect - SUPC->INTENSET.bit.BOD33DET = 1; - SUPC->BOD33.bit.ENABLE = 1; - - // External wake depends on RTC; calendar is a required module. - _watch_rtc_init(); - - // set up state - btn_alarm_callback = NULL; - a2_callback = NULL; - a4_callback = NULL; -} - -static inline void _watch_wait_for_entropy() { - while (!hri_trng_get_INTFLAG_reg(TRNG, TRNG_INTFLAG_DATARDY)); -} - -// this function is called by arc4random to get entropy for random number generation. -// let's use the SAM L22's true random number generator to seed the PRNG! -int getentropy(void *buf, size_t buflen) { - hri_mclk_set_APBCMASK_TRNG_bit(MCLK); - hri_trng_set_CTRLA_ENABLE_bit(TRNG); - - size_t i = 0; - while(i < buflen / 4) { - _watch_wait_for_entropy(); - ((uint32_t *)buf)[i++] = hri_trng_read_DATA_reg(TRNG); - } - - // but what if they asked for an awkward number of bytes? - if (buflen % 4) { - // all good: let's fill in one, two or three bytes at the end of the buffer. - _watch_wait_for_entropy(); - uint32_t last_little_bit = hri_trng_read_DATA_reg(TRNG); - for(size_t j = 0; j <= (buflen % 4); j++) { - ((uint8_t *)buf)[i * 4 + j] = (last_little_bit >> (j * 8)) & 0xFF; - } - } - - hri_trng_clear_CTRLA_ENABLE_bit(TRNG); - hri_mclk_clear_APBCMASK_TRNG_bit(MCLK); - - return 0; -} - -int _gettimeofday(struct timeval *tv, void *tzvp) { - (void)tzvp; - watch_date_time date_time = watch_rtc_get_date_time(); - - // FIXME: this assumes the system time is UTC! Will break for any other time zone. - tv->tv_sec = watch_utility_date_time_to_unix_time(date_time, 0); - tv->tv_usec = 0; - - return 0; -} - -void _watch_enable_tcc(void) { - // clock TCC0 with the main clock (8 MHz) and enable the peripheral clock. - hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK0_Val | GCLK_PCHCTRL_CHEN); - hri_mclk_set_APBCMASK_TCC0_bit(MCLK); - // disable and reset TCC0. - hri_tcc_clear_CTRLA_ENABLE_bit(TCC0); - hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_ENABLE); - hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_SWRST); - hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_SWRST); - // divide the clock down to 1 MHz - if (hri_usbdevice_get_CTRLA_ENABLE_bit(USB)) { - // if USB is enabled, we are running an 8 MHz clock. - hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_PRESCALER_DIV8); - } else { - // otherwise it's 4 Mhz. - hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_PRESCALER_DIV4); - } - // We're going to use normal PWM mode, which means period is controlled by PER, and duty cycle is controlled by - // each compare channel's value: - // * Buzzer tones are set by setting PER to the desired period for a given frequency, and CC[1] to half of that - // period (i.e. a square wave with a 50% duty cycle). - // * LEDs on CC[2] and CC[3] can be set to any value from 0 (off) to PER (fully on). - hri_tcc_write_WAVE_reg(TCC0, TCC_WAVE_WAVEGEN_NPWM); - #ifdef WATCH_INVERT_LED_POLARITY - // This is here for the dev board, which uses a common anode LED (instead of common cathode like the actual watch). - hri_tcc_set_WAVE_reg(TCC0, (1 << (TCC_WAVE_POL0_Pos + WATCH_RED_TCC_CHANNEL)) | - (1 << (TCC_WAVE_POL0_Pos + WATCH_GREEN_TCC_CHANNEL))); - #endif - // The buzzer will set the period depending on the tone it wants to play, but we have to set some period here to - // get the LED working. Almost any period will do, tho it should be below 20000 (i.e. 50 Hz) to avoid flickering. - hri_tcc_write_PER_reg(TCC0, 4096); - // Set the duty cycle of all pins to 0: LED's off, buzzer not buzzing. - hri_tcc_write_CC_reg(TCC0, WATCH_BUZZER_TCC_CHANNEL, 0); - hri_tcc_write_CC_reg(TCC0, WATCH_RED_TCC_CHANNEL, 0); - hri_tcc_write_CC_reg(TCC0, WATCH_GREEN_TCC_CHANNEL, 0); - // Enable the TCC - hri_tcc_set_CTRLA_ENABLE_bit(TCC0); - hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_ENABLE); - - // enable LED PWM pins (the LED driver assumes if the TCC is on, the pins are enabled) - gpio_set_pin_direction(RED, GPIO_DIRECTION_OUT); - gpio_set_pin_function(RED, WATCH_RED_TCC_PINMUX); - gpio_set_pin_direction(GREEN, GPIO_DIRECTION_OUT); - gpio_set_pin_function(GREEN, WATCH_GREEN_TCC_PINMUX); -} - -void _watch_disable_tcc(void) { - // disable all PWM pins - gpio_set_pin_direction(BUZZER, GPIO_DIRECTION_OFF); - gpio_set_pin_function(BUZZER, GPIO_PIN_FUNCTION_OFF); - gpio_set_pin_direction(RED, GPIO_DIRECTION_OFF); - gpio_set_pin_function(RED, GPIO_PIN_FUNCTION_OFF); - gpio_set_pin_direction(GREEN, GPIO_DIRECTION_OFF); - gpio_set_pin_function(GREEN, GPIO_PIN_FUNCTION_OFF); - - // disable the TCC - hri_tcc_clear_CTRLA_ENABLE_bit(TCC0); - hri_mclk_clear_APBCMASK_TCC0_bit(MCLK); -} - -void _watch_enable_usb(void) { - // disable USB, just in case. - hri_usb_clear_CTRLA_ENABLE_bit(USB); - - // bump clock up to 8 MHz - hri_oscctrl_write_OSC16MCTRL_FSEL_bf(OSCCTRL, OSCCTRL_OSC16MCTRL_FSEL_8_Val); - - // reset flags and disable DFLL - OSCCTRL->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; - OSCCTRL->DFLLCTRL.reg = 0; - while (!(OSCCTRL->STATUS.reg & OSCCTRL_STATUS_DFLLRDY)); - - // set the coarse and fine values to speed up frequency lock. - uint32_t coarse =(*((uint32_t *)NVMCTRL_OTP5)) >> 26; - OSCCTRL->DFLLVAL.reg = OSCCTRL_DFLLVAL_COARSE(coarse) | - OSCCTRL_DFLLVAL_FINE(0x200); - // set coarse and fine steps, and multiplier (48 MHz = 32768 Hz * 1465) - OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_CSTEP( 1 ) | - OSCCTRL_DFLLMUL_FSTEP( 1 ) | - OSCCTRL_DFLLMUL_MUL( 1465 ); - // set closed loop mode, chill cycle disable and USB clock recovery mode, and enable the DFLL. - OSCCTRL->DFLLCTRL.reg = OSCCTRL_DFLLCTRL_MODE | OSCCTRL_DFLLCTRL_CCDIS | OSCCTRL_DFLLCTRL_ONDEMAND | OSCCTRL_DFLLCTRL_RUNSTDBY | OSCCTRL_DFLLCTRL_USBCRM | OSCCTRL_DFLLCTRL_ENABLE; - while (!(OSCCTRL->STATUS.reg & OSCCTRL_STATUS_DFLLRDY)); - - // assign DFLL to GCLK1 - GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL48M) | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;// | GCLK_GENCTRL_OE; - while (GCLK->SYNCBUSY.bit.GENCTRL1); - - // assign GCLK1 to USB - hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN); - hri_mclk_set_AHBMASK_USB_bit(MCLK); - hri_mclk_set_APBBMASK_USB_bit(MCLK); - - // USB Pin Init - gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); - gpio_set_pin_level(PIN_PA24, false); - gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); - gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); - gpio_set_pin_level(PIN_PA25, false); - gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); - - gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); - gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); - - // before we init TinyUSB, we are going to need a periodic callback to handle TinyUSB tasks. - // TC2 and TC3 are reserved for devices on the 9-pin connector, so let's use TC0. - // clock TC0 with the 8 MHz clock on GCLK0. - hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK0_Val | GCLK_PCHCTRL_CHEN); - // and enable the peripheral clock. - hri_mclk_set_APBCMASK_TC0_bit(MCLK); - // disable and reset TC0. - hri_tc_clear_CTRLA_ENABLE_bit(TC0); - hri_tc_wait_for_sync(TC0, TC_SYNCBUSY_ENABLE); - hri_tc_write_CTRLA_reg(TC0, TC_CTRLA_SWRST); - hri_tc_wait_for_sync(TC0, TC_SYNCBUSY_SWRST); - // configure the TC to overflow 1,000 times per second - hri_tc_write_CTRLA_reg(TC0, TC_CTRLA_PRESCALER_DIV64 | // divide the 8 MHz clock by 64 to count at 125 KHz - TC_CTRLA_MODE_COUNT8 | // count in 8-bit mode - TC_CTRLA_RUNSTDBY); // run in standby, just in case we figure that out - hri_tccount8_write_PER_reg(TC0, 125); // 125000 Hz / 125 = 1,000 Hz - // set an interrupt on overflow; this will call TC0_Handler below. - hri_tc_set_INTEN_OVF_bit(TC0); - NVIC_ClearPendingIRQ(TC0_IRQn); - NVIC_EnableIRQ (TC0_IRQn); - - // now we can init TinyUSB - tusb_init(); - // and start the timer that handles USB device tasks. - hri_tc_set_CTRLA_ENABLE_bit(TC0); -} - -// this function ends up getting called by printf to log stuff to the USB console. -int _write(int file, char *ptr, int len) { - (void)file; - if (hri_usbdevice_get_CTRLA_ENABLE_bit(USB)) { - tud_cdc_n_write(0, (void const*)ptr, len); - tud_cdc_n_write_flush(0); - return len; - } - - return 0; -} - -// this method could be overridden to read stuff from the USB console? but no need rn. -int _read(void) { - return 0; -} - -// Alternate function that outputs to the debug UART. useful for debugging USB issues. -// int _write(int file, char *ptr, int len) { -// (void)file; -// int pos = 0; -// while(pos < len) watch_debug_putc(ptr[pos++]); - -// return 0; -// } - -void USB_Handler(void) { - tud_int_handler(0); -} - -void TC0_Handler(void) { - tud_task(); - TC0->COUNT8.INTFLAG.reg |= TC_INTFLAG_OVF; -} - - -// USB Descriptors and tinyUSB callbacks follow. - -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - */ - -//--------------------------------------------------------------------+ -// Device Descriptors -//--------------------------------------------------------------------+ -tusb_desc_device_t const desc_device = -{ - .bLength = sizeof(tusb_desc_device_t), - .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, - - // Use Interface Association Descriptor (IAD) for CDC - // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) - .bDeviceClass = TUSB_CLASS_MISC, - .bDeviceSubClass = MISC_SUBCLASS_COMMON, - .bDeviceProtocol = MISC_PROTOCOL_IAD, - - .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - - .idVendor = 0x1209, - .idProduct = 0x2151, - .bcdDevice = 0x0100, - - .iManufacturer = 0x01, - .iProduct = 0x02, - .iSerialNumber = 0x03, - - .bNumConfigurations = 0x01 -}; - -// Invoked when received GET DEVICE DESCRIPTOR -// Application return pointer to descriptor -uint8_t const * tud_descriptor_device_cb(void) { - return (uint8_t const *) &desc_device; -} - -//--------------------------------------------------------------------+ -// Configuration Descriptor -//--------------------------------------------------------------------+ - -enum { - ITF_NUM_CDC = 0, - ITF_NUM_CDC_DATA, - ITF_NUM_TOTAL -}; - -#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN) - -#define EPNUM_CDC_NOTIF 0x81 -#define EPNUM_CDC_OUT 0x02 -#define EPNUM_CDC_IN 0x82 - - -uint8_t const desc_fs_configuration[] = { - // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), - - // Interface number, string index, EP notification address and size, EP data address (out, in) and size. - TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64), -}; - -// Invoked when received GET CONFIGURATION DESCRIPTOR -// Application return pointer to descriptor -// Descriptor contents must exist long enough for transfer to complete -uint8_t const * tud_descriptor_configuration_cb(uint8_t index) { - (void) index; // for multiple configurations - return desc_fs_configuration; -} - -//--------------------------------------------------------------------+ -// String Descriptors -//--------------------------------------------------------------------+ - -// array of pointer to string descriptors -char const* string_desc_arr [] = -{ - (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) - "TinyUSB", // 1: Manufacturer - "TinyUSB Device", // 2: Product - "123456", // 3: Serials, should use chip ID - "TinyUSB CDC", // 4: CDC Interface -}; - -static uint16_t _desc_str[32]; - -// Invoked when received GET STRING DESCRIPTOR request -// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete -uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) -{ - (void) langid; - - uint8_t chr_count; - - if ( index == 0) { - memcpy(&_desc_str[1], string_desc_arr[0], 2); - chr_count = 1; - } else { - // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. - // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors - - if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL; - - const char* str = string_desc_arr[index]; - - // Cap at max char - chr_count = strlen(str); - if ( chr_count > 31 ) chr_count = 31; - - // Convert ASCII string into UTF-16 - for(uint8_t i=0; iMODE2.CTRLA.bit.ENABLE; -} - -static void _sync_rtc(void) { - while (RTC->MODE2.SYNCBUSY.reg); -} - -void _watch_rtc_init(void) { - MCLK->APBAMASK.reg |= MCLK_APBAMASK_RTC; - - if (_watch_rtc_is_enabled()) return; // don't reset the RTC if it's already set up. - - RTC->MODE2.CTRLA.bit.ENABLE = 0; - _sync_rtc(); - - RTC->MODE2.CTRLA.bit.SWRST = 1; - _sync_rtc(); - - RTC->MODE2.CTRLA.bit.MODE = RTC_MODE2_CTRLA_MODE_CLOCK_Val; - RTC->MODE2.CTRLA.bit.PRESCALER = RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val; - RTC->MODE2.CTRLA.bit.CLOCKSYNC = 1; - RTC->MODE2.CTRLA.bit.ENABLE = 1; - _sync_rtc(); -} - -void watch_rtc_set_date_time(watch_date_time date_time) { - RTC->MODE2.CLOCK.reg = date_time.reg; - _sync_rtc(); -} - -watch_date_time watch_rtc_get_date_time(void) { - watch_date_time retval; - - _sync_rtc(); - retval.reg = RTC->MODE2.CLOCK.reg; - - return retval; -} - -void watch_rtc_register_tick_callback(ext_irq_cb_t callback) { - watch_rtc_register_periodic_callback(callback, 1); -} - -void watch_rtc_disable_tick_callback(void) { - watch_rtc_disable_periodic_callback(1); -} - -void watch_rtc_register_periodic_callback(ext_irq_cb_t callback, uint8_t frequency) { - // we told them, it has to be a power of 2. - if (__builtin_popcount(frequency) != 1) return; - - // this left-justifies the period in a 32-bit integer. - uint32_t tmp = frequency << 24; - // now we can count the leading zeroes to get the value we need. - // 0x01 (1 Hz) will have 7 leading zeros for PER7. 0xF0 (128 Hz) will have no leading zeroes for PER0. - uint8_t per_n = __builtin_clz(tmp); - - // this also maps nicely to an index for our list of tick callbacks. - tick_callbacks[per_n] = callback; - - NVIC_ClearPendingIRQ(RTC_IRQn); - NVIC_EnableIRQ(RTC_IRQn); - RTC->MODE2.INTENSET.reg = 1 << per_n; -} - -void watch_rtc_disable_periodic_callback(uint8_t frequency) { - if (__builtin_popcount(frequency) != 1) return; - uint8_t per_n = __builtin_clz(frequency << 24); - RTC->MODE2.INTENCLR.reg = 1 << per_n; -} - -void watch_rtc_disable_all_periodic_callbacks(void) { - RTC->MODE2.INTENCLR.reg = 0xFF; -} - -void watch_rtc_register_alarm_callback(ext_irq_cb_t callback, watch_date_time alarm_time, watch_rtc_alarm_match mask) { - RTC->MODE2.Mode2Alarm[0].ALARM.reg = alarm_time.reg; - RTC->MODE2.Mode2Alarm[0].MASK.reg = mask; - RTC->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; - alarm_callback = callback; - NVIC_ClearPendingIRQ(RTC_IRQn); - NVIC_EnableIRQ(RTC_IRQn); - RTC->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; -} - -void watch_rtc_disable_alarm_callback(void) { - RTC->MODE2.INTENCLR.reg = RTC_MODE2_INTENCLR_ALARM0; -} - -void RTC_Handler(void) { - uint16_t interrupt_status = RTC->MODE2.INTFLAG.reg; - uint16_t interrupt_enabled = RTC->MODE2.INTENSET.reg; - - if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_PER_Msk) { - // handle the tick callback first, it's what we do the most. - // start from PER7, the 1 Hz tick. - for(int8_t i = 7; i >= 0; i--) { - if ((interrupt_status & interrupt_enabled) & (1 << i)) { - if (tick_callbacks[i] != NULL) { - tick_callbacks[i](); - } - RTC->MODE2.INTFLAG.reg = 1 << i; - break; - } - } - } else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) { - // handle the extwake interrupts next. - uint8_t reason = RTC->MODE2.TAMPID.reg; - if (reason & RTC_TAMPID_TAMPID2) { - if (btn_alarm_callback != NULL) btn_alarm_callback(); - } else if (reason & RTC_TAMPID_TAMPID1) { - if (a2_callback != NULL) a2_callback(); - } else if (reason & RTC_TAMPID_TAMPID0) { - if (a4_callback != NULL) a4_callback(); - } - RTC->MODE2.TAMPID.reg = reason; - RTC->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; - } else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_ALARM0) { - // finally handle the alarm. - if (alarm_callback != NULL) { - alarm_callback(); - } - RTC->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; - } -} - -/////////////////////// -// Deprecated functions - -void watch_set_date_time(struct calendar_date_time date_time) { - RTC_MODE2_CLOCK_Type val; - - val.bit.SECOND = date_time.time.sec; - val.bit.MINUTE = date_time.time.min; - val.bit.HOUR = date_time.time.hour; - val.bit.DAY = date_time.date.day; - val.bit.MONTH = date_time.date.month; - val.bit.YEAR = (uint8_t)(date_time.date.year - WATCH_RTC_REFERENCE_YEAR); - - RTC->MODE2.CLOCK.reg = val.reg; - - _sync_rtc(); -} - -void watch_get_date_time(struct calendar_date_time *date_time) { - _sync_rtc(); - RTC_MODE2_CLOCK_Type val = RTC->MODE2.CLOCK; - - date_time->time.sec = val.bit.SECOND; - date_time->time.min = val.bit.MINUTE; - date_time->time.hour = val.bit.HOUR; - date_time->date.day = val.bit.DAY; - date_time->date.month = val.bit.MONTH; - date_time->date.year = val.bit.YEAR + WATCH_RTC_REFERENCE_YEAR; -} - -void watch_register_tick_callback(ext_irq_cb_t callback) { - tick_callbacks[7] = callback; - NVIC_ClearPendingIRQ(RTC_IRQn); - NVIC_EnableIRQ(RTC_IRQn); - RTC->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; -} diff --git a/watch-library/watch/watch_rtc.h b/watch-library/watch/watch_rtc.h deleted file mode 100644 index 6dac63f5..00000000 --- a/watch-library/watch/watch_rtc.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef _WATCH_RTC_H_INCLUDED -#define _WATCH_RTC_H_INCLUDED -////< @file watch_rtc.h - -#include "watch.h" -#include "hpl_calendar.h" - -/** @addtogroup rtc Real-Time Clock - * @brief This section covers functions related to the SAM L22's real-time clock peripheral, including - * date, time and alarm functions. - * @details The real-time clock is the only peripheral that main.c enables for you. It is the cornerstone - * of low power operation on the watch, and it is required for several key functions that we - * assume will be available, namely the wake from BACKUP mode and the callback on the ALARM button. - * It is also required for the operation of the 1 Hz tick interrupt, which you will most likely use - * to wake from STANDBY mode. - */ -/// @{ - -#define WATCH_RTC_REFERENCE_YEAR (2020) - -typedef union { - struct { - uint32_t second : 6; // 0-59 - uint32_t minute : 6; // 0-59 - uint32_t hour : 5; // 0-23 - uint32_t day : 5; // 1-31 - uint32_t month : 4; // 1-12 - uint32_t year : 6; // 0-63 (representing 2020-2083) - } unit; - uint32_t reg; // the bit-packed value as expected by the RTC peripheral's CLOCK register. -} watch_date_time; - -typedef enum watch_rtc_alarm_match { - ALARM_MATCH_DISABLED = 0, - ALARM_MATCH_SS, - ALARM_MATCH_MMSS, - ALARM_MATCH_HHMMSS, -} watch_rtc_alarm_match; - -/** @brief Called by main.c to check if the RTC is enabled. - * You may call this function, but outside of app_init, it should always return true. - */ -bool _watch_rtc_is_enabled(void); - -/** @brief Sets the date and time. - * @param date_time The date and time you wish to set, with a year value from 0-63 representing 2020-2083. - * @note The SAM L22 stores the year as six bits representing a value from 0 to 63. It treats this as a year - * offset from a reference year, which must be a leap year. Since 2020 was a leap year, and it allows - * useful dates through 2083, it is assumed that watch apps will use 2020 as the reference year; thus - * 1 means 2021, 2 means 2022, etc. **You will be responsible for handling this offset in your code**, - * if the calendar year is needed for timestamp calculation logic or display purposes. - */ -void watch_rtc_set_date_time(watch_date_time date_time); - -/** @brief Returns the date and time. - * @return A watch_date_time with the current date and time, with a year value from 0-63 representing 2020-2083. - * @see watch_rtc_set_date_time for notes about how the year is stored. - */ -watch_date_time watch_rtc_get_date_time(void); - -/** @brief Registers an alarm callback that will be called when the RTC time matches the target time, as masked - * by the provided mask. - * @param callback The function you wish to have called when the alarm fires. If this value is NULL, the alarm - * interrupt will still be enabled, but no callback function will be called. - * @param alarm_time The time that you wish to match. The date is currently ignored. - * @param mask One of the values in watch_rtc_alarm_match indicating which values to check. - * @details The alarm interrupt is a versatile tool for scheduling events in the future, especially since it can - * wake the device from all sleep modes. The key to its versatility is the mask parameter. - * Suppose we set an alarm for midnight, 00:00:00. - * * if mask is ALARM_MATCH_SS, the alarm will fire every minute when the clock ticks to seconds == 0. - * * with ALARM_MATCH_MMSS, the alarm will once an hour, at the top of each hour. - * * with ALARM_MATCH_HHMMSS, the alarm will fire at midnight every day. - * In theory the SAM L22's alarm function can match on days, months and even years, but I have not had - * success with this yet; as such, I am omitting these options for now. - */ -void watch_rtc_register_alarm_callback(ext_irq_cb_t callback, watch_date_time alarm_time, watch_rtc_alarm_match mask); - -/** @brief Disables the alarm callback. - */ -void watch_rtc_disable_alarm_callback(void); - -/** @brief Registers a "tick" callback that will be called once per second. - * @param callback The function you wish to have called when the clock ticks. If you pass in NULL, the tick - * interrupt will still be enabled, but no callback function will be called. - * @note this is equivalent to calling watch_rtc_register_periodic_callback with a frequency of 1. It can be - * disabled with either watch_rtc_disable_tick_callback() or watch_rtc_disable_periodic_callback(1), - * and will also be disabled when watch_rtc_disable_all_periodic_callbacks is called. - */ -void watch_rtc_register_tick_callback(ext_irq_cb_t callback); - -/** @brief Disables the tick callback for the given period. - */ -void watch_rtc_disable_tick_callback(void); - -/** @brief Registers a callback that will be called at a configurable period. - * @param callback The function you wish to have called at the specified period. If you pass in NULL, the periodic - * interrupt will still be enabled, but no callback function will be called. - * @param frequency The frequency of the tick in Hz. **Must be a power of 2**, from 1 to 128 inclusive. - * @note A 1 Hz tick (@see watch_rtc_register_tick_callback) is suitable for most applications, in that it gives you a - * chance to update the display once a second — an ideal update rate for a watch! If however you are displaying - * a value (such as an accelerometer output) that updates more frequently than once per second, you may want to - * tick at 16 or 32 Hz to update the screen more quickly. Just remember that the more frequent the tick, the more - * power your app will consume. Ideally you should enable the fast tick only when the user requires it (i.e. in - * response to an input event), and move back to the slow tick after some time. - * - * Also note that the RTC peripheral does not have sub-second resolution, so even if you set a 2 or 4 Hz interval, - * the system will not have any way of telling you where you are within a given second; watch_rtc_get_date_time - * will return the exact same timestamp until the second ticks over. - */ -void watch_rtc_register_periodic_callback(ext_irq_cb_t callback, uint8_t frequency); - -/** @brief Disables the tick callback for the given period. - * @param frequency The frequency of the tick you wish to disable, in Hz. **Must be a power of 2**, from 1 to 128. - */ -void watch_rtc_disable_periodic_callback(uint8_t frequency); - -/** @brief Disables all periodic callbacks, including the once-per-second tick callback. - */ -void watch_rtc_disable_all_periodic_callbacks(void); - -/** @brief Sets the system date and time. - * @param date_time A struct representing the date and time you wish to set. - */ -__attribute__((deprecated("Use watch_rtc_set_date_time function instead"))) -void watch_set_date_time(struct calendar_date_time date_time); - -/** @brief Returns the system date and time in the provided struct. - * @param date_time A pointer to a calendar_date_time struct. It will have with the correct date and time on return. - */ -__attribute__((deprecated("Use the watch_rtc_get_date_time function instead"))) -void watch_get_date_time(struct calendar_date_time *date_time); - -/** @brief Registers a "tick" callback that will be called once per second. - * @param callback The function you wish to have called when the clock ticks. If you pass in NULL, the tick - * interrupt will still be enabled, but no callback function will be called. - */ -__attribute__((deprecated("Use the watch_rtc_register_tick_callback function instead"))) -void watch_register_tick_callback(ext_irq_cb_t callback); - -/// @} -#endif diff --git a/watch-library/watch/watch_slcd.c b/watch-library/watch/watch_slcd.c deleted file mode 100644 index 1b1e53e4..00000000 --- a/watch-library/watch/watch_slcd.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "watch_slcd.h" -#include "hpl_slcd_config.h" - - ////////////////////////////////////////////////////////////////////////////////////////// -// Segmented Display - -static const uint8_t Character_Set[] = -{ - 0b00000000, // - 0b01100000, // ! (L in the top half for positions 4 and 6) - 0b00100010, // " - 0b01100011, // # (degree symbol, hash mark doesn't fit) - 0b00000000, // $ (unused) - 0b00000000, // % (unused) - 0b01000100, // & ("lowercase 7" for positions 4 and 6) - 0b00100000, // ' - 0b00111001, // ( - 0b00001111, // ) - 0b00000000, // * (unused) - 0b11000000, // + (only works in position 0) - 0b00000100, // , - 0b01000000, // - - 0b01000000, // . (same as -, semantically most useful) - 0b00010010, // / - 0b00111111, // 0 - 0b00000110, // 1 - 0b01011011, // 2 - 0b01001111, // 3 - 0b01100110, // 4 - 0b01101101, // 5 - 0b01111101, // 6 - 0b00000111, // 7 - 0b01111111, // 8 - 0b01101111, // 9 - 0b00000000, // : (unused) - 0b00000000, // ; (unused) - 0b01011000, // < - 0b01001000, // = - 0b01001100, // > - 0b01010011, // ? - 0b11111111, // @ (all segments on) - 0b01110111, // A - 0b01111111, // B - 0b00111001, // C - 0b00111111, // D - 0b01111001, // E - 0b01110001, // F - 0b00111101, // G - 0b01110110, // H - 0b10001001, // I (only works in position 0) - 0b00001110, // J - 0b01110101, // K - 0b00111000, // L - 0b10110111, // M (only works in position 0) - 0b00110111, // N - 0b00111111, // O - 0b01110011, // P - 0b01100111, // Q - 0b11110111, // R (only works in position 1) - 0b01101101, // S - 0b10000001, // T (only works in position 0; set (1, 12) to make it work in position 1) - 0b00111110, // U - 0b00111110, // V - 0b10111110, // W (only works in position 0) - 0b01111110, // X - 0b01101110, // Y - 0b00011011, // Z - 0b00111001, // [ - 0b00100100, // backslash - 0b00001111, // ] - 0b00100011, // ^ - 0b00001000, // _ - 0b00000010, // ` - 0b01011111, // a - 0b01111100, // b - 0b01011000, // c - 0b01011110, // d - 0b01111011, // e - 0b01110001, // f - 0b01101111, // g - 0b01110100, // h - 0b00010000, // i - 0b01000010, // j (appears as superscript to work in more positions) - 0b01110101, // k - 0b00110000, // l - 0b10110111, // m (only works in position 0) - 0b01010100, // n - 0b01011100, // o - 0b01110011, // p - 0b01100111, // q - 0b01010000, // r - 0b01101101, // s - 0b01111000, // t - 0b01100010, // u (appears in (u)pper half to work in more positions) - 0b00011100, // v (looks like u but in the lower half) - 0b10111110, // w (only works in position 0) - 0b01111110, // x - 0b01101110, // y - 0b00011011, // z - 0b00111001, // { - 0b00110000, // | - 0b00001111, // } - 0b00000001, // ~ -}; - -static const uint64_t Segment_Map[] = { - 0x4e4f0e8e8f8d4d0d, // Position 0, mode - 0xc8c4c4c8b4b4b0b, // Position 1, mode (Segments B and C shared, as are segments E and F) - 0xc049c00a49890949, // Position 2, day of month (Segments A, D, G shared; missing segment F) - 0xc048088886874707, // Position 3, day of month - 0xc053921252139352, // Position 4, clock hours (Segments A and D shared) - 0xc054511415559594, // Position 5, clock hours - 0xc057965616179716, // Position 6, clock minutes (Segments A and D shared) - 0xc041804000018a81, // Position 7, clock minutes - 0xc043420203048382, // Position 8, clock seconds - 0xc045440506468584, // Position 9, clock seconds -}; - -static const uint8_t Num_Chars = 10; - -static const uint32_t IndicatorSegments[6] = { - SLCD_SEGID(0, 17), // WATCH_INDICATOR_SIGNAL - SLCD_SEGID(0, 16), // WATCH_INDICATOR_BELL - SLCD_SEGID(2, 17), // WATCH_INDICATOR_PM - SLCD_SEGID(2, 16), // WATCH_INDICATOR_24H - SLCD_SEGID(1, 10), // WATCH_INDICATOR_LAP -}; - -static void _sync_slcd(void) { - while (SLCD->SYNCBUSY.reg); -} - -void watch_enable_display(void) { - SEGMENT_LCD_0_init(); - slcd_sync_enable(&SEGMENT_LCD_0); -} - -inline void watch_set_pixel(uint8_t com, uint8_t seg) { - slcd_sync_seg_on(&SEGMENT_LCD_0, SLCD_SEGID(com, seg)); -} - -inline void watch_clear_pixel(uint8_t com, uint8_t seg) { - slcd_sync_seg_off(&SEGMENT_LCD_0, SLCD_SEGID(com, seg)); -} - -void watch_clear_display(void) { - SLCD->SDATAL0.reg = 0; - SLCD->SDATAL1.reg = 0; - SLCD->SDATAL2.reg = 0; -} - -static void watch_display_character(uint8_t character, uint8_t position) { - // special cases for positions 4 and 6 - if (position == 4 || position == 6) { - if (character == '7') character = '&'; // "lowercase" 7 - else if (character == 'A') character = 'a'; // A needs to be lowercase - else if (character == 'o') character = 'O'; // O needs to be uppercase - else if (character == 'L') character = '!'; // L needs to be in top half - else if (character == 'M' || character == 'm' || character == 'N') character = 'n'; // M and uppercase N need to be lowercase n - else if (character == 'c') character = 'C'; // C needs to be uppercase - else if (character == 'J') character = 'j'; // same - else if (character == 'v' || character == 'V' || character == 'U' || character == 'W' || character == 'w') character = 'u'; // bottom segment duplicated, so show in top half - } else { - if (character == 'u') character = 'v'; // we can use the bottom segment; move to lower half - else if (character == 'j') character = 'J'; // same but just display a normal J - } - if (position > 1) { - if (character == 'T') character = 't'; // uppercase T only works in positions 0 and 1 - } - if (position == 1) { - if (character == 'o') character = 'O'; // O needs to be uppercase - if (character == 'i') character = 'l'; // I needs to be uppercase (use an l, it looks the same) - if (character == 'n') character = 'N'; // N needs to be uppercase - if (character == 'r') character = 'R'; // R needs to be uppercase - if (character == 'd') character = 'D'; // D needs to be uppercase - if (character == 'v' || character == 'V' || character == 'u') character = 'U'; // side segments shared, make uppercase - if (character == 'b') character = 'B'; // B needs to be uppercase - if (character == 'c') character = 'C'; // C needs to be uppercase - } else { - if (character == 'R') character = 'r'; // R needs to be lowercase almost everywhere - } - if (position == 0) { - slcd_sync_seg_off(&SEGMENT_LCD_0, SLCD_SEGID(0, 15)); // clear funky ninth segment - } else { - if (character == 'I') character = 'l'; // uppercase I only works in position 0 - } - - uint64_t segmap = Segment_Map[position]; - uint64_t segdata = Character_Set[character - 0x20]; - - for (int i = 0; i < 8; i++) { - uint8_t com = (segmap & 0xFF) >> 6; - if (com > 2) { - // COM3 means no segment exists; skip it. - segmap = segmap >> 8; - segdata = segdata >> 1; - continue; - } - uint8_t seg = segmap & 0x3F; - slcd_sync_seg_off(&SEGMENT_LCD_0, SLCD_SEGID(com, seg)); - if (segdata & 1) slcd_sync_seg_on(&SEGMENT_LCD_0, SLCD_SEGID(com, seg)); - segmap = segmap >> 8; - segdata = segdata >> 1; - } - if (character == 'T' && position == 1) slcd_sync_seg_on(&SEGMENT_LCD_0, SLCD_SEGID(1, 12)); // add descender - else if (position == 0 && (character == 'B' || character == 'D')) slcd_sync_seg_on(&SEGMENT_LCD_0, SLCD_SEGID(0, 15)); // add funky ninth segment - else if (position == 1 && (character == 'B' || character == 'D' || character == '@')) slcd_sync_seg_on(&SEGMENT_LCD_0, SLCD_SEGID(0, 12)); // add funky ninth segment -} - -void watch_display_string(char *string, uint8_t position) { - size_t i = 0; - while(string[i] != 0) { - watch_display_character(string[i], position + i); - i++; - if (position + i >= Num_Chars) break; - } - // uncomment this line to see screen output on terminal, i.e. - // FR 29 - // 11 50 23 - // note that for partial displays (positon > 0) it will only show the characters that were updated. - // printf("________\n %c%c %c%c\n%c%c %c%c %c%c\n--------\n", (position > 0) ? ' ' : string[0], (position > 1) ? ' ' : string[1 - position], (position > 2) ? ' ' : string[2 - position], (position > 3) ? ' ' : string[3 - position], (position > 4) ? ' ' : string[4 - position], (position > 5) ? ' ' : string[5 - position], (position > 6) ? ' ' : string[6 - position], (position > 7) ? ' ' : string[7 - position], (position > 8) ? ' ' : string[8 - position], (position > 9) ? ' ' : string[9 - position]); -} - -inline void watch_set_colon(void) { - slcd_sync_seg_on(&SEGMENT_LCD_0, SLCD_SEGID(1, 16)); -} - -inline void watch_clear_colon(void) { - slcd_sync_seg_off(&SEGMENT_LCD_0, SLCD_SEGID(1, 16)); -} - -inline void watch_set_indicator(WatchIndicatorSegment indicator) { - slcd_sync_seg_on(&SEGMENT_LCD_0, IndicatorSegments[indicator]); -} - -inline void watch_clear_indicator(WatchIndicatorSegment indicator) { - slcd_sync_seg_off(&SEGMENT_LCD_0, IndicatorSegments[indicator]); -} - -void watch_clear_all_indicators(void) { - slcd_sync_seg_off(&SEGMENT_LCD_0, SLCD_SEGID(2, 17)); - slcd_sync_seg_off(&SEGMENT_LCD_0, SLCD_SEGID(2, 16)); - slcd_sync_seg_off(&SEGMENT_LCD_0, SLCD_SEGID(0, 17)); - slcd_sync_seg_off(&SEGMENT_LCD_0, SLCD_SEGID(0, 16)); - slcd_sync_seg_off(&SEGMENT_LCD_0, SLCD_SEGID(1, 10)); -} - -void watch_start_character_blink(char character, uint32_t duration) { - SLCD->CTRLD.bit.FC0EN = 0; - _sync_slcd(); - - if (duration <= SLCD_FC_BYPASS_MAX_MS) { - SLCD->FC0.reg = SLCD_FC0_PB | ((duration / (1000 / SLCD_FRAME_FREQUENCY)) - 1); - } else { - SLCD->FC0.reg = (((duration / (1000 / SLCD_FRAME_FREQUENCY)) / 8 - 1)); - } - SLCD->CTRLD.bit.FC0EN = 1; - - watch_display_character(character, 7); - watch_clear_pixel(2, 10); // clear segment B of position 7 since it can't blink - - SLCD->CTRLD.bit.BLINK = 0; - SLCD->CTRLA.bit.ENABLE = 0; - _sync_slcd(); - - SLCD->BCFG.bit.BSS0 = 0x07; - SLCD->BCFG.bit.BSS1 = 0x07; - - SLCD->CTRLD.bit.BLINK = 1; - _sync_slcd(); - SLCD->CTRLA.bit.ENABLE = 1; - _sync_slcd(); -} - -void watch_stop_blink(void) { - SLCD->CTRLD.bit.FC0EN = 0; - SLCD->CTRLD.bit.BLINK = 0; -} - -void watch_start_tick_animation(uint32_t duration) { - watch_display_character(' ', 8); - const uint32_t segs[] = { SLCD_SEGID(0, 2)}; - slcd_sync_start_animation(&SEGMENT_LCD_0, segs, 1, duration); -} - -bool watch_tick_animation_is_running(void) { - return hri_slcd_get_CTRLD_CSREN_bit(SLCD); -} - -void watch_stop_tick_animation(void) { - const uint32_t segs[] = { SLCD_SEGID(0, 2)}; - slcd_sync_stop_animation(&SEGMENT_LCD_0, segs, 1); - watch_display_character(' ', 8); -} diff --git a/watch-library/watch/watch_slcd.h b/watch-library/watch/watch_slcd.h deleted file mode 100644 index 3f550bb0..00000000 --- a/watch-library/watch/watch_slcd.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef _WATCH_SLCD_H_INCLUDED -#define _WATCH_SLCD_H_INCLUDED -////< @file watch_slcd.h - -#include "watch.h" - -/** @addtogroup slcd Segment LCD Display - * @brief This section covers functions related to the Segment LCD display driver, which is responsible - * for displaying strings of characters and indicators on the main watch display. - * @details The segment LCD controller consumes about 3 microamperes of power with no segments on, and - * about 4 microamperes with all segments on. There is also a slight power impact associated - * with updating the screen (about 1 microampere to update at 1 Hz). For the absolute lowest - * power operation, update the display only when its contents have changed, and disable the - * SLCD peripheral when the screen is not in use. - * For a map of all common and segment pins, see segmap.html. You can - * hover over any segment in that diagram to view the common and segment pins associated with - * each segment of the display. - */ -/// @{ - -/// An enum listing the icons and indicators available on the watch. -typedef enum WatchIndicatorSegment { - WATCH_INDICATOR_SIGNAL = 0, ///< The hourly signal indicator; also useful for indicating that sensors are on. - WATCH_INDICATOR_BELL, ///< The small bell indicating that an alarm is set. - WATCH_INDICATOR_PM, ///< The PM indicator, indicating that a time is in the afternoon. - WATCH_INDICATOR_24H, ///< The 24H indicator, indicating that the watch is in a 24-hour mode. - WATCH_INDICATOR_LAP ///< The LAP indicator; the F-91W uses this in its stopwatch UI. -} WatchIndicatorSegment; - -/** @brief Enables the Segment LCD display. - * Call this before attempting to set pixels or display strings. - */ -void watch_enable_display(void); - -/** @brief Sets a pixel. Use this to manually set a pixel with a given common and segment number. - * See segmap.html. - * @param com the common pin, numbered from 0-2. - * @param seg the segment pin, numbered from 0-23. - */ -void watch_set_pixel(uint8_t com, uint8_t seg); - -/** @brief Clears a pixel. Use this to manually clear a pixel with a given common and segment number. - * See segmap.html. - * @param com the common pin, numbered from 0-2. - * @param seg the segment pin, numbered from 0-23. - */ -void watch_clear_pixel(uint8_t com, uint8_t seg); - -/** @brief Clears all segments of the display, including incicators and the colon. - */ -void watch_clear_display(void); - -/** @brief Displays a string at the given position, starting from the top left. There are ten digits. - A space in any position will clear that digit. - * @param string A null-terminated string. - * @param position The position where you wish to start displaying the string. The day of week digits - * are positions 0 and 1; the day of month digits are positions 2 and 3, and the main - * clock line occupies positions 4-9. - * @note This method does not clear the display; if for example you display a two-character string at - position 0, positions 2-9 will retain whatever state they were previously displaying. - */ -void watch_display_string(char *string, uint8_t position); - -/** @brief Turns the colon segment on. - */ -void watch_set_colon(void); - -/** @brief Turns the colon segment off. - */ -void watch_clear_colon(void); - -/** @brief Sets an indicator on the LCD. Use this to turn on one of the indicator segments. - * @param indicator One of the indicator segments from the enum. @see WatchIndicatorSegment - */ -void watch_set_indicator(WatchIndicatorSegment indicator); - -/** @brief Clears an indicator on the LCD. Use this to turn off one of the indicator segments. - * @param indicator One of the indicator segments from the enum. @see WatchIndicatorSegment - */ -void watch_clear_indicator(WatchIndicatorSegment indicator); - -/** @brief Clears all indicator segments. - * @see WatchIndicatorSegment - */ -void watch_clear_all_indicators(void); - -/** @brief Blinks a single character in position 7. Does not affect other positions. - * @details Six of the seven segments in position 7 (and only position 7) are capable of autonomous - * blinking. This blinking does not require any CPU resources, and will continue even in - * STANDBY and Sleep mode (but not Deep Sleep mode, since that mode turns off the LCD). - * @param character The character you wish to blink. - * @param duration The duration of the on/off cycle in milliseconds, from 50 to ~4250 ms. - * @note Segment B of position 7 cannot blink autonomously, so not all characters will work well. - * Supported characters for blinking: - * * Punctuation: underscore, apostrophe, comma, hyphen, equals sign, tilde (top segment only) - * * Numbers: 5, 6, ampersand (lowercase 7) - * * Letters: b, C, c, E, F, h, i, L, l, n, o, S, t - */ -void watch_start_character_blink(char character, uint32_t duration); - -/** @brief Stops and clears all blinking segments. - * @details This will stop all blinking in position 7, and clear all segments in that digit. - */ -void watch_stop_blink(void); - -/** @brief Begins a two-segment "tick-tock" animation in position 8. - * @details Six of the seven segments in position 8 (and only position 8) are capable of autonomous - * animation. This animation is very basic, and consists of moving a bit pattern forward - * or backward in a shift register whose positions map to fixed segments on the LCD. Given - * this constraint, an animation across all six segments does not make sense; so the watch - * library offers only a simple "tick/tock" in segments D and E. This animation does not - * require any CPU resources, and will continue even in STANDBY and Sleep mode (but not Deep - * Sleep mode, since that mode turns off the LCD). - * @param duration The duration of each frame in ms. 500 milliseconds produces a classic tick/tock. - */ -void watch_start_tick_animation(uint32_t duration); - -/** @brief Checks if the tick animation is currently running. - * @return true if the animation is running; false otherwise. - */ -bool watch_tick_animation_is_running(void); - -/** @brief Stops the tick/tock animation and clears all animating segments. - * @details This will stop the animation and clear all segments in position 8. - */ -void watch_stop_tick_animation(void); -/// @} -#endif diff --git a/watch-library/watch/watch_uart.c b/watch-library/watch/watch_uart.c deleted file mode 100644 index 64b63bee..00000000 --- a/watch-library/watch/watch_uart.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - - /* - * UART methods are Copyright (c) 2014-2017, Alex Taradov - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "watch_uart.h" -#include "peripheral_clk_config.h" - -void watch_enable_debug_uart(uint32_t baud) { - uint64_t br = (uint64_t)65536 * ((CONF_CPU_FREQUENCY * 4) - 16 * baud) / (CONF_CPU_FREQUENCY * 4); - - gpio_set_pin_direction(A2, GPIO_DIRECTION_OUT); - gpio_set_pin_function(A2, PINMUX_PB02C_SERCOM3_PAD0); - - MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3; - - GCLK->PCHCTRL[SERCOM3_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN(0) | GCLK_PCHCTRL_CHEN; - while (0 == (GCLK->PCHCTRL[SERCOM3_GCLK_ID_CORE].reg & GCLK_PCHCTRL_CHEN)); - - SERCOM3->USART.CTRLA.reg = - SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE(1/*USART_INT_CLK*/) | - SERCOM_USART_CTRLA_RXPO(1/*PAD1*/) | SERCOM_USART_CTRLA_TXPO(0/*PAD0*/); - - SERCOM3->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN | - SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/); - - SERCOM3->USART.BAUD.reg = (uint16_t)br; - - SERCOM3->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; -} - -void watch_debug_putc(char c) { - while (!(SERCOM3->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)); - SERCOM3->USART.DATA.reg = c; -} - -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" -void watch_debug_puts(char *s) { - while (*s) watch_debug_putc(*s++); -} -#pragma GCC diagnostic pop diff --git a/watch-library/watch/watch_uart.h b/watch-library/watch/watch_uart.h deleted file mode 100644 index 3e98bd35..00000000 --- a/watch-library/watch/watch_uart.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2020 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef _WATCH_UART_H_INCLUDED -#define _WATCH_UART_H_INCLUDED -////< @file watch_uart.h - -#include "watch.h" - -/** @addtogroup debug Debug UART - * @brief This section covers functions related to the debug UART, available on - * pin D1 of the 9-pin connector. - * @warning These functions were used early on in development, before the TinyUSB - * CDC was implemented. You can now print debug messages to the USB console - * using printf, rendering this bit irrelevant. These methods will likely - * be refactored out in the future, in favor of a more full-featured UART - * on the nine-pin connector. - **/ -/// @{ -/** @brief Initializes the debug UART. - * @param baud The baud rate - */ -__attribute__((deprecated("Use printf to log debug messages over USB."))) -void watch_enable_debug_uart(uint32_t baud); - -/** @brief Outputs a single character on the debug UART. - * @param c The character you wish to output. - */ -__attribute__((deprecated("Use printf to log debug messages over USB."))) -void watch_debug_putc(char c); - -/** @brief Outputs a string on the debug UART. - * @param s A null-terminated string. - */ -__attribute__((deprecated("Use printf to log debug messages over USB."))) -void watch_debug_puts(char *s); -/// @} -#endif diff --git a/watch-library/watch/watch_utility.c b/watch-library/watch/watch_utility.c deleted file mode 100644 index 835076d9..00000000 --- a/watch-library/watch/watch_utility.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2021 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include -#include "watch_utility.h" - -const char * watch_utility_get_weekday(watch_date_time date_time) { - static const char weekdays[7][3] = {"SA", "SU", "MO", "TU", "WE", "TH", "FR"}; - date_time.unit.year += 20; - if (date_time.unit.month <= 2) { - date_time.unit.month += 12; - date_time.unit.year--; - } - return weekdays[(date_time.unit.day + 13 * (date_time.unit.month + 1) / 5 + date_time.unit.year + date_time.unit.year / 4 + 525) % 7]; -} - -uint32_t watch_utility_convert_to_unix_time(uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second, uint32_t utc_offset) { - uint16_t DAYS_SO_FAR[] = { - 0, // Jan - 31, // Feb - 59, // March - 90, // April - 120, // May - 151, // June - 181, // July - 212, // August - 243, // September - 273, // October - 304, // November - 334 // December - }; - - uint32_t year_adj = year + 4800; - uint32_t febs = year_adj - (month <= 2 ? 1 : 0); /* Februaries since base. */ - uint32_t leap_days = 1 + (febs / 4) - (febs / 100) + (febs / 400); - uint32_t days = 365 * year_adj + leap_days + DAYS_SO_FAR[month - 1] + day - 1; - days -= 2472692; /* Adjust to Unix epoch. */ - - uint32_t timestamp = days * 86400; - timestamp += hour * 3600; - timestamp += minute * 60; - timestamp += second; - timestamp -= utc_offset; - - return timestamp; -} - -uint32_t watch_utility_date_time_to_unix_time(watch_date_time date_time, uint32_t utc_offset) { - return watch_utility_convert_to_unix_time(date_time.unit.year + WATCH_RTC_REFERENCE_YEAR, date_time.unit.month, date_time.unit.day, date_time.unit.hour, date_time.unit.minute, date_time.unit.second, utc_offset); -} - -#define LEAPOCH (946684800LL + 86400*(31+29)) - -#define DAYS_PER_400Y (365*400 + 97) -#define DAYS_PER_100Y (365*100 + 24) -#define DAYS_PER_4Y (365*4 + 1) - -watch_date_time watch_utility_date_time_from_unix_time(uint32_t timestamp, uint32_t utc_offset) { - watch_date_time retval; - retval.reg = 0; - int32_t days, secs; - int32_t remdays, remsecs, remyears; - int32_t qc_cycles, c_cycles, q_cycles; - int32_t years, months; - int32_t wday, yday, leap; - static const int8_t days_in_month[] = {31,30,31,30,31,31,30,31,30,31,31,29}; - timestamp += utc_offset; - - secs = timestamp - LEAPOCH; - days = secs / 86400; - remsecs = secs % 86400; - if (remsecs < 0) { - remsecs += 86400; - days--; - } - - wday = (3+days)%7; - if (wday < 0) wday += 7; - - qc_cycles = (int)(days / DAYS_PER_400Y); - remdays = days % DAYS_PER_400Y; - if (remdays < 0) { - remdays += DAYS_PER_400Y; - qc_cycles--; - } - - c_cycles = remdays / DAYS_PER_100Y; - if (c_cycles == 4) c_cycles--; - remdays -= c_cycles * DAYS_PER_100Y; - - q_cycles = remdays / DAYS_PER_4Y; - if (q_cycles == 25) q_cycles--; - remdays -= q_cycles * DAYS_PER_4Y; - - remyears = remdays / 365; - if (remyears == 4) remyears--; - remdays -= remyears * 365; - - leap = !remyears && (q_cycles || !c_cycles); - yday = remdays + 31 + 28 + leap; - if (yday >= 365+leap) yday -= 365+leap; - - years = remyears + 4*q_cycles + 100*c_cycles + 400*qc_cycles; - - for (months=0; days_in_month[months] <= remdays; months++) - remdays -= days_in_month[months]; - - years += 2000; - - months += 2; - if (months >= 12) { - months -=12; - years++; - } - - if (years < 2020 || years > 2083) return retval; - retval.unit.year = years - WATCH_RTC_REFERENCE_YEAR; - retval.unit.month = months + 1; - retval.unit.day = remdays + 1; - - retval.unit.hour = remsecs / 3600; - retval.unit.minute = remsecs / 60 % 60; - retval.unit.second = remsecs % 60; - - return retval; -} - -watch_date_time watch_utility_date_time_convert_zone(watch_date_time date_time, uint32_t origin_utc_offset, uint32_t destination_utc_offset) { - uint32_t timestamp = watch_utility_date_time_to_unix_time(date_time, origin_utc_offset); - return watch_utility_date_time_from_unix_time(timestamp, destination_utc_offset); -} - -float watch_utility_thermistor_temperature(uint16_t value, bool highside, float b_coefficient, float nominal_temperature, float nominal_resistance, float series_resistance) { - float reading = (float)value; - - if (highside) { - reading = (1023.0 * series_resistance) / (reading / 64.0); - reading -= series_resistance; - } else { - reading = series_resistance / (65535.0 / value - 1.0); - } - - reading = reading / nominal_resistance; - reading = log(reading); - reading /= b_coefficient; - reading += 1.0 / (nominal_temperature + 273.15); - reading = 1.0 / reading; - reading -= 273.15; - - return reading; -} diff --git a/watch-library/watch/watch_utility.h b/watch-library/watch/watch_utility.h deleted file mode 100644 index 66af6ed5..00000000 --- a/watch-library/watch/watch_utility.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * MIT License - * - * Copyright (c) 2021 Joey Castillo - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#ifndef _WATCH_UTILITY_H_INCLUDED -#define _WATCH_UTILITY_H_INCLUDED -////< @file watch_utility.h - -#include "watch.h" - -/** @addtogroup utility Utility Functions - * @brief This section covers various useful functions that don't fit anywhere else. - **/ -/// @{ -/** @brief Returns a two-letter weekday for the given timestamp, suitable for display - * in positions 0-1 of the watch face - * @param date_time The watch_date_time whose weekday you want. - */ -const char * watch_utility_get_weekday(watch_date_time date_time); - -/** @brief Returns the UNIX time (seconds since 1970) for a given date/time in UTC. - * @param date_time The watch_date_time that you wish to convert. - * @param year The year of the date you wish to convert. - * @param month The month of the date you wish to convert. - * @param day The day of the date you wish to convert. - * @param hour The hour of the date you wish to convert. - * @param minute The minute of the date you wish to convert. - * @param second The second of the date you wish to convert. - * @param utc_offset The number of seconds that date_time is offset from UTC, or 0 if the time is UTC. - * @return A UNIX timestamp for the given date/time and UTC offset. - * @note Implemented by Wesley Ellis (tahnok) and based on BSD-licensed code by Josh Haberman: - * https://blog.reverberate.org/2020/05/12/optimizing-date-algorithms.html - */ -uint32_t watch_utility_convert_to_unix_time(uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second, uint32_t utc_offset); - -/** @brief Returns the UNIX time (seconds since 1970) for a given watch_date_time struct. - * @param date_time The watch_date_time that you wish to convert. - * @param utc_offset The number of seconds that date_time is offset from UTC, or 0 if the time is UTC. - * @return A UNIX timestamp for the given watch_date_time and UTC offset. - */ -uint32_t watch_utility_date_time_to_unix_time(watch_date_time date_time, uint32_t utc_offset); - -/** @brief Returns the UNIX time (seconds since 1970) for a given watch_date_time struct. - * @param timestamp The UNIX timestamp that you wish to convert. - * @param utc_offset The number of seconds that you wish date_time to be offset from UTC. - * @return A watch_date_time for the given UNIX timestamp and UTC offset, or if outside the range that - * watch_date_time can represent, a watch_date_time with all fields set to 0. - * @note Adapted from MIT-licensed code from musl, Copyright © 2005-2014 Rich Felker, et al.: - * https://github.com/esmil/musl/blob/1cc81f5cb0df2b66a795ff0c26d7bbc4d16e13c6/src/time/__secs_to_tm.c - */ -watch_date_time watch_utility_date_time_from_unix_time(uint32_t timestamp, uint32_t utc_offset); - -/** @brief Converts a time from a given time zone to another time zone. - * @param date_time The watch_date_time that you wish to convert - * @param origin_utc_offset The number of seconds from UTC in the origin time zone - * @param destination_utc_offset The number of seconds from UTC in the destination time zone - * @return A watch_date_time for the given UNIX timestamp and UTC offset, or if outside the range that - * watch_date_time can represent, a watch_date_time with all fields set to 0. - * @note Adapted from MIT-licensed code from musl, Copyright © 2005-2014 Rich Felker, et al.: - * https://github.com/esmil/musl/blob/1cc81f5cb0df2b66a795ff0c26d7bbc4d16e13c6/src/time/__secs_to_tm.c - */ -watch_date_time watch_utility_date_time_convert_zone(watch_date_time date_time, uint32_t origin_utc_offset, uint32_t destination_utc_offset); - -/** @brief Returns a temperature in degrees Celsius for a given thermistor voltage divider circuit. - * @param value The raw analog reading from the thermistor pin (0-65535) - * @param highside True if the thermistor is connected to VCC and the series resistor is connected - * to GND; false if the thermistor is connected to GND and the series resistor is - * connected to VCC. - * @param b_coefficient From your thermistor's data sheet, the B25/85 coefficient. A typical value - * will be between 2000 and 5000. - * @param nominal_temperature From your thermistor's data sheet, the temperature (in Celsius) at - * which the thermistor's resistance is at its nominal value. - * @param nominal_resistance The thermistor's resistance at the nominal temperature. - * @param series_resistance The value of the other resistor in the voltage divider. - * @note Ported from Adafruit's MIT-licensed CircuitPython thermistor code, (c) 2017 Scott Shawcroft: - * https://github.com/adafruit/Adafruit_CircuitPython_Thermistor/blob/main/adafruit_thermistor.py - */ -float watch_utility_thermistor_temperature(uint16_t value, bool highside, float b_coefficient, float nominal_temperature, float nominal_resistance, float series_resistance); - -#endif -- cgit v1.2.3