From 68f38652273bd6356e35dfcec0949f6783009dcf Mon Sep 17 00:00:00 2001 From: Alex Maestas Date: Sun, 17 Dec 2023 17:40:19 +0000 Subject: work around silicon erratum in SUPC/VREG --- watch-library/hardware/watch/watch_private.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/watch-library/hardware/watch/watch_private.c b/watch-library/hardware/watch/watch_private.c index 4cae3ccb..20f4ee54 100644 --- a/watch-library/hardware/watch/watch_private.c +++ b/watch-library/hardware/watch/watch_private.c @@ -35,6 +35,10 @@ void _watch_init(void) { // Use switching regulator for lower power consumption. SUPC->VREG.bit.SEL = 1; + // work around a silicon erratum that causes the microcontroller to lock up on leaving standby: + // request that the voltage regulator run in standby, and also that it switch to PL0. + SUPC->VREG.bit.RUNSTDBY = 1; + SUPC->VREG.bit.STDBYPL0 = 1; while(!SUPC->STATUS.bit.VREGRDY); // wait for voltage regulator to become ready // check the battery voltage... -- cgit v1.2.3