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Diffstat (limited to 'watch-library/include/instance/sercom3.h')
| -rw-r--r-- | watch-library/include/instance/sercom3.h | 142 |
1 files changed, 0 insertions, 142 deletions
diff --git a/watch-library/include/instance/sercom3.h b/watch-library/include/instance/sercom3.h deleted file mode 100644 index f7256e22..00000000 --- a/watch-library/include/instance/sercom3.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM3 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM3_INSTANCE_ -#define _SAML22_SERCOM3_INSTANCE_ - -/* ========== Register definition for SERCOM3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM3_I2CM_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (0x4200100C) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CM Synchronization Busy */ -#define REG_SERCOM3_I2CM_ADDR (0x42001024) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (0x42001028) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (0x42001030) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CS Synchronization Busy */ -#define REG_SERCOM3_I2CS_ADDR (0x42001024) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (0x42001028) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (0x42001000) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (0x42001004) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (0x4200100C) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (0x42001014) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (0x42001016) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (0x42001018) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (0x4200101A) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) SPI Synchronization Busy */ -#define REG_SERCOM3_SPI_ADDR (0x42001024) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (0x42001028) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (0x42001030) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (0x42001000) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (0x42001004) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_CTRLC (0x42001008) /**< \brief (SERCOM3) USART Control C */ -#define REG_SERCOM3_USART_BAUD (0x4200100C) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (0x4200100E) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (0x42001014) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (0x42001016) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (0x42001018) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (0x4200101A) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) USART Synchronization Busy */ -#define REG_SERCOM3_USART_RXERRCNT (0x42001020) /**< \brief (SERCOM3) USART Receive Error Count */ -#define REG_SERCOM3_USART_DATA (0x42001028) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (0x42001030) /**< \brief (SERCOM3) USART Debug Control */ -#else -#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200100CUL) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CM Synchronization Busy */ -#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CS Synchronization Busy */ -#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) SPI Synchronization Busy */ -#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001028UL) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_CTRLC (*(RwReg *)0x42001008UL) /**< \brief (SERCOM3) USART Control C */ -#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200100CUL) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) USART Synchronization Busy */ -#define REG_SERCOM3_USART_RXERRCNT (*(RoReg8 *)0x42001020UL) /**< \brief (SERCOM3) USART Receive Error Count */ -#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001028UL) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM3 peripheral ========== */ -#define SERCOM3_DMAC_ID_RX 8 // Index of DMA RX trigger -#define SERCOM3_DMAC_ID_TX 9 // Index of DMA TX trigger -#define SERCOM3_GCLK_ID_CORE 19 -#define SERCOM3_GCLK_ID_SLOW 15 -#define SERCOM3_INT_MSB 6 -#define SERCOM3_PMSB 3 -#define SERCOM3_SPI 1 // SPI mode implemented? -#define SERCOM3_TWIM 1 // TWI Master mode implemented? -#define SERCOM3_TWIS 1 // TWI Slave mode implemented? -#define SERCOM3_TWI_HSMODE 0 // TWI HighSpeed mode implemented? -#define SERCOM3_USART 1 // USART mode implemented? -#define SERCOM3_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM3_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM3_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM3_INSTANCE_ */ |