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Diffstat (limited to 'watch-library/include/instance/ccl.h')
| -rw-r--r-- | watch-library/include/instance/ccl.h | 58 |
1 files changed, 0 insertions, 58 deletions
diff --git a/watch-library/include/instance/ccl.h b/watch-library/include/instance/ccl.h deleted file mode 100644 index b1e6e8e5..00000000 --- a/watch-library/include/instance/ccl.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * \file - * - * \brief Instance description for CCL - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_CCL_INSTANCE_ -#define _SAML22_CCL_INSTANCE_ - -/* ========== Register definition for CCL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CCL_CTRL (0x42004800) /**< \brief (CCL) Control */ -#define REG_CCL_SEQCTRL0 (0x42004804) /**< \brief (CCL) SEQ Control x 0 */ -#define REG_CCL_SEQCTRL1 (0x42004805) /**< \brief (CCL) SEQ Control x 1 */ -#define REG_CCL_LUTCTRL0 (0x42004808) /**< \brief (CCL) LUT Control x 0 */ -#define REG_CCL_LUTCTRL1 (0x4200480C) /**< \brief (CCL) LUT Control x 1 */ -#define REG_CCL_LUTCTRL2 (0x42004810) /**< \brief (CCL) LUT Control x 2 */ -#define REG_CCL_LUTCTRL3 (0x42004814) /**< \brief (CCL) LUT Control x 3 */ -#else -#define REG_CCL_CTRL (*(RwReg8 *)0x42004800UL) /**< \brief (CCL) Control */ -#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42004804UL) /**< \brief (CCL) SEQ Control x 0 */ -#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42004805UL) /**< \brief (CCL) SEQ Control x 1 */ -#define REG_CCL_LUTCTRL0 (*(RwReg *)0x42004808UL) /**< \brief (CCL) LUT Control x 0 */ -#define REG_CCL_LUTCTRL1 (*(RwReg *)0x4200480CUL) /**< \brief (CCL) LUT Control x 1 */ -#define REG_CCL_LUTCTRL2 (*(RwReg *)0x42004810UL) /**< \brief (CCL) LUT Control x 2 */ -#define REG_CCL_LUTCTRL3 (*(RwReg *)0x42004814UL) /**< \brief (CCL) LUT Control x 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for CCL peripheral ========== */ -#define CCL_GCLK_ID 28 // GCLK index for CCL -#define CCL_IO_NUM 12 // Numer of input pins -#define CCL_LUT_NUM 4 // Number of LUT in a CCL -#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL - -#endif /* _SAML22_CCL_INSTANCE_ */ |