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From a10d0b8516bc3f48f0c1005f8e69efce12cea8f9 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Mon, 23 Sep 2019 09:09:38 +0800
Subject: [PATCH] drm: imx: hdmi: support arc function
Add HDMI ARC configurate function.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
---
drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c | 59 +++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
--- a/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c
+++ b/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c
@@ -192,6 +192,62 @@ static const struct hdmi_pll_tuning imx8
{ 7, 5200000, 6000000, 0x7, 0x1, 0x0, 0x04, 0x0D, 680, 0x04F, 0, 0, 0 }
};
+static void hdmi_arc_config(struct cdns_mhdp_device *mhdp)
+{
+ u16 txpu_calib_code;
+ u16 txpd_calib_code;
+ u16 txpu_adj_calib_code;
+ u16 txpd_adj_calib_code;
+ u16 prev_calib_code;
+ u16 new_calib_code;
+ u16 rdata;
+
+ /* Power ARC */
+ cdns_phy_reg_write(mhdp, TXDA_CYA_AUXDA_CYA, 0x0001);
+
+ prev_calib_code = cdns_phy_reg_read(mhdp, TX_DIG_CTRL_REG_2);
+ txpu_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPUCAL_CTRL);
+ txpd_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPDCAL_CTRL);
+ txpu_adj_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPU_ADJ_CTRL);
+ txpd_adj_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPD_ADJ_CTRL);
+
+ new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2)
+ + txpu_adj_calib_code + txpd_adj_calib_code;
+
+ if (new_calib_code != prev_calib_code) {
+ rdata = cdns_phy_reg_read(mhdp, TX_ANA_CTRL_REG_1);
+ rdata &= 0xDFFF;
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, rdata);
+ cdns_phy_reg_write(mhdp, TX_DIG_CTRL_REG_2, new_calib_code);
+ mdelay(10);
+ rdata |= 0x2000;
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, rdata);
+ udelay(150);
+ }
+
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x0100);
+ udelay(100);
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x0300);
+ udelay(100);
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_3, 0x0000);
+ udelay(100);
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2008);
+ udelay(100);
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2018);
+ udelay(100);
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2098);
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030C);
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_5, 0x0010);
+ udelay(100);
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_4, 0x4001);
+ mdelay(5);
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2198);
+ mdelay(5);
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030D);
+ udelay(100);
+ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030F);
+}
+
static void hdmi_phy_set_vswing(struct cdns_mhdp_device *mhdp)
{
const u32 num_lanes = 4;
@@ -604,6 +660,9 @@ static int hdmi_phy_power_up(struct cdns
return -1;
}
+ /* Power up ARC */
+ hdmi_arc_config(mhdp);
+
/* Configure PHY in A0 mode (PHY must be in the A0 power
* state in order to transmit data)
*/
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