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From 916df9ddac295df428a304fd03ed492ad10e900c Mon Sep 17 00:00:00 2001
From: Marc Kleine-Budde <mkl@pengutronix.de>
Date: Fri, 1 Mar 2019 10:22:26 +0100
Subject: [PATCH] can: flexcan: remove TX mailbox bit from struct
flexcan_priv::rx_mask{1,2}
The flexcan IP core has up to 64 mailboxes, each one has a corresponding
interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
imask1 or imask2 registers.
In the timestamp (i.e. non FIFO) mode the driver needs to mask out all
non RX interrupt sources and uses the precomputed values rx_mask1 and
rx_mask2 of struct flexcan_priv for this.
Currently these values cannot be used directly, as they contain the TX
mailbox flag. This patch removes the TX flag from flexcan_priv::rx_mask1
and flexcan_priv::rx_mask2, and sets the TX flag directly when writing
the regs->iflag1 and regs->iflag2 into the hardware.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
drivers/net/can/flexcan.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -886,8 +886,7 @@ static inline u64 flexcan_read_reg_iflag
struct flexcan_regs __iomem *regs = priv->regs;
u32 iflag1, iflag2;
- iflag2 = priv->read(®s->iflag2) & priv->rx_mask2 &
- ~FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
+ iflag2 = priv->read(®s->iflag2) & priv->rx_mask2;
iflag1 = priv->read(®s->iflag1) & priv->rx_mask1;
return (u64)iflag2 << 32 | iflag1;
@@ -1234,7 +1233,7 @@ static int flexcan_chip_start(struct net
disable_irq(dev->irq);
priv->write(priv->reg_ctrl_default, ®s->ctrl);
priv->write(priv->rx_mask1, ®s->imask1);
- priv->write(priv->rx_mask2, ®s->imask2);
+ priv->write(priv->rx_mask2 | FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), ®s->imask2);
enable_irq(dev->irq);
/* print chip status */
@@ -1328,9 +1327,6 @@ static int flexcan_open(struct net_devic
priv->tx_mb_idx = priv->mb_count - 1;
priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
- priv->rx_mask1 = 0;
- priv->rx_mask2 = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
-
priv->offload.mailbox_read = flexcan_mailbox_read;
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
@@ -1341,12 +1337,12 @@ static int flexcan_open(struct net_devic
imask = GENMASK_ULL(priv->offload.mb_last,
priv->offload.mb_first);
- priv->rx_mask1 |= imask;
- priv->rx_mask2 |= imask >> 32;
+ priv->rx_mask1 = imask;
+ priv->rx_mask2 = imask >> 32;
err = can_rx_offload_add_timestamp(dev, &priv->offload);
} else {
- priv->rx_mask1 |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
+ priv->rx_mask1 = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
err = can_rx_offload_add_fifo(dev, &priv->offload,
FLEXCAN_NAPI_WEIGHT);
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