# # Copyright (C) 2006 OpenWrt.org # # This is free software, licensed under the GNU General Public License v2. # See /LICENSE for more information. # include $(TOPDIR)/rules.mk ARCH:=mipsel BOARD:=au1000 BOARDNAME:=RMI/AMD AU1x00 FEATURES:=jffs2 usb pci LINUX_VERSION:=2.6.25.16 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += yamonenv define Target/Description Build firmware for AMD Alchemy 1500 boards (e.g. 4G-Systems Mesh/Access Cube ...) endef define Kernel/BuildImage $(call Kernel/BuildImage/Default) $(CP) $(LINUX_DIR)/arch/mips/boot/compressed/images/zImage.flash.srec $(LINUX_DIR)/zImage.flash.srec $(CP) $(LINUX_DIR)/arch/mips/boot/compressed/images/zImage.srec $(LINUX_DIR)/zImage.srec endef $(eval $(call BuildTarget)) git/'><img src='/cgit.png' alt='cgit logo'/></a></td> <td class='main'><a href='/cgit/'>index</a> : <a title='openwrt/upstream' href='/cgit/openwrt/upstream/'>openwrt/upstream</a></td><td class='form'><form method='get'> <input type='hidden' name='id' value='5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'/><select name='h' onchange='this.form.submit();'> <option value='attitude_adjustment'>attitude_adjustment</option> <option value='barrier_breaker'>barrier_breaker</option> <option value='chaos_calmer'>chaos_calmer</option> <option value='lede-17.01'>lede-17.01</option> <option value='less-old-master'>less-old-master</option> <option value='master'>master</option> <option value='old-master'>old-master</option> <option value='openwrt-18.06'>openwrt-18.06</option> <option value='openwrt-19.07'>openwrt-19.07</option> <option value='upstream'>upstream</option> </select> <input type='submit' value='switch'/></form></td></tr> <tr><td class='sub'>upstream openwrt</td><td class='sub right'>James</td></tr></table> <table class='tabs'><tr><td> <a href='/cgit/openwrt/upstream/about/?h=v19.07.5'>about</a><a href='/cgit/openwrt/upstream/?h=v19.07.5'>summary</a><a href='/cgit/openwrt/upstream/refs/?h=v19.07.5&id=5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'>refs</a><a href='/cgit/openwrt/upstream/log/target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch?h=v19.07.5'>log</a><a class='active' href='/cgit/openwrt/upstream/tree/target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch?h=v19.07.5&id=5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'>tree</a><a href='/cgit/openwrt/upstream/commit/target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch?h=v19.07.5&id=5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'>commit</a><a href='/cgit/openwrt/upstream/diff/target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch?h=v19.07.5&id=5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'>diff</a><a href='/cgit/openwrt/upstream/stats/target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch?h=v19.07.5'>stats</a></td><td class='form'><form class='right' method='get' action='/cgit/openwrt/upstream/log/target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch'> <input type='hidden' name='h' value='v19.07.5'/><input type='hidden' name='id' value='5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'/><select name='qt'> <option value='grep'>log msg</option> <option value='author'>author</option> <option value='committer'>committer</option> <option value='range'>range</option> </select> <input class='txt' type='search' size='10' name='q' value=''/> <input type='submit' value='search'/> </form> </td></tr></table> <div class='path'>path: <a href='/cgit/openwrt/upstream/tree/?h=v19.07.5&id=5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'>root</a>/<a href='/cgit/openwrt/upstream/tree/target?h=v19.07.5&id=5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'>target</a>/<a href='/cgit/openwrt/upstream/tree/target/linux?h=v19.07.5&id=5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'>linux</a>/<a href='/cgit/openwrt/upstream/tree/target/linux/layerscape?h=v19.07.5&id=5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'>layerscape</a>/<a href='/cgit/openwrt/upstream/tree/target/linux/layerscape/patches-4.9?h=v19.07.5&id=5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'>patches-4.9</a>/<a href='/cgit/openwrt/upstream/tree/target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch?h=v19.07.5&id=5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'>808-guts-support-layerscape.patch</a></div><div class='content'>blob: ffda8a6cf823fa6ba55a841cb7812dcabef9d132 (<a href='/cgit/openwrt/upstream/plain/target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch?h=v19.07.5&id=5b8639f02e2680cbf3a0a5ffe0a9959386e9230b'>plain</a>) <table summary='blob content' class='blob'> <tr><td class='linenumbers'><pre><a id='n1' href='#n1'>1</a> <a id='n2' href='#n2'>2</a> <a id='n3' href='#n3'>3</a> <a id='n4' href='#n4'>4</a> <a id='n5' href='#n5'>5</a> <a id='n6' href='#n6'>6</a> <a id='n7' href='#n7'>7</a> <a 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href='#n452'>452</a> </pre></td> <td class='lines'><pre><code><style>pre { line-height: 125%; margin: 0; } td.linenos pre { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; } span.linenos { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; } td.linenos pre.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; } span.linenos.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; } .highlight .hll { background-color: #ffffcc } .highlight { background: #ffffff; } .highlight .c { color: #888888 } /* Comment */ .highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */ .highlight .k { color: #008800; font-weight: bold } /* Keyword */ .highlight .ch { color: #888888 } /* Comment.Hashbang */ .highlight .cm { color: #888888 } /* Comment.Multiline */ .highlight .cp { color: #cc0000; font-weight: bold } /* Comment.Preproc */ .highlight .cpf { color: #888888 } /* Comment.PreprocFile */ .highlight .c1 { color: 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Name.Property */ .highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */ .highlight .nv { color: #336699 } /* Name.Variable */ .highlight .ow { color: #008800 } /* Operator.Word */ .highlight .w { color: #bbbbbb } /* Text.Whitespace */ .highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */ .highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */ .highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */ .highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */ .highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */ .highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */ .highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */ .highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */ .highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter 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.highlight .vg { color: #dd7700 } /* Name.Variable.Global */ .highlight .vi { color: #3333bb } /* Name.Variable.Instance */ .highlight .vm { color: #336699 } /* Name.Variable.Magic */ .highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span>From d51e307e4ecf51832c9e3bc30acb5dbd559d5f4d Mon Sep 17 00:00:00 2001 From: Yangbo Lu <yangbo.lu@nxp.com> Date: Mon, 25 Sep 2017 12:19:34 +0800 Subject: [PATCH] guts: support layerscape This is a integrated patch for layerscape guts support. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> <span class="gd">---</span> drivers/base/soc.c | 12 ++- drivers/soc/fsl/guts.c | 238 +++++++++++++++++++++++++++++++++++++++++++++++ include/linux/fsl/guts.h | 125 +++++++++++++++---------- 3 files changed, 323 insertions(+), 52 deletions(-) create mode 100644 drivers/soc/fsl/guts.c <span class="gd">--- a/drivers/base/soc.c</span> <span class="gi">+++ b/drivers/base/soc.c</span> <span class="gu">@@ -167,19 +167,23 @@ static int soc_device_match_one(struct d</span> const struct soc_device_attribute *match = arg; if (match->machine && <span class="gd">- !glob_match(match->machine, soc_dev->attr->machine))</span> <span class="gi">+ (!soc_dev->attr->machine ||</span> <span class="gi">+ !glob_match(match->machine, soc_dev->attr->machine)))</span> return 0; if (match->family && <span class="gd">- !glob_match(match->family, soc_dev->attr->family))</span> <span class="gi">+ (!soc_dev->attr->family ||</span> <span class="gi">+ !glob_match(match->family, soc_dev->attr->family)))</span> return 0; if (match->revision && <span class="gd">- !glob_match(match->revision, soc_dev->attr->revision))</span> <span class="gi">+ (!soc_dev->attr->revision ||</span> <span class="gi">+ !glob_match(match->revision, soc_dev->attr->revision)))</span> return 0; if (match->soc_id && <span class="gd">- !glob_match(match->soc_id, soc_dev->attr->soc_id))</span> <span class="gi">+ (!soc_dev->attr->soc_id ||</span> <span class="gi">+ !glob_match(match->soc_id, soc_dev->attr->soc_id)))</span> return 0; return 1; <span class="gd">--- /dev/null</span> <span class="gi">+++ b/drivers/soc/fsl/guts.c</span> <span class="gu">@@ -0,0 +1,238 @@</span> <span class="gi">+/*</span> <span class="gi">+ * Freescale QorIQ Platforms GUTS Driver</span> <span class="gi">+ *</span> <span class="gi">+ * Copyright (C) 2016 Freescale Semiconductor, Inc.</span> <span class="gi">+ *</span> <span class="gi">+ * This program is free software; you can redistribute it and/or modify</span> <span class="gi">+ * it under the terms of the GNU General Public License as published by</span> <span class="gi">+ * the Free Software Foundation; either version 2 of the License, or</span> <span class="gi">+ * (at your option) any later version.</span> <span class="gi">+ */</span> <span class="gi">+</span> <span class="gi">+#include <linux/io.h></span> <span class="gi">+#include <linux/slab.h></span> <span class="gi">+#include <linux/module.h></span> <span class="gi">+#include <linux/of_fdt.h></span> <span class="gi">+#include <linux/sys_soc.h></span> <span class="gi">+#include <linux/of_address.h></span> <span class="gi">+#include <linux/platform_device.h></span> <span class="gi">+#include <linux/fsl/guts.h></span> <span class="gi">+</span> <span class="gi">+struct guts {</span> <span class="gi">+ struct ccsr_guts __iomem *regs;</span> <span class="gi">+ bool little_endian;</span> <span class="gi">+};</span> <span class="gi">+</span> <span class="gi">+struct fsl_soc_die_attr {</span> <span class="gi">+ char *die;</span> <span class="gi">+ u32 svr;</span> <span class="gi">+ u32 mask;</span> <span class="gi">+};</span> <span class="gi">+</span> <span class="gi">+static struct guts *guts;</span> <span class="gi">+static struct soc_device_attribute soc_dev_attr;</span> <span class="gi">+static struct soc_device *soc_dev;</span> <span class="gi">+</span> <span class="gi">+</span> <span class="gi">+/* SoC die attribute definition for QorIQ platform */</span> <span class="gi">+static const struct fsl_soc_die_attr fsl_soc_die[] = {</span> <span class="gi">+ /*</span> <span class="gi">+ * Power Architecture-based SoCs T Series</span> <span class="gi">+ */</span> <span class="gi">+</span> <span class="gi">+ /* Die: T4240, SoC: T4240/T4160/T4080 */</span> <span class="gi">+ { .die = "T4240",</span> <span class="gi">+ .svr = 0x82400000,</span> <span class="gi">+ .mask = 0xfff00000,</span> <span class="gi">+ },</span> <span class="gi">+ /* Die: T1040, SoC: T1040/T1020/T1042/T1022 */</span> <span class="gi">+ { .die = "T1040",</span> <span class="gi">+ .svr = 0x85200000,</span> <span class="gi">+ .mask = 0xfff00000,</span> <span class="gi">+ },</span> <span class="gi">+ /* Die: T2080, SoC: T2080/T2081 */</span> <span class="gi">+ { .die = "T2080",</span> <span class="gi">+ .svr = 0x85300000,</span> <span class="gi">+ .mask = 0xfff00000,</span> <span class="gi">+ },</span> <span class="gi">+ /* Die: T1024, SoC: T1024/T1014/T1023/T1013 */</span> <span class="gi">+ { .die = "T1024",</span> <span class="gi">+ .svr = 0x85400000,</span> <span class="gi">+ .mask = 0xfff00000,</span> <span class="gi">+ },</span> <span class="gi">+</span> <span class="gi">+ /*</span> <span class="gi">+ * ARM-based SoCs LS Series</span> <span class="gi">+ */</span> <span class="gi">+</span> <span class="gi">+ /* Die: LS1043A, SoC: LS1043A/LS1023A */</span> <span class="gi">+ { .die = "LS1043A",</span> <span class="gi">+ .svr = 0x87920000,</span> <span class="gi">+ .mask = 0xffff0000,</span> <span class="gi">+ },</span> <span class="gi">+ /* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */</span> <span class="gi">+ { .die = "LS2080A",</span> <span class="gi">+ .svr = 0x87010000,</span> <span class="gi">+ .mask = 0xff3f0000,</span> <span class="gi">+ },</span> <span class="gi">+ /* Die: LS1088A, SoC: LS1088A/LS1048A/LS1084A/LS1044A */</span> <span class="gi">+ { .die = "LS1088A",</span> <span class="gi">+ .svr = 0x87030000,</span> <span class="gi">+ .mask = 0xff3f0000,</span> <span class="gi">+ },</span> <span class="gi">+ /* Die: LS1012A, SoC: LS1012A */</span> <span class="gi">+ { .die = "LS1012A",</span> <span class="gi">+ .svr = 0x87040000,</span> <span class="gi">+ .mask = 0xffff0000,</span> <span class="gi">+ },</span> <span class="gi">+ /* Die: LS1046A, SoC: LS1046A/LS1026A */</span> <span class="gi">+ { .die = "LS1046A",</span> <span class="gi">+ .svr = 0x87070000,</span> <span class="gi">+ .mask = 0xffff0000,</span> <span class="gi">+ },</span> <span class="gi">+ /* Die: LS2088A, SoC: LS2088A/LS2048A/LS2084A/LS2044A */</span> <span class="gi">+ { .die = "LS2088A",</span> <span class="gi">+ .svr = 0x87090000,</span> <span class="gi">+ .mask = 0xff3f0000,</span> <span class="gi">+ },</span> <span class="gi">+ /* Die: LS1021A, SoC: LS1021A/LS1020A/LS1022A */</span> <span class="gi">+ { .die = "LS1021A",</span> <span class="gi">+ .svr = 0x87000000,</span> <span class="gi">+ .mask = 0xfff70000,</span> <span class="gi">+ },</span> <span class="gi">+ { },</span> <span class="gi">+};</span> <span class="gi">+</span> <span class="gi">+static const struct fsl_soc_die_attr *fsl_soc_die_match(</span> <span class="gi">+ u32 svr, const struct fsl_soc_die_attr *matches)</span> <span class="gi">+{</span> <span class="gi">+ while (matches->svr) {</span> <span class="gi">+ if (matches->svr == (svr & matches->mask))</span> <span class="gi">+ return matches;</span> <span class="gi">+ matches++;</span> <span class="gi">+ };</span> <span class="gi">+ return NULL;</span> <span class="gi">+}</span> <span class="gi">+</span> <span class="gi">+u32 fsl_guts_get_svr(void)</span> <span class="gi">+{</span> <span class="gi">+ u32 svr = 0;</span> <span class="gi">+</span> <span class="gi">+ if (!guts || !guts->regs)</span> <span class="gi">+ return svr;</span> <span class="gi">+</span> <span class="gi">+ if (guts->little_endian)</span> <span class="gi">+ svr = ioread32(&guts->regs->svr);</span> <span class="gi">+ else</span> <span class="gi">+ svr = ioread32be(&guts->regs->svr);</span> <span class="gi">+</span> <span class="gi">+ return svr;</span> <span class="gi">+}</span> <span class="gi">+EXPORT_SYMBOL(fsl_guts_get_svr);</span> <span class="gi">+</span> <span class="gi">+static int fsl_guts_probe(struct platform_device *pdev)</span> <span class="gi">+{</span> <span class="gi">+ struct device_node *np = pdev->dev.of_node;</span> <span class="gi">+ struct device *dev = &pdev->dev;</span> <span class="gi">+ struct resource *res;</span> <span class="gi">+ const struct fsl_soc_die_attr *soc_die;</span> <span class="gi">+ const char *machine;</span> <span class="gi">+ u32 svr;</span> <span class="gi">+</span> <span class="gi">+ /* Initialize guts */</span> <span class="gi">+ guts = devm_kzalloc(dev, sizeof(*guts), GFP_KERNEL);</span> <span class="gi">+ if (!guts)</span> <span class="gi">+ return -ENOMEM;</span> <span class="gi">+</span> <span class="gi">+ guts->little_endian = of_property_read_bool(np, "little-endian");</span> <span class="gi">+</span> <span class="gi">+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);</span> <span class="gi">+ guts->regs = devm_ioremap_resource(dev, res);</span> <span class="gi">+ if (IS_ERR(guts->regs))</span> <span class="gi">+ return PTR_ERR(guts->regs);</span> <span class="gi">+</span> <span class="gi">+ /* Register soc device */</span> <span class="gi">+ machine = of_flat_dt_get_machine_name();</span> <span class="gi">+ if (machine)</span> <span class="gi">+ soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL);</span> <span class="gi">+</span> <span class="gi">+ svr = fsl_guts_get_svr();</span> <span class="gi">+ soc_die = fsl_soc_die_match(svr, fsl_soc_die);</span> <span class="gi">+ if (soc_die) {</span> <span class="gi">+ soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL,</span> <span class="gi">+ "QorIQ %s", soc_die->die);</span> <span class="gi">+ } else {</span> <span class="gi">+ soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, "QorIQ");</span> <span class="gi">+ }</span> <span class="gi">+ soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL,</span> <span class="gi">+ "svr:0x%08x", svr);</span> <span class="gi">+ soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL, "%d.%d",</span> <span class="gi">+ (svr >> 4) & 0xf, svr & 0xf);</span> <span class="gi">+</span> <span class="gi">+ soc_dev = soc_device_register(&soc_dev_attr);</span> <span class="gi">+ if (IS_ERR(soc_dev))</span> <span class="gi">+ return PTR_ERR(soc_dev);</span> <span class="gi">+</span> <span class="gi">+ pr_info("Machine: %s\n", soc_dev_attr.machine);</span> <span class="gi">+ pr_info("SoC family: %s\n", soc_dev_attr.family);</span> <span class="gi">+ pr_info("SoC ID: %s, Revision: %s\n",</span> <span class="gi">+ soc_dev_attr.soc_id, soc_dev_attr.revision);</span> <span class="gi">+ return 0;</span> <span class="gi">+}</span> <span class="gi">+</span> <span class="gi">+static int fsl_guts_remove(struct platform_device *dev)</span> <span class="gi">+{</span> <span class="gi">+ soc_device_unregister(soc_dev);</span> <span class="gi">+ return 0;</span> <span class="gi">+}</span> <span class="gi">+</span> <span class="gi">+/*</span> <span class="gi">+ * Table for matching compatible strings, for device tree</span> <span class="gi">+ * guts node, for Freescale QorIQ SOCs.</span> <span class="gi">+ */</span> <span class="gi">+static const struct of_device_id fsl_guts_of_match[] = {</span> <span class="gi">+ { .compatible = "fsl,qoriq-device-config-1.0", },</span> <span class="gi">+ { .compatible = "fsl,qoriq-device-config-2.0", },</span> <span class="gi">+ { .compatible = "fsl,p1010-guts", },</span> <span class="gi">+ { .compatible = "fsl,p1020-guts", },</span> <span class="gi">+ { .compatible = "fsl,p1021-guts", },</span> <span class="gi">+ { .compatible = "fsl,p1022-guts", },</span> <span class="gi">+ { .compatible = "fsl,p1023-guts", },</span> <span class="gi">+ { .compatible = "fsl,p2020-guts", },</span> <span class="gi">+ { .compatible = "fsl,bsc9131-guts", },</span> <span class="gi">+ { .compatible = "fsl,bsc9132-guts", },</span> <span class="gi">+ { .compatible = "fsl,mpc8536-guts", },</span> <span class="gi">+ { .compatible = "fsl,mpc8544-guts", },</span> <span class="gi">+ { .compatible = "fsl,mpc8548-guts", },</span> <span class="gi">+ { .compatible = "fsl,mpc8568-guts", },</span> <span class="gi">+ { .compatible = "fsl,mpc8569-guts", },</span> <span class="gi">+ { .compatible = "fsl,mpc8572-guts", },</span> <span class="gi">+ { .compatible = "fsl,ls1021a-dcfg", },</span> <span class="gi">+ { .compatible = "fsl,ls1043a-dcfg", },</span> <span class="gi">+ { .compatible = "fsl,ls1046a-dcfg", },</span> <span class="gi">+ { .compatible = "fsl,ls2080a-dcfg", },</span> <span class="gi">+ { .compatible = "fsl,ls1088a-dcfg", },</span> <span class="gi">+ {}</span> <span class="gi">+};</span> <span class="gi">+MODULE_DEVICE_TABLE(of, fsl_guts_of_match);</span> <span class="gi">+</span> <span class="gi">+static struct platform_driver fsl_guts_driver = {</span> <span class="gi">+ .driver = {</span> <span class="gi">+ .name = "fsl-guts",</span> <span class="gi">+ .of_match_table = fsl_guts_of_match,</span> <span class="gi">+ },</span> <span class="gi">+ .probe = fsl_guts_probe,</span> <span class="gi">+ .remove = fsl_guts_remove,</span> <span class="gi">+};</span> <span class="gi">+</span> <span class="gi">+static int __init fsl_guts_init(void)</span> <span class="gi">+{</span> <span class="gi">+ return platform_driver_register(&fsl_guts_driver);</span> <span class="gi">+}</span> <span class="gi">+core_initcall(fsl_guts_init);</span> <span class="gi">+</span> <span class="gi">+static void __exit fsl_guts_exit(void)</span> <span class="gi">+{</span> <span class="gi">+ platform_driver_unregister(&fsl_guts_driver);</span> <span class="gi">+}</span> <span class="gi">+module_exit(fsl_guts_exit);</span> <span class="gd">--- a/include/linux/fsl/guts.h</span> <span class="gi">+++ b/include/linux/fsl/guts.h</span> <span class="gu">@@ -29,83 +29,112 @@</span> * #ifdefs. */ struct ccsr_guts { <span class="gd">- __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */</span> <span class="gd">- __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */</span> <span class="gd">- __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */</span> <span class="gd">- __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */</span> <span class="gd">- __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */</span> <span class="gd">- __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */</span> <span class="gi">+ u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */</span> <span class="gi">+ u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */</span> <span class="gi">+ u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and</span> <span class="gi">+ * Control Register</span> <span class="gi">+ */</span> <span class="gi">+ u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */</span> <span class="gi">+ u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */</span> <span class="gi">+ u32 pordevsr2; /* 0x.0014 - POR device status register 2 */</span> u8 res018[0x20 - 0x18]; <span class="gd">- __be32 porcir; /* 0x.0020 - POR Configuration Information Register */</span> <span class="gi">+ u32 porcir; /* 0x.0020 - POR Configuration Information</span> <span class="gi">+ * Register</span> <span class="gi">+ */</span> u8 res024[0x30 - 0x24]; <span class="gd">- __be32 gpiocr; /* 0x.0030 - GPIO Control Register */</span> <span class="gi">+ u32 gpiocr; /* 0x.0030 - GPIO Control Register */</span> u8 res034[0x40 - 0x34]; <span class="gd">- __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */</span> <span class="gi">+ u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data</span> <span class="gi">+ * Register</span> <span class="gi">+ */</span> u8 res044[0x50 - 0x44]; <span class="gd">- __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */</span> <span class="gi">+ u32 gpindr; /* 0x.0050 - General-Purpose Input Data</span> <span class="gi">+ * Register</span> <span class="gi">+ */</span> u8 res054[0x60 - 0x54]; <span class="gd">- __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */</span> <span class="gd">- __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */</span> <span class="gd">- __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */</span> <span class="gi">+ u32 pmuxcr; /* 0x.0060 - Alternate Function Signal</span> <span class="gi">+ * Multiplex Control</span> <span class="gi">+ */</span> <span class="gi">+ u32 pmuxcr2; /* 0x.0064 - Alternate function signal</span> <span class="gi">+ * multiplex control 2</span> <span class="gi">+ */</span> <span class="gi">+ u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */</span> u8 res06c[0x70 - 0x6c]; <span class="gd">- __be32 devdisr; /* 0x.0070 - Device Disable Control */</span> <span class="gi">+ u32 devdisr; /* 0x.0070 - Device Disable Control */</span> #define CCSR_GUTS_DEVDISR_TB1 0x00001000 #define CCSR_GUTS_DEVDISR_TB0 0x00004000 <span class="gd">- __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */</span> <span class="gi">+ u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */</span> u8 res078[0x7c - 0x78]; <span class="gd">- __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */</span> <span class="gd">- __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */</span> <span class="gd">- __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */</span> <span class="gd">- __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */</span> <span class="gd">- __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */</span> <span class="gd">- __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */</span> <span class="gd">- __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */</span> <span class="gd">- __be32 ectrstcr; /* 0x.0098 - Exception reset control register */</span> <span class="gd">- __be32 autorstsr; /* 0x.009c - Automatic reset status register */</span> <span class="gd">- __be32 pvr; /* 0x.00a0 - Processor Version Register */</span> <span class="gd">- __be32 svr; /* 0x.00a4 - System Version Register */</span> <span class="gi">+ u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control</span> <span class="gi">+ * Register</span> <span class="gi">+ */</span> <span class="gi">+ u32 powmgtcsr; /* 0x.0080 - Power Management Status and</span> <span class="gi">+ * Control Register</span> <span class="gi">+ */</span> <span class="gi">+ u32 pmrccr; /* 0x.0084 - Power Management Reset Counter</span> <span class="gi">+ * Configuration Register</span> <span class="gi">+ */</span> <span class="gi">+ u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter</span> <span class="gi">+ * Configuration Register</span> <span class="gi">+ */</span> <span class="gi">+ u32 pmcdr; /* 0x.008c - 4Power management clock disable</span> <span class="gi">+ * register</span> <span class="gi">+ */</span> <span class="gi">+ u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */</span> <span class="gi">+ u32 rstrscr; /* 0x.0094 - Reset Request Status and</span> <span class="gi">+ * Control Register</span> <span class="gi">+ */</span> <span class="gi">+ u32 ectrstcr; /* 0x.0098 - Exception reset control register */</span> <span class="gi">+ u32 autorstsr; /* 0x.009c - Automatic reset status register */</span> <span class="gi">+ u32 pvr; /* 0x.00a0 - Processor Version Register */</span> <span class="gi">+ u32 svr; /* 0x.00a4 - System Version Register */</span> u8 res0a8[0xb0 - 0xa8]; <span class="gd">- __be32 rstcr; /* 0x.00b0 - Reset Control Register */</span> <span class="gi">+ u32 rstcr; /* 0x.00b0 - Reset Control Register */</span> u8 res0b4[0xc0 - 0xb4]; <span class="gd">- __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register</span> <span class="gi">+ u32 iovselsr; /* 0x.00c0 - I/O voltage select status register</span> Called 'elbcvselcr' on 86xx SOCs */ u8 res0c4[0x100 - 0xc4]; <span class="gd">- __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers</span> <span class="gi">+ u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers</span> There are 16 registers */ u8 res140[0x224 - 0x140]; <span class="gd">- __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */</span> <span class="gd">- __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */</span> <span class="gi">+ u32 iodelay1; /* 0x.0224 - IO delay control register 1 */</span> <span class="gi">+ u32 iodelay2; /* 0x.0228 - IO delay control register 2 */</span> u8 res22c[0x604 - 0x22c]; <span class="gd">- __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */</span> <span class="gi">+ u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */</span> u8 res608[0x800 - 0x608]; <span class="gd">- __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */</span> <span class="gi">+ u32 clkdvdr; /* 0x.0800 - Clock Divide Register */</span> u8 res804[0x900 - 0x804]; <span class="gd">- __be32 ircr; /* 0x.0900 - Infrared Control Register */</span> <span class="gi">+ u32 ircr; /* 0x.0900 - Infrared Control Register */</span> u8 res904[0x908 - 0x904]; <span class="gd">- __be32 dmacr; /* 0x.0908 - DMA Control Register */</span> <span class="gi">+ u32 dmacr; /* 0x.0908 - DMA Control Register */</span> u8 res90c[0x914 - 0x90c]; <span class="gd">- __be32 elbccr; /* 0x.0914 - eLBC Control Register */</span> <span class="gi">+ u32 elbccr; /* 0x.0914 - eLBC Control Register */</span> u8 res918[0xb20 - 0x918]; <span class="gd">- __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */</span> <span class="gd">- __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */</span> <span class="gd">- __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */</span> <span class="gi">+ u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */</span> <span class="gi">+ u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */</span> <span class="gi">+ u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */</span> u8 resb2c[0xe00 - 0xb2c]; <span class="gd">- __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */</span> <span class="gi">+ u32 clkocr; /* 0x.0e00 - Clock Out Select Register */</span> u8 rese04[0xe10 - 0xe04]; <span class="gd">- __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */</span> <span class="gi">+ u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */</span> u8 rese14[0xe20 - 0xe14]; <span class="gd">- __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */</span> <span class="gd">- __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */</span> <span class="gi">+ u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */</span> <span class="gi">+ u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override</span> <span class="gi">+ * register</span> <span class="gi">+ */</span> u8 rese28[0xf04 - 0xe28]; <span class="gd">- __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */</span> <span class="gd">- __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */</span> <span class="gi">+ u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */</span> <span class="gi">+ u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */</span> u8 resf0c[0xf2c - 0xf0c]; <span class="gd">- __be32 itcr; /* 0x.0f2c - Internal transaction control register */</span> <span class="gi">+ u32 itcr; /* 0x.0f2c - Internal transaction control</span> <span class="gi">+ * register</span> <span class="gi">+ */</span> u8 resf30[0xf40 - 0xf30]; <span class="gd">- __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */</span> <span class="gd">- __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */</span> <span class="gi">+ u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */</span> <span class="gi">+ u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */</span> } __attribute__ ((packed)); <span class="gi">+u32 fsl_guts_get_svr(void);</span> /* Alternate function signal multiplex control */ #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x)) </pre></div> </code></pre></td></tr></table> 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