diff --git a/package/boot/uboot-sunxi/patches/004-sunxi-mmc-set-transfer-timeout-according-to-byte_cnt.patch b/package/boot/uboot-sunxi/patches/004-sunxi-mmc-set-transfer-timeout-according-to-byte_cnt.patch new file mode 100644 index 0000000..180b60b --- /dev/null +++ b/package/boot/uboot-sunxi/patches/004-sunxi-mmc-set-transfer-timeout-according-to-byte_cnt.patch @@ -0,0 +1,36 @@ +From 8a5481e2e51a86e858c4f1481729421f26cc240c Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Sat, 29 Aug 2015 21:26:11 +0800 +Subject: [PATCH] sunxi: mmc: set transfer timeout according to byte_cnt. + +Originally a timeout value of 2 seconds was used regardless of the size +of data to be transfered. This prevented slow devices from working +correctly while there was no much gain for faster devices, e.g. it takes +3708ms for a transfer of uImage of size 1899008 bytes. + +Signed-off-by: Yousong Zhou +--- + drivers/mmc/sunxi_mmc.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c +index e7ab828..7a990f7 100644 +--- a/drivers/mmc/sunxi_mmc.c ++++ b/drivers/mmc/sunxi_mmc.c +@@ -257,9 +257,11 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) + const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : + SUNXI_MMC_STATUS_FIFO_FULL; + unsigned i; +- unsigned byte_cnt = data->blocksize * data->blocks; +- unsigned timeout_msecs = 2000; + unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); ++ unsigned byte_cnt = data->blocksize * data->blocks; ++ unsigned timeout_msecs = byte_cnt >> 8; ++ if (timeout_msecs < 2000) ++ timeout_msecs = 2000; + + /* Always read / write data through the CPU */ + setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); +-- +1.7.10.4 + git/openwrt/upstream/?h=v18.06.4'>summaryrefslogtreecommitdiffstats
path: root/target/linux/layerscape/patches-4.4/3117-armv8-aarch32-Run-32-bit-Linux-for-LayerScape-SoCs.patch
blob: 9b580b4730ac43a7a68d4a3d4ebe1a6f6642d88a (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

From f6dcf8936845ea95eba432ee725cec761032fe2a Mon Sep 17 00:00:00 2001
From: Ying Zhang <ying.zhang22455@nxp.com>
Date: Thu, 29 Sep 2016 10:12:29 +0800
Subject: [PATCH 117/124] armv8: aarch32: Run 32-bit Linux for LayerScape SoCs

This patch adds AArch32 execution state support for LayerScape SoCs.

Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
---
 arch/arm/mach-imx/Makefile          |    2 ++
 arch/arm/mach-imx/mach-layerscape.c |   22 ++++++++++++++++++++++
 2 files changed, 24 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-layerscape.c

--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -103,4 +103,6 @@ obj-$(CONFIG_SOC_LS1021A) += mach-ls1021
 
 obj-$(CONFIG_ARCH_LAYERSCAPE) += mach-ls1043a.o
 
+obj-$(CONFIG_ARCH_LAYERSCAPE) += mach-layerscape.o
+
 obj-y += devices/
--- /dev/null
+++ b/arch/arm/mach-imx/mach-layerscape.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const char * const layerscape_dt_compat[] __initconst = {
+	"fsl,ls1043a",
+	"fsl,ls1012a",
+	NULL,
+};
+
+DT_MACHINE_START(LAYERSCAPE, "Freescale LAYERSCAPE")
+	.dt_compat	= layerscape_dt_compat,
+MACHINE_END
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-13 20:48:35 +0000