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--- a/arch/mips/ath79/common.h
+++ b/arch/mips/ath79/common.h
@@ -28,6 +28,7 @@ void ath79_gpio_function_enable(u32 mask);
void ath79_gpio_function_disable(u32 mask);
void ath79_gpio_function_setup(u32 set, u32 clear);
void ath79_gpio_output_select(unsigned gpio, u8 val);
+int ath79_gpio_direction_select(unsigned gpio, bool oe);
void ath79_gpio_init(void);
#endif /* __ATH79_COMMON_H */
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
@@ -130,6 +130,30 @@ static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
return 0;
}
+int ath79_gpio_direction_select(unsigned gpio, bool oe)
+{
+ void __iomem *base = ath79_gpio_base;
+ unsigned long flags;
+ bool ieq_1 = (soc_is_ar934x() ||
+ soc_is_qca953x());
+
+ if (gpio >= ath79_gpio_count)
+ return -1;
+
+ spin_lock_irqsave(&ath79_gpio_lock, flags);
+
+ if ((ieq_1 && oe) || (!ieq_1 && !oe))
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio),
+ base + AR71XX_GPIO_REG_OE);
+ else
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio),
+ base + AR71XX_GPIO_REG_OE);
+
+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+
+ return 0;
+}
+
static struct gpio_chip ath79_gpio_chip = {
.label = "ath79",
.get = ath79_gpio_get_value,
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