/* * This file is part of the flashrom project. * * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger * Copyright (C) 2008 Ronald Hoogenboom * Copyright (C) 2008 coresystems GmbH * Copyright (C) 2010 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* * Contains the ITE IT85* SPI specific routines */ #if defined(__i386__) || defined(__x86_64__) #include #include #include #include "flash.h" #include "spi.h" #include "programmer.h" #include "hwaccess.h" #define MAX_TIMEOUT 100000 #define MAX_TRY 5 /* Constants for I/O ports */ #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e /* Legacy I/O */ #define LEGACY_KBC_PORT_DATA 0x60 #define LEGACY_KBC_PORT_CMD 0x64 /* Constants for Logical Device registers */ #define LDNSEL 0x07 /* These are standard Super I/O 16-bit base address registers */ #define SHM_IO_BAR0 0x60 /* big-endian, this is high bits */ #define SHM_IO_BAR1 0x61 /* The 8042 keyboard controller uses an input buffer and an output buffer to * communicate with the host CPU. Both buffers are 1-byte depth. That means * IBF is set to 1 when the host CPU sends a command to the input buffer * of the EC. IBF is cleared to 0 once the command is read by the EC. */ #define KB_IBF (1 << 1) /* Input Buffer Full */ #define KB_OBF (1 << 0) /* Output Buffer Full */ /* IT8502 supports two access modes: * LPC_MEMORY: through the memory window in 0xFFFFFxxx (follow mode) * LPC_IO: through I/O port (so called indirect memory) */ #undef LPC_MEMORY #define LPC_IO #ifdef LPC_IO /* macro to fill in indirect-access registers. */ #define INDIRECT_A0(base, value) OUTB(value, (base) + 0) /* little-endian */ #define INDIRECT_A1(base, value) OUTB(value, (base) + 1) #define INDIRECT_A2(base, value) OUTB(value, (base) + 2) #define INDIRECT_A3(base, value) OUTB(value, (base) + 3) #define INDIRECT_READ(base) INB((base) + 4) #define INDIRECT_WRITE(base, value) OUTB(value, (base) + 4) #endif /* LPC_IO */ #ifdef LPC_IO unsigned int shm_io_base; #endif unsigned char *ce_high, *ce_low; static int it85xx_scratch_rom_reenter = 0; /* This function will poll the keyboard status register until either * an expected value shows up, or the timeout is reached. * timeout is in usec. * * Returns: 0 -- the expected value showed up. * 1 -- timeout. */ static int wait_for(const unsigned int mask, const unsigned int expected_value, const int timeout, const char * error_message, const char * function_name, const int lineno) { int time_passed; for (time_passed = 0;; ++time_passed) { if ((INB(LEGACY_KBC_PORT_CMD) & mask) == expected_value) return 0; if (time_passed >= timeout) break; programmer_delay(1); } if (error_message) msg_perr("%s():%d %s", function_name, lineno, error_message); return 1; } /* IT8502 employs a scratch RAM when flash is being updated. Call the following * two functions before/after flash erase/program. */ void it85xx_enter_scratch_rom(void) { int ret, tries; msg_pdbg("%s():%d was called ...\n", __func__, __LINE__); if (it85xx_scratch_rom_reenter > 0) return; #if 0 /* FIXME: this a workaround for the bug that SMBus signal would * interfere the EC firmware update. Should be removed if * we find out the root cause. */ ret = system("stop powerd >&2"); if (ret) msg_perr("Cannot stop powerd.\n"); #endif for (tries = 0; tries < MAX_TRY; ++tries) { /* Wait until IBF (input buffer) is not full. */ if (wait_for(KB_IBF, 0, MAX_TIMEOUT, "* timeout at waiting for IBF==0.\n", __func__, __LINE__)) continue; /* Copy EC firmware to SRAM. */ OUTB(0xb4, LEGACY_KBC_PORT_CMD); /* Confirm EC has taken away the command. */ if (wait_
config BR2_PACKAGE_SETSERIAL
	tristate "setserial - Serial port configuration utility"
	default m if CONFIG_DEVEL
	help
	  setserial  is a program designed to set and/or report the
	  configuration information associated with a serial port.  This
	  information  includes what I/O port and IRQ a particular
	  serial port is using, and whether or not the break key should
	  be interpreted as the Secure  Attention  Key, and so on.
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-25 06:16:59 +0000
ef LPC_MEMORY mmio_writeb(0, ce_high); #endif for (i = 0; i < writecnt; ++i) { #ifdef LPC_IO INDIRECT_WRITE(shm_io_base, writearr[i]); #endif #ifdef LPC_MEMORY mmio_writeb(writearr[i], ce_low); #endif } for (i = 0; i < readcnt; ++i) { #ifdef LPC_IO readarr[i] = INDIRECT_READ(shm_io_base); #endif #ifdef LPC_MEMORY readarr[i] = mmio_readb(ce_low); #endif } #ifdef LPC_IO INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ #endif #ifdef LPC_MEMORY mmio_writeb(0, ce_high); #endif return 0; } #endif