#ifndef __X86_PAGE_H__ #define __X86_PAGE_H__ /* * It is important that the masks are signed quantities. This ensures that * the compiler sign-extends a 32-bit mask to 64 bits if that is required. */ #ifndef __ASSEMBLY__ #define PAGE_SIZE (1L << PAGE_SHIFT) #else #define PAGE_SIZE (1 << PAGE_SHIFT) #endif #define PAGE_MASK (~(PAGE_SIZE-1)) #define PAGE_FLAG_MASK (~0) #ifndef __ASSEMBLY__ # include # include #endif #if defined(__i386__) # include #elif defined(__x86_64__) # include #endif /* Get direct integer representation of a pte's contents (intpte_t). */ #define l1e_get_intpte(x) ((x).l1) #define l2e_get_intpte(x) ((x).l2) #define l3e_get_intpte(x) ((x).l3) #define l4e_get_intpte(x) ((x).l4) /* Get pfn mapped by pte (unsigned long). */ #define l1e_get_pfn(x) \ ((unsigned long)(((x).l1 & (PADDR_MASK&PAGE_MASK)) >> PAGE_SHIFT)) #define l2e_get_pfn(x) \ ((unsigned long)(((x).l2 & (PADDR_MASK&PAGE_MASK)) >> PAGE_SHIFT)) #define l3e_get_pfn(x) \ ((unsigned long)(((x).l3 & (PADDR_MASK&PAGE_MASK)) >> PAGE_SHIFT)) #define l4e_get_pfn(x) \ ((unsigned long)(((x).l4 & (PADDR_MASK&PAGE_MASK)) >> PAGE_SHIFT)) /* Get physical address of page mapped by pte (physaddr_t). */ #define l1e_get_paddr(x) \ ((physaddr_t)(((x).l1 & (PADDR_MASK&PAGE_MASK)))) #define l2e_get_paddr(x) \ ((physaddr_t)(((x).l2 & (PADDR_MASK&PAGE_MASK)))) #define l3e_get_paddr(x) \ ((physaddr_t)(((x).l3 & (PADDR_MASK&PAGE_MASK)))) #define l4e_get_paddr(x) \ ((physaddr_t)(((x).l4 & (PADDR_MASK&PAGE_MASK)))) /* Get pointer to info structure of page mapped by pte (struct pfn_info *). */ #define l1e_get_page(x) (pfn_to_page(l1e_get_pfn(x))) #define l2e_get_page(x) (pfn_to_page(l2e_get_pfn(x))) #define l3e_get_page(x) (pfn_to_page(l3e_get_pfn(x))) #define l4e_get_page(x) (pfn_to_page(l4e_get_pfn(x))) /* Get pte access flags (unsigned int). */ #define l1e_get_flags(x) (get_pte_flags((x).l1)) #define l2e_get_flags(x) (get_pte_flags((x).l2)) #define l3e_get_flags(x) (get_pte_flags((x).l3)) #define l4e_get_flags(x) (get_pte_flags((x).l4)) /* Construct an empty pte. */ #define l1e_empty() ((l1_pgentry_t) { 0 }) #define l2e_empty() ((l2_pgentry_t) { 0 }) #define l3e_empty() ((l3_pgentry_t) { 0 }) #define l4e_empty() ((l4_pgentry_t) { 0 }) /* Construct a pte from a pfn and access flags. */ #define l1e_from_pfn(pfn, flags) \ ((l1_pgentry_t) { ((intpte_t)(pfn) << PAGE_SHIFT) | put_pte_flags(flags) }) #define l2e_from_pfn(pfn, flags) \ ((l2_pgentry_t) { ((intpte_t)(pfn) << PAGE_SHIFT) | put_pte_flags(flags) }) #define l3e_from_pfn(pfn, flags) \ ((l3_pgentry_t) { ((intpte_t)(pfn) << PAGE_SHIFT) | put_pte_flags(flags) }) #define l4e_from_pfn(pfn, flags) \ ((l4_pgentry_t) { ((intpte_t)(pfn) << PAGE_SHIFT) | put_pte_flags(flags) }) /* Construct a pte from a physical address and access flags. */ #ifndef __ASSEMBLY__ static inline l1_pgentry_t l1e_from_paddr(physaddr_t pa, unsigned int flags) { ASSERT((pa & ~(PADDR_MASK & PAGE_MASK)) == 0); return (l1_pgentry_t) { pa | put_pte_flags(flags) }; } static inline l2_pgentry_t l2e_from_paddr(physaddr_t pa, unsigned int flags) { ASSERT((pa & ~(PADDR_MASK & PAGE_MASK)) == 0); return (l2_pgentry_t) { pa | put_pte_flags(flags) }; } #if CONFIG_PAGING_LEVELS >= 3 static inline l3_pgentry_t l3e_from_paddr(physaddr_t pa, unsigned int flags) { ASSERT((pa & ~(PADDR_MASK & PAGE_MASK)) == 0); return (l3_pgentry_t) { pa | put_pte_flags(flags) }; } #endif #if CONFIG_PAGING_LEVELS >= 4 static inline l4_pgentry_t l4e_from_paddr(physaddr_t pa, unsigned int flags) { ASSERT((pa & ~(PADDR_MASK & PAGE_MASK)) == 0); return (l4_pgentry_t) { pa | put_pte_flags(flags) }; } #endif #endif /* !__ASSEMBLY__ */ /* Construct a pte from its direct integer representation. */ #define l1e_from_intpte(intpte) ((l1_pgentry_t) { (intpte_t)(intpte) }) #define l2e_from_intpte(intpte) ((l2_pgentry_t) { (intpte_t)(intpte) }) #define l3e_from_intpte(intpte) ((l3_pgentry_t) { (intpte_t)(intpte) }) #define l4e_from_intpte(intpte) ((l4_pgentry_t) { (intpte_t)(intpte) }) /* Construct a pte from a page pointer and access flags. */ #define l1e_from_page(page, flags) (l1e_from_pfn(page_to_pfn(page),(flags))) #define l2e_from_page(page, flags) (l2e_from_pfn(page_to_pfn(page),(flags))) #define l3e_from_page(page, flags) (l3e_from_pfn(page_to_pfn(page),(flags))) #define l4e_from_page(page, flags) (l4e_from_pfn(page_to_pfn(page),(flags))) /* Add extra flags to an existing pte. */ #define l1e_add_flags(x, flags) ((x).l1 |= put_pte_flags(flags)) #define l2e_add_flags(x, flags) ((x).l2 |= put_pte_flags(flags)) #define l3e_add_flags(x, flags) ((x).l3 |= put_pte_flags(flags)) #define l4e_add_flags(x, flags) ((x).l4 |= put_pte_flags(flags)) /* Remove flags from an existing pte. */ #define l1e_remove_flags(x, flags) ((x).l1 &= ~put_pte_flags(flags)) #define l2e_remove_flags(x, flags) ((x).l2 &= ~put_pte_flags(flags)) #define l3e_remove_flags(x, flags) ((x).l3 &= ~put_pte_flags(flags)) #define l4e_remove_flags(x, flags) ((x).l4 &= ~put_pte_flags(flags)) /* Check if a pte's page mapping or significant access flags have changed. */ #define l1e_has_changed(x,y,flags) \ ( !!(((x).l1 ^ (y).l1) & ((PADDR_MASK&PAGE_MASK)|put_pte_flags(flags))) ) #define l2e_has_changed(x,y,flags) \ ( !!(((x).l2 ^ (y).l2) & ((PADDR_MASK&PAGE_MASK)|put_pte_flags(flags))) ) #define l3e_has_changed(x,y,flags) \ ( !!(((x).l3 ^ (y).l3) & ((PADDR_MASK&PAGE_MASK)|put_pte_flags(flags))) ) #define l4e_has_changed(x,y,flags) \ ( !!(((x).l4 ^ (y).l4) & ((PADDR_MASK&PAGE_MASK)|put_pte_flags(flags))) ) /* Pagetable walking. */ #define l2e_to_l1e(x) ((l1_pgentry_t *)__va(l2e_get_paddr(x))) #define l3e_to_l2e(x) ((l2_pgentry_t *)__va(l3e_get_paddr(x))) #define l4e_to_l3e(x) ((l3_pgentry_t *)__va(l4e_get_paddr(x))) /* Given a virtual address, get an entry offset into a page table. */ #define l1_table_offset(a) \ (((a) >> L1_PAGETABLE_SHIFT) & (L1_PAGETABLE_ENTRIES - 1)) #define l2_table_offset(a) \ (((a) >> L2_PAGETABLE_SHIFT) & (L2_PAGETABLE_ENTRIES - 1)) #define l3_table_offset(a) \ (((a) >> L3_PAGETABLE_SHIFT) & (L3_PAGETABLE_ENTRIES - 1)) #define l4_table_offset(a) \ (((a) >> L4_PAGETABLE_SHIFT) & (L4_PAGETABLE_ENTRIES - 1)) /* Convert a pointer to a page-table entry into pagetable slot index. */ #define pgentry_ptr_to_slot(_p) \ (((unsigned long)(_p) & ~PAGE_MASK) / sizeof(*(_p))) /* Page-table type. */ #ifndef __ASSEMBLY__ #if CONFIG_PAGING_LEVELS == 2 /* x86_32 default */ typedef struct { u32 pfn; } pagetable_t; #elif CONFIG_PAGING_LEVELS == 3 /* x86_32 PAE */ typedef struct { u32 pfn; } pagetable_t; #elif CONFIG_PAGING_LEVELS == 4 /* x86_64 */ typedef struct { u64 pfn; } pagetable_t; #endif #define pagetable_get_paddr(x) ((physaddr_t)(x).pfn << PAGE_SHIFT) #define pagetable_get_pfn(x) ((x).pfn) #define mk_pagetable(pa) \ ({ pagetable_t __p; __p.pfn = (pa) >> PAGE_SHIFT; __p; }) #endif #define clear_page(_p) memset((void *)(_p), 0, PAGE_SIZE) #define copy_page(_t,_f) memcpy((void *)(_t), (void *)(_f), PAGE_SIZE) #define PAGE_OFFSET ((unsigned long)__PAGE_OFFSET) #define __pa(x) ((unsigned long)(x)-PAGE_OFFSET) #define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET)) #define pfn_to_page(_pfn) (frame_table + (_pfn)) #define phys_to_page(kaddr) (frame_table + ((kaddr) >> PAGE_SHIFT)) #define virt_to_page(kaddr) (frame_table + (__pa(kaddr) >> PAGE_SHIFT)) #define pfn_valid(_pfn) ((_pfn) < max_page) /* High table entries are reserved by the hypervisor. */ #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) #define DOMAIN_ENTRIES_PER_L2_PAGETABLE \ (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT) #define HYPERVISOR_ENTRIES_PER_L2_PAGETABLE \ (L2_PAGETABLE_ENTRIES - DOMAIN_ENTRIES_PER_L2_PAGETABLE) #else #define DOMAIN_ENTRIES_PER_L2_PAGETABLE 0 #define HYPERVISOR_ENTRIES_PER_L2_PAGETABLE 0 #endif #define linear_l1_table \ ((l1_pgentry_t *)(LINEAR_PT_VIRT_START)) #define __linear_l2_table \ ((l2_pgentry_t *)(LINEAR_PT_VIRT_START + \ (LINEAR_PT_VIRT_START >> (PAGETABLE_ORDER<<0)))) #define __linear_l3_table \ ((l3_pgentry_t *)(LINEAR_PT_VIRT_START + \ (LINEAR_PT_VIRT_START >> (PAGETABLE_ORDER<<0)) + \ (LINEAR_PT_VIRT_START >> (PAGETABLE_ORDER<<1)))) #define __linear_l4_table \ ((l4_pgentry_t *)(LINEAR_PT_VIRT_START + \ (LINEAR_PT_VIRT_START >> (PAGETABLE_ORDER<<0)) + \ (LINEAR_PT_VIRT_START >> (PAGETABLE_ORDER<<1)) + \ (LINEAR_PT_VIRT_START >> (PAGETABLE_ORDER<<2)))) #define linear_pg_table linear_l1_table #define linear_l2_table(_ed) ((_ed)->arch.guest_vtable) #define linear_l3_table(_ed) ((_ed)->arch.guest_vl3table) #define linear_l4_table(_ed) ((_ed)->arch.guest_vl4table) #define va_to_l1mfn(_ed, _va) \ (l2e_get_pfn(linear_l2_table(_ed)[_va>>L2_PAGETABLE_SHIFT])) #ifndef __ASSEMBLY__ #if CONFIG_PAGING_LEVELS == 3 extern root_pgentry_t idle_pg_table[ROOT_PAGETABLE_ENTRIES]; extern l3_pgentry_t idle_pg_table_l3[ROOT_PAGETABLE_ENTRIES]; extern l2_pgentry_t idle_pg_table_l2[ROOT_PAGETABLE_ENTRIES*L2_PAGETABLE_ENTRIES]; #else extern root_pgentry_t idle_pg_table[ROOT_PAGETABLE_ENTRIES]; extern l2_pgentry_t idle_pg_table_l2[ROOT_PAGETABLE_ENTRIES]; #endif extern void paging_init(void); #endif #define __pge_off() \ do { \ __asm__ __volatile__( \ "mov %0, %%cr4; # turn off PGE " \ : : "r" (mmu_cr4_features & ~X86_CR4_PGE) ); \ } while ( 0 ) #define __pge_on() \ do { \ __asm__ __volatile__( \ "mov %0, %%cr4; # turn off PGE " \ : : "r" (mmu_cr4_features) ); \ } while ( 0 ) #define _PAGE_PRESENT 0x001U #define _PAGE_RW 0x002U #define _PAGE_USER 0x004U #define _PAGE_PWT 0x008U #define _PAGE_PCD 0x010U #define _PAGE_ACCESSED 0x020U #define _PAGE_DIRTY 0x040U #define _PAGE_PAT 0x080U #define _PAGE_PSE 0x080U #define _PAGE_GLOBAL 0x100U #define _PAGE_AVAIL 0xE00U #define __PAGE_HYPERVISOR \ (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED) #define __PAGE_HYPERVISOR_NOCACHE \ (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_PCD | _PAGE_ACCESSED) #ifndef __ASSEMBLY__ static __inline__ int get_order(unsigned long size) { int order; size = (size-1) >> (PAGE_SHIFT-1); order = -1; do { size >>= 1; order++; } while (size); return order; } /* Allocator functions for Xen pagetables. */ struct pfn_info *alloc_xen_pagetable(void); void free_xen_pagetable(struct pfn_info *pg); l2_pgentry_t *virt_to_xen_l2e(unsigned long v); /* Map physical page range in Xen virtual address space. */ #define MAP_SMALL_PAGES (1UL<<16) /* don't use superpages for the mapping */ int map_pages_to_xen( unsigned long virt, unsigned long pfn, unsigned long nr_pfns, unsigned long flags); #endif /* !__ASSEMBLY__ */ #endif /* __I386_PAGE_H__ */ /* * Local variables: * mode: C * c-set-style: "BSD" * c-basic-offset: 4 * tab-width: 4 * indent-tabs-mode: nil * End: */ 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 
#ifndef B43_PHY_H_
#define B43_PHY_H_

#include <linux/types.h>

struct b43_wldev;
struct b43_phy;

/*** PHY Registers ***/

/* Routing */
#define B43_PHYROUTE_OFDM_GPHY		0x400
#define B43_PHYROUTE_EXT_GPHY		0x800

/* Base registers. */
#define B43_PHY_BASE(reg)		(reg)
/* OFDM (A) registers of a G-PHY */
#define B43_PHY_OFDM(reg)		((reg) | B43_PHYROUTE_OFDM_GPHY)
/* Extended G-PHY registers */
#define B43_PHY_EXTG(reg)		((reg) | B43_PHYROUTE_EXT_GPHY)

/* OFDM (A) PHY Registers */
#define B43_PHY_VERSION_OFDM		B43_PHY_OFDM(0x00)	/* Versioning register for A-PHY */
#define B43_PHY_BBANDCFG		B43_PHY_OFDM(0x01)	/* Baseband config */
#define  B43_PHY_BBANDCFG_RXANT		0x180	/* RX Antenna selection */
#define  B43_PHY_BBANDCFG_RXANT_SHIFT	7
#define B43_PHY_PWRDOWN			B43_PHY_OFDM(0x03)	/* Powerdown */
#define B43_PHY_CRSTHRES1		B43_PHY_OFDM(0x06)	/* CRS Threshold 1 */
#define B43_PHY_LNAHPFCTL		B43_PHY_OFDM(0x1C)	/* LNA/HPF control */
#define B43_PHY_ADIVRELATED		B43_PHY_OFDM(0x27)	/* FIXME rename */
#define B43_PHY_CRS0			B43_PHY_OFDM(0x29)
#define B43_PHY_ANTDWELL		B43_PHY_OFDM(0x2B)	/* Antenna dwell */
#define  B43_PHY_ANTDWELL_AUTODIV1	0x0100	/* Automatic RX diversity start antenna */
#define B43_PHY_ENCORE			B43_PHY_OFDM(0x49)	/* "Encore" (RangeMax / BroadRange) */
#define  B43_PHY_ENCORE_EN		0x0200	/* Encore enable */
#define B43_PHY_LMS			B43_PHY_OFDM(0x55)
#define B43_PHY_OFDM61			B43_PHY_OFDM(0x61)	/* FIXME rename */
#define  B43_PHY_OFDM61_10		0x0010	/* FIXME rename */
#define B43_PHY_IQBAL			B43_PHY_OFDM(0x69)	/* I/Q balance */
#define B43_PHY_OTABLECTL		B43_PHY_OFDM(0x72)	/* OFDM table control (see below) */
#define  B43_PHY_OTABLEOFF		0x03FF	/* OFDM table offset (see below) */
#define  B43_PHY_OTABLENR		0xFC00	/* OFDM table number (see below) */
#define  B43_PHY_OTABLENR_SHIFT		10
#define B43_PHY_OTABLEI			B43_PHY_OFDM(0x73)	/* OFDM table data I */
#define B43_PHY_OTABLEQ			B43_PHY_OFDM(0x74)	/* OFDM table data Q */
#define B43_PHY_HPWR_TSSICTL		B43_PHY_OFDM(0x78)	/* Hardware power TSSI control */
#define B43_PHY_NRSSITHRES		B43_PHY_OFDM(0x8A)	/* NRSSI threshold */
#define B43_PHY_ANTWRSETT		B43_PHY_OFDM(0x8C)	/* Antenna WR settle */
#define  B43_PHY_ANTWRSETT_ARXDIV	0x2000	/* Automatic RX diversity enabled */
#define B43_PHY_CLIPPWRDOWNT		B43_PHY_OFDM(0x93)	/* Clip powerdown threshold */
#define B43_PHY_OFDM9B			B43_PHY_OFDM(0x9B)	/* FIXME rename */
#define B43_PHY_N1P1GAIN		B43_PHY_OFDM(0xA0)
#define B43_PHY_P1P2GAIN		B43_PHY_OFDM(0xA1)
#define B43_PHY_N1N2GAIN		B43_PHY_OFDM(0xA2)
#define B43_PHY_CLIPTHRES		B43_PHY_OFDM(0xA3)
#define B43_PHY_CLIPN1P2THRES		B43_PHY_OFDM(0xA4)
#define B43_PHY_DIVSRCHIDX		B43_PHY_OFDM(0xA8)	/* Divider search gain/index */
#define B43_PHY_CLIPP2THRES		B43_PHY_OFDM(0xA9)
#define B43_PHY_CLIPP3THRES		B43_PHY_OFDM(0xAA)
#define B43_PHY_DIVP1P2GAIN		B43_PHY_OFDM(0xAB)
#define B43_PHY_DIVSRCHGAINBACK		B43_PHY_OFDM(0xAD)	/* Divider search gain back */
#define B43_PHY_DIVSRCHGAINCHNG		B43_PHY_OFDM(0xAE)	/* Divider search gain change */
#define B43_PHY_CRSTHRES1_R1		B43_PHY_OFDM(0xC0)	/* CRS Threshold 1 (rev 1 only) */
#define B43_PHY_CRSTHRES2_R1		B43_PHY_OFDM(0xC1)	/* CRS Threshold 2 (rev 1 only) */
#define B43_PHY_TSSIP_LTBASE		B43_PHY_OFDM(0x380)	/* TSSI power lookup table base */
#define B43_PHY_DC_LTBASE		B43_PHY_OFDM(0x3A0)	/* DC lookup table base */
#define B43_PHY_GAIN_LTBASE		B43_PHY_OFDM(0x3C0)	/* Gain lookup table base */

/* CCK (B) PHY Registers */
#define B43_PHY_VERSION_CCK		B43_PHY_BASE(0x00)	/* Versioning register for B-PHY */
#define B43_PHY_CCKBBANDCFG		B43_PHY_BASE(0x01)	/* Contains antenna 0/1 control bit */
#define B43_PHY_PGACTL			B43_PHY_BASE(0x15)	/* PGA control */
#define  B43_PHY_PGACTL_LPF		0x1000	/* Low pass filter (?) */
#define  B43_PHY_PGACTL_LOWBANDW	0x0040	/* Low bandwidth flag */
#define  B43_PHY_PGACTL_UNKNOWN		0xEFA0
#define B43_PHY_FBCTL1			B43_PHY_BASE(0x18)	/* Frequency bandwidth control 1 */
#define B43_PHY_ITSSI			B43_PHY_BASE(0x29)	/* Idle TSSI */
#define B43_PHY_LO_LEAKAGE		B43_PHY_BASE(0x2D)	/* Measured LO leakage */
#define B43_PHY_ENERGY			B43_PHY_BASE(0x33)	/* Energy */
#define B43_PHY_SYNCCTL			B43_PHY_BASE(0x35)
#define B43_PHY_FBCTL2			B43_PHY_BASE(0x38)	/* Frequency bandwidth control 2 */
#define B43_PHY_DACCTL			B43_PHY_BASE(0x60)	/* DAC control */
#define B43_PHY_RCCALOVER		B43_PHY_BASE(0x78)	/* RC calibration override */

/* Extended G-PHY Registers */
#define B43_PHY_CLASSCTL		B43_PHY_EXTG(0x02)	/* Classify control */
#define B43_PHY_GTABCTL			B43_PHY_EXTG(0x03)	/* G-PHY table control (see below) */
#define  B43_PHY_GTABOFF		0x03FF	/* G-PHY table offset (see below) */
#define  B43_PHY_GTABNR			0xFC00	/* G-PHY table number (see below) */
#define  B43_PHY_GTABNR_SHIFT		10
#define B43_PHY_GTABDATA		B43_PHY_EXTG(0x04)	/* G-PHY table data */
#define B43_PHY_LO_MASK			B43_PHY_EXTG(0x0F)	/* Local Oscillator control mask */
#define B43_PHY_LO_CTL			B43_PHY_EXTG(0x10)	/* Local Oscillator control */
#define B43_PHY_RFOVER			B43_PHY_EXTG(0x11)	/* RF override */
#define B43_PHY_RFOVERVAL		B43_PHY_EXTG(0x12)	/* RF override value */
#define  B43_PHY_RFOVERVAL_EXTLNA	0x8000
#define  B43_PHY_RFOVERVAL_LNA		0x7000
#define  B43_PHY_RFOVERVAL_LNA_SHIFT	12
#define  B43_PHY_RFOVERVAL_PGA		0x0F00
#define  B43_PHY_RFOVERVAL_PGA_SHIFT	8
#define  B43_PHY_RFOVERVAL_UNK		0x0010	/* Unknown, always set. */
#define  B43_PHY_RFOVERVAL_TRSWRX	0x00E0
#define  B43_PHY_RFOVERVAL_BW		0x0003	/* Bandwidth flags */
#define   B43_PHY_RFOVERVAL_BW_LPF	0x0001	/* Low Pass Filter */
#define   B43_PHY_RFOVERVAL_BW_LBW	0x0002	/* Low Bandwidth (when set), high when unset */
#define B43_PHY_ANALOGOVER		B43_PHY_EXTG(0x14)	/* Analog override */
#define B43_PHY_ANALOGOVERVAL		B43_PHY_EXTG(0x15)	/* Analog override value */

/*** OFDM table numbers ***/
#define B43_OFDMTAB(number, offset)	(((number) << B43_PHY_OTABLENR_SHIFT) | (offset))
#define B43_OFDMTAB_AGC1		B43_OFDMTAB(0x00, 0)
#define B43_OFDMTAB_GAIN0		B43_OFDMTAB(0x00, 0)
#define B43_OFDMTAB_GAINX		B43_OFDMTAB(0x01, 0)	//TODO rename
#define B43_OFDMTAB_GAIN1		B43_OFDMTAB(0x01, 4)
#define B43_OFDMTAB_AGC3		B43_OFDMTAB(0x02, 0)
#define B43_OFDMTAB_GAIN2		B43_OFDMTAB(0x02, 3)
#define B43_OFDMTAB_LNAHPFGAIN1		B43_OFDMTAB(0x03, 0)
#define B43_OFDMTAB_WRSSI		B43_OFDMTAB(0x04, 0)
#define B43_OFDMTAB_LNAHPFGAIN2		B43_OFDMTAB(0x04, 0)
#define B43_OFDMTAB_NOISESCALE		B43_OFDMTAB(0x05, 0)
#define B43_OFDMTAB_AGC2		B43_OFDMTAB(0x06, 0)
#define B43_OFDMTAB_ROTOR		B43_OFDMTAB(0x08, 0)
#define B43_OFDMTAB_ADVRETARD		B43_OFDMTAB(0x09, 0)
#define B43_OFDMTAB_DAC			B43_OFDMTAB(0x0C, 0)
#define B43_OFDMTAB_DC			B43_OFDMTAB(0x0E, 7)
#define B43_OFDMTAB_PWRDYN2		B43_OFDMTAB(0x0E, 12)
#define B43_OFDMTAB_LNAGAIN		B43_OFDMTAB(0x0E, 13)
//TODO
#define B43_OFDMTAB_LPFGAIN		B43_OFDMTAB(0x0F, 12)
#define B43_OFDMTAB_RSSI		B43_OFDMTAB(0x10, 0)
//TODO
#define B43_OFDMTAB_AGC1_R1		B43_OFDMTAB(0x13, 0)
#define B43_OFDMTAB_GAINX_R1		B43_OFDMTAB(0x14, 0)	//TODO rename
#define B43_OFDMTAB_MINSIGSQ		B43_OFDMTAB(0x14, 1)
#define B43_OFDMTAB_AGC3_R1		B43_OFDMTAB(0x15, 0)
#define B43_OFDMTAB_WRSSI_R1		B43_OFDMTAB(0x15, 4)
#define B43_OFDMTAB_TSSI		B43_OFDMTAB(0x15, 0)
#define B43_OFDMTAB_DACRFPABB		B43_OFDMTAB(0x16, 0)
#define B43_OFDMTAB_DACOFF		B43_OFDMTAB(0x17, 0)
#define B43_OFDMTAB_DCBIAS		B43_OFDMTAB(0x18, 0)

u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
			 u16 offset, u16 value);
u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
			 u16 offset, u32 value);

/*** G-PHY table numbers */
#define B43_GTAB(number, offset)	(((number) << B43_PHY_GTABNR_SHIFT) | (offset))
#define B43_GTAB_NRSSI			B43_GTAB(0x00, 0)
#define B43_GTAB_TRFEMW			B43_GTAB(0x0C, 0x120)
#define B43_GTAB_ORIGTR			B43_GTAB(0x2E, 0x298)

u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset);	//TODO implement
void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value);	//TODO implement

#define B43_DEFAULT_CHANNEL_A	36
#define B43_DEFAULT_CHANNEL_BG	6

enum {
	B43_ANTENNA0,		/* Antenna 0 */
	B43_ANTENNA1,		/* Antenna 0 */
	B43_ANTENNA_AUTO1,	/* Automatic, starting with antenna 1 */
	B43_ANTENNA_AUTO0,	/* Automatic, starting with antenna 0 */

	B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
	B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
};

enum {
	B43_INTERFMODE_NONE,
	B43_INTERFMODE_NONWLAN,
	B43_INTERFMODE_MANUALWLAN,
	B43_INTERFMODE_AUTOWLAN,
};

/* Masks for the different PHY versioning registers. */
#define B43_PHYVER_ANALOG		0xF000
#define B43_PHYVER_ANALOG_SHIFT		12
#define B43_PHYVER_TYPE			0x0F00
#define B43_PHYVER_TYPE_SHIFT		8
#define B43_PHYVER_VERSION		0x00FF

void b43_raw_phy_lock(struct b43_wldev *dev);
#define b43_phy_lock(dev, flags) \
	do {					\
		local_irq_save(flags);		\
		b43_raw_phy_lock(dev);	\
	} while (0)
void b43_raw_phy_unlock(struct b43_wldev *dev);
#define b43_phy_unlock(dev, flags) \
	do {					\
		b43_raw_phy_unlock(dev);	\
		local_irq_restore(flags);	\
	} while (0)

u16 b43_phy_read(struct b43_wldev *dev, u16 offset);
void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val);

int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev);

void b43_phy_early_init(struct b43_wldev *dev);
int b43_phy_init(struct b43_wldev *dev);

void b43_set_rx_antenna(struct b43_wldev *dev, int antenna);

void b43_phy_xmitpower(struct b43_wldev *dev);
void b43_gphy_dc_lt_init(struct b43_wldev *dev);

/* Returns the boolean whether the board has HardwarePowerControl */
bool b43_has_hardware_pctl(struct b43_phy *phy);
/* Returns the boolean whether "TX Magnification" is enabled. */
#define has_tx_magnification(phy) \
	(((phy)->rev >= 2) &&			\
	 ((phy)->radio_ver == 0x2050) &&	\
	 ((phy)->radio_rev == 8))
/* Card uses the loopback gain stuff */
#define has_loopback_gain(phy) \
	(((phy)->rev > 1) || ((phy)->gmode))

/* Radio Attenuation (RF Attenuation) */
struct b43_rfatt {
	u8 att;			/* Attenuation value */
	bool with_padmix;	/* Flag, PAD Mixer enabled. */
};
struct b43_rfatt_list {
	/* Attenuation values list */
	const struct b43_rfatt *list;
	u8 len;
	/* Minimum/Maximum attenuation values */
	u8 min_val;
	u8 max_val;
};

/* Baseband Attenuation */
struct b43_bbatt {
	u8 att;			/* Attenuation value */
};
struct b43_bbatt_list {
	/* Attenuation values list */
	const struct b43_bbatt *list;
	u8 len;
	/* Minimum/Maximum attenuation values */
	u8 min_val;
	u8 max_val;
};

/* tx_control bits. */
#define B43_TXCTL_PA3DB		0x40	/* PA Gain 3dB */
#define B43_TXCTL_PA2DB		0x20	/* PA Gain 2dB */
#define B43_TXCTL_TXMIX		0x10	/* TX Mixer Gain */

/* Write BasebandAttenuation value to the device. */
void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
				      u16 baseband_attenuation);

extern const u8 b43_radio_channel_codes_bg[];

void b43_radio_lock(struct b43_wldev *dev);
void b43_radio_unlock(struct b43_wldev *dev);

u16 b43_radio_read16(struct b43_wldev *dev, u16 offset);
void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val);

u16 b43_radio_init2050(struct b43_wldev *dev);
void b43_radio_init2060(struct b43_wldev *dev);

void b43_radio_turn_on(struct b43_wldev *dev);
void b43_radio_turn_off(struct b43_wldev *dev, bool force);

int b43_radio_selectchannel(struct b43_wldev *dev, u8 channel,
			    int synthetic_pu_workaround);

u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel);
u8 b43_radio_aci_scan(struct b43_wldev *dev);

int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode);

void b43_calc_nrssi_slope(struct b43_wldev *dev);
void b43_calc_nrssi_threshold(struct b43_wldev *dev);
s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset);
void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val);
void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val);
void b43_nrssi_mem_update(struct b43_wldev *dev);

void b43_radio_set_tx_iq(struct b43_wldev *dev);
u16 b43_radio_calibrationvalue(struct b43_wldev *dev);

void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
				     int *_bbatt, int *_rfatt);

void b43_set_txpower_g(struct b43_wldev *dev,
		       const struct b43_bbatt *bbatt,
		       const struct b43_rfatt *rfatt, u8 tx_control);

#endif /* B43_PHY_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-22 00:06:43 +0000