From 65153846b18c486ce3c90477c467d53915114e3f Mon Sep 17 00:00:00 2001
From: Andy Yan <andy.yan@rock-chips.com>
Date: Mon, 28 Aug 2017 10:00:46 +0800
Subject: [PATCH 2/2] mtd: spi-nor: add support for GD25Q256

Add support for GD25Q256, a 32MiB SPI Nor flash
from GigaDevice.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>

--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -872,6 +872,8 @@ static int spi_nor_is_locked(struct mtd_
 	return ret;
 }
 
+static int macronix_quad_enable(struct spi_nor *nor);
+
 /* Used when the "_ext_id" is two bytes at most */
 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)	\
 		.id = {							\
@@ -999,6 +1001,12 @@ static const struct flash_info spi_nor_i
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
+	{
+		"gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			.quad_enable = macronix_quad_enable,
+	},
 
 	/* Intel/Numonyx -- xxxs33b */
 	{ "160s33b",  INFO(0x898911, 0, 64 * 1024,  32, 0) },