From 1167f92ac63facf940024ce11357c14ca63924f8 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 29 Nov 2013 20:18:43 +0000 Subject: ag71xx: add F1E specific feature bit definitions to AR934X register file The F1E Phy (AR8035?) requires additional bits to be set in order to provide a fast and reliable connection over gigabit links. When enabled, the link doesn't suffer anymore from a small package loss under load and the performance is improved quite a bit as well. (203 mbit/s vs 112 mbit/s, iperf tcp). Signed-off-by: Christian Lamparter Patchwork: http://patchwork.openwrt.org/patch/4460/ Signed-off-by: Gabor Juhos SVN-Revision: 38948 --- .../patches-3.10/601-MIPS-ath79-add-more-register-defines.patch | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/linux/ar71xx/patches-3.10/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.10/601-MIPS-ath79-add-more-register-defines.patch index 014c7696af..4812a624f2 100644 --- a/target/linux/ar71xx/patches-3.10/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.10/601-MIPS-ath79-add-more-register-defines.patch @@ -207,7 +207,7 @@ #define AR934X_GPIO_REG_FUNC 0x6c #define AR71XX_GPIO_COUNT 16 -@@ -561,4 +664,144 @@ +@@ -561,4 +664,146 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 @@ -341,6 +341,8 @@ +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) ++#define AR934X_ETH_CFG_RXD_DELAY BIT(14) ++#define AR934X_ETH_CFG_RDV_DELAY BIT(16) + +/* + * QCA955X GMAC Interface -- cgit v1.2.3