From 8437c24f0976596a0eb1c7d19d0f5262df06312f Mon Sep 17 00:00:00 2001 From: David Bauer Date: Thu, 15 Apr 2021 00:30:24 +0200 Subject: ath79: fix 10 Mbit PLL data for TP-Link EAP2xx Fix the PLL register value for 10 Mbit/s link modes on TP-Link EAP boards using a AR8033 SGMII PHY. Otherwise, 10 Mbit/s links do not transfer data. Reported-by: Tom Herbers Tested-by: Tom Herbers Signed-off-by: David Bauer (cherry picked from commit bbff6239e2ea273388f4ca0f8586945ff5f36271) --- target/linux/ath79/dts/qca9563_tplink_eap2x5-1port.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'target/linux') diff --git a/target/linux/ath79/dts/qca9563_tplink_eap2x5-1port.dtsi b/target/linux/ath79/dts/qca9563_tplink_eap2x5-1port.dtsi index cc9e0b7ff6..a6aefc7b55 100644 --- a/target/linux/ath79/dts/qca9563_tplink_eap2x5-1port.dtsi +++ b/target/linux/ath79/dts/qca9563_tplink_eap2x5-1port.dtsi @@ -112,6 +112,7 @@ phy-handle = <&phy4>; phy-mode = "sgmii"; + pll-data = <0x03000000 0x00000101 0x00001313>; mtd-mac-address = <&info 0x8>; -- cgit v1.2.3