From 1d55249d7cf3811b02cd9221b5ae93df14a2ff9a Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 4 Mar 2013 11:48:15 +0000 Subject: ar71xx: use backported QCA955x patches Signed-off-by: Gabor Juhos SVN-Revision: 35878 --- .../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 8 +- .../024-ath79-add-ATH79_CPU_IRQ-macro.patch | 266 +++++++++++++++++++++ .../025-ath79-remove-ATH79_MISC_IRQ_-defines.patch | 85 +++++++ ...use-dynamically-allocated-USB-platform-de.patch | 205 ++++++++++++++++ ...PS-ath79-fix-WMAC-IRQ-resource-assignment.patch | 29 +++ ...add-early-printk-support-for-the-QCA955X-.patch | 43 ++++ ...add-SoC-detection-code-for-the-QCA955X-So.patch | 113 +++++++++ ...add-clock-setup-code-for-the-QCA955X-SoCs.patch | 177 ++++++++++++++ ...add-IRQ-handling-code-for-the-QCA955X-SoC.patch | 246 +++++++++++++++++++ ...-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch | 50 ++++ ...add-QCA955X-specific-glue-to-ath79_device.patch | 53 ++++ ...-ath79-register-UART-for-the-QCA955X-SoCs.patch | 34 +++ ...add-WMAC-registration-code-for-the-QCA955.patch | 81 +++++++ ...add-PCI-controller-registration-code-for-.patch | 115 +++++++++ ...add-USB-controller-registration-code-for-.patch | 65 +++++ ...add-support-for-the-Qualcomm-Atheros-AP13.patch | 234 ++++++++++++++++++ ...add-early-printk-support-for-the-QCA955X-.patch | 31 --- ...add-SoC-detection-code-for-the-QCA9558-So.patch | 91 ------- ...th79-add-clock-setup-for-the-QCA955X-SoCs.patch | 167 ------------- ...add-IRQ-handling-code-for-the-QCA955X-SoC.patch | 239 ------------------ ...-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch | 39 --- ...add-QCA955X-specific-glue-to-ath79_device.patch | 31 --- ...-ath79-register-UART-for-the-QCA955X-SoCs.patch | 22 -- ...add-USB-controller-registration-code-for-.patch | 93 ------- ...add-WMAC-registration-code-for-the-QCA955.patch | 70 ------ ...add-PCI-controller-registration-code-for-.patch | 103 -------- ...add-support-for-the-Qualcomm-Atheros-AP13.patch | 213 ----------------- ...IPS-ath79-add-support-for-the-QCA9556-SoC.patch | 56 ----- .../503-MIPS-ath79-add-flash-acquire-release.patch | 2 +- ...504-MIPS-ath79-add-ath79_device_reset_get.patch | 2 +- ...1-MIPS-ath79-enable-UART-for-early_serial.patch | 2 +- .../patches-3.8/523-MIPS-ath79-OTP-support.patch | 2 +- .../601-MIPS-ath79-add-more-register-defines.patch | 19 +- .../patches-3.8/603-MIPS-ath79-ap121-fixes.patch | 2 +- .../patches-3.8/609-MIPS-ath79-ap136-fixes.patch | 64 +++-- 35 files changed, 1862 insertions(+), 1190 deletions(-) create mode 100644 target/linux/ar71xx/patches-3.8/024-ath79-add-ATH79_CPU_IRQ-macro.patch create mode 100644 target/linux/ar71xx/patches-3.8/025-ath79-remove-ATH79_MISC_IRQ_-defines.patch create mode 100644 target/linux/ar71xx/patches-3.8/026-MIPS-ath79-use-dynamically-allocated-USB-platform-de.patch create mode 100644 target/linux/ar71xx/patches-3.8/027-MIPS-ath79-fix-WMAC-IRQ-resource-assignment.patch create mode 100644 target/linux/ar71xx/patches-3.8/028-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch create mode 100644 target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch create mode 100644 target/linux/ar71xx/patches-3.8/030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch create mode 100644 target/linux/ar71xx/patches-3.8/031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch create mode 100644 target/linux/ar71xx/patches-3.8/032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch create mode 100644 target/linux/ar71xx/patches-3.8/033-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch create mode 100644 target/linux/ar71xx/patches-3.8/034-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch create mode 100644 target/linux/ar71xx/patches-3.8/035-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch create mode 100644 target/linux/ar71xx/patches-3.8/036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch create mode 100644 target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch create mode 100644 target/linux/ar71xx/patches-3.8/038-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch delete mode 100644 target/linux/ar71xx/patches-3.8/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch delete mode 100644 target/linux/ar71xx/patches-3.8/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch delete mode 100644 target/linux/ar71xx/patches-3.8/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch delete mode 100644 target/linux/ar71xx/patches-3.8/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch delete mode 100644 target/linux/ar71xx/patches-3.8/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch delete mode 100644 target/linux/ar71xx/patches-3.8/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch delete mode 100644 target/linux/ar71xx/patches-3.8/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch delete mode 100644 target/linux/ar71xx/patches-3.8/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch delete mode 100644 target/linux/ar71xx/patches-3.8/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch delete mode 100644 target/linux/ar71xx/patches-3.8/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch delete mode 100644 target/linux/ar71xx/patches-3.8/171-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch delete mode 100644 target/linux/ar71xx/patches-3.8/172-MIPS-ath79-add-support-for-the-QCA9556-SoC.patch (limited to 'target/linux') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index 249323246c..d7f3595b88 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -439,8 +439,8 @@ static struct resource ath79_eth0_resources[] = { }, { .name = "mac_irq", .flags = IORESOURCE_IRQ, - .start = ATH79_CPU_IRQ_GE0, - .end = ATH79_CPU_IRQ_GE0, + .start = ATH79_CPU_IRQ(4), + .end = ATH79_CPU_IRQ(4), }, }; @@ -467,8 +467,8 @@ static struct resource ath79_eth1_resources[] = { }, { .name = "mac_irq", .flags = IORESOURCE_IRQ, - .start = ATH79_CPU_IRQ_GE1, - .end = ATH79_CPU_IRQ_GE1, + .start = ATH79_CPU_IRQ(5), + .end = ATH79_CPU_IRQ(5), }, }; diff --git a/target/linux/ar71xx/patches-3.8/024-ath79-add-ATH79_CPU_IRQ-macro.patch b/target/linux/ar71xx/patches-3.8/024-ath79-add-ATH79_CPU_IRQ-macro.patch new file mode 100644 index 0000000000..36244331bc --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/024-ath79-add-ATH79_CPU_IRQ-macro.patch @@ -0,0 +1,266 @@ +From 7377d32d37490f0804662c76a72b68d45d93966e Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Thu, 7 Feb 2013 19:32:23 +0000 +Subject: [PATCH] ath79: add ATH79_CPU_IRQ() macro + +commit 7e69c10a8ee1f201c040997c6742c27e915730ad upstream. + +Remove the individual ATH79_CPU_IRQ_* constants and +use the new macro instead of those. + +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4929/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/dev-usb.c | 12 ++++++------ + arch/mips/ath79/dev-wmac.c | 8 ++++---- + arch/mips/ath79/irq.c | 32 ++++++++++++++++---------------- + arch/mips/ath79/pci.c | 6 +++--- + arch/mips/include/asm/mach-ath79/irq.h | 9 ++------- + 5 files changed, 31 insertions(+), 36 deletions(-) + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -111,7 +111,7 @@ static void __init ath79_usb_setup(void) + platform_device_register(&ath79_ohci_device); + + ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, +- AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB); ++ AR71XX_EHCI_SIZE, ATH79_CPU_IRQ(3)); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; + platform_device_register(&ath79_ehci_device); + } +@@ -136,7 +136,7 @@ static void __init ar7240_usb_setup(void + iounmap(usb_ctrl_base); + + ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE, +- AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB); ++ AR7240_OHCI_SIZE, ATH79_CPU_IRQ(3)); + platform_device_register(&ath79_ohci_device); + } + +@@ -152,7 +152,7 @@ static void __init ar724x_usb_setup(void + mdelay(10); + + ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE, +- AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB); ++ AR724X_EHCI_SIZE, ATH79_CPU_IRQ(3)); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } +@@ -169,7 +169,7 @@ static void __init ar913x_usb_setup(void + mdelay(10); + + ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE, +- AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB); ++ AR913X_EHCI_SIZE, ATH79_CPU_IRQ(3)); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } +@@ -186,7 +186,7 @@ static void __init ar933x_usb_setup(void + mdelay(10); + + ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE, +- AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB); ++ AR933X_EHCI_SIZE, ATH79_CPU_IRQ(3)); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } +@@ -212,7 +212,7 @@ static void __init ar934x_usb_setup(void + udelay(1000); + + ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE, +- AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB); ++ AR934X_EHCI_SIZE, ATH79_CPU_IRQ(3)); + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; + platform_device_register(&ath79_ehci_device); + } +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -55,8 +55,8 @@ static void __init ar913x_wmac_setup(voi + + ath79_wmac_resources[0].start = AR913X_WMAC_BASE; + ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; +- ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; +- ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; ++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); ++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); + } + + +@@ -83,8 +83,8 @@ static void __init ar933x_wmac_setup(voi + + ath79_wmac_resources[0].start = AR933X_WMAC_BASE; + ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; +- ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; +- ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; ++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); ++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + if (t & AR933X_BOOTSTRAP_REF_CLK_40) +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -114,7 +114,7 @@ static void __init ath79_misc_irq_init(v + handle_level_irq); + } + +- irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); ++ irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler); + } + + static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) +@@ -147,7 +147,7 @@ static void ar934x_ip2_irq_init(void) + irq_set_chip_and_handler(i, &dummy_irq_chip, + handle_level_irq); + +- irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch); ++ irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); + } + + asmlinkage void plat_irq_dispatch(void) +@@ -157,22 +157,22 @@ asmlinkage void plat_irq_dispatch(void) + pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) +- do_IRQ(ATH79_CPU_IRQ_TIMER); ++ do_IRQ(ATH79_CPU_IRQ(7)); + + else if (pending & STATUSF_IP2) + ath79_ip2_handler(); + + else if (pending & STATUSF_IP4) +- do_IRQ(ATH79_CPU_IRQ_GE0); ++ do_IRQ(ATH79_CPU_IRQ(4)); + + else if (pending & STATUSF_IP5) +- do_IRQ(ATH79_CPU_IRQ_GE1); ++ do_IRQ(ATH79_CPU_IRQ(5)); + + else if (pending & STATUSF_IP3) + ath79_ip3_handler(); + + else if (pending & STATUSF_IP6) +- do_IRQ(ATH79_CPU_IRQ_MISC); ++ do_IRQ(ATH79_CPU_IRQ(6)); + + else + spurious_interrupt(); +@@ -188,60 +188,60 @@ asmlinkage void plat_irq_dispatch(void) + static void ar71xx_ip2_handler(void) + { + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); +- do_IRQ(ATH79_CPU_IRQ_IP2); ++ do_IRQ(ATH79_CPU_IRQ(2)); + } + + static void ar724x_ip2_handler(void) + { + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE); +- do_IRQ(ATH79_CPU_IRQ_IP2); ++ do_IRQ(ATH79_CPU_IRQ(2)); + } + + static void ar913x_ip2_handler(void) + { + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC); +- do_IRQ(ATH79_CPU_IRQ_IP2); ++ do_IRQ(ATH79_CPU_IRQ(2)); + } + + static void ar933x_ip2_handler(void) + { + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC); +- do_IRQ(ATH79_CPU_IRQ_IP2); ++ do_IRQ(ATH79_CPU_IRQ(2)); + } + + static void ar934x_ip2_handler(void) + { +- do_IRQ(ATH79_CPU_IRQ_IP2); ++ do_IRQ(ATH79_CPU_IRQ(2)); + } + + static void ar71xx_ip3_handler(void) + { + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); +- do_IRQ(ATH79_CPU_IRQ_USB); ++ do_IRQ(ATH79_CPU_IRQ(3)); + } + + static void ar724x_ip3_handler(void) + { + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB); +- do_IRQ(ATH79_CPU_IRQ_USB); ++ do_IRQ(ATH79_CPU_IRQ(3)); + } + + static void ar913x_ip3_handler(void) + { + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB); +- do_IRQ(ATH79_CPU_IRQ_USB); ++ do_IRQ(ATH79_CPU_IRQ(3)); + } + + static void ar933x_ip3_handler(void) + { + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB); +- do_IRQ(ATH79_CPU_IRQ_USB); ++ do_IRQ(ATH79_CPU_IRQ(3)); + } + + static void ar934x_ip3_handler(void) + { + ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB); +- do_IRQ(ATH79_CPU_IRQ_USB); ++ do_IRQ(ATH79_CPU_IRQ(3)); + } + + void __init arch_init_irq(void) +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -127,8 +127,8 @@ ath79_register_pci_ar71xx(void) + res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1; + + res[1].flags = IORESOURCE_IRQ; +- res[1].start = ATH79_CPU_IRQ_IP2; +- res[1].end = ATH79_CPU_IRQ_IP2; ++ res[1].start = ATH79_CPU_IRQ(2); ++ res[1].end = ATH79_CPU_IRQ(2); + + res[2].name = "io_base"; + res[2].flags = IORESOURCE_IO; +@@ -208,7 +208,7 @@ int __init ath79_register_pci(void) + AR724X_PCI_MEM_BASE, + AR724X_PCI_MEM_SIZE, + 0, +- ATH79_CPU_IRQ_IP2); ++ ATH79_CPU_IRQ(2)); + } else if (soc_is_ar9342() || + soc_is_ar9344()) { + u32 bootstrap; +--- a/arch/mips/include/asm/mach-ath79/irq.h ++++ b/arch/mips/include/asm/mach-ath79/irq.h +@@ -12,6 +12,8 @@ + #define MIPS_CPU_IRQ_BASE 0 + #define NR_IRQS 48 + ++#define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x)) ++ + #define ATH79_MISC_IRQ_BASE 8 + #define ATH79_MISC_IRQ_COUNT 32 + #define ATH79_MISC_IRQ(_x) (ATH79_MISC_IRQ_BASE + (_x)) +@@ -24,13 +26,6 @@ + #define ATH79_IP2_IRQ_COUNT 2 + #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) + +-#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) +-#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) +-#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) +-#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5) +-#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) +-#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7) +- + #define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0) + #define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1) + #define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2) diff --git a/target/linux/ar71xx/patches-3.8/025-ath79-remove-ATH79_MISC_IRQ_-defines.patch b/target/linux/ar71xx/patches-3.8/025-ath79-remove-ATH79_MISC_IRQ_-defines.patch new file mode 100644 index 0000000000..8278ad3521 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/025-ath79-remove-ATH79_MISC_IRQ_-defines.patch @@ -0,0 +1,85 @@ +From f4414336ae509d20c043264bc9f8f6bafb0e8a6f Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Thu, 7 Feb 2013 19:32:24 +0000 +Subject: [PATCH] ath79: remove ATH79_MISC_IRQ_* defines + +commit fd633cf1cfe978003888dc78ff94f926fbe7dd8a upstream. + +Use the ATH79_MISC_IRQ() macro instead. + +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4930/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/dev-common.c | 6 +++--- + arch/mips/ath79/dev-usb.c | 2 +- + arch/mips/ath79/irq.c | 2 +- + arch/mips/include/asm/mach-ath79/irq.h | 13 ------------- + 4 files changed, 5 insertions(+), 18 deletions(-) + +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -36,7 +36,7 @@ static struct resource ath79_uart_resour + static struct plat_serial8250_port ath79_uart_data[] = { + { + .mapbase = AR71XX_UART_BASE, +- .irq = ATH79_MISC_IRQ_UART, ++ .irq = ATH79_MISC_IRQ(3), + .flags = AR71XX_UART_FLAGS, + .iotype = UPIO_MEM32, + .regshift = 2, +@@ -62,8 +62,8 @@ static struct resource ar933x_uart_resou + .flags = IORESOURCE_MEM, + }, + { +- .start = ATH79_MISC_IRQ_UART, +- .end = ATH79_MISC_IRQ_UART, ++ .start = ATH79_MISC_IRQ(3), ++ .end = ATH79_MISC_IRQ(3), + .flags = IORESOURCE_IRQ, + }, + }; +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -107,7 +107,7 @@ static void __init ath79_usb_setup(void) + mdelay(900); + + ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE, +- AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI); ++ AR71XX_OHCI_SIZE, ATH79_MISC_IRQ(6)); + platform_device_register(&ath79_ohci_device); + + ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -265,7 +265,7 @@ void __init arch_init_irq(void) + BUG(); + } + +- cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; ++ cp0_perfcount_irq = ATH79_MISC_IRQ(5); + mips_cpu_irq_init(); + ath79_misc_irq_init(); + +--- a/arch/mips/include/asm/mach-ath79/irq.h ++++ b/arch/mips/include/asm/mach-ath79/irq.h +@@ -26,19 +26,6 @@ + #define ATH79_IP2_IRQ_COUNT 2 + #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) + +-#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0) +-#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1) +-#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2) +-#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3) +-#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4) +-#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) +-#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) +-#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) +-#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8) +-#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9) +-#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10) +-#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12) +- + #include_next + + #endif /* __ASM_MACH_ATH79_IRQ_H */ diff --git a/target/linux/ar71xx/patches-3.8/026-MIPS-ath79-use-dynamically-allocated-USB-platform-de.patch b/target/linux/ar71xx/patches-3.8/026-MIPS-ath79-use-dynamically-allocated-USB-platform-de.patch new file mode 100644 index 0000000000..e7770cce99 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/026-MIPS-ath79-use-dynamically-allocated-USB-platform-de.patch @@ -0,0 +1,205 @@ +From 9c3c3f7be27c88b59359e743be0437eb6f9af41f Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Sat, 9 Feb 2013 17:57:52 +0000 +Subject: [PATCH] MIPS: ath79: use dynamically allocated USB platform devices + +commit 90a938d1add4859ad3e43c3dd5ee54bd0627e42d upstream. + +The current code uses static resources and static platform +device instances for the possible USB controllers in the +system. These static variables contains initial values which +leads to data segment pollution. + +Remove the static variables and use dynamically allocated +structures instead. + +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4933/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/dev-usb.c | 111 +++++++++++++++++++++------------------------ + 1 file changed, 51 insertions(+), 60 deletions(-) + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -25,29 +25,11 @@ + #include "common.h" + #include "dev-usb.h" + +-static struct resource ath79_ohci_resources[2]; +- +-static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32); ++static u64 ath79_usb_dmamask = DMA_BIT_MASK(32); + + static struct usb_ohci_pdata ath79_ohci_pdata = { + }; + +-static struct platform_device ath79_ohci_device = { +- .name = "ohci-platform", +- .id = -1, +- .resource = ath79_ohci_resources, +- .num_resources = ARRAY_SIZE(ath79_ohci_resources), +- .dev = { +- .dma_mask = &ath79_ohci_dmamask, +- .coherent_dma_mask = DMA_BIT_MASK(32), +- .platform_data = &ath79_ohci_pdata, +- }, +-}; +- +-static struct resource ath79_ehci_resources[2]; +- +-static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32); +- + static struct usb_ehci_pdata ath79_ehci_pdata_v1 = { + .has_synopsys_hc_bug = 1, + }; +@@ -57,22 +39,16 @@ static struct usb_ehci_pdata ath79_ehci_ + .has_tt = 1, + }; + +-static struct platform_device ath79_ehci_device = { +- .name = "ehci-platform", +- .id = -1, +- .resource = ath79_ehci_resources, +- .num_resources = ARRAY_SIZE(ath79_ehci_resources), +- .dev = { +- .dma_mask = &ath79_ehci_dmamask, +- .coherent_dma_mask = DMA_BIT_MASK(32), +- }, +-}; +- +-static void __init ath79_usb_init_resource(struct resource res[2], +- unsigned long base, +- unsigned long size, +- int irq) ++static void __init ath79_usb_register(const char *name, int id, ++ unsigned long base, unsigned long size, ++ int irq, const void *data, ++ size_t data_size) + { ++ struct resource res[2]; ++ struct platform_device *pdev; ++ ++ memset(res, 0, sizeof(res)); ++ + res[0].flags = IORESOURCE_MEM; + res[0].start = base; + res[0].end = base + size - 1; +@@ -80,6 +56,19 @@ static void __init ath79_usb_init_resour + res[1].flags = IORESOURCE_IRQ; + res[1].start = irq; + res[1].end = irq; ++ ++ pdev = platform_device_register_resndata(NULL, name, id, ++ res, ARRAY_SIZE(res), ++ data, data_size); ++ ++ if (IS_ERR(pdev)) { ++ pr_err("ath79: unable to register USB at %08lx, err=%d\n", ++ base, (int) PTR_ERR(pdev)); ++ return; ++ } ++ ++ pdev->dev.dma_mask = &ath79_usb_dmamask; ++ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + } + + #define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ +@@ -106,14 +95,15 @@ static void __init ath79_usb_setup(void) + + mdelay(900); + +- ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE, +- AR71XX_OHCI_SIZE, ATH79_MISC_IRQ(6)); +- platform_device_register(&ath79_ohci_device); +- +- ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, +- AR71XX_EHCI_SIZE, ATH79_CPU_IRQ(3)); +- ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; +- platform_device_register(&ath79_ehci_device); ++ ath79_usb_register("ohci-platform", -1, ++ AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE, ++ ATH79_MISC_IRQ(6), ++ &ath79_ohci_pdata, sizeof(ath79_ohci_pdata)); ++ ++ ath79_usb_register("ehci-platform", -1, ++ AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE, ++ ATH79_CPU_IRQ(3), ++ &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1)); + } + + static void __init ar7240_usb_setup(void) +@@ -135,9 +125,10 @@ static void __init ar7240_usb_setup(void + + iounmap(usb_ctrl_base); + +- ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE, +- AR7240_OHCI_SIZE, ATH79_CPU_IRQ(3)); +- platform_device_register(&ath79_ohci_device); ++ ath79_usb_register("ohci-platform", -1, ++ AR7240_OHCI_BASE, AR7240_OHCI_SIZE, ++ ATH79_CPU_IRQ(3), ++ &ath79_ohci_pdata, sizeof(ath79_ohci_pdata)); + } + + static void __init ar724x_usb_setup(void) +@@ -151,10 +142,10 @@ static void __init ar724x_usb_setup(void + ath79_device_reset_clear(AR724X_RESET_USB_PHY); + mdelay(10); + +- ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE, +- AR724X_EHCI_SIZE, ATH79_CPU_IRQ(3)); +- ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; +- platform_device_register(&ath79_ehci_device); ++ ath79_usb_register("ehci-platform", -1, ++ AR724X_EHCI_BASE, AR724X_EHCI_SIZE, ++ ATH79_CPU_IRQ(3), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + + static void __init ar913x_usb_setup(void) +@@ -168,10 +159,10 @@ static void __init ar913x_usb_setup(void + ath79_device_reset_clear(AR913X_RESET_USB_PHY); + mdelay(10); + +- ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE, +- AR913X_EHCI_SIZE, ATH79_CPU_IRQ(3)); +- ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; +- platform_device_register(&ath79_ehci_device); ++ ath79_usb_register("ehci-platform", -1, ++ AR913X_EHCI_BASE, AR913X_EHCI_SIZE, ++ ATH79_CPU_IRQ(3), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + + static void __init ar933x_usb_setup(void) +@@ -185,10 +176,10 @@ static void __init ar933x_usb_setup(void + ath79_device_reset_clear(AR933X_RESET_USB_PHY); + mdelay(10); + +- ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE, +- AR933X_EHCI_SIZE, ATH79_CPU_IRQ(3)); +- ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; +- platform_device_register(&ath79_ehci_device); ++ ath79_usb_register("ehci-platform", -1, ++ AR933X_EHCI_BASE, AR933X_EHCI_SIZE, ++ ATH79_CPU_IRQ(3), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + + static void __init ar934x_usb_setup(void) +@@ -211,10 +202,10 @@ static void __init ar934x_usb_setup(void + ath79_device_reset_clear(AR934X_RESET_USB_HOST); + udelay(1000); + +- ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE, +- AR934X_EHCI_SIZE, ATH79_CPU_IRQ(3)); +- ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; +- platform_device_register(&ath79_ehci_device); ++ ath79_usb_register("ehci-platform", -1, ++ AR934X_EHCI_BASE, AR934X_EHCI_SIZE, ++ ATH79_CPU_IRQ(3), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + + void __init ath79_register_usb(void) diff --git a/target/linux/ar71xx/patches-3.8/027-MIPS-ath79-fix-WMAC-IRQ-resource-assignment.patch b/target/linux/ar71xx/patches-3.8/027-MIPS-ath79-fix-WMAC-IRQ-resource-assignment.patch new file mode 100644 index 0000000000..97065d52b4 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/027-MIPS-ath79-fix-WMAC-IRQ-resource-assignment.patch @@ -0,0 +1,29 @@ +From acb28a2a03a93e351e26230511a9f38d0da62fdd Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 18:51:57 +0000 +Subject: [PATCH] MIPS: ath79: fix WMAC IRQ resource assignment + +commit e3b25cead4b58fbf60270ba73a1669bf9e5635f5 upstream. + +The '.start' field of the IRQ resource assigned twice +in ar934x_wmac_setup(). The second assignment must +set the '.end' field. Fix it. + +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4954/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/dev-wmac.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -107,7 +107,7 @@ static void ar934x_wmac_setup(void) + ath79_wmac_resources[0].start = AR934X_WMAC_BASE; + ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); +- ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); + + t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); + if (t & AR934X_BOOTSTRAP_REF_CLK_40) diff --git a/target/linux/ar71xx/patches-3.8/028-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch b/target/linux/ar71xx/patches-3.8/028-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch new file mode 100644 index 0000000000..38d735bd24 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/028-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch @@ -0,0 +1,43 @@ +From 8a4de56e3b7a6fbb777c78f87142bafc22c32ac2 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 13:38:15 +0000 +Subject: [PATCH] MIPS: ath79: add early printk support for the QCA955X SoCs + +commit 908987797076b848f01b32c21d61d0e152efc236 upstream. + +The patch allows to see kernel messages on the +QCA955X SoCs in early boot stage. + +Cc: Rodriguez, Luis +Cc: Giori, Kathy +Cc: QCA Linux Team +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4944/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/early_printk.c | 2 ++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ + 2 files changed, 4 insertions(+) + +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -74,6 +74,8 @@ static void prom_putchar_init(void) + case REV_ID_MAJOR_AR9341: + case REV_ID_MAJOR_AR9342: + case REV_ID_MAJOR_AR9344: ++ case REV_ID_MAJOR_QCA9556: ++ case REV_ID_MAJOR_QCA9558: + _prom_putchar = prom_putchar_ar71xx; + break; + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -370,6 +370,8 @@ + #define REV_ID_MAJOR_AR9341 0x0120 + #define REV_ID_MAJOR_AR9342 0x1120 + #define REV_ID_MAJOR_AR9344 0x2120 ++#define REV_ID_MAJOR_QCA9556 0x0130 ++#define REV_ID_MAJOR_QCA9558 0x1130 + + #define AR71XX_REV_ID_MINOR_MASK 0x3 + #define AR71XX_REV_ID_MINOR_AR7130 0x0 diff --git a/target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch b/target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch new file mode 100644 index 0000000000..5a60ffe898 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/029-MIPS-ath79-add-SoC-detection-code-for-the-QCA955X-So.patch @@ -0,0 +1,113 @@ +From f48780829e9de625cb7fa0850fc31d050da6adeb Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 13:38:16 +0000 +Subject: [PATCH] MIPS: ath79: add SoC detection code for the QCA955X SoCs + +commit 2e6c91e392fd7be2ef0ba1e9a20e0ebe8ab79cf3 upstream. + +Also add 'soc_is_qca955[68x]' helper functions +and a Kconfig symbol for the SoC family. + +Cc: Rodriguez, Luis +Cc: Giori, Kathy +Cc: QCA Linux Team +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4943/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/Kconfig | 4 ++++ + arch/mips/ath79/setup.c | 18 +++++++++++++++++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ + arch/mips/include/asm/mach-ath79/ath79.h | 17 +++++++++++++++++ + 4 files changed, 40 insertions(+), 1 deletion(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -88,6 +88,10 @@ config SOC_AR934X + select PCI_AR724X if PCI + def_bool n + ++config SOC_QCA955X ++ select USB_ARCH_HAS_EHCI ++ def_bool n ++ + config PCI_AR724X + def_bool n + +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -164,13 +164,29 @@ static void __init ath79_detect_sys_type + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + ++ case REV_ID_MAJOR_QCA9556: ++ ath79_soc = ATH79_SOC_QCA9556; ++ chip = "9556"; ++ rev = id & QCA955X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_QCA9558: ++ ath79_soc = ATH79_SOC_QCA9558; ++ chip = "9558"; ++ rev = id & QCA955X_REV_ID_REVISION_MASK; ++ break; ++ + default: + panic("ath79: unknown SoC, id:0x%08x", id); + } + + ath79_soc_rev = rev; + +- sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); ++ if (soc_is_qca955x()) ++ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", ++ chip, rev); ++ else ++ sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); + pr_info("SoC: %s\n", ath79_sys_type); + } + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -392,6 +392,8 @@ + + #define AR934X_REV_ID_REVISION_MASK 0xf + ++#define QCA955X_REV_ID_REVISION_MASK 0xf ++ + /* + * SPI block + */ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -32,6 +32,8 @@ enum ath79_soc_type { + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, ++ ATH79_SOC_QCA9556, ++ ATH79_SOC_QCA9558, + }; + + extern enum ath79_soc_type ath79_soc; +@@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void) + return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); + } + ++static inline int soc_is_qca9556(void) ++{ ++ return ath79_soc == ATH79_SOC_QCA9556; ++} ++ ++static inline int soc_is_qca9558(void) ++{ ++ return ath79_soc == ATH79_SOC_QCA9558; ++} ++ ++static inline int soc_is_qca955x(void) ++{ ++ return soc_is_qca9556() || soc_is_qca9558(); ++} ++ + extern void __iomem *ath79_ddr_base; + extern void __iomem *ath79_pll_base; + extern void __iomem *ath79_reset_base; diff --git a/target/linux/ar71xx/patches-3.8/030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch new file mode 100644 index 0000000000..e1d4bfcfcb --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/030-MIPS-ath79-add-clock-setup-code-for-the-QCA955X-SoCs.patch @@ -0,0 +1,177 @@ +From 64d8592fd1f7265de8b31dbf294928eaf9983db5 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 13:38:17 +0000 +Subject: [PATCH] MIPS: ath79: add clock setup code for the QCA955X SoCs + +commit 41583c05c15cd3adb848f9ee8316bf8084c961cb upstream. + +The patch adds code to get various clock frequencies +from the PLLs used in the QCA955x SoCs. + +Cc: Rodriguez, Luis +Cc: Giori, Kathy +Cc: QCA Linux Team +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4945/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 39 ++++++++++++ + 2 files changed, 117 insertions(+) + +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo + iounmap(dpll_base); + } + ++static void __init qca955x_clocks_init(void) ++{ ++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ++ u32 cpu_pll, ddr_pll; ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) ++ ath79_ref_clk.rate = 40 * 1000 * 1000; ++ else ++ ath79_ref_clk.rate = 25 * 1000 * 1000; ++ ++ pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); ++ out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ QCA955X_PLL_CPU_CONFIG_REFDIV_MASK; ++ nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & ++ QCA955X_PLL_CPU_CONFIG_NINT_MASK; ++ frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & ++ QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; ++ ++ cpu_pll = nint * ath79_ref_clk.rate / ref_div; ++ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); ++ cpu_pll /= (1 << out_div); ++ ++ pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); ++ out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & ++ QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ++ QCA955X_PLL_DDR_CONFIG_REFDIV_MASK; ++ nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & ++ QCA955X_PLL_DDR_CONFIG_NINT_MASK; ++ frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & ++ QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; ++ ++ ddr_pll = nint * ath79_ref_clk.rate / ref_div; ++ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); ++ ddr_pll /= (1 << out_div); ++ ++ clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); ++ ++ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & ++ QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) ++ ath79_cpu_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) ++ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); ++ else ++ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & ++ QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) ++ ath79_ddr_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) ++ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); ++ else ++ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & ++ QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) ++ ath79_ahb_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) ++ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); ++ else ++ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); ++ ++ ath79_wdt_clk.rate = ath79_ref_clk.rate; ++ ath79_uart_clk.rate = ath79_ref_clk.rate; ++} ++ + void __init ath79_clocks_init(void) + { + if (soc_is_ar71xx()) +@@ -307,6 +383,8 @@ void __init ath79_clocks_init(void) + ar933x_clocks_init(); + else if (soc_is_ar934x()) + ar934x_clocks_init(); ++ else if (soc_is_qca955x()) ++ qca955x_clocks_init(); + else + BUG(); + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -225,6 +225,41 @@ + #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define QCA955X_PLL_CPU_CONFIG_REG 0x00 ++#define QCA955X_PLL_DDR_CONFIG_REG 0x04 ++#define QCA955X_PLL_CLK_CTRL_REG 0x08 ++ ++#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 ++#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f ++#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 ++#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f ++#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 ++#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f ++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 ++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 ++ ++#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 ++#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff ++#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 ++#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f ++#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 ++#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f ++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 ++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 ++ ++#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) ++#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) ++#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) ++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 ++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f ++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 ++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f ++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 ++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f ++#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) ++#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) ++#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) ++ + /* + * USB_CONFIG block + */ +@@ -264,6 +299,8 @@ + #define AR934X_RESET_REG_BOOTSTRAP 0xb0 + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + ++#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 ++ + #define MISC_INT_ETHSW BIT(12) + #define MISC_INT_TIMER4 BIT(10) + #define MISC_INT_TIMER3 BIT(9) +@@ -341,6 +378,8 @@ + #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) + #define AR934X_BOOTSTRAP_DDR1 BIT(0) + ++#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) ++ + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) + #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) + #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) diff --git a/target/linux/ar71xx/patches-3.8/031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch b/target/linux/ar71xx/patches-3.8/031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch new file mode 100644 index 0000000000..dd79fa9415 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch @@ -0,0 +1,246 @@ +From f1c0239d61d6d43469133d144e458f485b6cbda6 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 18:53:47 +0000 +Subject: [PATCH] MIPS: ath79: add IRQ handling code for the QCA955X SoCs + +commit 53330332f176eaa9567481c69bbad8b2176b4eb5 upstream. + +The IRQ routing in the QCA955x SoCs is slightly +different from the routing implemented in the +already supported SoCs. + +Cc: Rodriguez, Luis +Cc: Giori, Kathy +Cc: QCA Linux Team +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4955/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/irq.c | 110 ++++++++++++++++++++++-- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 32 +++++++ + arch/mips/include/asm/mach-ath79/irq.h | 6 +- + 3 files changed, 140 insertions(+), 8 deletions(-) + +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -103,7 +103,10 @@ static void __init ath79_misc_irq_init(v + + if (soc_is_ar71xx() || soc_is_ar913x()) + ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; +- else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) ++ else if (soc_is_ar724x() || ++ soc_is_ar933x() || ++ soc_is_ar934x() || ++ soc_is_qca955x()) + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; + else + BUG(); +@@ -150,6 +153,88 @@ static void ar934x_ip2_irq_init(void) + irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); + } + ++static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); ++ status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL; ++ ++ if (status == 0) { ++ spurious_interrupt(); ++ goto enable; ++ } ++ ++ if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP2_IRQ(0)); ++ } ++ ++ if (status & QCA955X_EXT_INT_WMAC_ALL) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP2_IRQ(1)); ++ } ++ ++enable: ++ enable_irq(irq); ++} ++ ++static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); ++ status &= QCA955X_EXT_INT_PCIE_RC2_ALL | ++ QCA955X_EXT_INT_USB1 | ++ QCA955X_EXT_INT_USB2; ++ ++ if (status == 0) { ++ spurious_interrupt(); ++ goto enable; ++ } ++ ++ if (status & QCA955X_EXT_INT_USB1) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(0)); ++ } ++ ++ if (status & QCA955X_EXT_INT_USB2) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(1)); ++ } ++ ++ if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(2)); ++ } ++ ++enable: ++ enable_irq(irq); ++} ++ ++static void qca955x_irq_init(void) ++{ ++ int i; ++ ++ for (i = ATH79_IP2_IRQ_BASE; ++ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); ++ ++ for (i = ATH79_IP3_IRQ_BASE; ++ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); ++} ++ + asmlinkage void plat_irq_dispatch(void) + { + unsigned long pending; +@@ -185,6 +270,17 @@ asmlinkage void plat_irq_dispatch(void) + * Issue a flush in the handlers to ensure that the driver sees + * the update. + */ ++ ++static void ath79_default_ip2_handler(void) ++{ ++ do_IRQ(ATH79_CPU_IRQ(2)); ++} ++ ++static void ath79_default_ip3_handler(void) ++{ ++ do_IRQ(ATH79_CPU_IRQ(3)); ++} ++ + static void ar71xx_ip2_handler(void) + { + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); +@@ -209,11 +305,6 @@ static void ar933x_ip2_handler(void) + do_IRQ(ATH79_CPU_IRQ(2)); + } + +-static void ar934x_ip2_handler(void) +-{ +- do_IRQ(ATH79_CPU_IRQ(2)); +-} +- + static void ar71xx_ip3_handler(void) + { + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); +@@ -259,8 +350,11 @@ void __init arch_init_irq(void) + ath79_ip2_handler = ar933x_ip2_handler; + ath79_ip3_handler = ar933x_ip3_handler; + } else if (soc_is_ar934x()) { +- ath79_ip2_handler = ar934x_ip2_handler; ++ ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ar934x_ip3_handler; ++ } else if (soc_is_qca955x()) { ++ ath79_ip2_handler = ath79_default_ip2_handler; ++ ath79_ip3_handler = ath79_default_ip3_handler; + } else { + BUG(); + } +@@ -271,4 +365,6 @@ void __init arch_init_irq(void) + + if (soc_is_ar934x()) + ar934x_ip2_irq_init(); ++ else if (soc_is_qca955x()) ++ qca955x_irq_init(); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -300,6 +300,7 @@ + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + + #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 ++#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + + #define MISC_INT_ETHSW BIT(12) + #define MISC_INT_TIMER4 BIT(10) +@@ -398,6 +399,37 @@ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + ++#define QCA955X_EXT_INT_WMAC_MISC BIT(0) ++#define QCA955X_EXT_INT_WMAC_TX BIT(1) ++#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) ++#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) ++#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) ++#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) ++#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) ++#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) ++#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) ++#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) ++#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) ++#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) ++#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) ++#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) ++#define QCA955X_EXT_INT_USB1 BIT(24) ++#define QCA955X_EXT_INT_USB2 BIT(28) ++ ++#define QCA955X_EXT_INT_WMAC_ALL \ ++ (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ ++ QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) ++ ++#define QCA955X_EXT_INT_PCIE_RC1_ALL \ ++ (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ ++ QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ ++ QCA955X_EXT_INT_PCIE_RC1_INT3) ++ ++#define QCA955X_EXT_INT_PCIE_RC2_ALL \ ++ (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ ++ QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ ++ QCA955X_EXT_INT_PCIE_RC2_INT3) ++ + #define REV_ID_MAJOR_MASK 0xfff0 + #define REV_ID_MAJOR_AR71XX 0x00a0 + #define REV_ID_MAJOR_AR913X 0x00b0 +--- a/arch/mips/include/asm/mach-ath79/irq.h ++++ b/arch/mips/include/asm/mach-ath79/irq.h +@@ -10,7 +10,7 @@ + #define __ASM_MACH_ATH79_IRQ_H + + #define MIPS_CPU_IRQ_BASE 0 +-#define NR_IRQS 48 ++#define NR_IRQS 51 + + #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x)) + +@@ -26,6 +26,10 @@ + #define ATH79_IP2_IRQ_COUNT 2 + #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) + ++#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT) ++#define ATH79_IP3_IRQ_COUNT 3 ++#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x)) ++ + #include_next + + #endif /* __ASM_MACH_ATH79_IRQ_H */ diff --git a/target/linux/ar71xx/patches-3.8/032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch new file mode 100644 index 0000000000..538da3c6f8 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/032-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch @@ -0,0 +1,50 @@ +From 8817bcbbaf64d54bd4d06659cc77d1bfc9e53dad Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 13:38:19 +0000 +Subject: [PATCH] MIPS: ath79: add GPIO setup code for the QCA955X SoCs + +commit f818ca3e6894d4a630a1ecc673c91df8fb6f6898 upstream. + +The existing code can handle the GPIO controller of +the QCA955x SoCs. Add a minimal glue code to make it +working. + +Cc: Rodriguez, Luis +Cc: Giori, Kathy +Cc: QCA Linux Team +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4947/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/gpio.c | 4 +++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + + 2 files changed, 4 insertions(+), 1 deletion(-) + +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -194,12 +194,14 @@ void __init ath79_gpio_init(void) + ath79_gpio_count = AR933X_GPIO_COUNT; + else if (soc_is_ar934x()) + ath79_gpio_count = AR934X_GPIO_COUNT; ++ else if (soc_is_qca955x()) ++ ath79_gpio_count = QCA955X_GPIO_COUNT; + else + BUG(); + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; +- if (soc_is_ar934x()) { ++ if (soc_is_ar934x() || soc_is_qca955x()) { + ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; + ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -510,6 +510,7 @@ + #define AR913X_GPIO_COUNT 22 + #define AR933X_GPIO_COUNT 30 + #define AR934X_GPIO_COUNT 23 ++#define QCA955X_GPIO_COUNT 24 + + /* + * SRIF block diff --git a/target/linux/ar71xx/patches-3.8/033-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch b/target/linux/ar71xx/patches-3.8/033-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch new file mode 100644 index 0000000000..42877ff63c --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/033-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch @@ -0,0 +1,53 @@ +From d3cc7a15c1e1a04e8d561c0b05d176434142bf9a Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 13:38:20 +0000 +Subject: [PATCH] MIPS: ath79: add QCA955X specific glue to + ath79_device_reset_{set, clear} + +commit 7d4c2af9bdbbe789fe4a93f32c5890d72cbf60a1 upstream. + +The ath79_device_reset_* are causing BUG when +those are used on the QCA955x SoCs. The patch +adds the required code to avoid that. + +Cc: Rodriguez, Luis +Cc: Giori, Kathy +Cc: QCA Linux Team +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4948/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/common.c | 4 ++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + + 2 files changed, 5 insertions(+) + +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -72,6 +72,8 @@ void ath79_device_reset_set(u32 mask) + reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca955x()) ++ reg = QCA955X_RESET_REG_RESET_MODULE; + else + BUG(); + +@@ -98,6 +100,8 @@ void ath79_device_reset_clear(u32 mask) + reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca955x()) ++ reg = QCA955X_RESET_REG_RESET_MODULE; + else + BUG(); + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -299,6 +299,7 @@ + #define AR934X_RESET_REG_BOOTSTRAP 0xb0 + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + ++#define QCA955X_RESET_REG_RESET_MODULE 0x1c + #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 + #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + diff --git a/target/linux/ar71xx/patches-3.8/034-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/034-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch new file mode 100644 index 0000000000..38acf45986 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/034-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch @@ -0,0 +1,34 @@ +From 25320dbceda508afc5b2de1986072caa9e04ad1b Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 13:38:21 +0000 +Subject: [PATCH] MIPS: ath79: register UART for the QCA955X SoCs + +commit 13992303fa705ae1e4acf4660c69687672996029 upstream. + +Similarly to the preceding SoCs, the QCA955X SoCs +also have a built-in NS16650 compatible UART. +Register the platform device for that to make +it usable. + +Cc: Rodriguez, Luis +Cc: Giori, Kathy +Cc: QCA Linux Team +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4949/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/dev-common.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -90,7 +90,8 @@ void __init ath79_register_uart(void) + if (soc_is_ar71xx() || + soc_is_ar724x() || + soc_is_ar913x() || +- soc_is_ar934x()) { ++ soc_is_ar934x() || ++ soc_is_qca955x()) { + ath79_uart_data[0].uartclk = clk_get_rate(clk); + platform_device_register(&ath79_uart_device); + } else if (soc_is_ar933x()) { diff --git a/target/linux/ar71xx/patches-3.8/035-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch b/target/linux/ar71xx/patches-3.8/035-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch new file mode 100644 index 0000000000..d208fff598 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/035-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch @@ -0,0 +1,81 @@ +From cf40fbb509eaa53ff787dce41911b2545bd001ea Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 18:54:33 +0000 +Subject: [PATCH] MIPS: ath79: add WMAC registration code for the QCA955X SoCs + +commit e9c0d0aaa3a7a6e66135e8b44f3323143a635098 upstream. + +The SoC has a built-in wireless MAC. Register a platform +device for that to make it usable with the ath9k driver. + +Cc: Rodriguez, Luis +Cc: Giori, Kathy +Cc: QCA Linux Team +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4956/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/Kconfig | 2 +- + arch/mips/ath79/dev-wmac.c | 20 ++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 +++ + 3 files changed, 24 insertions(+), 1 deletion(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -108,7 +108,7 @@ config ATH79_DEV_USB + def_bool n + + config ATH79_DEV_WMAC +- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X) ++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) + def_bool n + + endif +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = true; + } + ++static void qca955x_wmac_setup(void) ++{ ++ u32 t; ++ ++ ath79_wmac_device.name = "qca955x_wmac"; ++ ++ ath79_wmac_resources[0].start = QCA955X_WMAC_BASE; ++ ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); ++ ++ t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); ++ if (t & QCA955X_BOOTSTRAP_REF_CLK_40) ++ ath79_wmac_data.is_clk_25mhz = false; ++ else ++ ath79_wmac_data.is_clk_25mhz = true; ++} ++ + void __init ath79_register_wmac(u8 *cal_data) + { + if (soc_is_ar913x()) +@@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_ + ar933x_wmac_setup(); + else if (soc_is_ar934x()) + ar934x_wmac_setup(); ++ else if (soc_is_qca955x()) ++ qca955x_wmac_setup(); + else + BUG(); + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -94,6 +94,9 @@ + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 + ++#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) ++#define QCA955X_WMAC_SIZE 0x20000 ++ + /* + * DDR_CTRL block + */ diff --git a/target/linux/ar71xx/patches-3.8/036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.8/036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch new file mode 100644 index 0000000000..c431f94b18 --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch @@ -0,0 +1,115 @@ +From bc14333054c5ecee4bc7e8760d0ffbb730f32c54 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 13:38:23 +0000 +Subject: [PATCH] MIPS: ath79: add PCI controller registration code for the + QCA955X SoCs + +commit 0a5f3b1c9f20eb44142e3b37662de15c944f759d upstream. + +Add SoC specific PCI IRQ map, and register platform +devices for the two built-in PCIe RCs. + +Cc: Rodriguez, Luis +Cc: Giori, Kathy +Cc: QCA Linux Team +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4951/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/Kconfig | 2 ++ + arch/mips/ath79/pci.c | 36 ++++++++++++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 13 +++++++++ + 3 files changed, 51 insertions(+) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -90,6 +90,8 @@ config SOC_AR934X + + config SOC_QCA955X + select USB_ARCH_HAS_EHCI ++ select HW_HAS_PCI ++ select PCI_AR724X if PCI + def_bool n + + config PCI_AR724X +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x + } + }; + ++static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = { ++ { ++ .bus = 0, ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(0), ++ }, ++ { ++ .bus = 1, ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(1), ++ }, ++}; ++ + int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) + { + int irq = -1; +@@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct + soc_is_ar9344()) { + ath79_pci_irq_map = ar724x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); ++ } else if (soc_is_qca955x()) { ++ ath79_pci_irq_map = qca955x_pci_irq_map; ++ ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); + } else { + pr_crit("pci %s: invalid irq map\n", + pci_name((struct pci_dev *) dev)); +@@ -225,6 +243,24 @@ int __init ath79_register_pci(void) + AR724X_PCI_MEM_SIZE, + 0, + ATH79_IP2_IRQ(0)); ++ } else if (soc_is_qca9558()) { ++ pdev = ath79_register_pci_ar724x(0, ++ QCA955X_PCI_CFG_BASE0, ++ QCA955X_PCI_CTRL_BASE0, ++ QCA955X_PCI_CRP_BASE0, ++ QCA955X_PCI_MEM_BASE0, ++ QCA955X_PCI_MEM_SIZE, ++ 0, ++ ATH79_IP2_IRQ(0)); ++ ++ pdev = ath79_register_pci_ar724x(1, ++ QCA955X_PCI_CFG_BASE1, ++ QCA955X_PCI_CTRL_BASE1, ++ QCA955X_PCI_CRP_BASE1, ++ QCA955X_PCI_MEM_BASE1, ++ QCA955X_PCI_MEM_SIZE, ++ 1, ++ ATH79_IP3_IRQ(2)); + } else { + /* No PCI support */ + return -ENODEV; +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -94,6 +94,19 @@ + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 + ++#define QCA955X_PCI_MEM_BASE0 0x10000000 ++#define QCA955X_PCI_MEM_BASE1 0x12000000 ++#define QCA955X_PCI_MEM_SIZE 0x02000000 ++#define QCA955X_PCI_CFG_BASE0 0x14000000 ++#define QCA955X_PCI_CFG_BASE1 0x16000000 ++#define QCA955X_PCI_CFG_SIZE 0x1000 ++#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) ++#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) ++#define QCA955X_PCI_CRP_SIZE 0x1000 ++#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) ++#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) ++#define QCA955X_PCI_CTRL_SIZE 0x100 ++ + #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define QCA955X_WMAC_SIZE 0x20000 + diff --git a/target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch new file mode 100644 index 0000000000..15b7c750ee --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/037-MIPS-ath79-add-USB-controller-registration-code-for-.patch @@ -0,0 +1,65 @@ +From 281db30007b5836ce8acf5a45160fde6b176eda4 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 13:38:24 +0000 +Subject: [PATCH] MIPS: ath79: add USB controller registration code for the + QCA955X SoCs + +commit 82c46840ae6bd8a147c59cd51f636d913989324a upstream. + +Register platfom devices for the built-in USB +controllers of the SoCs. + +Cc: Rodriguez, Luis +Cc: Giori, Kathy +Cc: QCA Linux Team +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4952/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/dev-usb.c | 15 +++++++++++++++ + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 +++ + 2 files changed, 18 insertions(+) + +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -208,6 +208,19 @@ static void __init ar934x_usb_setup(void + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + ++static void __init qca955x_usb_setup(void) ++{ ++ ath79_usb_register("ehci-platform", 0, ++ QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE, ++ ATH79_IP3_IRQ(0), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); ++ ++ ath79_usb_register("ehci-platform", 1, ++ QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE, ++ ATH79_IP3_IRQ(1), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); ++} ++ + void __init ath79_register_usb(void) + { + if (soc_is_ar71xx()) +@@ -222,6 +235,8 @@ void __init ath79_register_usb(void) + ar933x_usb_setup(); + else if (soc_is_ar934x()) + ar934x_usb_setup(); ++ else if (soc_is_qca955x()) ++ qca955x_usb_setup(); + else + BUG(); + } +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -109,6 +109,9 @@ + + #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define QCA955X_WMAC_SIZE 0x20000 ++#define QCA955X_EHCI0_BASE 0x1b000000 ++#define QCA955X_EHCI1_BASE 0x1b400000 ++#define QCA955X_EHCI_SIZE 0x1000 + + /* + * DDR_CTRL block diff --git a/target/linux/ar71xx/patches-3.8/038-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch b/target/linux/ar71xx/patches-3.8/038-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch new file mode 100644 index 0000000000..e235570e8a --- /dev/null +++ b/target/linux/ar71xx/patches-3.8/038-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch @@ -0,0 +1,234 @@ +From 7f8c0c731409b9c3e62fa8a6eb4830ace8568769 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Fri, 15 Feb 2013 13:38:25 +0000 +Subject: [PATCH] MIPS: ath79: add support for the Qualcomm Atheros AP136-010 + board + +commit 27ea052acb9eaca98cc90bf1b8738b6d0ea5bc2f upstream. + +Also enable the board in the default configuration. + +Cc: Rodriguez, Luis +Cc: Giori, Kathy +Cc: QCA Linux Team +Signed-off-by: Gabor Juhos +Patchwork: http://patchwork.linux-mips.org/patch/4953/ +Signed-off-by: John Crispin +--- + arch/mips/ath79/Kconfig | 12 +++ + arch/mips/ath79/Makefile | 1 + + arch/mips/ath79/mach-ap136.c | 156 +++++++++++++++++++++++++++++++++++++ + arch/mips/ath79/machtypes.h | 1 + + arch/mips/configs/ath79_defconfig | 1 + + 5 files changed, 171 insertions(+) + create mode 100644 arch/mips/ath79/mach-ap136.c + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -14,6 +14,18 @@ config ATH79_MACH_AP121 + Say 'Y' here if you want your kernel to support the + Atheros AP121 reference board. + ++config ATH79_MACH_AP136 ++ bool "Atheros AP136 reference board" ++ select SOC_QCA955X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP136 reference board. ++ + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wma + # Machines + # + obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o ++obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o + obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o + obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o + obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o +--- /dev/null ++++ b/arch/mips/ath79/mach-ap136.c +@@ -0,0 +1,156 @@ ++/* ++ * Qualcomm Atheros AP136 reference board support ++ * ++ * Copyright (c) 2012 Qualcomm Atheros ++ * Copyright (c) 2012-2013 Gabor Juhos ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ * ++ */ ++ ++#include ++#include ++ ++#include "machtypes.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-spi.h" ++#include "dev-usb.h" ++#include "dev-wmac.h" ++#include "pci.h" ++ ++#define AP136_GPIO_LED_STATUS_RED 14 ++#define AP136_GPIO_LED_STATUS_GREEN 19 ++#define AP136_GPIO_LED_USB 4 ++#define AP136_GPIO_LED_WLAN_2G 13 ++#define AP136_GPIO_LED_WLAN_5G 12 ++#define AP136_GPIO_LED_WPS_RED 15 ++#define AP136_GPIO_LED_WPS_GREEN 20 ++ ++#define AP136_GPIO_BTN_WPS 16 ++#define AP136_GPIO_BTN_RFKILL 21 ++ ++#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) ++ ++#define AP136_WMAC_CALDATA_OFFSET 0x1000 ++#define AP136_PCIE_CALDATA_OFFSET 0x5000 ++ ++static struct gpio_led ap136_leds_gpio[] __initdata = { ++ { ++ .name = "qca:green:status", ++ .gpio = AP136_GPIO_LED_STATUS_GREEN, ++ .active_low = 1, ++ }, ++ { ++ .name = "qca:red:status", ++ .gpio = AP136_GPIO_LED_STATUS_RED, ++ .active_low = 1, ++ }, ++ { ++ .name = "qca:green:wps", ++ .gpio = AP136_GPIO_LED_WPS_GREEN, ++ .active_low = 1, ++ }, ++ { ++ .name = "qca:red:wps", ++ .gpio = AP136_GPIO_LED_WPS_RED, ++ .active_low = 1, ++ }, ++ { ++ .name = "qca:red:wlan-2g", ++ .gpio = AP136_GPIO_LED_WLAN_2G, ++ .active_low = 1, ++ }, ++ { ++ .name = "qca:red:usb", ++ .gpio = AP136_GPIO_LED_USB, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button ap136_gpio_keys[] __initdata = { ++ { ++ .desc = "WPS button", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP136_GPIO_BTN_WPS, ++ .active_low = 1, ++ }, ++ { ++ .desc = "RFKILL button", ++ .type = EV_KEY, ++ .code = KEY_RFKILL, ++ .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP136_GPIO_BTN_RFKILL, ++ .active_low = 1, ++ }, ++}; ++ ++static struct spi_board_info ap136_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "mx25l6405d", ++ } ++}; ++ ++static struct ath79_spi_platform_data ap136_spi_data = { ++ .bus_num = 0, ++ .num_chipselect = 1, ++}; ++ ++#ifdef CONFIG_PCI ++static struct ath9k_platform_data ap136_ath9k_data; ++ ++static int ap136_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) ++ dev->dev.platform_data = &ap136_ath9k_data; ++ ++ return 0; ++} ++ ++static void __init ap136_pci_init(u8 *eeprom) ++{ ++ memcpy(ap136_ath9k_data.eeprom_data, eeprom, ++ sizeof(ap136_ath9k_data.eeprom_data)); ++ ++ ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); ++ ath79_register_pci(); ++} ++#else ++static inline void ap136_pci_init(void) {} ++#endif /* CONFIG_PCI */ ++ ++static void __init ap136_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), ++ ap136_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap136_gpio_keys), ++ ap136_gpio_keys); ++ ath79_register_spi(&ap136_spi_data, ap136_spi_info, ++ ARRAY_SIZE(ap136_spi_info)); ++ ath79_register_usb(); ++ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); ++ ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); ++} ++ ++MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", ++ "Atheros AP136-010 reference board", ++ ap136_setup); +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -17,6 +17,7 @@ + enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP121, /* Atheros AP121 reference board */ ++ ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ +--- a/arch/mips/configs/ath79_defconfig ++++ b/arch/mips/configs/ath79_defconfig +@@ -1,5 +1,6 @@ + CONFIG_ATH79=y + CONFIG_ATH79_MACH_AP121=y ++CONFIG_ATH79_MACH_AP136=y + CONFIG_ATH79_MACH_AP81=y + CONFIG_ATH79_MACH_DB120=y + CONFIG_ATH79_MACH_PB44=y diff --git a/target/linux/ar71xx/patches-3.8/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch b/target/linux/ar71xx/patches-3.8/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch deleted file mode 100644 index 7f1f2302f9..0000000000 --- a/target/linux/ar71xx/patches-3.8/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 114df1e368b8503de1fe63e97d6eea521eecfbe4 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 24 Jun 2012 13:40:38 +0200 -Subject: [PATCH 16/34] MIPS: ath79: add early printk support for the QCA955X SoCs - -Signed-off-by: Gabor Juhos ---- - arch/mips/ath79/early_printk.c | 1 + - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + - 2 files changed, 2 insertions(+), 0 deletions(-) - ---- a/arch/mips/ath79/early_printk.c -+++ b/arch/mips/ath79/early_printk.c -@@ -74,6 +74,7 @@ static void prom_putchar_init(void) - case REV_ID_MAJOR_AR9341: - case REV_ID_MAJOR_AR9342: - case REV_ID_MAJOR_AR9344: -+ case REV_ID_MAJOR_QCA9558: - _prom_putchar = prom_putchar_ar71xx; - break; - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -370,6 +370,7 @@ - #define REV_ID_MAJOR_AR9341 0x0120 - #define REV_ID_MAJOR_AR9342 0x1120 - #define REV_ID_MAJOR_AR9344 0x2120 -+#define REV_ID_MAJOR_QCA9558 0x1130 - - #define AR71XX_REV_ID_MINOR_MASK 0x3 - #define AR71XX_REV_ID_MINOR_AR7130 0x0 diff --git a/target/linux/ar71xx/patches-3.8/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch b/target/linux/ar71xx/patches-3.8/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch deleted file mode 100644 index 1d9dd4beb4..0000000000 --- a/target/linux/ar71xx/patches-3.8/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 3c3c0eccf63b12fea98fd0eb65d0ccf69a7c5a57 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 24 Jun 2012 13:42:16 +0200 -Subject: [PATCH 17/34] MIPS: ath79: add SoC detection code for the QCA9558 SoC - -Signed-off-by: Gabor Juhos ---- - arch/mips/ath79/Kconfig | 4 ++++ - arch/mips/ath79/setup.c | 12 +++++++++++- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ - arch/mips/include/asm/mach-ath79/ath79.h | 11 +++++++++++ - 4 files changed, 28 insertions(+), 1 deletions(-) - ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -88,6 +88,10 @@ config SOC_AR934X - select PCI_AR724X if PCI - def_bool n - -+config SOC_QCA955X -+ select USB_ARCH_HAS_EHCI -+ def_bool n -+ - config PCI_AR724X - def_bool n - ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -164,13 +164,23 @@ static void __init ath79_detect_sys_type - rev = id & AR934X_REV_ID_REVISION_MASK; - break; - -+ case REV_ID_MAJOR_QCA9558: -+ ath79_soc = ATH79_SOC_QCA9558; -+ chip = "9558"; -+ rev = id & AR944X_REV_ID_REVISION_MASK; -+ break; -+ - default: - panic("ath79: unknown SoC, id:0x%08x", id); - } - - ath79_soc_rev = rev; - -- sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); -+ if (soc_is_qca955x()) -+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", -+ chip, rev); -+ else -+ sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); - pr_info("SoC: %s\n", ath79_sys_type); - } - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -391,6 +391,8 @@ - - #define AR934X_REV_ID_REVISION_MASK 0xf - -+#define AR944X_REV_ID_REVISION_MASK 0xf -+ - /* - * SPI block - */ ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -32,6 +32,7 @@ enum ath79_soc_type { - ATH79_SOC_AR9341, - ATH79_SOC_AR9342, - ATH79_SOC_AR9344, -+ ATH79_SOC_QCA9558, - }; - - extern enum ath79_soc_type ath79_soc; -@@ -98,6 +99,16 @@ static inline int soc_is_ar934x(void) - return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); - } - -+static inline int soc_is_qca9558(void) -+{ -+ return ath79_soc == ATH79_SOC_QCA9558; -+} -+ -+static inline int soc_is_qca955x(void) -+{ -+ return soc_is_qca9558(); -+} -+ - extern void __iomem *ath79_ddr_base; - extern void __iomem *ath79_pll_base; - extern void __iomem *ath79_reset_base; diff --git a/target/linux/ar71xx/patches-3.8/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch deleted file mode 100644 index bb0924c430..0000000000 --- a/target/linux/ar71xx/patches-3.8/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch +++ /dev/null @@ -1,167 +0,0 @@ -From f465a16766a015a31d4e83af1ad62cc718d64f5a Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 24 Jun 2012 13:43:08 +0200 -Subject: [PATCH 18/34] MIPS: ath79: add clock setup for the QCA955X SoCs - -Signed-off-by: Gabor Juhos ---- - arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++ - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 39 ++++++++++++ - 2 files changed, 117 insertions(+), 0 deletions(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo - iounmap(dpll_base); - } - -+static void __init qca955x_clocks_init(void) -+{ -+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; -+ u32 cpu_pll, ddr_pll; -+ u32 bootstrap; -+ -+ bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); -+ if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) -+ ath79_ref_clk.rate = 40 * 1000 * 1000; -+ else -+ ath79_ref_clk.rate = 25 * 1000 * 1000; -+ -+ pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); -+ out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & -+ QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -+ QCA955X_PLL_CPU_CONFIG_REFDIV_MASK; -+ nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & -+ QCA955X_PLL_CPU_CONFIG_NINT_MASK; -+ frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & -+ QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; -+ -+ cpu_pll = nint * ath79_ref_clk.rate / ref_div; -+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); -+ cpu_pll /= (1 << out_div); -+ -+ pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); -+ out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & -+ QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; -+ ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & -+ QCA955X_PLL_DDR_CONFIG_REFDIV_MASK; -+ nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & -+ QCA955X_PLL_DDR_CONFIG_NINT_MASK; -+ frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & -+ QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; -+ -+ ddr_pll = nint * ath79_ref_clk.rate / ref_div; -+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); -+ ddr_pll /= (1 << out_div); -+ -+ clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); -+ -+ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & -+ QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) -+ ath79_cpu_clk.rate = ath79_ref_clk.rate; -+ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) -+ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); -+ else -+ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & -+ QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) -+ ath79_ddr_clk.rate = ath79_ref_clk.rate; -+ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) -+ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); -+ else -+ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); -+ -+ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & -+ QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; -+ -+ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) -+ ath79_ahb_clk.rate = ath79_ref_clk.rate; -+ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) -+ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); -+ else -+ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); -+ -+ ath79_wdt_clk.rate = ath79_ref_clk.rate; -+ ath79_uart_clk.rate = ath79_ref_clk.rate; -+} -+ - void __init ath79_clocks_init(void) - { - if (soc_is_ar71xx()) -@@ -307,6 +383,8 @@ void __init ath79_clocks_init(void) - ar933x_clocks_init(); - else if (soc_is_ar934x()) - ar934x_clocks_init(); -+ else if (soc_is_qca955x()) -+ qca955x_clocks_init(); - else - BUG(); - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -225,6 +225,41 @@ - #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) - #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -+#define QCA955X_PLL_CPU_CONFIG_REG 0x00 -+#define QCA955X_PLL_DDR_CONFIG_REG 0x04 -+#define QCA955X_PLL_CLK_CTRL_REG 0x08 -+ -+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 -+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 -+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f -+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 -+ -+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 -+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff -+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 -+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f -+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 -+ -+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) -+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) -+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) -+ - /* - * USB_CONFIG block - */ -@@ -264,6 +299,8 @@ - #define AR934X_RESET_REG_BOOTSTRAP 0xb0 - #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac - -+#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 -+ - #define MISC_INT_ETHSW BIT(12) - #define MISC_INT_TIMER4 BIT(10) - #define MISC_INT_TIMER3 BIT(9) -@@ -341,6 +378,8 @@ - #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) - #define AR934X_BOOTSTRAP_DDR1 BIT(0) - -+#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) -+ - #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) - #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) - #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) diff --git a/target/linux/ar71xx/patches-3.8/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch b/target/linux/ar71xx/patches-3.8/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch deleted file mode 100644 index e30e4e7032..0000000000 --- a/target/linux/ar71xx/patches-3.8/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch +++ /dev/null @@ -1,239 +0,0 @@ -From 5d0de52f8e36916485a61b820916b71b5d918e6f Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 24 Jun 2012 13:44:23 +0200 -Subject: [PATCH 19/34] MIPS: ath79: add IRQ handling code for the QCA955X SoCs - -Signed-off-by: Gabor Juhos ---- - arch/mips/ath79/irq.c | 110 ++++++++++++++++++++++-- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 32 +++++++ - arch/mips/include/asm/mach-ath79/irq.h | 9 ++- - 3 files changed, 142 insertions(+), 9 deletions(-) - ---- a/arch/mips/ath79/irq.c -+++ b/arch/mips/ath79/irq.c -@@ -103,7 +103,10 @@ static void __init ath79_misc_irq_init(v - - if (soc_is_ar71xx() || soc_is_ar913x()) - ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; -- else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) -+ else if (soc_is_ar724x() || -+ soc_is_ar933x() || -+ soc_is_ar934x() || -+ soc_is_qca955x()) - ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; - else - BUG(); -@@ -150,6 +153,88 @@ static void ar934x_ip2_irq_init(void) - irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch); - } - -+static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) -+{ -+ u32 status; -+ -+ disable_irq_nosync(irq); -+ -+ status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); -+ status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL; -+ -+ if (status == 0) { -+ spurious_interrupt(); -+ goto enable; -+ } -+ -+ if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { -+ /* TODO: flush DDR? */ -+ generic_handle_irq(ATH79_IP2_IRQ(0)); -+ } -+ -+ if (status & QCA955X_EXT_INT_WMAC_ALL) { -+ /* TODO: flsuh DDR? */ -+ generic_handle_irq(ATH79_IP2_IRQ(1)); -+ } -+ -+enable: -+ enable_irq(irq); -+} -+ -+static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc) -+{ -+ u32 status; -+ -+ disable_irq_nosync(irq); -+ -+ status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); -+ status &= QCA955X_EXT_INT_PCIE_RC2_ALL | -+ QCA955X_EXT_INT_USB1 | -+ QCA955X_EXT_INT_USB2; -+ -+ if (status == 0) { -+ spurious_interrupt(); -+ goto enable; -+ } -+ -+ if (status & QCA955X_EXT_INT_USB1) { -+ /* TODO: flush DDR? */ -+ generic_handle_irq(ATH79_IP3_IRQ(0)); -+ } -+ -+ if (status & QCA955X_EXT_INT_USB2) { -+ /* TODO: flsuh DDR? */ -+ generic_handle_irq(ATH79_IP3_IRQ(1)); -+ } -+ -+ if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) { -+ /* TODO: flush DDR? */ -+ generic_handle_irq(ATH79_IP3_IRQ(2)); -+ } -+ -+enable: -+ enable_irq(irq); -+} -+ -+static void qca955x_irq_init(void) -+{ -+ int i; -+ -+ for (i = ATH79_IP2_IRQ_BASE; -+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &dummy_irq_chip, -+ handle_level_irq); -+ -+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, qca955x_ip2_irq_dispatch); -+ -+ for (i = ATH79_IP3_IRQ_BASE; -+ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &dummy_irq_chip, -+ handle_level_irq); -+ -+ irq_set_chained_handler(ATH79_CPU_IRQ_IP3, qca955x_ip3_irq_dispatch); -+} -+ - asmlinkage void plat_irq_dispatch(void) - { - unsigned long pending; -@@ -185,6 +270,17 @@ asmlinkage void plat_irq_dispatch(void) - * Issue a flush in the handlers to ensure that the driver sees - * the update. - */ -+ -+static void ath79_default_ip2_handler(void) -+{ -+ do_IRQ(ATH79_CPU_IRQ_IP2); -+} -+ -+static void ath79_default_ip3_handler(void) -+{ -+ do_IRQ(ATH79_CPU_IRQ_USB); -+} -+ - static void ar71xx_ip2_handler(void) - { - ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); -@@ -209,11 +305,6 @@ static void ar933x_ip2_handler(void) - do_IRQ(ATH79_CPU_IRQ_IP2); - } - --static void ar934x_ip2_handler(void) --{ -- do_IRQ(ATH79_CPU_IRQ_IP2); --} -- - static void ar71xx_ip3_handler(void) - { - ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); -@@ -259,8 +350,11 @@ void __init arch_init_irq(void) - ath79_ip2_handler = ar933x_ip2_handler; - ath79_ip3_handler = ar933x_ip3_handler; - } else if (soc_is_ar934x()) { -- ath79_ip2_handler = ar934x_ip2_handler; -+ ath79_ip2_handler = ath79_default_ip2_handler; - ath79_ip3_handler = ar934x_ip3_handler; -+ } else if (soc_is_qca955x()) { -+ ath79_ip2_handler = ath79_default_ip2_handler; -+ ath79_ip3_handler = ath79_default_ip3_handler; - } else { - BUG(); - } -@@ -271,4 +365,6 @@ void __init arch_init_irq(void) - - if (soc_is_ar934x()) - ar934x_ip2_irq_init(); -+ else if (soc_is_qca955x()) -+ qca955x_irq_init(); - } ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -300,6 +300,7 @@ - #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac - - #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 -+#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac - - #define MISC_INT_ETHSW BIT(12) - #define MISC_INT_TIMER4 BIT(10) -@@ -398,6 +399,37 @@ - AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ - AR934X_PCIE_WMAC_INT_PCIE_RC3) - -+#define QCA955X_EXT_INT_WMAC_MISC BIT(0) -+#define QCA955X_EXT_INT_WMAC_TX BIT(1) -+#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) -+#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) -+#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) -+#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) -+#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) -+#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) -+#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) -+#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) -+#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) -+#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) -+#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) -+#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) -+#define QCA955X_EXT_INT_USB1 BIT(24) -+#define QCA955X_EXT_INT_USB2 BIT(28) -+ -+#define QCA955X_EXT_INT_WMAC_ALL \ -+ (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ -+ QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) -+ -+#define QCA955X_EXT_INT_PCIE_RC1_ALL \ -+ (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ -+ QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ -+ QCA955X_EXT_INT_PCIE_RC1_INT3) -+ -+#define QCA955X_EXT_INT_PCIE_RC2_ALL \ -+ (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ -+ QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ -+ QCA955X_EXT_INT_PCIE_RC2_INT3) -+ - #define REV_ID_MAJOR_MASK 0xfff0 - #define REV_ID_MAJOR_AR71XX 0x00a0 - #define REV_ID_MAJOR_AR913X 0x00b0 ---- a/arch/mips/include/asm/mach-ath79/irq.h -+++ b/arch/mips/include/asm/mach-ath79/irq.h -@@ -10,7 +10,7 @@ - #define __ASM_MACH_ATH79_IRQ_H - - #define MIPS_CPU_IRQ_BASE 0 --#define NR_IRQS 48 -+#define NR_IRQS 51 - - #define ATH79_MISC_IRQ_BASE 8 - #define ATH79_MISC_IRQ_COUNT 32 -@@ -24,8 +24,13 @@ - #define ATH79_IP2_IRQ_COUNT 2 - #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) - -+#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT) -+#define ATH79_IP3_IRQ_COUNT 3 -+#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x)) -+ - #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) --#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) -+#define ATH79_CPU_IRQ_IP3 (MIPS_CPU_IRQ_BASE + 3) -+#define ATH79_CPU_IRQ_USB ATH79_CPU_IRQ_IP3 - #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) - #define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5) - #define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) diff --git a/target/linux/ar71xx/patches-3.8/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch deleted file mode 100644 index 279ba33bf8..0000000000 --- a/target/linux/ar71xx/patches-3.8/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch +++ /dev/null @@ -1,39 +0,0 @@ -From c9a552f3007f0621b2440ae17bad816578299e52 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 24 Jun 2012 13:45:27 +0200 -Subject: [PATCH 20/34] MIPS: ath79: add GPIO setup code for the QCA955X SoCs - -Signed-off-by: Gabor Juhos ---- - arch/mips/ath79/gpio.c | 4 +++- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + - 2 files changed, 4 insertions(+), 1 deletions(-) - ---- a/arch/mips/ath79/gpio.c -+++ b/arch/mips/ath79/gpio.c -@@ -194,12 +194,14 @@ void __init ath79_gpio_init(void) - ath79_gpio_count = AR933X_GPIO_COUNT; - else if (soc_is_ar934x()) - ath79_gpio_count = AR934X_GPIO_COUNT; -+ else if (soc_is_qca955x()) -+ ath79_gpio_count = QCA955X_GPIO_COUNT; - else - BUG(); - - ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); - ath79_gpio_chip.ngpio = ath79_gpio_count; -- if (soc_is_ar934x()) { -+ if (soc_is_ar934x() || soc_is_qca955x()) { - ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; - ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; - } ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -509,6 +509,7 @@ - #define AR913X_GPIO_COUNT 22 - #define AR933X_GPIO_COUNT 30 - #define AR934X_GPIO_COUNT 23 -+#define QCA955X_GPIO_COUNT 24 - - /* - * SRIF block diff --git a/target/linux/ar71xx/patches-3.8/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch b/target/linux/ar71xx/patches-3.8/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch deleted file mode 100644 index f3e3b6eecf..0000000000 --- a/target/linux/ar71xx/patches-3.8/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 68368e80b4db83afe39664a7d43c8b5c7b8ac3b4 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 24 Jun 2012 13:49:33 +0200 -Subject: [PATCH 21/34] MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set,clear} - ---- - arch/mips/ath79/common.c | 6 ++++-- - 1 files changed, 4 insertions(+), 2 deletions(-) - ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -70,7 +70,8 @@ void ath79_device_reset_set(u32 mask) - reg = AR913X_RESET_REG_RESET_MODULE; - else if (soc_is_ar933x()) - reg = AR933X_RESET_REG_RESET_MODULE; -- else if (soc_is_ar934x()) -+ else if (soc_is_ar934x() || -+ soc_is_qca955x()) - reg = AR934X_RESET_REG_RESET_MODULE; - else - BUG(); -@@ -96,7 +97,8 @@ void ath79_device_reset_clear(u32 mask) - reg = AR913X_RESET_REG_RESET_MODULE; - else if (soc_is_ar933x()) - reg = AR933X_RESET_REG_RESET_MODULE; -- else if (soc_is_ar934x()) -+ else if (soc_is_ar934x() || -+ soc_is_qca955x()) - reg = AR934X_RESET_REG_RESET_MODULE; - else - BUG(); diff --git a/target/linux/ar71xx/patches-3.8/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch deleted file mode 100644 index aacb8bbeb0..0000000000 --- a/target/linux/ar71xx/patches-3.8/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch +++ /dev/null @@ -1,22 +0,0 @@ -From f7d7b362b51c51c1ae80bb7ade2039d6f74d4070 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 24 Jun 2012 13:46:26 +0200 -Subject: [PATCH 22/34] MIPS: ath79: register UART for the QCA955X SoCs - -Signed-off-by: Gabor Juhos ---- - arch/mips/ath79/dev-common.c | 3 ++- - 1 files changed, 2 insertions(+), 1 deletions(-) - ---- a/arch/mips/ath79/dev-common.c -+++ b/arch/mips/ath79/dev-common.c -@@ -90,7 +90,8 @@ void __init ath79_register_uart(void) - if (soc_is_ar71xx() || - soc_is_ar724x() || - soc_is_ar913x() || -- soc_is_ar934x()) { -+ soc_is_ar934x() || -+ soc_is_qca955x()) { - ath79_uart_data[0].uartclk = clk_get_rate(clk); - platform_device_register(&ath79_uart_device); - } else if (soc_is_ar933x()) { diff --git a/target/linux/ar71xx/patches-3.8/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.8/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch deleted file mode 100644 index c0d8857de5..0000000000 --- a/target/linux/ar71xx/patches-3.8/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch +++ /dev/null @@ -1,93 +0,0 @@ -From e4ba5e2bffd1f373f57dd692233aa6b7b46ae76c Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 24 Jun 2012 13:47:35 +0200 -Subject: [PATCH 23/34] MIPS: ath79: add USB controller registration code for the QCA955X SoCs - -Signed-off-by: Gabor Juhos ---- - arch/mips/ath79/dev-usb.c | 46 ++++++++++++++++++++++++ - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++ - 2 files changed, 50 insertions(+), 0 deletions(-) - ---- a/arch/mips/ath79/dev-usb.c -+++ b/arch/mips/ath79/dev-usb.c -@@ -73,6 +73,8 @@ static void __init ath79_usb_init_resour - unsigned long size, - int irq) - { -+ memset(res, 0, sizeof(res)); -+ - res[0].flags = IORESOURCE_MEM; - res[0].start = base; - res[0].end = base + size - 1; -@@ -217,6 +219,48 @@ static void __init ar934x_usb_setup(void - platform_device_register(&ath79_ehci_device); - } - -+static void __init qca955x_usb_setup(void) -+{ -+ struct platform_device *pdev; -+ -+ ath79_usb_init_resource(ath79_ehci_resources, -+ QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE, -+ ATH79_IP3_IRQ(0)); -+ -+ pdev = platform_device_register_resndata(NULL, "ehci-platform", 0, -+ ath79_ehci_resources, -+ ARRAY_SIZE(ath79_ehci_resources), -+ &ath79_ehci_pdata_v2, -+ sizeof(ath79_ehci_pdata_v2)); -+ if (IS_ERR(pdev)) { -+ pr_err("Unable to register USB %d device, err=%d\n", 0, -+ (int) PTR_ERR(pdev)); -+ return; -+ } -+ -+ pdev->dev.dma_mask = &ath79_ehci_dmamask; -+ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); -+ -+ ath79_usb_init_resource(ath79_ehci_resources, -+ QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE, -+ ATH79_IP3_IRQ(1)); -+ -+ pdev = platform_device_register_resndata(NULL, "ehci-platform", 1, -+ ath79_ehci_resources, -+ ARRAY_SIZE(ath79_ehci_resources), -+ &ath79_ehci_pdata_v2, -+ sizeof(ath79_ehci_pdata_v2)); -+ -+ if (IS_ERR(pdev)) { -+ pr_err("Unable to register USB %d device, err=%d\n", 1, -+ (int) PTR_ERR(pdev)); -+ return; -+ } -+ -+ pdev->dev.dma_mask = &ath79_ehci_dmamask; -+ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); -+} -+ - void __init ath79_register_usb(void) - { - if (soc_is_ar71xx()) -@@ -231,6 +275,8 @@ void __init ath79_register_usb(void) - ar933x_usb_setup(); - else if (soc_is_ar934x()) - ar934x_usb_setup(); -+ else if (soc_is_qca955x()) -+ qca955x_usb_setup(); - else - BUG(); - } ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -94,6 +94,10 @@ - #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) - #define AR934X_SRIF_SIZE 0x1000 - -+#define QCA955X_EHCI0_BASE 0x1b000000 -+#define QCA955X_EHCI1_BASE 0x1b400000 -+#define QCA955X_EHCI_SIZE 0x200 -+ - /* - * DDR_CTRL block - */ diff --git a/target/linux/ar71xx/patches-3.8/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch b/target/linux/ar71xx/patches-3.8/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch deleted file mode 100644 index efc354e9d9..0000000000 --- a/target/linux/ar71xx/patches-3.8/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 0568e7f92ecf2bfd2af0a5c59b1249fef002c89f Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Tue, 3 Jul 2012 10:24:43 +0200 -Subject: [PATCH 24/34] MIPS: ath79: add WMAC registration code for the QCA955X SoCs - -Signed-off-by: Gabor Juhos ---- - arch/mips/ath79/Kconfig | 2 +- - arch/mips/ath79/dev-wmac.c | 20 ++++++++++++++++++++ - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++ - 3 files changed, 23 insertions(+), 1 deletions(-) - ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -108,7 +108,7 @@ config ATH79_DEV_USB - def_bool n - - config ATH79_DEV_WMAC -- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X) -+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) - def_bool n - - endif ---- a/arch/mips/ath79/dev-wmac.c -+++ b/arch/mips/ath79/dev-wmac.c -@@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void) - ath79_wmac_data.is_clk_25mhz = true; - } - -+static void qca955x_wmac_setup(void) -+{ -+ u32 t; -+ -+ ath79_wmac_device.name = "qca955x_wmac"; -+ -+ ath79_wmac_resources[0].start = QCA955X_WMAC_BASE; -+ ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1; -+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); -+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); -+ -+ t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); -+ if (t & QCA955X_BOOTSTRAP_REF_CLK_40) -+ ath79_wmac_data.is_clk_25mhz = false; -+ else -+ ath79_wmac_data.is_clk_25mhz = true; -+} -+ - void __init ath79_register_wmac(u8 *cal_data) - { - if (soc_is_ar913x()) -@@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_ - ar933x_wmac_setup(); - else if (soc_is_ar934x()) - ar934x_wmac_setup(); -+ else if (soc_is_qca955x()) -+ qca955x_wmac_setup(); - else - BUG(); - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -94,6 +94,8 @@ - #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) - #define AR934X_SRIF_SIZE 0x1000 - -+#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -+#define QCA955X_WMAC_SIZE 0x20000 - #define QCA955X_EHCI0_BASE 0x1b000000 - #define QCA955X_EHCI1_BASE 0x1b400000 - #define QCA955X_EHCI_SIZE 0x200 diff --git a/target/linux/ar71xx/patches-3.8/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.8/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch deleted file mode 100644 index b94daf1e5c..0000000000 --- a/target/linux/ar71xx/patches-3.8/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 8bb54348722216a1dd6905d9d031ebdaa3a544a4 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 24 Jun 2012 23:05:20 +0200 -Subject: [PATCH 26/34] MIPS: ath79: add PCI controller registration code for the QCA9558 SoC - ---- - arch/mips/ath79/Kconfig | 2 + - arch/mips/ath79/pci.c | 36 ++++++++++++++++++++++++ - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 13 ++++++++ - 3 files changed, 51 insertions(+), 0 deletions(-) - ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -90,6 +90,8 @@ config SOC_AR934X - - config SOC_QCA955X - select USB_ARCH_HAS_EHCI -+ select HW_HAS_PCI -+ select PCI_AR724X if PCI - def_bool n - - config PCI_AR724X ---- a/arch/mips/ath79/pci.c -+++ b/arch/mips/ath79/pci.c -@@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x - } - }; - -+static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = { -+ { -+ .bus = 0, -+ .slot = 0, -+ .pin = 1, -+ .irq = ATH79_PCI_IRQ(0), -+ }, -+ { -+ .bus = 1, -+ .slot = 0, -+ .pin = 1, -+ .irq = ATH79_PCI_IRQ(1), -+ }, -+}; -+ - int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) - { - int irq = -1; -@@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct - soc_is_ar9344()) { - ath79_pci_irq_map = ar724x_pci_irq_map; - ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); -+ } else if (soc_is_qca955x()) { -+ ath79_pci_irq_map = qca955x_pci_irq_map; -+ ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); - } else { - pr_crit("pci %s: invalid irq map\n", - pci_name((struct pci_dev *) dev)); -@@ -225,6 +243,24 @@ int __init ath79_register_pci(void) - AR724X_PCI_MEM_SIZE, - 0, - ATH79_IP2_IRQ(0)); -+ } else if (soc_is_qca9558()) { -+ pdev = ath79_register_pci_ar724x(0, -+ QCA955X_PCI_CFG_BASE0, -+ QCA955X_PCI_CTRL_BASE0, -+ QCA955X_PCI_CRP_BASE0, -+ QCA955X_PCI_MEM_BASE0, -+ QCA955X_PCI_MEM_SIZE, -+ 0, -+ ATH79_IP2_IRQ(0)); -+ -+ pdev = ath79_register_pci_ar724x(1, -+ QCA955X_PCI_CFG_BASE1, -+ QCA955X_PCI_CTRL_BASE1, -+ QCA955X_PCI_CRP_BASE1, -+ QCA955X_PCI_MEM_BASE1, -+ QCA955X_PCI_MEM_SIZE, -+ 1, -+ ATH79_IP3_IRQ(2)); - } else { - /* No PCI support */ - return -ENODEV; ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -94,6 +94,19 @@ - #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) - #define AR934X_SRIF_SIZE 0x1000 - -+#define QCA955X_PCI_MEM_BASE0 0x10000000 -+#define QCA955X_PCI_MEM_BASE1 0x12000000 -+#define QCA955X_PCI_MEM_SIZE 0x02000000 -+#define QCA955X_PCI_CFG_BASE0 0x14000000 -+#define QCA955X_PCI_CFG_BASE1 0x16000000 -+#define QCA955X_PCI_CFG_SIZE 0x1000 -+#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) -+#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) -+#define QCA955X_PCI_CRP_SIZE 0x1000 -+#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) -+#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) -+#define QCA955X_PCI_CTRL_SIZE 0x100 -+ - #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) - #define QCA955X_WMAC_SIZE 0x20000 - #define QCA955X_EHCI0_BASE 0x1b000000 diff --git a/target/linux/ar71xx/patches-3.8/171-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch b/target/linux/ar71xx/patches-3.8/171-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch deleted file mode 100644 index dc26f9c7bc..0000000000 --- a/target/linux/ar71xx/patches-3.8/171-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch +++ /dev/null @@ -1,213 +0,0 @@ -From a034da3e4d4960266a94d15c811d5f4529fdff44 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Sun, 24 Jun 2012 13:52:23 +0200 -Subject: [PATCH 27/34] MIPS: ath79: add support for the Qualcomm Atheros AP136 board - -Signed-off-by: Gabor Juhos ---- - arch/mips/ath79/Kconfig | 12 +++ - arch/mips/ath79/Makefile | 1 + - arch/mips/ath79/mach-ap136.c | 155 ++++++++++++++++++++++++++++++++++++++++++ - arch/mips/ath79/machtypes.h | 1 + - 4 files changed, 169 insertions(+), 0 deletions(-) - create mode 100644 arch/mips/ath79/mach-ap136.c - ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -14,6 +14,18 @@ config ATH79_MACH_AP121 - Say 'Y' here if you want your kernel to support the - Atheros AP121 reference board. - -+config ATH79_MACH_AP136 -+ bool "Atheros AP136 reference board" -+ select SOC_QCA955X -+ select ATH79_DEV_GPIO_BUTTONS -+ select ATH79_DEV_LEDS_GPIO -+ select ATH79_DEV_SPI -+ select ATH79_DEV_USB -+ select ATH79_DEV_WMAC -+ help -+ Say 'Y' here if you want your kernel to support the -+ Atheros AP136 reference board. -+ - config ATH79_MACH_AP81 - bool "Atheros AP81 reference board" - select SOC_AR913X ---- a/arch/mips/ath79/Makefile -+++ b/arch/mips/ath79/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wma - # Machines - # - obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o -+obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o - obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o - obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o - obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o ---- /dev/null -+++ b/arch/mips/ath79/mach-ap136.c -@@ -0,0 +1,155 @@ -+/* -+ * Qualcomm Atheros AP136 reference board support -+ * -+ * Copyright (c) 2012 Qualcomm Atheros -+ * Copyright (c) 2012 Gabor Juhos -+ * -+ * Permission to use, copy, modify, and/or distribute this software for any -+ * purpose with or without fee is hereby granted, provided that the above -+ * copyright notice and this permission notice appear in all copies. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ * -+ */ -+ -+#include -+#include -+ -+#include "machtypes.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-spi.h" -+#include "dev-usb.h" -+#include "dev-wmac.h" -+#include "pci.h" -+ -+#define AP136_GPIO_LED_STATUS_RED 14 -+#define AP136_GPIO_LED_STATUS_GREEN 19 -+#define AP136_GPIO_LED_USB 4 -+#define AP136_GPIO_LED_WLAN_2G 13 -+#define AP136_GPIO_LED_WLAN_5G 12 -+#define AP136_GPIO_LED_WPS_RED 15 -+#define AP136_GPIO_LED_WPS_GREEN 20 -+ -+#define AP136_GPIO_BTN_WPS 16 -+#define AP136_GPIO_BTN_RFKILL 21 -+ -+#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) -+ -+#define AP136_WMAC_CALDATA_OFFSET 0x1000 -+#define AP136_PCIE_CALDATA_OFFSET 0x5000 -+ -+static struct gpio_led ap136_leds_gpio[] __initdata = { -+ { -+ .name = "ap136:green:status", -+ .gpio = AP136_GPIO_LED_STATUS_GREEN, -+ .active_low = 1, -+ }, -+ { -+ .name = "ap136:red:status", -+ .gpio = AP136_GPIO_LED_STATUS_RED, -+ .active_low = 1, -+ }, -+ { -+ .name = "ap136:green:wps", -+ .gpio = AP136_GPIO_LED_WPS_GREEN, -+ .active_low = 1, -+ }, -+ { -+ .name = "ap136:red:wps", -+ .gpio = AP136_GPIO_LED_WPS_RED, -+ .active_low = 1, -+ }, -+ { -+ .name = "ap136:red:wlan-2g", -+ .gpio = AP136_GPIO_LED_WLAN_2G, -+ .active_low = 1, -+ }, -+ { -+ .name = "ap136:red:usb", -+ .gpio = AP136_GPIO_LED_USB, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button ap136_gpio_keys[] __initdata = { -+ { -+ .desc = "WPS button", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP136_GPIO_BTN_WPS, -+ .active_low = 1, -+ }, -+ { -+ .desc = "RFKILL button", -+ .type = EV_KEY, -+ .code = KEY_RFKILL, -+ .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP136_GPIO_BTN_RFKILL, -+ .active_low = 1, -+ }, -+}; -+ -+static struct spi_board_info ap136_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "mx25l6405d", -+ } -+}; -+ -+static struct ath79_spi_platform_data ap136_spi_data = { -+ .bus_num = 0, -+ .num_chipselect = 1, -+}; -+ -+#ifdef CONFIG_PCI -+static struct ath9k_platform_data ap136_ath9k_data; -+ -+static int ap136_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) -+ dev->dev.platform_data = &ap136_ath9k_data; -+ -+ return 0; -+} -+ -+static void __init ap136_pci_init(u8 *eeprom) -+{ -+ memcpy(ap136_ath9k_data.eeprom_data, eeprom, -+ sizeof(ap136_ath9k_data.eeprom_data)); -+ -+ ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); -+ ath79_register_pci(); -+} -+#else -+static inline void ap136_pci_init(void) {} -+#endif /* CONFIG_PCI */ -+ -+static void __init ap136_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), -+ ap136_leds_gpio); -+ ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(ap136_gpio_keys), -+ ap136_gpio_keys); -+ ath79_register_spi(&ap136_spi_data, ap136_spi_info, -+ ARRAY_SIZE(ap136_spi_info)); -+ ath79_register_usb(); -+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); -+ ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); -+} -+ -+MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board", -+ ap136_setup); ---- a/arch/mips/ath79/machtypes.h -+++ b/arch/mips/ath79/machtypes.h -@@ -17,6 +17,7 @@ - enum ath79_mach_type { - ATH79_MACH_GENERIC = 0, - ATH79_MACH_AP121, /* Atheros AP121 reference board */ -+ ATH79_MACH_AP136, /* Atheros AP136 reference board */ - ATH79_MACH_AP81, /* Atheros AP81 reference board */ - ATH79_MACH_DB120, /* Atheros DB120 reference board */ - ATH79_MACH_PB44, /* Atheros PB44 reference board */ diff --git a/target/linux/ar71xx/patches-3.8/172-MIPS-ath79-add-support-for-the-QCA9556-SoC.patch b/target/linux/ar71xx/patches-3.8/172-MIPS-ath79-add-support-for-the-QCA9556-SoC.patch deleted file mode 100644 index 2d039cb42f..0000000000 --- a/target/linux/ar71xx/patches-3.8/172-MIPS-ath79-add-support-for-the-QCA9556-SoC.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -164,6 +164,12 @@ static void __init ath79_detect_sys_type - rev = id & AR934X_REV_ID_REVISION_MASK; - break; - -+ case REV_ID_MAJOR_QCA9556: -+ ath79_soc = ATH79_SOC_QCA9556; -+ chip = "9556"; -+ rev = id & AR944X_REV_ID_REVISION_MASK; -+ break; -+ - case REV_ID_MAJOR_QCA9558: - ath79_soc = ATH79_SOC_QCA9558; - chip = "9558"; ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -460,6 +460,7 @@ - #define REV_ID_MAJOR_AR9341 0x0120 - #define REV_ID_MAJOR_AR9342 0x1120 - #define REV_ID_MAJOR_AR9344 0x2120 -+#define REV_ID_MAJOR_QCA9556 0x0130 - #define REV_ID_MAJOR_QCA9558 0x1130 - - #define AR71XX_REV_ID_MINOR_MASK 0x3 ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -32,6 +32,7 @@ enum ath79_soc_type { - ATH79_SOC_AR9341, - ATH79_SOC_AR9342, - ATH79_SOC_AR9344, -+ ATH79_SOC_QCA9556, - ATH79_SOC_QCA9558, - }; - -@@ -99,6 +100,11 @@ static inline int soc_is_ar934x(void) - return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); - } - -+static inline int soc_is_qca9556(void) -+{ -+ return ath79_soc == ATH79_SOC_QCA9556; -+} -+ - static inline int soc_is_qca9558(void) - { - return ath79_soc == ATH79_SOC_QCA9558; -@@ -106,7 +112,7 @@ static inline int soc_is_qca9558(void) - - static inline int soc_is_qca955x(void) - { -- return soc_is_qca9558(); -+ return soc_is_qca9556() || soc_is_qca9558(); - } - - extern void __iomem *ath79_ddr_base; diff --git a/target/linux/ar71xx/patches-3.8/503-MIPS-ath79-add-flash-acquire-release.patch b/target/linux/ar71xx/patches-3.8/503-MIPS-ath79-add-flash-acquire-release.patch index 15e7faac1b..06f790299d 100644 --- a/target/linux/ar71xx/patches-3.8/503-MIPS-ath79-add-flash-acquire-release.patch +++ b/target/linux/ar71xx/patches-3.8/503-MIPS-ath79-add-flash-acquire-release.patch @@ -8,7 +8,7 @@ u32 ath79_cpu_freq; EXPORT_SYMBOL_GPL(ath79_cpu_freq); -@@ -109,3 +110,16 @@ void ath79_device_reset_clear(u32 mask) +@@ -111,3 +112,16 @@ void ath79_device_reset_clear(u32 mask) spin_unlock_irqrestore(&ath79_device_reset_lock, flags); } EXPORT_SYMBOL_GPL(ath79_device_reset_clear); diff --git a/target/linux/ar71xx/patches-3.8/504-MIPS-ath79-add-ath79_device_reset_get.patch b/target/linux/ar71xx/patches-3.8/504-MIPS-ath79-add-ath79_device_reset_get.patch index e99b66faa2..024a85d06a 100644 --- a/target/linux/ar71xx/patches-3.8/504-MIPS-ath79-add-ath79_device_reset_get.patch +++ b/target/linux/ar71xx/patches-3.8/504-MIPS-ath79-add-ath79_device_reset_get.patch @@ -10,7 +10,7 @@ void ath79_flash_release(void); --- a/arch/mips/ath79/common.c +++ b/arch/mips/ath79/common.c -@@ -111,6 +111,32 @@ void ath79_device_reset_clear(u32 mask) +@@ -113,6 +113,32 @@ void ath79_device_reset_clear(u32 mask) } EXPORT_SYMBOL_GPL(ath79_device_reset_clear); diff --git a/target/linux/ar71xx/patches-3.8/521-MIPS-ath79-enable-UART-for-early_serial.patch b/target/linux/ar71xx/patches-3.8/521-MIPS-ath79-enable-UART-for-early_serial.patch index 489bc96738..3d6ddfe18c 100644 --- a/target/linux/ar71xx/patches-3.8/521-MIPS-ath79-enable-UART-for-early_serial.patch +++ b/target/linux/ar71xx/patches-3.8/521-MIPS-ath79-enable-UART-for-early_serial.patch @@ -47,7 +47,7 @@ static void prom_putchar_init(void) { void __iomem *base; -@@ -85,8 +125,10 @@ static void prom_putchar_init(void) +@@ -86,8 +126,10 @@ static void prom_putchar_init(void) default: _prom_putchar = prom_putchar_dummy; diff --git a/target/linux/ar71xx/patches-3.8/523-MIPS-ath79-OTP-support.patch b/target/linux/ar71xx/patches-3.8/523-MIPS-ath79-OTP-support.patch index 556a95175b..84273d3d48 100644 --- a/target/linux/ar71xx/patches-3.8/523-MIPS-ath79-OTP-support.patch +++ b/target/linux/ar71xx/patches-3.8/523-MIPS-ath79-OTP-support.patch @@ -151,7 +151,7 @@ +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h @@ -113,6 +113,14 @@ #define QCA955X_EHCI1_BASE 0x1b400000 - #define QCA955X_EHCI_SIZE 0x200 + #define QCA955X_EHCI_SIZE 0x1000 +#define AR9300_OTP_BASE 0x14000 +#define AR9300_OTP_STATUS 0x15f18 diff --git a/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch index fb7d169ad6..5cb7584fdc 100644 --- a/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch @@ -42,12 +42,17 @@ #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) #define AR934X_SRIF_SIZE 0x1000 -@@ -112,6 +124,10 @@ - #define QCA955X_EHCI0_BASE 0x1b000000 - #define QCA955X_EHCI1_BASE 0x1b400000 - #define QCA955X_EHCI_SIZE 0x200 +@@ -107,11 +119,15 @@ + #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) + #define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 + #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define QCA955X_WMAC_SIZE 0x20000 + #define QCA955X_EHCI0_BASE 0x1b000000 + #define QCA955X_EHCI1_BASE 0x1b400000 + #define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 @@ -105,7 +110,7 @@ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -378,16 +408,83 @@ +@@ -379,16 +409,83 @@ #define AR913X_RESET_USB_HOST BIT(5) #define AR913X_RESET_USB_PHY BIT(4) @@ -189,7 +194,7 @@ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -529,6 +626,12 @@ +@@ -530,6 +627,12 @@ #define AR71XX_GPIO_REG_INT_ENABLE 0x24 #define AR71XX_GPIO_REG_FUNC 0x28 @@ -202,7 +207,7 @@ #define AR934X_GPIO_REG_FUNC 0x6c #define AR71XX_GPIO_COUNT 16 -@@ -560,4 +663,133 @@ +@@ -561,4 +664,133 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 diff --git a/target/linux/ar71xx/patches-3.8/603-MIPS-ath79-ap121-fixes.patch b/target/linux/ar71xx/patches-3.8/603-MIPS-ath79-ap121-fixes.patch index 1cacde6046..a51f587cae 100644 --- a/target/linux/ar71xx/patches-3.8/603-MIPS-ath79-ap121-fixes.patch +++ b/target/linux/ar71xx/patches-3.8/603-MIPS-ath79-ap121-fixes.patch @@ -158,6 +158,6 @@ ATH79_MACH_GENERIC = 0, ATH79_MACH_AP121, /* Atheros AP121 reference board */ + ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ - ATH79_MACH_AP136, /* Atheros AP136 reference board */ + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ ATH79_MACH_AP81, /* Atheros AP81 reference board */ ATH79_MACH_DB120, /* Atheros DB120 reference board */ diff --git a/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch index 6358e47807..0a8fe0e4b8 100644 --- a/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch +++ b/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch @@ -1,12 +1,5 @@ --- a/arch/mips/ath79/mach-ap136.c +++ b/arch/mips/ath79/mach-ap136.c -@@ -1,5 +1,5 @@ - /* -- * Qualcomm Atheros AP136 reference board support -+ * Atheros AP136 reference board support - * - * Copyright (c) 2012 Qualcomm Atheros - * Copyright (c) 2012 Gabor Juhos @@ -18,23 +18,28 @@ * */ @@ -44,7 +37,7 @@ #define AP136_GPIO_LED_WPS_GREEN 20 #define AP136_GPIO_BTN_WPS 16 -@@ -43,8 +48,10 @@ +@@ -43,37 +48,39 @@ #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) @@ -57,7 +50,42 @@ static struct gpio_led ap136_leds_gpio[] __initdata = { { -@@ -98,64 +105,158 @@ static struct gpio_keys_button ap136_gpi +- .name = "qca:green:status", ++ .name = "ap136:green:status", + .gpio = AP136_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, + { +- .name = "qca:red:status", ++ .name = "ap136:red:status", + .gpio = AP136_GPIO_LED_STATUS_RED, + .active_low = 1, + }, + { +- .name = "qca:green:wps", ++ .name = "ap136:green:wps", + .gpio = AP136_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, + { +- .name = "qca:red:wps", ++ .name = "ap136:red:wps", + .gpio = AP136_GPIO_LED_WPS_RED, + .active_low = 1, + }, + { +- .name = "qca:red:wlan-2g", ++ .name = "ap136:red:wlan-2g", + .gpio = AP136_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { +- .name = "qca:red:usb", ++ .name = "ap136:red:usb", + .gpio = AP136_GPIO_LED_USB, + .active_low = 1, + } +@@ -98,65 +105,158 @@ static struct gpio_keys_button ap136_gpi }, }; @@ -204,10 +232,11 @@ + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ap136_common_setup(); -+} -+ -+MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", -+ "Atheros AP136-010 reference board", + } + + MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", + "Atheros AP136-010 reference board", +- ap136_setup); + ap136_010_setup); + +static void __init ap136_020_setup(void) @@ -247,10 +276,8 @@ + ap136_leds_gpio[5].name = "ap135:red:usb"; + + ap136_020_setup(); - } - --MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board", -- ap136_setup); ++} ++ +MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020", + "Atheros AP135-020 reference board", + ap135_020_setup); @@ -260,9 +287,8 @@ ATH79_MACH_GENERIC = 0, ATH79_MACH_AP121, /* Atheros AP121 reference board */ ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ -- ATH79_MACH_AP136, /* Atheros AP136 reference board */ + ATH79_MACH_AP135_020, /* Atheros AP135-020 reference board */ -+ ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ + ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */ ATH79_MACH_AP81, /* Atheros AP81 reference board */ ATH79_MACH_DB120, /* Atheros DB120 reference board */ -- cgit v1.2.3